[ARM] Fix Coprocessor instructions availability
A few coprocessor instructions introduced in ARMv2 are currently accepted by GAS when targeting ARMv1 due to a typo in the code. This patch fixes the issue and introduce a more fine grained testing for coprocessor instructions availability. Coprocessor instructions are grouped as follows: * ARM coprocessor instructions introduced in ARMv2 Includes: ldc, stc, mcr, mrc, cdp, ldcl, stcl Guarded by: ARM_EXT_V2 Tests: copro-arm_v2plus-arm_v*.d * ARM coprocessor instructions introduced in ARMv5 Includes: ldc2, ldc2l, stc2, stc2l, cdp2, mcr2, mrc2 Guarded by: ARM_EXT_V5 Tests: copro-arm_v5plus-arm_v*.d * ARM coprocessor instructions introduced in ARMv5TE Includes: mcrr, mrrc Guarded by: ARM_EXT_V5E Tests: copro-arm_v5teplus-arm_v*.d * ARM coprocessor instructions introduced in ARMv6 Includes: mcrr2, mrrc2 Guarded by: ARM_EXT_V6 Tests: copro-arm_v6plus-arm_v*.d * Thumb coprocessor instructions introduced in ARMv6T2 Includes: ldc, ldcl, stc, stcl, mcr, mrc, mcrr, mrrc, cdp, ldc2, ldc2l, stc2, stc2l, cdp2, mcr2, mrc2, mcrr2, mrrc2 Guarded by: ARM_EXT_V6T2 Tests: copro-thumb_v6t2plus-thumb_v*.d For each of these groups, at least 2 tests are performed: * instructions are not available in earlier architecture * instructions are available in architecture where they were introduced More tests need to be performed when instructions in a group span several assembly files. Note that an instruction in the original coprocessor testcase is changed to unified syntax to allow the testcase to be assembled for ARM and Thumb state. Correct processing of legacy syntax is covered in other testcases. 2017-11-01 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_v2): Define to ARM_EXT_V2 feature bit. * testsuite/gas/arm/copro.s: Split into ... * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus.s: This while changing it to unified syntax and ... * testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus.s: this and ... * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus.s: This and ... * testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus.s: This. * testsuite/gas/arm/copro.d: Split into ... * testsuite/gas/arm/copro-arm_v2plus-arm_v2.d: This but target ARMv2 and ... * testsuite/gas/arm/copro-arm_v5plus-arm_v5.d: this but target ARMv5 and ... * testsuite/gas/arm/copro-arm_v5teplus-arm_v5te.d: This but target ARMv5TE and ... * testsuite/gas/arm/copro-arm_v6plus-arm_v6.d: This but target ARMv6. * testsuite/gas/arm/copro-arm_v2plus-arm_v1.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-1.d: New testcase. * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d: New testcase. * testsuite/gas/arm/copro-arm_v5plus-arm_v4.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-2.d: New testcase. * testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d: New testcase. * testsuite/gas/arm/copro-arm_v5teplus-arm_v5.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-3.d: New testcase. * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-3.d: New testcase. * testsuite/gas/arm/copro-arm_v6plus-arm_v5te.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-4.d: New testcase. * testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-4.d: New testcase.
This commit is contained in:
Thomas Preud'homme
parent
3988aed54a
commit
4070243b5c
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@ -1,3 +1,41 @@
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2017-11-01 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* config/tc-arm.c (arm_ext_v2): Define to ARM_EXT_V2 feature bit.
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* testsuite/gas/arm/copro.s: Split into ...
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* testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus.s: This while
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changing it to unified syntax and ...
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* testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus.s: this and ...
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* testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus.s: This and ...
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* testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus.s: This.
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* testsuite/gas/arm/copro.d: Split into ...
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* testsuite/gas/arm/copro-arm_v2plus-arm_v2.d: This but target ARMv2
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and ...
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* testsuite/gas/arm/copro-arm_v5plus-arm_v5.d: this but target ARMv5
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and ...
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* testsuite/gas/arm/copro-arm_v5teplus-arm_v5te.d: This but target
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ARMv5TE and ...
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* testsuite/gas/arm/copro-arm_v6plus-arm_v6.d: This but target ARMv6.
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* testsuite/gas/arm/copro-arm_v2plus-arm_v1.d: New testcase.
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* testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-1.d: New testcase.
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* testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus-unavail.l: Expected
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errors for the above two testcases.
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* testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d: New testcase.
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* testsuite/gas/arm/copro-arm_v5plus-arm_v4.d: New testcase.
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* testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-2.d: New testcase.
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* testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus-unavail.l:
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Expected errors for the above two testcases.
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* testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d: New testcase.
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* testsuite/gas/arm/copro-arm_v5teplus-arm_v5.d: New testcase.
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* testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-3.d: New testcase.
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* testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus-unavail.l:
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Expected errors for the above two testcases.
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* testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-3.d: New testcase.
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* testsuite/gas/arm/copro-arm_v6plus-arm_v5te.d: New testcase.
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* testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-4.d: New testcase.
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* testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus-unavail.l:
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Expected errors for the above two testcases.
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* testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-4.d: New testcase.
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2017-10-26 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/22352
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@ -173,7 +173,7 @@ static const arm_feature_set cpu_default = CPU_DEFAULT;
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#endif
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static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
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static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
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static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2);
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static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
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static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
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static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
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@ -0,0 +1,5 @@
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#source: copro-arm_v2plus-thumb_v6t2plus.s
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: No ARMv2 ARM CoProcessor Instructions on ARMv1
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#as: -march=armv1 -EL
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#error-output: copro-arm_v2plus-thumb_v6t2plus-unavail.l
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@ -1,6 +1,7 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: ARM CoProcessor Instructions
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#as: -march=armv5te -EL
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#source: copro-arm_v2plus-thumb_v6t2plus.s
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: ARMv2 ARM CoProcessor Instructions
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#as: -march=armv2 -EL
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# Test the standard ARM co-processor instructions:
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@ -25,18 +26,10 @@ Disassembly of section .text:
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0+03c <[^>]*> be228519 mcrlt 5, 1, r8, cr2, cr9, \{0\}
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0+040 <[^>]*> ec907300 ldc 3, cr7, \[r0\], \{0\}
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0+044 <[^>]*> ec816e01 stc 14, cr6, \[r1\], \{1\}
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0+048 <[^>]*> fc925502 ldc2 5, cr5, \[r2\], \{2\}
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0+04c <[^>]*> fc834603 stc2 6, cr4, \[r3\], \{3\}
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0+050 <[^>]*> ecd43704 ldcl 7, cr3, \[r4\], \{4\}
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0+054 <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\}
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0+058 <[^>]*> fcd61c06 ldc2l 12, cr1, \[r6\], \{6\}
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0+05c <[^>]*> fcc70c07 stc2l 12, cr0, \[r7\], \{7\}
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0+060 <[^>]*> ecd88cff ldcl 12, cr8, \[r8\], \{255\}.*
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0+064 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\}.*
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0+068 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4
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0+06c <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5
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0+070 <[^>]*> ec507fff mrrc 15, 15, r7, r0, cr15
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0+074 <[^>]*> ec407efe mcrr 14, 15, r7, r0, cr14
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0+078 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+07c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+080 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
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0+048 <[^>]*> ecd43704 ldcl 7, cr3, \[r4\], \{4\}
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0+04c <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\}
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0+050 <[^>]*> ecd88cff ldcl 12, cr8, \[r8\], \{255\}.*
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0+054 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\}.*
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0+058 <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+05c <[^>]*> e1a00000 nop ; \(mov r0, r0\)
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0+060 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
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@ -0,0 +1,24 @@
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[^:]*: Assembler messages:
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[^:]*:4: Error: selected processor does not support `cdp [^']*' in (ARM|Thumb) mode
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[^:]*:5: Error: selected processor does not support `cdpeq [^']*' in (ARM|Thumb) mode
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[^:]*:7: Error: selected processor does not support `ldc [^.]*' in (ARM|Thumb) mode
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[^:]*:8: Error: selected processor does not support `ldcl [^']*' in (ARM|Thumb) mode
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[^:]*:9: Error: selected processor does not support `ldcmi [^']*' in (ARM|Thumb) mode
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[^:]*:10: Error: selected processor does not support `ldclpl [^']*' in (ARM|Thumb) mode
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[^:]*:11: Error: selected processor does not support `ldc [^']*' in (ARM|Thumb) mode
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[^:]*:14: Error: selected processor does not support `stc [^']*' in (ARM|Thumb) mode
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[^:]*:15: Error: selected processor does not support `stcl [^']*' in (ARM|Thumb) mode
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[^:]*:16: Error: selected processor does not support `stceq [^']*' in (ARM|Thumb) mode
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[^:]*:17: Error: selected processor does not support `stccc [^']*' in (ARM|Thumb) mode
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[^:]*:18: Error: selected processor does not support `stc [^']*' in (ARM|Thumb) mode
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[^:]*:21: Error: selected processor does not support `mrc [^']*' in (ARM|Thumb) mode
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[^:]*:22: Error: selected processor does not support `mrcge [^']*' in (ARM|Thumb) mode
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[^:]*:24: Error: selected processor does not support `mcr [^']*' in (ARM|Thumb) mode
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[^:]*:25: Error: selected processor does not support `mcrlt [^']*' in (ARM|Thumb) mode
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[^:]*:28: Error: selected processor does not support `ldc [^']*' in (ARM|Thumb) mode
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[^:]*:29: Error: selected processor does not support `stc [^']*' in (ARM|Thumb) mode
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[^:]*:30: Error: selected processor does not support `ldcl [^']*' in (ARM|Thumb) mode
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[^:]*:31: Error: selected processor does not support `stcl [^']*' in (ARM|Thumb) mode
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[^:]*:33: Error: selected processor does not support `ldcl [^']*' in (ARM|Thumb) mode
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[^:]*:34: Error: selected processor does not support `stcl [^']*' in (ARM|Thumb) mode
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[^:]*:41: Error: selected processor does not support `mrcge [^']*' in (ARM|Thumb) mode
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@ -1,3 +1,4 @@
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.syntax unified
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.text
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.align 0
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cdp p1, 4, cr1, cr2, cr3
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@ -6,7 +7,7 @@
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ldc 5, cr9, [r3]
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ldcl 1, cr14, [r1, #32]
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ldcmi 0, cr0, [r2, #1020]!
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ldcpll p7, c1, [r3], #64
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ldclpl p7, c1, [r3], #64
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ldc p0, c8, foo
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foo:
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@ -24,23 +25,13 @@ bar:
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mcrlt 5, 1, r8, cr2, cr9, 0
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@ The following patterns test Addressing Mode 5 "Unindexed"
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ldc 3, c7, [r0], {0}
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stc p14, c6, [r1], {1}
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ldc2 5, c5, [r2], {2}
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stc2 p6, c4, [r3], {3}
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ldcl 7, c3, [r4], {4}
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stcl p8, c2, [r5], {5}
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@ using '9, 10, 11' below results in an invalid ldc2l/stc2l instruction.
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ldc2l 12, c1, [r6], {6}
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stc2l p12, c0, [r7], {7}
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@ using '11' below results in an (invalid) Neon vldmia instruction.
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ldcl 12, c8, [r8], {255}
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stcl p12, c9, [r9], {254}
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mrrc 13, 0, r7, r0, cr4
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mcrr p14, 0, r7, r0, cr5
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mrrc 15, 15, r7, r0, cr15
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mcrr p14, 15, r7, r0, cr14
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ldcl 7, c3, [r4], {4}
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stcl p8, c2, [r5], {5}
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@ using '11' below results in an (invalid) Neon vldmia instruction.
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ldcl 12, c8, [r8], {255}
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stcl p12, c9, [r9], {254}
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# Extra instructions to allow for code alignment in arm-aout target.
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nop
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@ -0,0 +1,5 @@
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#source: copro-arm_v5plus-thumb_v6t2plus.s
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: No ARMv5 ARM CoProcessor Instructions on ARMv4
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#as: -march=armv4 -EL
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#error-output: copro-arm_v5plus-thumb_v6t2plus-unavail.l
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@ -0,0 +1,23 @@
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#source: copro-arm_v5plus-thumb_v6t2plus.s
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: ARMv5 ARM CoProcessor Instructions
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#as: -march=armv5 -EL
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# Test the standard ARM co-processor instructions:
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+000 <[^>]*> fe421103 cdp2 1, 4, cr1, cr2, cr3, \{0\}
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0+004 <[^>]*> fd939500 ldc2 5, cr9, \[r3\]
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0+008 <[^>]*> fdd1e108 ldc2l 1, cr14, \[r1, #32\]
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0+00c <[^>]*> fd1f8001 ldc2 0, cr8, \[pc, #-4\] ; .* <foo>
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0+010 <[^>]*> fd830500 stc2 5, cr0, \[r3\]
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0+014 <[^>]*> fdc0f302 stc2l 3, cr15, \[r0, #8\]
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0+018 <[^>]*> fd0f7101 stc2 1, cr7, \[pc, #-4\] ; .* <bar>
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0+01c <[^>]*> fe715212 mrc2 2, 3, r5, cr1, cr2, \{0\}
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0+020 <[^>]*> fe215711 mcr2 7, 1, r5, cr1, cr1, \{0\}
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0+024 <[^>]*> fc925502 ldc2 5, cr5, \[r2\], \{2\}
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0+028 <[^>]*> fc834603 stc2 6, cr4, \[r3\], \{3\}
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0+02c <[^>]*> fcd61c06 ldc2l 12, cr1, \[r6\], \{6\}
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0+030 <[^>]*> fcc70c07 stc2l 12, cr0, \[r7\], \{7\}
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@ -0,0 +1,14 @@
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[^:]*: Assembler messages:
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[^:]*:3: Error: selected processor does not support `cdp2 [^']*' in (ARM|Thumb) mode
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[^:]*:5: Error: selected processor does not support `ldc2 [^.]*' in (ARM|Thumb) mode
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[^:]*:6: Error: selected processor does not support `ldc2l [^']*' in (ARM|Thumb) mode
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[^:]*:7: Error: selected processor does not support `ldc2 [^']*' in (ARM|Thumb) mode
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[^:]*:10: Error: selected processor does not support `stc2 [^']*' in (ARM|Thumb) mode
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[^:]*:11: Error: selected processor does not support `stc2l [^']*' in (ARM|Thumb) mode
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[^:]*:12: Error: selected processor does not support `stc2 [^']*' in (ARM|Thumb) mode
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[^:]*:15: Error: selected processor does not support `mrc2 [^']*' in (ARM|Thumb) mode
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[^:]*:16: Error: selected processor does not support `mcr2 [^']*' in (ARM|Thumb) mode
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[^:]*:20: Error: selected processor does not support `ldc2 [^']*' in (ARM|Thumb) mode
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[^:]*:21: Error: selected processor does not support `stc2 [^']*' in (ARM|Thumb) mode
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[^:]*:23: Error: selected processor does not support `ldc2l [^']*' in (ARM|Thumb) mode
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[^:]*:24: Error: selected processor does not support `stc2l [^']*' in (ARM|Thumb) mode
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@ -0,0 +1,24 @@
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.text
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.align 0
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cdp2 p1, 4, cr1, cr2, cr3
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ldc2 5, cr9, [r3]
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ldc2l 1, cr14, [r1, #32]
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ldc2 p0, c8, foo
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foo:
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stc2 5, cr0, [r3]
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stc2l 3, cr15, [r0, #8]
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stc2 p1, c7, bar
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bar:
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mrc2 2, 3, r5, c1, c2
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mcr2 p7, 1, r5, cr1, cr1
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@ The following patterns test Addressing Mode 5 "Unindexed"
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ldc2 5, c5, [r2], {2}
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stc2 p6, c4, [r3], {3}
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@ using '9, 10, 11' below results in an invalid ldc2l/stc2l instruction.
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ldc2l 12, c1, [r6], {6}
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stc2l p12, c0, [r7], {7}
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@ -0,0 +1,5 @@
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#source: copro-arm_v5teplus-thumb_v6t2plus.s
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: No ARMv5TE ARM CoProcessor Instructions on ARMv5
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#as: -march=armv5 -EL
|
||||
#error-output: copro-arm_v5teplus-thumb_v6t2plus-unavail.l
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#source: copro-arm_v5teplus-thumb_v6t2plus.s
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: ARMv5TE ARM CoProcessor Instructions
|
||||
#as: -march=armv5te -EL
|
||||
|
||||
# Test the standard ARM co-processor instructions:
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+000 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4
|
||||
0+004 <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5
|
||||
0+008 <[^>]*> ec507fff mrrc 15, 15, r7, r0, cr15
|
||||
0+00c <[^>]*> ec407efe mcrr 14, 15, r7, r0, cr14
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:4: Error: selected processor does not support `mrrc [^']*' in (ARM|Thumb) mode
|
||||
[^:]*:5: Error: selected processor does not support `mcrr [^']*' in (ARM|Thumb) mode
|
||||
[^:]*:6: Error: selected processor does not support `mrrc [^']*' in (ARM|Thumb) mode
|
||||
[^:]*:7: Error: selected processor does not support `mcrr [^']*' in (ARM|Thumb) mode
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
.text
|
||||
.align 0
|
||||
bar:
|
||||
mrrc 13, 0, r7, r0, cr4
|
||||
mcrr p14, 0, r7, r0, cr5
|
||||
mrrc 15, 15, r7, r0, cr15
|
||||
mcrr p14, 15, r7, r0, cr14
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#source: copro-arm_v6plus-thumb_v6t2plus.s
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: No ARMv6 ARM CoProcessor Instructions on ARMv5TE
|
||||
#as: -march=armv5te -EL
|
||||
#error-output: copro-arm_v6plus-thumb_v6t2plus-unavail.l
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#source: copro-arm_v6plus-thumb_v6t2plus.s
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: ARMv6 ARM CoProcessor Instructions
|
||||
#as: -march=armv6 -EL
|
||||
|
||||
# Test the standard ARM co-processor instructions:
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+000 <[^>]*> fc507d04 mrrc2 13, 0, r7, r0, cr4
|
||||
0+004 <[^>]*> fc407e05 mcrr2 14, 0, r7, r0, cr5
|
||||
0+008 <[^>]*> fc507fff mrrc2 15, 15, r7, r0, cr15
|
||||
0+00c <[^>]*> fc407efe mcrr2 14, 15, r7, r0, cr14
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:4: Error: selected processor does not support `mrrc2 [^']*' in (ARM|Thumb) mode
|
||||
[^:]*:5: Error: selected processor does not support `mcrr2 [^']*' in (ARM|Thumb) mode
|
||||
[^:]*:6: Error: selected processor does not support `mrrc2 [^']*' in (ARM|Thumb) mode
|
||||
[^:]*:7: Error: selected processor does not support `mcrr2 [^']*' in (ARM|Thumb) mode
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
.text
|
||||
.align 0
|
||||
bar:
|
||||
mrrc2 13, 0, r7, r0, cr4
|
||||
mcrr2 p14, 0, r7, r0, cr5
|
||||
mrrc2 15, 15, r7, r0, cr15
|
||||
mcrr2 p14, 15, r7, r0, cr14
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#source: copro-arm_v2plus-thumb_v6t2plus.s
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: No ARMv6T2 Thumb CoProcessor Instructions on ARMv4T (1)
|
||||
#as: -march=armv4t -mthumb -EL
|
||||
#error-output: copro-arm_v2plus-thumb_v6t2plus-unavail.l
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#source: copro-arm_v5plus-thumb_v6t2plus.s
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: No ARMv6T2 Thumb CoProcessor Instructions on ARMv4T (2)
|
||||
#as: -march=armv4t -mthumb -EL
|
||||
#error-output: copro-arm_v5plus-thumb_v6t2plus-unavail.l
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#source: copro-arm_v5teplus-thumb_v6t2plus.s
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: No ARMv6T2 Thumb CoProcessor Instructions on ARMv4T (3)
|
||||
#as: -march=armv4t -mthumb -EL
|
||||
#error-output: copro-arm_v5teplus-thumb_v6t2plus-unavail.l
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#source: copro-arm_v6plus-thumb_v6t2plus.s
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: No ARMv6T2 Thumb CoProcessor Instructions on ARMv4T (4)
|
||||
#as: -march=armv4t -mthumb -EL
|
||||
#error-output: copro-arm_v6plus-thumb_v6t2plus-unavail.l
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
#source: copro-arm_v2plus-thumb_v6t2plus.s
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: ARMv6T2 Thumb CoProcessor Instructions (1)
|
||||
#as: -march=armv6t2 -mthumb -mimplicit-it=always -EL
|
||||
|
||||
# Test the standard ARM co-processor instructions:
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+000 <[^>]*> ee42 1103 dvfs f1, f2, f3
|
||||
0+004 <[^>]*> [^ ]* it eq
|
||||
0+006 <[^>]*> ee34 14a5 cfadddeq mvd1, mvd4, mvd5
|
||||
0+00a <[^>]*> ed93 9500 cfldr32 mvfx9, \[r3\]
|
||||
0+00e <[^>]*> edd1 e108 ldfp f6, \[r1, #32\]
|
||||
0+012 <[^>]*> [^ ]* ite mi
|
||||
0+014 <[^>]*> edb2 00ff ldcmi 0, cr0, \[r2, #1020\]!.*
|
||||
0+018 <[^>]*> ecf3 1710 ldclpl 7, cr1, \[r3\], #64.*
|
||||
0+01c <[^>]*> ed9f 8000 ldc 0, cr8, \[pc] ; .* <foo>
|
||||
0+020 <[^>]*> ed83 0500 cfstr32 mvfx0, \[r3\]
|
||||
0+024 <[^>]*> edc0 f302 stcl 3, cr15, \[r0, #8\]
|
||||
0+028 <[^>]*> [^ ]* it eq
|
||||
0+02a <[^>]*> eda2 c419 cfstrseq mvf12, \[r2, #100\]!.*
|
||||
0+02e <[^>]*> [^ ]* it cc
|
||||
0+030 <[^>]*> eca4 860c stccc 6, cr8, \[r4\], #48.*
|
||||
0+034 <[^>]*> ed8f 7100 stfs f7, \[pc\] ; .* <bar>
|
||||
0+038 <[^>]*> ee71 5212 mrc 2, 3, r5, cr1, cr2, \{0\}
|
||||
0+03c <[^>]*> [^ ]* it ge
|
||||
0+03e <[^>]*> eeb1 f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
|
||||
0+042 <[^>]*> ee21 5711 mcr 7, 1, r5, cr1, cr1, \{0\}
|
||||
0+046 <[^>]*> [^ ]* it lt
|
||||
0+048 <[^>]*> ee22 8519 mcrlt 5, 1, r8, cr2, cr9, \{0\}
|
||||
0+04c <[^>]*> ec90 7300 ldc 3, cr7, \[r0\], \{0\}
|
||||
0+050 <[^>]*> ec81 6e01 stc 14, cr6, \[r1\], \{1\}
|
||||
0+054 <[^>]*> ecd4 3704 ldcl 7, cr3, \[r4\], \{4\}
|
||||
0+058 <[^>]*> ecc5 2805 stcl 8, cr2, \[r5\], \{5\}
|
||||
0+05c <[^>]*> ecd8 8cff ldcl 12, cr8, \[r8\], \{255\}.*
|
||||
0+060 <[^>]*> ecc9 9cfe stcl 12, cr9, \[r9\], \{254\}.*
|
||||
0+064 <[^>]*> bf00 nop
|
||||
0+066 <[^>]*> bf00 nop
|
||||
0+068 <[^>]*> [^ ]* it ge
|
||||
0+06a <[^>]*> eeb1 f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\}
|
||||
#...
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
#source: copro-arm_v5plus-thumb_v6t2plus.s
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: ARMv6T2 Thumb CoProcessor Instructions (2)
|
||||
#as: -march=armv6t2 -mthumb -EL
|
||||
|
||||
# Test the standard ARM co-processor instructions:
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+000 <[^>]*> fe42 1103 cdp2 1, 4, cr1, cr2, cr3, \{0\}
|
||||
0+004 <[^>]*> fd93 9500 ldc2 5, cr9, \[r3\]
|
||||
0+008 <[^>]*> fdd1 e108 ldc2l 1, cr14, \[r1, #32\]
|
||||
0+00c <[^>]*> fd9f 8000 ldc2 0, cr8, \[pc\] ; .* <foo>
|
||||
0+010 <[^>]*> fd83 0500 stc2 5, cr0, \[r3\]
|
||||
0+014 <[^>]*> fdc0 f302 stc2l 3, cr15, \[r0, #8\]
|
||||
0+018 <[^>]*> fd8f 7100 stc2 1, cr7, \[pc\] ; .* <bar>
|
||||
0+01c <[^>]*> fe71 5212 mrc2 2, 3, r5, cr1, cr2, \{0\}
|
||||
0+020 <[^>]*> fe21 5711 mcr2 7, 1, r5, cr1, cr1, \{0\}
|
||||
0+024 <[^>]*> fc92 5502 ldc2 5, cr5, \[r2\], \{2\}
|
||||
0+028 <[^>]*> fc83 4603 stc2 6, cr4, \[r3\], \{3\}
|
||||
0+02c <[^>]*> fcd6 1c06 ldc2l 12, cr1, \[r6\], \{6\}
|
||||
0+030 <[^>]*> fcc7 0c07 stc2l 12, cr0, \[r7\], \{7\}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#source: copro-arm_v5teplus-thumb_v6t2plus.s
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: ARMv6T2 Thumb CoProcessor Instructions (3)
|
||||
#as: -march=armv6t2 -mthumb -EL
|
||||
|
||||
# Test the standard ARM co-processor instructions:
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+000 <[^>]*> ec50 7d04 mrrc 13, 0, r7, r0, cr4
|
||||
0+004 <[^>]*> ec40 7e05 mcrr 14, 0, r7, r0, cr5
|
||||
0+008 <[^>]*> ec50 7fff mrrc 15, 15, r7, r0, cr15
|
||||
0+00c <[^>]*> ec40 7efe mcrr 14, 15, r7, r0, cr14
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#source: copro-arm_v6plus-thumb_v6t2plus.s
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: ARMv6T2 Thumb CoProcessor Instructions (4)
|
||||
#as: -march=armv6t2 -mthumb -EL
|
||||
|
||||
# Test the standard ARM co-processor instructions:
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+000 <[^>]*> fc50 7d04 mrrc2 13, 0, r7, r0, cr4
|
||||
0+004 <[^>]*> fc40 7e05 mcrr2 14, 0, r7, r0, cr5
|
||||
0+008 <[^>]*> fc50 7fff mrrc2 15, 15, r7, r0, cr15
|
||||
0+00c <[^>]*> fc40 7efe mcrr2 14, 15, r7, r0, cr14
|
||||
Loading…
Reference in New Issue