NDS32/opcodes: Add audio ISA extension and modify the disassemble implemnt.
First, add nds32 audio ISA extension including opcodes and registers. Second, redesign the disassemble implement. The original disassemble decode instruction opcode using switch-case. It is hard to synchronize when adding new instructions. Therefore, the new implement reuses nds32_opcodes to dump the instructions.
This commit is contained in:
Kuan-Lin Chen
parent
5b636fed3a
commit
40c7a7cb74
@ -1,3 +1,7 @@
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2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
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* readelf.c (decode_NDS32_machine_flags): Display ABI2 FP+.
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2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
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Matthew Fortune <matthew.fortune@imgtec.com>
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@ -2326,7 +2326,8 @@ decode_NDS32_machine_flags (unsigned e_flags, char buf[], size_t size)
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"ABI v1", /* use r0 as return register */
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"ABI v2", /* use r0 as return register and don't reserve 24 bytes for arguments */
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"ABI v2fp", /* for FPU */
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"AABI"
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"AABI",
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"ABI2 FP+"
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};
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static const char *VER_STRINGS[] =
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{
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@ -2357,6 +2358,7 @@ decode_NDS32_machine_flags (unsigned e_flags, char buf[], size_t size)
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case E_NDS_ABI_V2:
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case E_NDS_ABI_V2FP:
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case E_NDS_ABI_AABI:
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case E_NDS_ABI_V2FP_PLUS:
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/* In case there are holes in the array. */
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r += snprintf (buf + r, size - r, ", %s", ABI_STRINGS[abi >> EF_NDS_ABI_SHIFT]);
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break;
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@ -1,3 +1,7 @@
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2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
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* nds32.h: Add new opcode declaration.
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2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
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Matthew Fortune <matthew.fortune@imgtec.com>
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@ -29,6 +29,7 @@
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#define REG_R16 16
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#define REG_R20 20
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#define REG_TA 15
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#define REG_TP 27
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#define REG_FP 28
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#define REG_GP 29
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#define REG_LP 30
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@ -358,12 +359,13 @@ enum n32_opcodes
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N32_ALU2_SUB_SC,
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N32_ALU2_ADD_WC,
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N32_ALU2_SUB_WC,
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N32_ALU2_0x14,
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N32_ALU2_KMxy,
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N32_ALU2_0x15,
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N32_ALU2_0x16,
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N32_ALU2_FFZMISM,
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N32_ALU2_QADD = 0x18,
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N32_ALU2_QSUB,
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N32_ALU2_KADD = 0x18,
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N32_ALU2_KSUB,
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N32_ALU2_KSLRA,
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N32_ALU2_MFUSR = 0x20,
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N32_ALU2_MTUSR,
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N32_ALU2_0x22,
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@ -459,7 +461,7 @@ enum n32_opcodes
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N32_MISC_TLBOP,
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N32_MISC_0xf,
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/* bit[0;4] */
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/* bit[0:4] */
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N32_SIMD_PBSAD = 0,
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N32_SIMD_PBSADA = 1,
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@ -1,3 +1,21 @@
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2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
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* nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
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keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
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keyword_aridxi): Add audio ISA extension.
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(keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
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keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
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keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
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for nds32-dis.c using.
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(build_opcode_syntax): Remove dead code.
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(parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
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parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
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parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
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operand parser.
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* nds32-asm.h: Declare.
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* nds32-dis.c: Use array nds32_opcodes to disassemble instead of
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decoding by switch.
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2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
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Matthew Fortune <matthew.fortune@imgtec.com>
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1990
opcodes/nds32-asm.c
1990
opcodes/nds32-asm.c
File diff suppressed because it is too large
Load Diff
@ -17,7 +17,7 @@
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA.*/
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02110-1301, USA. */
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#ifndef NDS32_ASM_H
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@ -70,7 +70,7 @@ enum
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NASM_ATTR_FPU_FMA = 0x0080000,
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NASM_ATTR_DXREG = 0x0100000,
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NASM_ATTR_BRANCH = 0x0200000,
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NASM_ATTR_RELAXABLE = 0x0400000,
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NASM_ATTR_SATURATION_EXT = 0x0400000,
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NASM_ATTR_PCREL = 0x0800000,
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NASM_ATTR_GPREL = 0x1000000,
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@ -83,6 +83,81 @@ enum
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NASM_ATTR_RDREG = 0x000100
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};
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enum
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{
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/* This is a field (operand) of just a separator char. */
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SYN_FIELD = 0x100,
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/* This operand is used for input or output. (define or use) */
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SYN_INPUT = 0x1000,
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SYN_OUTPUT = 0x2000,
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SYN_LOPT = 0x4000,
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SYN_ROPT = 0x8000,
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/* Hardware resources. */
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HW_GPR = 0,
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HW_USR,
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HW_DXR,
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HW_SR,
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HW_FSR,
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HW_FDR,
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HW_CP, /* Co-processor ID. */
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HW_CPR, /* Co-processor registers. */
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HW_ABDIM, /* [ab][di]m? flag for LSMWA?. */
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HW_ABM, /* [ab]m? flag for LSMWZB. */
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HW_DTITON,
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HW_DTITOFF,
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HW_DPREF_ST,
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HW_CCTL_ST0,
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HW_CCTL_ST1,
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HW_CCTL_ST2,
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HW_CCTL_ST3,
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HW_CCTL_ST4,
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HW_CCTL_ST5,
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HW_CCTL_LV,
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HW_TLBOP_ST,
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HW_STANDBY_ST,
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HW_MSYNC_ST,
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HW_AEXT_IM_I,
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HW_AEXT_IM_M,
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HW_AEXT_ACC,
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HW_AEXT_ARIDX,
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HW_AEXT_ARIDX2,
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HW_AEXT_ARIDXI,
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_HW_LAST,
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/* TODO: Maybe we should add a new type to distinguish address and
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const int. Only the former allows symbols and relocations. */
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HW_INT,
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HW_UINT
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};
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/* for audio-extension. */
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enum
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{
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N32_AEXT_AMADD = 0,
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N32_AEXT_AMSUB,
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N32_AEXT_AMULT,
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N32_AEXT_AMFAR,
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N32_AEXT_AMADDS,
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N32_AEXT_AMSUBS,
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N32_AEXT_AMULTS,
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N32_AEXT_AMNEGS,
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N32_AEXT_AADDL,
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N32_AEXT_AMTARI,
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N32_AEXT_AMAWBS = 0x0c,
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N32_AEXT_AMAWTS,
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N32_AEXT_AMWBS,
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N32_AEXT_AMWTS,
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N32_AEXT_AMABBS,
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N32_AEXT_AMABTS,
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N32_AEXT_AMATBS,
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N32_AEXT_AMATTS,
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N32_AEXT_AMBBS,
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N32_AEXT_AMBTS,
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N32_AEXT_AMTBS,
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N32_AEXT_AMTTS
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};
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/* Macro for instruction attribute. */
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#define ATTR(attr) NASM_ATTR_ ## attr
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#define ATTR_NONE 0
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@ -131,6 +206,7 @@ typedef struct nds32_opcode
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int variant;
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/* Next form of the same mnemonic. */
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struct nds32_opcode *next;
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/* TODO: Extra constrains and verification.
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For example, `mov55 $sp, $sp' is not allowed in v3. */
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} opcode_t;
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@ -187,4 +263,35 @@ typedef struct nds32_field
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extern void nds32_assemble (nds32_asm_desc_t *, nds32_asm_insn_t *, char *);
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extern void nds32_asm_init (nds32_asm_desc_t *, int);
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#define OP6(op6) (N32_OP6_ ## op6 << 25)
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#define LSMW(sub) (OP6 (LSMW) | N32_LSMW_ ## sub)
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#define JREG(sub) (OP6 (JREG) | N32_JREG_ ## sub)
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#define JREG_RET (1 << 5)
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#define JREG_IFC (1 << 6)
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#define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16))
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#define SIMD(sub) (OP6 (SIMD) | N32_SIMD_ ## sub)
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#define ALU1(sub) (OP6 (ALU1) | N32_ALU1_ ## sub)
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#define ALU2(sub) (OP6 (ALU2) | N32_ALU2_ ## sub)
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#define MISC(sub) (OP6 (MISC) | N32_MISC_ ## sub)
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#define MEM(sub) (OP6 (MEM) | N32_MEM_ ## sub)
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#define FPU_RA_IMMBI(sub) (OP6 (sub) | __BIT (12))
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#define FS1(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_ ## sub << 6))
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#define FS1_F2OP(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_F2OP << 6) \
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| (N32_FPU_FS1_F2OP_ ## sub << 10))
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#define FS2(sub) (OP6 (COP) | N32_FPU_FS2 | (N32_FPU_FS2_ ## sub << 6))
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#define FD1(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_ ## sub << 6))
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#define FD1_F2OP(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_F2OP << 6) \
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| (N32_FPU_FD1_F2OP_ ## sub << 10))
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#define FD2(sub) (OP6 (COP) | N32_FPU_FD2 | (N32_FPU_FD2_ ## sub << 6))
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#define MFCP(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_ ## sub << 6))
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#define MFCP_XR(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_XR << 6) \
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| (N32_FPU_MFCP_XR_ ## sub << 10))
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#define MTCP(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_ ## sub << 6))
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#define MTCP_XR(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_XR << 6) \
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| (N32_FPU_MTCP_XR_ ## sub << 10))
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#define FPU_MEM(sub) (OP6 (COP) | N32_FPU_ ## sub)
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#define FPU_MEMBI(sub) (OP6 (COP) | N32_FPU_ ## sub | 0x1 << 7)
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#define AUDIO(sub) (OP6 (AEXT) | (N32_AEXT_ ## sub << 20))
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#endif
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2072
opcodes/nds32-dis.c
2072
opcodes/nds32-dis.c
File diff suppressed because it is too large
Load Diff
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