2000-05-25 Alexandre Oliva <aoliva@cygnus.com>
* m10300-dis.c (disassemble): Negate negative accumulator's shift. 2000-05-24 Alexandre Oliva <aoliva@cygnus.com> * m10300-dis.c (disassemble, case FSREG, FDREG): Don't assume 32-bit longs when sign-extending operands. 2000-04-20 Alexandre Oliva <aoliva@cygnus.com> * m10300-opc.c: Remove MN10300_OPERAND_RELAX from all FSREGs. * m10300-dis.c (HAVE_AM33_2): Define. (disassemble): Use it. (HAVE_AM33): Redefine. (print_insn_mn10300): Fix mask for 5-byte extended insns. 2000-04-01 Alexandre Oliva <aoliva@cygnus.com> * m10300-opc.c: Renamed AM332 to AM33_2. 2000-03-31 Alexandre Oliva <aoliva@cygnus.com> * m10300-opc.c: Defined AM33 2.0 register operands. Added support for AM33 2.0 `imm8,(abs16)' addressing mode for btst, bset and bclr. Implemented `fbCC', `flCC', `dcpf' and all FP insns. * m10300-dis.c (print_insn_mn10300): Recognize 5byte extended insn code of AM33 2.0. (disassemble): Recognize FMT_D3. Print out FP register names.
This commit is contained in:
Alexandre Oliva
parent
b08fa4d3bf
commit
40fa02078b
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@ -1,3 +1,26 @@
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2003-07-09 Alexandre Oliva <aoliva@redhat.com>
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2000-05-25 Alexandre Oliva <aoliva@cygnus.com>
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* m10300-dis.c (disassemble): Negate negative accumulator's shift.
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2000-05-24 Alexandre Oliva <aoliva@cygnus.com>
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* m10300-dis.c (disassemble, case FSREG, FDREG): Don't assume
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32-bit longs when sign-extending operands.
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2000-04-20 Alexandre Oliva <aoliva@cygnus.com>
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* m10300-opc.c: Remove MN10300_OPERAND_RELAX from all FSREGs.
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* m10300-dis.c (HAVE_AM33_2): Define.
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(disassemble): Use it.
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(HAVE_AM33): Redefine.
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(print_insn_mn10300): Fix mask for 5-byte extended insns.
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2000-04-01 Alexandre Oliva <aoliva@cygnus.com>
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* m10300-opc.c: Renamed AM332 to AM33_2.
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2000-03-31 Alexandre Oliva <aoliva@cygnus.com>
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* m10300-opc.c: Defined AM33 2.0 register operands. Added support
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for AM33 2.0 `imm8,(abs16)' addressing mode for btst, bset and
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bclr. Implemented `fbCC', `flCC', `dcpf' and all FP insns.
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* m10300-dis.c (print_insn_mn10300): Recognize 5byte extended
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insn code of AM33 2.0.
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(disassemble): Recognize FMT_D3. Print out FP register names.
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2003-07-09 Chris Demetriou <cgd@broadcom.com>
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* mips-dis.c (set_default_mips_dis_options): Get BFD from
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@ -26,7 +26,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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static void disassemble PARAMS ((bfd_vma, struct disassemble_info *,
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unsigned long insn, unsigned int));
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#define HAVE_AM33 (info->mach == AM33)
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#define HAVE_AM33_2 (info->mach == AM33_2)
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#define HAVE_AM33 (info->mach == AM33 || HAVE_AM33_2)
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#define HAVE_AM30 (info->mach == AM30)
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int
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@ -200,6 +201,9 @@ print_insn_mn10300 (memaddr, info)
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insn = bfd_getb32 (buffer);
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consume = 7;
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/* Handle the 5-byte extended instruction codes. */
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if ((insn & 0xfff80000) == 0xfe800000)
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consume = 5;
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}
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disassemble (memaddr, info, insn, consume);
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@ -237,6 +241,8 @@ disassemble (memaddr, info, insn, size)
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mysize = 5;
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else if (op->format == FMT_D2)
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mysize = 4;
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else if (op->format == FMT_D3)
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mysize = 5;
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else if (op->format == FMT_D4)
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mysize = 6;
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else if (op->format == FMT_D6)
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@ -253,6 +259,7 @@ disassemble (memaddr, info, insn, size)
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if ((op->mask & insn) == op->opcode
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&& size == (unsigned int) mysize
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&& (op->machine == 0
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|| (op->machine == AM33_2 && HAVE_AM33_2)
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|| (op->machine == AM33 && HAVE_AM33)
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|| (op->machine == AM30 && HAVE_AM30)))
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{
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@ -343,6 +350,25 @@ disassemble (memaddr, info, insn, size)
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insn |= (temp & 0xffffff00) >> 8;
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extension = temp & 0xff;
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}
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else if (size == 5 && op->format == FMT_D3)
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{
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status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return;
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}
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insn &= 0xffff0000;
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insn |= bfd_getl16 (buffer);
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status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return;
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}
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extension = *(unsigned char *) buffer;
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}
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else if (size == 5)
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{
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unsigned long temp = 0;
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@ -498,6 +524,52 @@ disassemble (memaddr, info, insn, size)
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if ((operand->flags & MN10300_OPERAND_SIGNED) != 0)
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value = ((value & 0xffffff) ^ 0x800000) - 0x800000;
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}
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else if ((operand->flags & (MN10300_OPERAND_FSREG
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| MN10300_OPERAND_FDREG)))
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{
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/* See m10300-opc.c just before #define FSM0 for an
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explanation of these variables. Note that
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FMT-implied shifts are not taken into account for
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FP registers. */
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unsigned long mask_low, mask_high;
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int shl_low, shr_high, shl_high;
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switch (operand->bits)
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{
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case 5:
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/* Handle regular FP registers. */
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if (operand->shift >= 0)
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{
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/* This is an `m' register. */
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shl_low = operand->shift;
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shl_high = 8 + (8 & shl_low) + (shl_low & 4) / 4;
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}
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else
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{
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/* This is an `n' register. */
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shl_low = -operand->shift;
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shl_high = shl_low / 4;
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}
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mask_low = 0x0f;
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mask_high = 0x10;
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shr_high = 4;
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break;
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case 3:
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/* Handle accumulators. */
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shl_low = -operand->shift;
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shl_high = 0;
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mask_low = 0x03;
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mask_high = 0x04;
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shr_high = 2;
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break;
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default:
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abort ();
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}
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value = ((((insn >> shl_high) << shr_high) & mask_high)
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| ((insn >> shl_low) & mask_low));
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}
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else if ((operand->flags & MN10300_OPERAND_EXTENDED) != 0)
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{
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value = ((extension >> (operand->shift))
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@ -567,6 +639,15 @@ disassemble (memaddr, info, insn, size)
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(*info->fprintf_func) (info->stream, "xr%d", (int) value);
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}
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else if ((operand->flags & MN10300_OPERAND_FSREG) != 0)
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(*info->fprintf_func) (info->stream, "fs%d", (int) value);
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else if ((operand->flags & MN10300_OPERAND_FDREG) != 0)
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(*info->fprintf_func) (info->stream, "fd%d", (int) value);
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else if ((operand->flags & MN10300_OPERAND_FPCR) != 0)
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(*info->fprintf_func) (info->stream, "fpcr");
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else if ((operand->flags & MN10300_OPERAND_USP) != 0)
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(*info->fprintf_func) (info->stream, "usp");
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@ -338,6 +338,85 @@ const struct mn10300_operand mn10300_operands[] = {
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#define SIMM4_6 (SIMM4_2+1)
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{4, 12, MN10300_OPERAND_SIGNED},
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#define FPCR (SIMM4_6+1)
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{0, 0, MN10300_OPERAND_FPCR},
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/* We call f[sd]m registers those whose most significant bit is stored
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* within the opcode half-word, i.e., in a bit on the left of the 4
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* least significant bits, and f[sd]n registers those whose most
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* significant bit is stored at the end of the full word, after the 4
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* least significant bits. They're not numbered after their position
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* in the mnemonic asm instruction, but after their position in the
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* opcode word, i.e., depending on the amount of shift they need.
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*
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* The additional bit is shifted as follows: for `n' registers, it
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* will be shifted by (|shift|/4); for `m' registers, it will be
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* shifted by (8+(8&shift)+(shift&4)/4); for accumulator, whose
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* specifications are only 3-bits long, the two least-significant bits
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* are shifted by 16, and the most-significant bit is shifted by -2
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* (i.e., it's stored in the least significant bit of the full
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* word). */
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/* fsm register in the first register operand position. */
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#define FSM0 (FPCR+1)
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{5, 0, MN10300_OPERAND_FSREG },
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/* fsm register in the second register operand position. */
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#define FSM1 (FSM0+1)
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{5, 4, MN10300_OPERAND_FSREG },
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/* fsm register in the third register operand position. */
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#define FSM2 (FSM1+1)
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{5, 8, MN10300_OPERAND_FSREG },
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/* fsm register in the fourth register operand position. */
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#define FSM3 (FSM2+1)
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{5, 12, MN10300_OPERAND_FSREG },
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/* fsn register in the first register operand position. */
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#define FSN1 (FSM3+1)
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{5, -4, MN10300_OPERAND_FSREG },
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/* fsn register in the second register operand position. */
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#define FSN2 (FSN1+1)
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{5, -8, MN10300_OPERAND_FSREG },
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/* fsm register in the third register operand position. */
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#define FSN3 (FSN2+1)
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{5, -12, MN10300_OPERAND_FSREG },
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/* fsm accumulator, in the fourth register operand position. */
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#define FSACC (FSN3+1)
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{3, -16, MN10300_OPERAND_FSREG },
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/* fdm register in the first register operand position. */
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#define FDM0 (FSACC+1)
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{5, 0, MN10300_OPERAND_FDREG },
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/* fdm register in the second register operand position. */
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#define FDM1 (FDM0+1)
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{5, 4, MN10300_OPERAND_FDREG },
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/* fdm register in the third register operand position. */
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#define FDM2 (FDM1+1)
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{5, 8, MN10300_OPERAND_FDREG },
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/* fdm register in the fourth register operand position. */
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#define FDM3 (FDM2+1)
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{5, 12, MN10300_OPERAND_FDREG },
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/* fdn register in the first register operand position. */
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#define FDN1 (FDM3+1)
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{5, -4, MN10300_OPERAND_FDREG },
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/* fdn register in the second register operand position. */
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#define FDN2 (FDN1+1)
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{5, -8, MN10300_OPERAND_FDREG },
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/* fdn register in the third register operand position. */
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#define FDN3 (FDN2+1)
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{5, -12, MN10300_OPERAND_FDREG },
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} ;
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#define MEM(ADDR) PAREN, ADDR, PAREN
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@ -810,14 +889,17 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "btst", 0xfbe90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
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{ "btst", 0xfde90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
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{ "btst", 0xfee90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
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{ "btst", 0xfe820000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
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{ "btst", 0xfe020000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}},
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{ "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
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{ "bset", 0xf080, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
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{ "bset", 0xfe800000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
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{ "bset", 0xfe000000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}},
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{ "bset", 0xfaf00000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
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{ "bclr", 0xf090, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
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{ "bclr", 0xfe810000, 0xffff0000, 0, FMT_D3, AM33_2, {IMM8E, MEM(IMM16_MEM)}},
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{ "bclr", 0xfe010000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}},
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{ "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
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@ -889,6 +971,36 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "lra", 0xda, 0xff, 0, FMT_S0, 0, {UNUSED}},
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{ "setlb", 0xdb, 0xff, 0, FMT_S0, 0, {UNUSED}},
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{ "fbeq", 0xf8d000, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fbne", 0xf8d100, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fbgt", 0xf8d200, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fbge", 0xf8d300, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fblt", 0xf8d400, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fble", 0xf8d500, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fbuo", 0xf8d600, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fblg", 0xf8d700, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fbleg", 0xf8d800, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fbug", 0xf8d900, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fbuge", 0xf8da00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fbul", 0xf8db00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fbule", 0xf8dc00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fbue", 0xf8dd00, 0xffff00, 0, FMT_D1, AM33_2, {SD8N_PCREL}},
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{ "fleq", 0xf0d0, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "flne", 0xf0d1, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "flgt", 0xf0d2, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "flge", 0xf0d3, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "fllt", 0xf0d4, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "flle", 0xf0d5, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "fluo", 0xf0d6, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "fllg", 0xf0d7, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "flleg", 0xf0d8, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "flug", 0xf0d9, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "fluge", 0xf0da, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "flul", 0xf0db, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "flule", 0xf0dc, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "flue", 0xf0dd, 0xffff, 0, FMT_D0, AM33_2, {UNUSED}},
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{ "jmp", 0xf0f4, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}},
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{ "jmp", 0xcc0000, 0xff0000, 0, FMT_S2, 0, {IMM16_PCREL}},
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{ "jmp", 0xdc000000, 0xff000000, 0, FMT_S4, 0, {IMM32_HIGH24}},
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@ -906,6 +1018,141 @@ const struct mn10300_opcode mn10300_opcodes[] = {
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{ "rtm", 0xf0ff, 0xffff, 0, FMT_D0, 0, {UNUSED}},
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{ "nop", 0xcb, 0xff, 0, FMT_S0, 0, {UNUSED}},
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{ "dcpf", 0xf9a600, 0xffff0f, 0, FMT_D6, AM33_2, {MEM (RM2)}},
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{ "dcpf", 0xf9a700, 0xffffff, 0, FMT_D6, AM33_2, {MEM (SP)}},
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{ "dcpf", 0xfba60000, 0xffff00ff, 0, FMT_D7, AM33_2, {MEM2 (RI,RM0)}},
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{ "dcpf", 0xfba70000, 0xffff0f00, 0, FMT_D7, AM33_2, {MEM2 (SD8,RM2)}},
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{ "dcpf", 0xfda70000, 0xffff0f00, 0, FMT_D8, AM33_2, {MEM2 (SD24,RM2)}},
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{ "dcpf", 0xfe460000, 0xffff0f00, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8,RM2)}},
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{ "fmov", 0xf92000, 0xfffe00, 0, FMT_D6, AM33_2, {MEM (RM2), FSM0}},
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{ "fmov", 0xf92200, 0xfffe00, 0, FMT_D6, AM33_2, {MEMINC (RM2), FSM0}},
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{ "fmov", 0xf92400, 0xfffef0, 0, FMT_D6, AM33_2, {MEM (SP), FSM0}},
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{ "fmov", 0xf92600, 0xfffe00, 0, FMT_D6, AM33_2, {RM2, FSM0}},
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{ "fmov", 0xf93000, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, MEM (RM0)}},
|
||||
{ "fmov", 0xf93100, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, MEMINC (RM0)}},
|
||||
{ "fmov", 0xf93400, 0xfffd0f, 0, FMT_D6, AM33_2, {FSM1, MEM (SP)}},
|
||||
{ "fmov", 0xf93500, 0xfffd00, 0, FMT_D6, AM33_2, {FSM1, RM0}},
|
||||
{ "fmov", 0xf94000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}},
|
||||
{ "fmov", 0xf9a000, 0xfffe01, 0, FMT_D6, AM33_2, {MEM (RM2), FDM0}},
|
||||
{ "fmov", 0xf9a200, 0xfffe01, 0, FMT_D6, AM33_2, {MEMINC (RM2), FDM0}},
|
||||
{ "fmov", 0xf9a400, 0xfffef1, 0, FMT_D6, AM33_2, {MEM (SP), FDM0}},
|
||||
{ "fmov", 0xf9b000, 0xfffd10, 0, FMT_D6, AM33_2, {FDM1, MEM (RM0)}},
|
||||
{ "fmov", 0xf9b100, 0xfffd10, 0, FMT_D6, AM33_2, {FDM1, MEMINC (RM0)}},
|
||||
{ "fmov", 0xf9b400, 0xfffd1f, 0, FMT_D6, AM33_2, {FDM1, MEM (SP)}},
|
||||
{ "fmov", 0xf9b500, 0xffff0f, 0, FMT_D6, AM33_2, {RM2, FPCR}},
|
||||
{ "fmov", 0xf9b700, 0xfffff0, 0, FMT_D6, AM33_2, {FPCR, RM0}},
|
||||
{ "fmov", 0xf9c000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}},
|
||||
{ "fmov", 0xfb200000, 0xfffe0000, 0, FMT_D7, AM33_2, {MEM2 (SD8, RM2), FSM2}},
|
||||
{ "fmov", 0xfb220000, 0xfffe0000, 0, FMT_D7, AM33_2, {MEMINC2 (RM2, SIMM8), FSM2}},
|
||||
{ "fmov", 0xfb240000, 0xfffef000, 0, FMT_D7, AM33_2, {MEM2 (IMM8, SP), FSM2}},
|
||||
{ "fmov", 0xfb270000, 0xffff000d, 0, FMT_D7, AM33_2, {MEM2 (RI, RM0), FSN1}},
|
||||
{ "fmov", 0xfb300000, 0xfffd0000, 0, FMT_D7, AM33_2, {FSM3, MEM2 (SD8, RM0)}},
|
||||
{ "fmov", 0xfb310000, 0xfffd0000, 0, FMT_D7, AM33_2, {FSM3, MEMINC2 (RM0, SIMM8)}},
|
||||
{ "fmov", 0xfb340000, 0xfffd0f00, 0, FMT_D7, AM33_2, {FSM3, MEM2 (IMM8, SP)}},
|
||||
{ "fmov", 0xfb370000, 0xffff000d, 0, FMT_D7, AM33_2, {FSN1, MEM2(RI, RM0)}},
|
||||
/* FIXME: the spec doesn't say the fd register must be even for the
|
||||
* next two insns. Assuming it was a mistake in the spec. */
|
||||
{ "fmov", 0xfb470000, 0xffff001d, 0, FMT_D7, AM33_2, {MEM2 (RI, RM0), FDN1}},
|
||||
{ "fmov", 0xfb570000, 0xffff001d, 0, FMT_D7, AM33_2, {FDN1, MEM2(RI, RM0)}},
|
||||
/* END of FIXME */
|
||||
{ "fmov", 0xfba00000, 0xfffe0100, 0, FMT_D7, AM33_2, {MEM2 (SD8, RM2), FDM2}},
|
||||
{ "fmov", 0xfba20000, 0xfffe0100, 0, FMT_D7, AM33_2, {MEMINC2 (RM2, SIMM8), FDM2}},
|
||||
{ "fmov", 0xfba40000, 0xfffef100, 0, FMT_D7, AM33_2, {MEM2 (IMM8, SP), FDM2}},
|
||||
{ "fmov", 0xfbb00000, 0xfffd1000, 0, FMT_D7, AM33_2, {FDM3, MEM2 (SD8, RM0)}},
|
||||
{ "fmov", 0xfbb10000, 0xfffd1000, 0, FMT_D7, AM33_2, {FDM3, MEMINC2 (RM0, SIMM8)}},
|
||||
{ "fmov", 0xfbb40000, 0xfffd1f00, 0, FMT_D7, AM33_2, {FDM3, MEM2 (IMM8, SP)}},
|
||||
{ "fmov", 0xfd200000, 0xfffe0000, 0, FMT_D8, AM33_2, {MEM2 (SIMM24, RM2), FSM2}},
|
||||
{ "fmov", 0xfd220000, 0xfffe0000, 0, FMT_D8, AM33_2, {MEMINC2 (RM2, SIMM24), FSM2}},
|
||||
{ "fmov", 0xfd240000, 0xfffef000, 0, FMT_D8, AM33_2, {MEM2 (IMM24, SP), FSM2}},
|
||||
{ "fmov", 0xfd300000, 0xfffd0000, 0, FMT_D8, AM33_2, {FSM3, MEM2 (SIMM24, RM0)}},
|
||||
{ "fmov", 0xfd310000, 0xfffd0000, 0, FMT_D8, AM33_2, {FSM3, MEMINC2 (RM0, SIMM24)}},
|
||||
{ "fmov", 0xfd340000, 0xfffd0f00, 0, FMT_D8, AM33_2, {FSM3, MEM2 (IMM24, SP)}},
|
||||
{ "fmov", 0xfda00000, 0xfffe0100, 0, FMT_D8, AM33_2, {MEM2 (SIMM24, RM2), FDM2}},
|
||||
{ "fmov", 0xfda20000, 0xfffe0100, 0, FMT_D8, AM33_2, {MEMINC2 (RM2, SIMM24), FDM2}},
|
||||
{ "fmov", 0xfda40000, 0xfffef100, 0, FMT_D8, AM33_2, {MEM2 (IMM24, SP), FDM2}},
|
||||
{ "fmov", 0xfdb00000, 0xfffd1000, 0, FMT_D8, AM33_2, {FDM3, MEM2 (SIMM24, RM0)}},
|
||||
{ "fmov", 0xfdb10000, 0xfffd1000, 0, FMT_D8, AM33_2, {FDM3, MEMINC2 (RM0, SIMM24)}},
|
||||
{ "fmov", 0xfdb40000, 0xfffd1f00, 0, FMT_D8, AM33_2, {FDM3, MEM2 (IMM24, SP)}},
|
||||
{ "fmov", 0xfdb50000, 0xffff0000, 0, FMT_D4, AM33_2, {IMM32, FPCR}},
|
||||
{ "fmov", 0xfe200000, 0xfffe0000, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, RM2), FSM2}},
|
||||
{ "fmov", 0xfe220000, 0xfffe0000, 0, FMT_D9, AM33_2, {MEMINC2 (RM2, IMM32_HIGH8), FSM2}},
|
||||
{ "fmov", 0xfe240000, 0xfffef000, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, SP), FSM2}},
|
||||
{ "fmov", 0xfe260000, 0xfffef000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM2}},
|
||||
{ "fmov", 0xfe300000, 0xfffd0000, 0, FMT_D9, AM33_2, {FSM3, MEM2 (IMM32_HIGH8, RM0)}},
|
||||
{ "fmov", 0xfe310000, 0xfffd0000, 0, FMT_D9, AM33_2, {FSM3, MEMINC2 (RM0, IMM32_HIGH8)}},
|
||||
{ "fmov", 0xfe340000, 0xfffd0f00, 0, FMT_D9, AM33_2, {FSM3, MEM2 (IMM32_HIGH8, SP)}},
|
||||
{ "fmov", 0xfe400000, 0xfffe0100, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, RM2), FDM2}},
|
||||
{ "fmov", 0xfe420000, 0xfffe0100, 0, FMT_D9, AM33_2, {MEMINC2 (RM2, IMM32_HIGH8), FDM2}},
|
||||
{ "fmov", 0xfe440000, 0xfffef100, 0, FMT_D9, AM33_2, {MEM2 (IMM32_HIGH8, SP), FDM2}},
|
||||
{ "fmov", 0xfe500000, 0xfffd1000, 0, FMT_D9, AM33_2, {FDM3, MEM2 (IMM32_HIGH8, RM0)}},
|
||||
{ "fmov", 0xfe510000, 0xfffd1000, 0, FMT_D9, AM33_2, {FDM3, MEMINC2 (RM0, IMM32_HIGH8)}},
|
||||
{ "fmov", 0xfe540000, 0xfffd1f00, 0, FMT_D9, AM33_2, {FDM3, MEM2 (IMM32_HIGH8, SP)}},
|
||||
|
||||
/* FIXME: these are documented in the instruction bitmap, but not in
|
||||
* the instruction manual. */
|
||||
{ "ftoi", 0xfb400000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}},
|
||||
{ "itof", 0xfb420000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}},
|
||||
{ "ftod", 0xfb520000, 0xffff0f15, 0, FMT_D10,AM33_2, {FSN3, FDN1}},
|
||||
{ "dtof", 0xfb560000, 0xffff1f05, 0, FMT_D10,AM33_2, {FDN3, FSN1}},
|
||||
/* END of FIXME */
|
||||
|
||||
{ "fabs", 0xfb440000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}},
|
||||
{ "fabs", 0xfbc40000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}},
|
||||
{ "fabs", 0xf94400, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}},
|
||||
{ "fabs", 0xf9c400, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}},
|
||||
|
||||
{ "fneg", 0xfb460000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}},
|
||||
{ "fneg", 0xfbc60000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}},
|
||||
{ "fneg", 0xf94600, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}},
|
||||
{ "fneg", 0xf9c600, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}},
|
||||
|
||||
{ "frsqrt", 0xfb500000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}},
|
||||
{ "frsqrt", 0xfbd00000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}},
|
||||
{ "frsqrt", 0xf95000, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}},
|
||||
{ "frsqrt", 0xf9d000, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}},
|
||||
|
||||
/* FIXME: this is documented in the instruction bitmap, but not in
|
||||
* the instruction manual. */
|
||||
{ "fsqrt", 0xfb540000, 0xffff0f05, 0, FMT_D10,AM33_2, {FSN3, FSN1}},
|
||||
{ "fsqrt", 0xfbd40000, 0xffff1f15, 0, FMT_D10,AM33_2, {FDN3, FDN1}},
|
||||
{ "fsqrt", 0xf95200, 0xfffef0, 0, FMT_D6, AM33_2, {FSM0}},
|
||||
{ "fsqrt", 0xf9d200, 0xfffef1, 0, FMT_D6, AM33_2, {FDM0}},
|
||||
/* END of FIXME */
|
||||
|
||||
{ "fcmp", 0xf95400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}},
|
||||
{ "fcmp", 0xf9d400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}},
|
||||
{ "fcmp", 0xfe350000, 0xfffd0f00, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3}},
|
||||
|
||||
{ "fadd", 0xfb600000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}},
|
||||
{ "fadd", 0xfbe00000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}},
|
||||
{ "fadd", 0xf96000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}},
|
||||
{ "fadd", 0xf9e000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}},
|
||||
{ "fadd", 0xfe600000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}},
|
||||
|
||||
{ "fsub", 0xfb640000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}},
|
||||
{ "fsub", 0xfbe40000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}},
|
||||
{ "fsub", 0xf96400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}},
|
||||
{ "fsub", 0xf9e400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}},
|
||||
{ "fsub", 0xfe640000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}},
|
||||
|
||||
{ "fmul", 0xfb700000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}},
|
||||
{ "fmul", 0xfbf00000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}},
|
||||
{ "fmul", 0xf97000, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}},
|
||||
{ "fmul", 0xf9f000, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}},
|
||||
{ "fmul", 0xfe700000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}},
|
||||
|
||||
{ "fdiv", 0xfb740000, 0xffff0001, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1}},
|
||||
{ "fdiv", 0xfbf40000, 0xffff1111, 0, FMT_D10,AM33_2, {FDN3, FDN2, FDN1}},
|
||||
{ "fdiv", 0xf97400, 0xfffc00, 0, FMT_D6, AM33_2, {FSM1, FSM0}},
|
||||
{ "fdiv", 0xf9f400, 0xfffc11, 0, FMT_D6, AM33_2, {FDM1, FDM0}},
|
||||
{ "fdiv", 0xfe740000, 0xfffc0000, 0, FMT_D9, AM33_2, {IMM32_HIGH8, FSM3, FSM2}},
|
||||
|
||||
{ "fmadd", 0xfb800000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
|
||||
{ "fmsub", 0xfb840000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
|
||||
{ "fnmadd", 0xfb900000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
|
||||
{ "fnmsub", 0xfb940000, 0xfffc0000, 0, FMT_D10,AM33_2, {FSN3, FSN2, FSN1, FSACC}},
|
||||
|
||||
/* UDF instructions. */
|
||||
{ "udf00", 0xf600, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
||||
{ "udf00", 0xf90000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
||||
|
|
|
|||
Loading…
Reference in New Issue