OpenE2K/binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

gas:

Browse Source 
* config/tc-arm.c (enum operand_parse_code): Add OP_RIWC_RIWG.
	(parse_operands): Handle it.
	(insns): Use it for tmcr and tmrc.

gas/testsuite:
	* gas/arm/iwmmxt.s: Test tmcr and tmrc with wcgr registers.
	* gas/arm/iwmmxt.d: Update.
This commit is contained in:
Joseph Myers 2006-08-03 15:57:04 +00:00
parent 1675c14702
commit 41adaa5cab
5 changed files with 34 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gas/ChangeLog
View File

@ -1,3 +1,9 @@
2006-08-03 Joseph Myers <joseph@codesourcery.com>
* config/tc-arm.c (enum operand_parse_code): Add OP_RIWC_RIWG.
(parse_operands): Handle it.
(insns): Use it for tmcr and tmrc.
2006-08-02 Petr Salinger <Petr.Salinger@seznam.cz>
PR binutils/2983

20
gas/config/tc-arm.c
View File

@ -5370,6 +5370,7 @@ enum operand_parse_code
OP_RR_EXi, /* ARM register or expression with imm prefix */
OP_RF_IF, /* FPA register or immediate */
OP_RIWR_RIWC, /* iWMMXt R or C reg */
OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
/* Optional operands. */
OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
@ -5760,6 +5761,21 @@ parse_operands (char *str, const unsigned char *pattern)
}
break;
case OP_RIWC_RIWG:
{
struct reg_entry *rege = arm_reg_parse_multi (&str);
if (!rege
|| (rege->type != REG_TYPE_MMXWC
&& rege->type != REG_TYPE_MMXWCG))
{
inst.error = _("iWMMXt control register expected");
goto failure;
}
inst.operands[i].reg = rege->number;
inst.operands[i].isreg = 1;
}
break;
/* Misc */
case OP_CPSF: val = parse_cps_flags (&str); break;
case OP_ENDI: val = parse_endian_specifier (&str); break;
@ -15712,7 +15728,7 @@ static const struct asm_opcode insns[] =
cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd),
cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
@ -15723,7 +15739,7 @@ static const struct asm_opcode insns[] =
cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn),
cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),

5
gas/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2006-08-03 Joseph Myers <joseph@codesourcery.com>
* gas/arm/iwmmxt.s: Test tmcr and tmrc with wcgr registers.
* gas/arm/iwmmxt.d: Update.
2006-08-01 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/nops-2-i386.d: Updated.

4
gas/testsuite/gas/arm/iwmmxt.d
View File

@ -166,6 +166,6 @@ Disassembly of section .text:
0+278 <[^>]*> 0e9540ea[ ]+wunpckilweq[ ]+wr4, wr5, wr10
0+27c <[^>]*> 1e143005[ ]+wxorne[ ]+wr3, wr4, wr5
0+280 <[^>]*> ae377007[ ]+wandnge[ ]+wr7, wr7, wr7
0+284 <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\)
0+288 <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\)
0+284 <[^>]*> ee080110[ ]+tmcr[ ]+wcgr0, r0
0+288 <[^>]*> ee1a1110[ ]+tmrc[ ]+r1, wcgr2
0+28c <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\)

5
gas/testsuite/gas/arm/iwmmxt.s
View File

@ -203,7 +203,8 @@ iwmmxt:
wzeroge wr7
tmcr wcgr0, r0
tmrc r1, wcgr2
@ a.out-required section size padding
nop
nop
nop