[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES
I had mistakenly given all variants of the new SVE2 instructions pmull{t,b} a dependency on the feature +sve2-aes. Only the variant specifying .Q -> .D sizes should have that restriction. This patch fixes that mistake and updates the testsuite to have extra tests (matching the given set of tests per line in aarch64-tbl.h that the rest of the SVE2 tests follow). We also add a line in the documentation of the command line to clarify how to enable `pmull{t,b}` of this larger size. This is needed because all other instructions gated under the `sve2-aes` architecture extension are marked in the instruction documentation by an `HaveSVE2AES` check while pmull{t,b} is gated under the `HaveSVE2PMULL128` check. Regtested targeting aarch64-linux. gas/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests. * testsuite/gas/aarch64/illegal-sve2.l: Update tests. * doc/c-aarch64.texi: Add special note of pmull{t,b} instructions under the sve2-aes architecture extension. * testsuite/gas/aarch64/illegal-sve2.s: Add small size pmull{t,b} instructions. * testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b} disassembly. * testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b} instructions. include/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): sve_size_013 renamed to sve_size_13. opcodes/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-dis-2.c: Regenerate. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier. (OP_SVE_VVV_Q_D): Add new qualifier. (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier. (struct aarch64_opcode): Split pmull{t,b} into those requiring AES and those not.
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@ -1,3 +1,16 @@
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2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
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* testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests.
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* testsuite/gas/aarch64/illegal-sve2.l: Update tests.
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* doc/c-aarch64.texi: Add special note of pmull{t,b}
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instructions under the sve2-aes architecture extension.
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* testsuite/gas/aarch64/illegal-sve2.s: Add small size
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pmull{t,b} instructions.
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* testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b}
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disassembly.
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* testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b}
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instructions.
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2019-07-01 Nick Clifton <nickc@redhat.com>
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PR 24738
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@ -203,7 +203,8 @@ automatically cause those extensions to be disabled.
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@item @code{sve2-sm4} @tab ARMv8-A @tab No
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@tab Enable SVE2 SM4 Extension.
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@item @code{sve2-aes} @tab ARMv8-A @tab No
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@tab Enable SVE2 AES Extension.
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@tab Enable SVE2 AES Extension. This also enables the .Q->.B form of the
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@code{pmullt} and @code{pmullb} instructions.
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@item @code{sve2-sha3} @tab ARMv8-A @tab No
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@tab Enable SVE2 SHA3 Extension.
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@end multitable
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@ -12,9 +12,5 @@
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#error: [^ :]+:[0-9]+: Error: selected processor does not support `aesmc z0\.b,z0\.b'
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#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullb z17\.q,z21\.d,z27\.d'
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#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullb z0\.q,z0\.d,z0\.d'
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#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullb z0\.h,z0\.b,z0\.b'
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#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullb z0\.d,z0\.s,z0\.s'
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#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullt z17\.q,z21\.d,z27\.d'
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#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullt z0\.q,z0\.d,z0\.d'
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#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullt z0\.h,z0\.b,z0\.b'
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#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullt z0\.d,z0\.s,z0\.s'
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@ -756,18 +756,24 @@
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[^ :]+:[0-9]+: Error: operand mismatch -- `pmullb z0\.d,z0\.d,z0\.d'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: pmullb z0\.q, z0\.d, z0\.d
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: pmullb z0\.h, z0\.b, z0\.b
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[^ :]+:[0-9]+: Info: pmullb z0\.d, z0\.s, z0\.s
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[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullb z32\.h,z0\.b,z0\.b'
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[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullb z0\.h,z32\.b,z0\.b'
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[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullb z0\.h,z0\.b,z32\.b'
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[^ :]+:[0-9]+: Error: operand mismatch -- `pmullb z0\.b,z0\.b,z0\.b'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: pmullb z0\.q, z0\.d, z0\.d
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[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullt z32\.q,z0\.d,z0\.d'
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[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullt z0\.q,z32\.d,z0\.d'
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[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullt z0\.q,z0\.d,z32\.d'
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[^ :]+:[0-9]+: Error: operand mismatch -- `pmullt z0\.d,z0\.d,z0\.d'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: pmullt z0\.q, z0\.d, z0\.d
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: pmullt z0\.h, z0\.b, z0\.b
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[^ :]+:[0-9]+: Info: pmullt z0\.d, z0\.s, z0\.s
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[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullt z32\.h,z0\.b,z0\.b'
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[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullt z0\.h,z32\.b,z0\.b'
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[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullt z0\.h,z0\.b,z32\.b'
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[^ :]+:[0-9]+: Error: operand mismatch -- `pmullt z0\.b,z0\.b,z0\.b'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: pmullt z0\.q, z0\.d, z0\.d
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[^ :]+:[0-9]+: Error: operand mismatch -- `raddhnb z0\.h,z0\.h,z0\.h'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: raddhnb z0\.b, z0\.h, z0\.h
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@ -519,11 +519,21 @@ pmullb z0.q, z32.d, z0.d
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pmullb z0.q, z0.d, z32.d
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pmullb z0.d, z0.d, z0.d
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pmullb z32.h, z0.b, z0.b
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pmullb z0.h, z32.b, z0.b
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pmullb z0.h, z0.b, z32.b
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pmullb z0.b, z0.b, z0.b
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pmullt z32.q, z0.d, z0.d
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pmullt z0.q, z32.d, z0.d
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pmullt z0.q, z0.d, z32.d
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pmullt z0.d, z0.d, z0.d
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pmullt z32.h, z0.b, z0.b
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pmullt z0.h, z32.b, z0.b
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pmullt z0.h, z0.b, z32.b
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pmullt z0.b, z0.b, z0.b
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raddhnb z0.h, z0.h, z0.h
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raddhnb z32.b, z0.h, z0.h
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raddhnb z0.b, z32.h, z0.h
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@ -264,10 +264,12 @@ Disassembly of section \.text:
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*[0-9a-f]+: 04206400 pmul z0\.b, z0\.b, z0\.b
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*[0-9a-f]+: 451b6ab1 pmullb z17\.q, z21\.d, z27\.d
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*[0-9a-f]+: 45006800 pmullb z0\.q, z0\.d, z0\.d
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*[0-9a-f]+: 455b6ab1 pmullb z17\.h, z21\.b, z27\.b
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*[0-9a-f]+: 45406800 pmullb z0\.h, z0\.b, z0\.b
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*[0-9a-f]+: 45c06800 pmullb z0\.d, z0\.s, z0\.s
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*[0-9a-f]+: 451b6eb1 pmullt z17\.q, z21\.d, z27\.d
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*[0-9a-f]+: 45006c00 pmullt z0\.q, z0\.d, z0\.d
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*[0-9a-f]+: 455b6eb1 pmullt z17\.h, z21\.b, z27\.b
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*[0-9a-f]+: 45406c00 pmullt z0\.h, z0\.b, z0\.b
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*[0-9a-f]+: 45c06c00 pmullt z0\.d, z0\.s, z0\.s
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*[0-9a-f]+: 457b6ab1 raddhnb z17\.b, z21\.h, z27\.h
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@ -338,11 +338,15 @@ pmul z0.b, z0.b, z0.b
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pmullb z17.q, z21.d, z27.d
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pmullb z0.q, z0.d, z0.d
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pmullb z17.h, z21.b, z27.b
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pmullb z0.h, z0.b, z0.b
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pmullb z0.d, z0.s, z0.s
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pmullt z17.q, z21.d, z27.d
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pmullt z0.q, z0.d, z0.d
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pmullt z17.h, z21.b, z27.b
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pmullt z0.h, z0.b, z0.b
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pmullt z0.d, z0.s, z0.s
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@ -1,3 +1,8 @@
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2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
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* opcode/aarch64.h (enum aarch64_insn_class): sve_size_013
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renamed to sve_size_13.
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2019-06-19 Nick Alcock <nick.alcock@oracle.com>
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* ctf.h (ctf_slice_t): Make cts_offset and cts_bits unsigned
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@ -599,7 +599,7 @@ enum aarch64_insn_class
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sve_size_sd,
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sve_size_bh,
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sve_size_sd2,
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sve_size_013,
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sve_size_13,
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sve_shift_tsz_hsd,
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sve_shift_tsz_bhsd,
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sve_size_tsz_bhs,
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@ -1,3 +1,18 @@
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2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
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* aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
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sve_size_13 icode to account for variant behaviour of
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pmull{t,b}.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
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sve_size_13 icode to account for variant behaviour of
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pmull{t,b}.
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* aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
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(OP_SVE_VVV_Q_D): Add new qualifier.
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(OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
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(struct aarch64_opcode): Split pmull{t,b} into those requiring
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AES and those not.
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2019-07-01 Jan Beulich <jbeulich@suse.com>
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* opcodes/i386-gen.c (operand_type_init): Remove
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@ -1679,8 +1679,8 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
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0, 2, FLD_SVE_tszl_19, FLD_SVE_sz);
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break;
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case sve_size_013:
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variant = aarch64_get_variant (inst);
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case sve_size_13:
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variant = aarch64_get_variant (inst) + 1;
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if (variant == 2)
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variant = 3;
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insert_field (FLD_size, &inst->value, variant, 0);
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File diff suppressed because it is too large
Load Diff
@ -2822,14 +2822,11 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
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variant = i - 1;
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break;
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case sve_size_013:
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i = extract_field (FLD_size, inst->value, 0);
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if (i == 2)
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return FALSE;
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if (i == 3)
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variant = 2;
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else
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variant = i;
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case sve_size_13:
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/* Ignore low bit of this field since that is set in the opcode for
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instructions of this iclass. */
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i = (extract_field (FLD_size, inst->value, 0) & 2);
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variant = (i >> 1);
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break;
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case sve_shift_tsz_bhsd:
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@ -1958,15 +1958,18 @@
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{ \
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QLF3(S_S,S_S,S_S), \
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}
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#define OP_SVE_VVV_HD_BS \
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{ \
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QLF3(S_H,S_B,S_B), \
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QLF3(S_D,S_S,S_S), \
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}
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#define OP_SVE_VVV_S_B \
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{ \
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QLF3(S_S,S_B,S_B), \
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}
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#define OP_SVE_VVV_QHD_DBS \
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#define OP_SVE_VVV_Q_D \
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{ \
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QLF3(S_Q,S_D,S_D), \
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QLF3(S_H,S_B,S_B), \
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QLF3(S_D,S_S,S_S), \
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}
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#define OP_SVE_VVV_HSD_BHS \
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{ \
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@ -4673,6 +4676,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
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SVE2_INSNC ("nbsl", 0x04e03c00, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1),
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SVE2_INSN ("nmatch", 0x45208010, 0xffa0e010, sve_size_bh, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BH, 0, 0),
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SVE2_INSN ("pmul", 0x04206400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_BBB, 0, 0),
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SVE2_INSN ("pmullb", 0x45406800, 0xff60fc00, sve_size_13, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HD_BS, 0, 0),
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SVE2_INSN ("pmullt", 0x45406c00, 0xff60fc00, sve_size_13, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HD_BS, 0, 0),
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SVE2_INSN ("raddhnb", 0x45206800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0),
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SVE2_INSN ("raddhnt", 0x45206c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0),
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SVE2_INSN ("rshrnb", 0x45201800, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
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@ -4892,8 +4897,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
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SVE2AES_INSN ("aese", 0x4522e000, 0xfffffc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zn), OP_SVE_BBB, 0, 1),
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SVE2AES_INSN ("aesimc", 0x4520e400, 0xffffffe0, sve_misc, 0, OP2 (SVE_Zd, SVE_Zd), OP_SVE_BB, 0, 1),
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SVE2AES_INSN ("aesmc", 0x4520e000, 0xffffffe0, sve_misc, 0, OP2 (SVE_Zd, SVE_Zd), OP_SVE_BB, 0, 1),
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SVE2AES_INSN ("pmullb", 0x45006800, 0xff20fc00, sve_size_013, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_QHD_DBS, 0, 0),
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SVE2AES_INSN ("pmullt", 0x45006c00, 0xff20fc00, sve_size_013, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_QHD_DBS, 0, 0),
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SVE2AES_INSN ("pmullb", 0x45006800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_Q_D, 0, 0),
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SVE2AES_INSN ("pmullt", 0x45006c00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_Q_D, 0, 0),
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/* SVE2_SHA3 instructions. */
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SVE2SHA3_INSN ("rax1", 0x4520f400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0),
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/* SVE2_BITPERM instructions. */
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