2006-09-04 Paul Brook <paul@codesourcery.com>
gas/ * config/tc-arm.c (do_neon_dyadic_if_i): Remove. (do_neon_dyadic_if_i_d): Avoid setting U bit. (do_neon_mac_maybe_scalar): Ditto. (do_neon_dyadic_narrow): Force operand type to NT_integer. (insns): Remove out of date comments. gas/testsuite/ * gas/arm/neon-cov.s: Test .u and .s aliases for .i suffixes. * gas/arm/neon-cov.d: Adjust expected output. opcodes/ * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
This commit is contained in:
parent
91bb255c67
commit
428e3f1f4e
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@ -1,3 +1,11 @@
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2006-09-04 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (do_neon_dyadic_if_i): Remove.
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(do_neon_dyadic_if_i_d): Avoid setting U bit.
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(do_neon_mac_maybe_scalar): Ditto.
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(do_neon_dyadic_narrow): Force operand type to NT_integer.
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(insns): Remove out of date comments.
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2006-08-29 Nick Clifton <nickc@redhat.com>
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2006-08-29 Nick Clifton <nickc@redhat.com>
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* read.c (s_align): Initialize the 'stopc' variable to prevent
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* read.c (s_align): Initialize the 'stopc' variable to prevent
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@ -11617,16 +11617,12 @@ do_neon_dyadic_if_su_d (void)
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neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
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neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
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}
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}
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static void
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do_neon_dyadic_if_i (void)
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{
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neon_dyadic_misc (NT_unsigned, N_IF_32, 0);
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}
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static void
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static void
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do_neon_dyadic_if_i_d (void)
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do_neon_dyadic_if_i_d (void)
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{
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{
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neon_dyadic_misc (NT_unsigned, N_IF_32, 0);
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/* The "untyped" case can't happen. Do this to stop the "U" bit being
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affected if we specify unsigned args. */
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neon_dyadic_misc (NT_untyped, N_IF_32, 0);
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}
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}
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enum vfp_or_neon_is_neon_bits
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enum vfp_or_neon_is_neon_bits
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@ -11841,7 +11837,11 @@ do_neon_mac_maybe_scalar (void)
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neon_mul_mac (et, neon_quad (rs));
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neon_mul_mac (et, neon_quad (rs));
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}
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}
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else
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else
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do_neon_dyadic_if_i ();
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{
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/* The "untyped" case can't happen. Do this to stop the "U" bit being
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affected if we specify unsigned args. */
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neon_dyadic_misc (NT_untyped, N_IF_32, 0);
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}
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}
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}
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static void
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static void
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@ -12492,6 +12492,9 @@ do_neon_dyadic_narrow (void)
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{
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{
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struct neon_type_el et = neon_check_type (3, NS_QDD,
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struct neon_type_el et = neon_check_type (3, NS_QDD,
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N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
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N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
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/* Operand sign is unimportant, and the U bit is part of the opcode,
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so force the operand type to integer. */
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et.type = NT_integer;
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neon_mixed_length (et, et.size / 2);
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neon_mixed_length (et, et.size / 2);
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}
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}
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@ -15533,14 +15536,13 @@ static const struct asm_opcode insns[] =
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nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
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nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
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nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
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nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
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nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
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nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
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/* Comparison. Type I8 I16 I32 F32. Non-immediate -> neon_dyadic_if_i. */
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/* Comparison. Type I8 I16 I32 F32. */
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nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
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nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
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nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
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nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
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/* As above, D registers only. */
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/* As above, D registers only. */
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nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
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nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
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nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
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nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
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/* Int and float variants, signedness unimportant. */
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/* Int and float variants, signedness unimportant. */
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/* If not scalar, fall back to neon_dyadic_if_i. */
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nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
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nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
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nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
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nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
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nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
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nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
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@ -1,3 +1,8 @@
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2006-09-04 Paul Brook <paul@codesourcery.com>
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* gas/arm/neon-cov.s: Test .u and .s aliases for .i suffixes.
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* gas/arm/neon-cov.d: Adjust expected output.
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2006-08-21 Joseph Myers <joseph@codesourcery.com>
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2006-08-21 Joseph Myers <joseph@codesourcery.com>
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* gas/arm/unwind.s: Test not merging iWMMXt register save with
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* gas/arm/unwind.s: Test not merging iWMMXt register save with
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@ -230,6 +230,12 @@ Disassembly of section \.text:
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0[0-9a-f]+ <[^>]+> f2a00550 vshl\.s32 q0, q0, #0
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0[0-9a-f]+ <[^>]+> f2a00550 vshl\.s32 q0, q0, #0
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0[0-9a-f]+ <[^>]+> f2a00550 vshl\.s32 q0, q0, #0
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0[0-9a-f]+ <[^>]+> f2a00550 vshl\.s32 q0, q0, #0
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0[0-9a-f]+ <[^>]+> f2a00510 vshl\.s32 d0, d0, #0
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0[0-9a-f]+ <[^>]+> f2a00510 vshl\.s32 d0, d0, #0
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0[0-9a-f]+ <[^>]+> f2a00550 vshl\.s32 q0, q0, #0
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0[0-9a-f]+ <[^>]+> f2a00550 vshl\.s32 q0, q0, #0
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0[0-9a-f]+ <[^>]+> f2a00510 vshl\.s32 d0, d0, #0
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0[0-9a-f]+ <[^>]+> f2a00550 vshl\.s32 q0, q0, #0
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0[0-9a-f]+ <[^>]+> f2a00550 vshl\.s32 q0, q0, #0
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0[0-9a-f]+ <[^>]+> f2a00510 vshl\.s32 d0, d0, #0
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0[0-9a-f]+ <[^>]+> f28005d0 vshl\.s64 q0, q0, #0
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0[0-9a-f]+ <[^>]+> f28005d0 vshl\.s64 q0, q0, #0
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0[0-9a-f]+ <[^>]+> f28005d0 vshl\.s64 q0, q0, #0
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0[0-9a-f]+ <[^>]+> f28005d0 vshl\.s64 q0, q0, #0
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0[0-9a-f]+ <[^>]+> f2800590 vshl\.s64 d0, d0, #0
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0[0-9a-f]+ <[^>]+> f2800590 vshl\.s64 d0, d0, #0
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@ -275,6 +281,12 @@ Disassembly of section \.text:
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00
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@ -293,6 +305,12 @@ Disassembly of section \.text:
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||||||
0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00
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@ -311,6 +329,12 @@ Disassembly of section \.text:
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||||||
0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
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||||||
0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00
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@ -329,6 +353,12 @@ Disassembly of section \.text:
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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||||||
0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff
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||||||
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0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff
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||||||
0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
|
0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
|
||||||
0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00
|
||||||
0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00
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0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00
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@ -509,6 +539,12 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f3200850 vceq\.i32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3200850 vceq\.i32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3200850 vceq\.i32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3200850 vceq\.i32 q0, q0, q0
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||||||
0[0-9a-f]+ <[^>]+> f3200810 vceq\.i32 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f3200810 vceq\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200850 vceq\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200850 vceq\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200810 vceq\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200850 vceq\.i32 q0, q0, q0
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||||||
|
0[0-9a-f]+ <[^>]+> f3200850 vceq\.i32 q0, q0, q0
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||||||
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0[0-9a-f]+ <[^>]+> f3200810 vceq\.i32 d0, d0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f2000e40 vceq\.f32 q0, q0, q0
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0[0-9a-f]+ <[^>]+> f2000e40 vceq\.f32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2000e40 vceq\.f32 q0, q0, q0
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0[0-9a-f]+ <[^>]+> f2000e40 vceq\.f32 q0, q0, q0
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||||||
0[0-9a-f]+ <[^>]+> f2000e00 vceq\.f32 d0, d0, d0
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0[0-9a-f]+ <[^>]+> f2000e00 vceq\.f32 d0, d0, d0
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@ -569,6 +605,12 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f3b90140 vceq\.i32 q0, q0, #0
|
0[0-9a-f]+ <[^>]+> f3b90140 vceq\.i32 q0, q0, #0
|
||||||
0[0-9a-f]+ <[^>]+> f3b90140 vceq\.i32 q0, q0, #0
|
0[0-9a-f]+ <[^>]+> f3b90140 vceq\.i32 q0, q0, #0
|
||||||
0[0-9a-f]+ <[^>]+> f3b90100 vceq\.i32 d0, d0, #0
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0[0-9a-f]+ <[^>]+> f3b90100 vceq\.i32 d0, d0, #0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b90140 vceq\.i32 q0, q0, #0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b90140 vceq\.i32 q0, q0, #0
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||||||
|
0[0-9a-f]+ <[^>]+> f3b90100 vceq\.i32 d0, d0, #0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b90140 vceq\.i32 q0, q0, #0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b90140 vceq\.i32 q0, q0, #0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b90100 vceq\.i32 d0, d0, #0
|
||||||
0[0-9a-f]+ <[^>]+> f3b90540 vceq\.f32 q0, q0, #0
|
0[0-9a-f]+ <[^>]+> f3b90540 vceq\.f32 q0, q0, #0
|
||||||
0[0-9a-f]+ <[^>]+> f3b90540 vceq\.f32 q0, q0, #0
|
0[0-9a-f]+ <[^>]+> f3b90540 vceq\.f32 q0, q0, #0
|
||||||
0[0-9a-f]+ <[^>]+> f3b90500 vceq\.f32 d0, d0, #0
|
0[0-9a-f]+ <[^>]+> f3b90500 vceq\.f32 d0, d0, #0
|
||||||
|
@ -595,6 +637,12 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2200900 vmla\.i32 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f2200900 vmla\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200900 vmla\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200900 vmla\.i32 d0, d0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f2000d50 vmla\.f32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2000d50 vmla\.f32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2000d50 vmla\.f32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2000d50 vmla\.f32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2000d10 vmla\.f32 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f2000d10 vmla\.f32 d0, d0, d0
|
||||||
|
@ -604,6 +652,12 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\]
|
0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\]
|
||||||
0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\]
|
0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\]
|
||||||
0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\]
|
0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\]
|
||||||
|
0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\]
|
||||||
|
0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\]
|
||||||
|
0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\]
|
||||||
|
0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\]
|
||||||
|
0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\]
|
||||||
|
0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\]
|
||||||
0[0-9a-f]+ <[^>]+> f3a00140 vmla\.f32 q0, q0, d0\[0\]
|
0[0-9a-f]+ <[^>]+> f3a00140 vmla\.f32 q0, q0, d0\[0\]
|
||||||
0[0-9a-f]+ <[^>]+> f3a00140 vmla\.f32 q0, q0, d0\[0\]
|
0[0-9a-f]+ <[^>]+> f3a00140 vmla\.f32 q0, q0, d0\[0\]
|
||||||
0[0-9a-f]+ <[^>]+> f2a00140 vmla\.f32 d0, d0, d0\[0\]
|
0[0-9a-f]+ <[^>]+> f2a00140 vmla\.f32 d0, d0, d0\[0\]
|
||||||
|
@ -616,6 +670,12 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f2200d50 vmls\.f32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2200d50 vmls\.f32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2200d50 vmls\.f32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2200d50 vmls\.f32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2200d10 vmls\.f32 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f2200d10 vmls\.f32 d0, d0, d0
|
||||||
|
@ -625,12 +685,20 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\]
|
0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\]
|
||||||
0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\]
|
0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\]
|
||||||
0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\]
|
0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\]
|
||||||
|
0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\]
|
||||||
|
0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\]
|
||||||
|
0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\]
|
||||||
|
0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\]
|
||||||
|
0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\]
|
||||||
|
0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\]
|
||||||
0[0-9a-f]+ <[^>]+> f3a00540 vmls\.f32 q0, q0, d0\[0\]
|
0[0-9a-f]+ <[^>]+> f3a00540 vmls\.f32 q0, q0, d0\[0\]
|
||||||
0[0-9a-f]+ <[^>]+> f3a00540 vmls\.f32 q0, q0, d0\[0\]
|
0[0-9a-f]+ <[^>]+> f3a00540 vmls\.f32 q0, q0, d0\[0\]
|
||||||
0[0-9a-f]+ <[^>]+> f2a00540 vmls\.f32 d0, d0, d0\[0\]
|
0[0-9a-f]+ <[^>]+> f2a00540 vmls\.f32 d0, d0, d0\[0\]
|
||||||
0[0-9a-f]+ <[^>]+> f2000b10 vpadd\.i8 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f2000b10 vpadd\.i8 d0, d0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f2100b10 vpadd\.i16 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f2100b10 vpadd\.i16 d0, d0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f3000d00 vpadd\.f32 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f3000d00 vpadd\.f32 d0, d0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f2000840 vadd\.i8 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2000840 vadd\.i8 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2000840 vadd\.i8 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2000840 vadd\.i8 q0, q0, q0
|
||||||
|
@ -641,6 +709,12 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f2300840 vadd\.i64 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2300840 vadd\.i64 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2300840 vadd\.i64 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2300840 vadd\.i64 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2300800 vadd\.i64 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f2300800 vadd\.i64 d0, d0, d0
|
||||||
|
@ -656,6 +730,12 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f3300840 vsub\.i64 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3300840 vsub\.i64 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3300840 vsub\.i64 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3300840 vsub\.i64 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3300800 vsub\.i64 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f3300800 vsub\.i64 d0, d0, d0
|
||||||
|
@ -680,6 +760,12 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f3000d50 vmul\.f32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3000d50 vmul\.f32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3000d50 vmul\.f32 q0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3000d50 vmul\.f32 q0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3000d10 vmul\.f32 d0, d0, d0
|
0[0-9a-f]+ <[^>]+> f3000d10 vmul\.f32 d0, d0, d0
|
||||||
|
@ -904,9 +990,13 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f3a10850 vqrshrun\.s64 d0, q0, #31
|
0[0-9a-f]+ <[^>]+> f3a10850 vqrshrun\.s64 d0, q0, #31
|
||||||
0[0-9a-f]+ <[^>]+> f2890810 vshrn\.i16 d0, q0, #7
|
0[0-9a-f]+ <[^>]+> f2890810 vshrn\.i16 d0, q0, #7
|
||||||
0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15
|
0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15
|
||||||
|
0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15
|
||||||
|
0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15
|
||||||
0[0-9a-f]+ <[^>]+> f2a10810 vshrn\.i64 d0, q0, #31
|
0[0-9a-f]+ <[^>]+> f2a10810 vshrn\.i64 d0, q0, #31
|
||||||
0[0-9a-f]+ <[^>]+> f2890850 vrshrn\.i16 d0, q0, #7
|
0[0-9a-f]+ <[^>]+> f2890850 vrshrn\.i16 d0, q0, #7
|
||||||
0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15
|
0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15
|
||||||
|
0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15
|
||||||
|
0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15
|
||||||
0[0-9a-f]+ <[^>]+> f2a10850 vrshrn\.i64 d0, q0, #31
|
0[0-9a-f]+ <[^>]+> f2a10850 vrshrn\.i64 d0, q0, #31
|
||||||
0[0-9a-f]+ <[^>]+> f2890a10 vshll\.s8 d0, q0, #1
|
0[0-9a-f]+ <[^>]+> f2890a10 vshll\.s8 d0, q0, #1
|
||||||
0[0-9a-f]+ <[^>]+> f2910a10 vshll\.s16 d0, q0, #1
|
0[0-9a-f]+ <[^>]+> f2910a10 vshll\.s16 d0, q0, #1
|
||||||
|
@ -917,6 +1007,8 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f3b20300 vshll\.i8 q0, d0, #8
|
0[0-9a-f]+ <[^>]+> f3b20300 vshll\.i8 q0, d0, #8
|
||||||
0[0-9a-f]+ <[^>]+> f3b60300 vshll\.i16 q0, d0, #16
|
0[0-9a-f]+ <[^>]+> f3b60300 vshll\.i16 q0, d0, #16
|
||||||
0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32
|
0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32
|
||||||
|
0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32
|
||||||
|
0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32
|
||||||
0[0-9a-f]+ <[^>]+> f3bb0740 vcvt\.s32\.f32 q0, q0
|
0[0-9a-f]+ <[^>]+> f3bb0740 vcvt\.s32\.f32 q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3bb07c0 vcvt\.u32\.f32 q0, q0
|
0[0-9a-f]+ <[^>]+> f3bb07c0 vcvt\.u32\.f32 q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3bb0640 vcvt\.f32\.s32 q0, q0
|
0[0-9a-f]+ <[^>]+> f3bb0640 vcvt\.f32\.s32 q0, q0
|
||||||
|
@ -955,6 +1047,14 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0
|
0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0
|
||||||
0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077
|
0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077
|
||||||
0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077
|
0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077
|
||||||
|
0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077
|
||||||
|
0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077
|
||||||
|
0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077
|
||||||
|
0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077
|
||||||
|
0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077
|
||||||
|
0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077
|
||||||
|
0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077
|
||||||
|
0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077
|
||||||
0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077
|
0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077
|
||||||
0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077
|
0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077
|
||||||
0[0-9a-f]+ <[^>]+> f2870257 vmov\.i32 q0, #30464 ; 0x00007700
|
0[0-9a-f]+ <[^>]+> f2870257 vmov\.i32 q0, #30464 ; 0x00007700
|
||||||
|
@ -1052,15 +1152,23 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f3a00300 vsubw\.u32 q0, q0, d0
|
0[0-9a-f]+ <[^>]+> f3a00300 vsubw\.u32 q0, q0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f2800400 vaddhn\.i16 d0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2800400 vaddhn\.i16 d0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2a00400 vaddhn\.i64 d0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2a00400 vaddhn\.i64 d0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3800400 vraddhn\.i16 d0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3800400 vraddhn\.i16 d0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3900400 vraddhn\.i32 d0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3900400 vraddhn\.i32 d0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3900400 vraddhn\.i32 d0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3900400 vraddhn\.i32 d0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3a00400 vraddhn\.i64 d0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3a00400 vraddhn\.i64 d0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2800600 vsubhn\.i16 d0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2800600 vsubhn\.i16 d0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2900600 vsubhn\.i32 d0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2900600 vsubhn\.i32 d0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2900600 vsubhn\.i32 d0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f2900600 vsubhn\.i32 d0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2a00600 vsubhn\.i64 d0, q0, q0
|
0[0-9a-f]+ <[^>]+> f2a00600 vsubhn\.i64 d0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3800600 vrsubhn\.i16 d0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3800600 vrsubhn\.i16 d0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3900600 vrsubhn\.i32 d0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3900600 vrsubhn\.i32 d0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3900600 vrsubhn\.i32 d0, q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3900600 vrsubhn\.i32 d0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3a00600 vrsubhn\.i64 d0, q0, q0
|
0[0-9a-f]+ <[^>]+> f3a00600 vrsubhn\.i64 d0, q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f2900900 vqdmlal\.s16 q0, d0, d0
|
0[0-9a-f]+ <[^>]+> f2900900 vqdmlal\.s16 q0, d0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f2a00900 vqdmlal\.s32 q0, d0, d0
|
0[0-9a-f]+ <[^>]+> f2a00900 vqdmlal\.s32 q0, d0, d0
|
||||||
|
@ -1130,9 +1238,11 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f3880a10 vmovl\.u8 q0, d0
|
0[0-9a-f]+ <[^>]+> f3880a10 vmovl\.u8 q0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f3900a10 vmovl\.u16 q0, d0
|
0[0-9a-f]+ <[^>]+> f3900a10 vmovl\.u16 q0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f3a00a10 vmovl\.u32 q0, d0
|
0[0-9a-f]+ <[^>]+> f3a00a10 vmovl\.u32 q0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f3b20200 vmovn\.i8 d0, q0
|
0[0-9a-f]+ <[^>]+> f3b20200 vmovn\.i16 d0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3b60200 vmovn\.i16 d0, q0
|
0[0-9a-f]+ <[^>]+> f3b60200 vmovn\.i32 d0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3ba0200 vmovn\.i32 d0, q0
|
0[0-9a-f]+ <[^>]+> f3ba0200 vmovn\.i64 d0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b60200 vmovn\.i32 d0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b60200 vmovn\.i32 d0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3b20280 vqmovn\.s16 d0, q0
|
0[0-9a-f]+ <[^>]+> f3b20280 vqmovn\.s16 d0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3b60280 vqmovn\.s32 d0, q0
|
0[0-9a-f]+ <[^>]+> f3b60280 vqmovn\.s32 d0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3ba0280 vqmovn\.s64 d0, q0
|
0[0-9a-f]+ <[^>]+> f3ba0280 vqmovn\.s64 d0, q0
|
||||||
|
@ -1244,6 +1354,12 @@ Disassembly of section \.text:
|
||||||
0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0
|
0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0
|
0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0
|
0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0
|
||||||
|
0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0
|
||||||
0[0-9a-f]+ <[^>]+> f3b00540 vcnt\.8 q0, q0
|
0[0-9a-f]+ <[^>]+> f3b00540 vcnt\.8 q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3b00540 vcnt\.8 q0, q0
|
0[0-9a-f]+ <[^>]+> f3b00540 vcnt\.8 q0, q0
|
||||||
0[0-9a-f]+ <[^>]+> f3b00500 vcnt\.8 d0, d0
|
0[0-9a-f]+ <[^>]+> f3b00500 vcnt\.8 d0, d0
|
||||||
|
|
|
@ -87,6 +87,8 @@
|
||||||
regs2i_1 \op \opq \imm .i8
|
regs2i_1 \op \opq \imm .i8
|
||||||
regs2i_1 \op \opq \imm .i16
|
regs2i_1 \op \opq \imm .i16
|
||||||
regs2i_1 \op \opq \imm .i32
|
regs2i_1 \op \opq \imm .i32
|
||||||
|
regs2i_1 \op \opq \imm .s32
|
||||||
|
regs2i_1 \op \opq \imm .u32
|
||||||
regs2i_1 \op \opq \imm .i64
|
regs2i_1 \op \opq \imm .i64
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
|
@ -111,6 +113,8 @@
|
||||||
|
|
||||||
.macro logic_imm op opq
|
.macro logic_imm op opq
|
||||||
logic_imm_1 \op \opq 0x000000ff .i32
|
logic_imm_1 \op \opq 0x000000ff .i32
|
||||||
|
logic_imm_1 \op \opq 0x000000ff .s32
|
||||||
|
logic_imm_1 \op \opq 0x000000ff .u32
|
||||||
logic_imm_1 \op \opq 0x0000ff00 .i32
|
logic_imm_1 \op \opq 0x0000ff00 .i32
|
||||||
logic_imm_1 \op \opq 0x00ff0000 .i32
|
logic_imm_1 \op \opq 0x00ff0000 .i32
|
||||||
logic_imm_1 \op \opq 0xff000000 .i32
|
logic_imm_1 \op \opq 0xff000000 .i32
|
||||||
|
@ -123,6 +127,8 @@
|
||||||
|
|
||||||
.macro logic_inv_imm op opq
|
.macro logic_inv_imm op opq
|
||||||
logic_imm_1 \op \opq 0xffffff00 .i32
|
logic_imm_1 \op \opq 0xffffff00 .i32
|
||||||
|
logic_imm_1 \op \opq 0xffffff00 .s32
|
||||||
|
logic_imm_1 \op \opq 0xffffff00 .u32
|
||||||
logic_imm_1 \op \opq 0xffff00ff .i32
|
logic_imm_1 \op \opq 0xffff00ff .i32
|
||||||
logic_imm_1 \op \opq 0xff00ffff .i32
|
logic_imm_1 \op \opq 0xff00ffff .i32
|
||||||
logic_imm_1 \op \opq 0x00ffffff .i32
|
logic_imm_1 \op \opq 0x00ffffff .i32
|
||||||
|
@ -151,6 +157,8 @@
|
||||||
regs3_1 \op \opq .i8
|
regs3_1 \op \opq .i8
|
||||||
regs3_1 \op \opq .i16
|
regs3_1 \op \opq .i16
|
||||||
regs3_1 \op \opq .i32
|
regs3_1 \op \opq .i32
|
||||||
|
regs3_1 \op \opq .s32
|
||||||
|
regs3_1 \op \opq .u32
|
||||||
regs3_1 \op \opq .f32
|
regs3_1 \op \opq .f32
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
|
@ -181,6 +189,8 @@
|
||||||
regs2i_1 \op \opq 0 .i8
|
regs2i_1 \op \opq 0 .i8
|
||||||
regs2i_1 \op \opq 0 .i16
|
regs2i_1 \op \opq 0 .i16
|
||||||
regs2i_1 \op \opq 0 .i32
|
regs2i_1 \op \opq 0 .i32
|
||||||
|
regs2i_1 \op \opq 0 .s32
|
||||||
|
regs2i_1 \op \opq 0 .u32
|
||||||
regs2i_1 \op \opq 0 .f32
|
regs2i_1 \op \opq 0 .f32
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
|
@ -215,9 +225,13 @@
|
||||||
regs3_1 \op \opq .i8
|
regs3_1 \op \opq .i8
|
||||||
regs3_1 \op \opq .i16
|
regs3_1 \op \opq .i16
|
||||||
regs3_1 \op \opq .i32
|
regs3_1 \op \opq .i32
|
||||||
|
regs3_1 \op \opq .s32
|
||||||
|
regs3_1 \op \opq .u32
|
||||||
regs3_1 \op \opq .f32
|
regs3_1 \op \opq .f32
|
||||||
sclr21_1 \op \opq .i16
|
sclr21_1 \op \opq .i16
|
||||||
sclr21_1 \op \opq .i32
|
sclr21_1 \op \opq .i32
|
||||||
|
sclr21_1 \op \opq .s32
|
||||||
|
sclr21_1 \op \opq .u32
|
||||||
sclr21_1 \op \opq .f32
|
sclr21_1 \op \opq .f32
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
|
@ -228,6 +242,8 @@
|
||||||
dregs3_1 \op .i8
|
dregs3_1 \op .i8
|
||||||
dregs3_1 \op .i16
|
dregs3_1 \op .i16
|
||||||
dregs3_1 \op .i32
|
dregs3_1 \op .i32
|
||||||
|
dregs3_1 \op .s32
|
||||||
|
dregs3_1 \op .u32
|
||||||
dregs3_1 \op .f32
|
dregs3_1 \op .f32
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
|
@ -237,6 +253,8 @@
|
||||||
regs3_1 \op \opq .i8
|
regs3_1 \op \opq .i8
|
||||||
regs3_1 \op \opq .i16
|
regs3_1 \op \opq .i16
|
||||||
regs3_1 \op \opq .i32
|
regs3_1 \op \opq .i32
|
||||||
|
regs3_1 \op \opq .s32
|
||||||
|
regs3_1 \op \opq .u32
|
||||||
regs3_1 \op \opq .i64
|
regs3_1 \op \opq .i64
|
||||||
regs3_1 \op \opq .f32
|
regs3_1 \op \opq .f32
|
||||||
.endm
|
.endm
|
||||||
|
@ -256,6 +274,8 @@
|
||||||
regs3_1 \op \opq .i8
|
regs3_1 \op \opq .i8
|
||||||
regs3_1 \op \opq .i16
|
regs3_1 \op \opq .i16
|
||||||
regs3_1 \op \opq .i32
|
regs3_1 \op \opq .i32
|
||||||
|
regs3_1 \op \opq .s32
|
||||||
|
regs3_1 \op \opq .u32
|
||||||
regs3_1 \op \opq .f32
|
regs3_1 \op \opq .f32
|
||||||
regs3_1 \op \opq .p8
|
regs3_1 \op \opq .p8
|
||||||
.endm
|
.endm
|
||||||
|
@ -338,6 +358,8 @@
|
||||||
.macro qrshifti_imm op
|
.macro qrshifti_imm op
|
||||||
regn3_1 \op 7 .i16
|
regn3_1 \op 7 .i16
|
||||||
regn3_1 \op 15 .i32
|
regn3_1 \op 15 .i32
|
||||||
|
regn3_1 \op 15 .s32
|
||||||
|
regn3_1 \op 15 .u32
|
||||||
regn3_1 \op 31 .i64
|
regn3_1 \op 31 .i64
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
|
@ -359,6 +381,8 @@
|
||||||
regl3_1 vshll 8 .i8
|
regl3_1 vshll 8 .i8
|
||||||
regl3_1 vshll 16 .i16
|
regl3_1 vshll 16 .i16
|
||||||
regl3_1 vshll 32 .i32
|
regl3_1 vshll 32 .i32
|
||||||
|
regl3_1 vshll 32 .s32
|
||||||
|
regl3_1 vshll 32 .u32
|
||||||
|
|
||||||
.macro convert op opr arg="" t1=".s32.f32" t2=".u32.f32" t3=".f32.s32" t4=".f32.u32"
|
.macro convert op opr arg="" t1=".s32.f32" t2=".u32.f32" t3=".f32.s32" t4=".f32.u32"
|
||||||
\op\t1 \opr,\opr\arg
|
\op\t1 \opr,\opr\arg
|
||||||
|
@ -393,7 +417,11 @@
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
mov_imm vmov 0x00000077 .i32
|
mov_imm vmov 0x00000077 .i32
|
||||||
|
mov_imm vmov 0x00000077 .s32
|
||||||
|
mov_imm vmov 0x00000077 .u32
|
||||||
mov_imm vmvn 0x00000077 .i32
|
mov_imm vmvn 0x00000077 .i32
|
||||||
|
mov_imm vmvn 0x00000077 .s32
|
||||||
|
mov_imm vmvn 0x00000077 .u32
|
||||||
mov_imm vmov 0x00007700 .i32
|
mov_imm vmov 0x00007700 .i32
|
||||||
mov_imm vmvn 0x00007700 .i32
|
mov_imm vmvn 0x00007700 .i32
|
||||||
mov_imm vmov 0x00770000 .i32
|
mov_imm vmov 0x00770000 .i32
|
||||||
|
@ -461,6 +489,8 @@
|
||||||
.macro narr_ops op
|
.macro narr_ops op
|
||||||
regn3_1 \op q0 .i16
|
regn3_1 \op q0 .i16
|
||||||
regn3_1 \op q0 .i32
|
regn3_1 \op q0 .i32
|
||||||
|
regn3_1 \op q0 .s32
|
||||||
|
regn3_1 \op q0 .u32
|
||||||
regn3_1 \op q0 .i64
|
regn3_1 \op q0 .i64
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
|
@ -531,6 +561,8 @@
|
||||||
binop_3typ vmovl q0 d0 .s8 .s16 .s32
|
binop_3typ vmovl q0 d0 .s8 .s16 .s32
|
||||||
binop_3typ vmovl q0 d0 .u8 .u16 .u32
|
binop_3typ vmovl q0 d0 .u8 .u16 .u32
|
||||||
binop_3typ vmovn d0 q0 .i16 .i32 .i64
|
binop_3typ vmovn d0 q0 .i16 .i32 .i64
|
||||||
|
vmovn.s32 d0, q0
|
||||||
|
vmovn.u32 d0, q0
|
||||||
binop_3typ vqmovn d0 q0 .s16 .s32 .s64
|
binop_3typ vqmovn d0 q0 .s16 .s32 .s64
|
||||||
binop_3typ vqmovn d0 q0 .u16 .u32 .u64
|
binop_3typ vqmovn d0 q0 .u16 .u32 .u64
|
||||||
binop_3typ vqmovun d0 q0 .s16 .s32 .s64
|
binop_3typ vqmovun d0 q0 .s16 .s32 .s64
|
||||||
|
@ -580,6 +612,8 @@
|
||||||
binops \op \opq .i8
|
binops \op \opq .i8
|
||||||
binops \op \opq .i16
|
binops \op \opq .i16
|
||||||
binops \op \opq .i32
|
binops \op \opq .i32
|
||||||
|
binops \op \opq .s32
|
||||||
|
binops \op \opq .u32
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
regs2_i_32 vclz vclzq
|
regs2_i_32 vclz vclzq
|
||||||
|
|
|
@ -1,3 +1,7 @@
|
||||||
|
2006-09-04 Paul Brook <paul@codesourcery.com>
|
||||||
|
|
||||||
|
* arm-dis.c (neon_opcode): Fix suffix on VMOVN.
|
||||||
|
|
||||||
2006-08-23 H.J. Lu <hongjiu.lu@intel.com>
|
2006-08-23 H.J. Lu <hongjiu.lu@intel.com>
|
||||||
|
|
||||||
* i386-dis.c (three_byte_table): Expand to 256 elements.
|
* i386-dis.c (three_byte_table): Expand to 256 elements.
|
||||||
|
|
|
@ -475,7 +475,7 @@ static const struct opcode32 neon_opcodes[] =
|
||||||
{FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
|
{FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
|
||||||
{FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
|
{FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
|
||||||
{FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
|
{FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
|
||||||
{FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19S2\t%12-15,22D, %0-3,5Q"},
|
{FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
|
||||||
{FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
|
{FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
|
||||||
{FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
|
{FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
|
||||||
{FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
|
{FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
|
||||||
|
|
Loading…
Reference in New Issue