(sim_compile): Tweak output text.
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@ -32,7 +32,7 @@ proc sim_compile { source dest type options } {
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regsub "\[\r\n\]*$" "$result" "" result
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regsub "^\[\r\n\]*" "$result" "" result
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if { $result != "" } {
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clone_output "sim compile failed, $result"
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clone_output "sim compile output: $result"
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}
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return $result
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}
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