Add Intel AVX-512 support
binutils/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and
numeration in comments.
(dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to
dwarf table.
gas/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/tc-i386-intel.c (O_zmmword_ptr): New.
(i386_types): Add zmmword.
(i386_intel_simplify_register): Allow regzmm.
(i386_intel_simplify): Handle zmmwords.
(i386_intel_operand): Handle RC/SAE, vector operations and
zmmwords.
* config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
(struct RC_Operation): New.
(struct Mask_Operation): New.
(struct Broadcast_Operation): New.
(vex_prefix): Size of bytes increased to 4 to support EVEX
encoding.
(enum i386_error): Add new error codes: unsupported_broadcast,
broadcast_not_on_src_operand, broadcast_needed,
unsupported_masking, mask_not_on_destination, no_default_mask,
unsupported_rc_sae, rc_sae_operand_not_last_imm,
invalid_register_operand, try_vector_disp8.
(struct _i386_insn): Add new fields vrex, need_vrex, mask,
rounding, broadcast, memshift.
(struct RC_name): New.
(RC_NamesTable): New.
(evexlig): New.
(evexwig): New.
(extra_symbol_chars): Add '{'.
(cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
(i386_operand_type): Add regzmm, regmask and vec_disp8.
(match_mem_size): Handle zmmwords.
(operand_type_match): Handle zmm-registers.
(mode_from_disp_size): Handle vec_disp8.
(fits_in_vec_disp8): New.
(md_begin): Handle {} properly.
(type_names): Add "rZMM", "Mask reg" and "Vector d8".
(build_vex_prefix): Handle vrex.
(build_evex_prefix): New.
(process_immext): Adjust to properly handle EVEX.
(md_assemble): Add EVEX encoding support.
(swap_2_operands): Correctly handle operands with masking,
broadcasting or RC/SAE.
(check_VecOperands): Support EVEX features.
(VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
(match_template): Support regzmm and handle new error codes.
(process_suffix): Handle zmmwords and zmm-registers.
(check_byte_reg): Extend to zmm-registers.
(process_operands): Extend to zmm-registers.
(build_modrm_byte): Handle EVEX.
(output_insn): Adjust to properly handle EVEX case.
(disp_size): Handle vec_disp8.
(output_disp): Support compressed disp8*N evex feature.
(output_imm): Handle RC/SAE immediates properly.
(check_VecOperations): New.
(i386_immediate): Handle EVEX features.
(i386_index_check): Handle zmmwords and zmm-registers.
(RC_SAE_immediate): New.
(i386_att_operand): Handle EVEX features.
(parse_real_register): Add a check for ZMM/Mask registers.
(OPTION_MEVEXLIG): New.
(OPTION_MEVEXWIG): New.
(md_longopts): Add mevexlig and mevexwig.
(md_parse_option): Handle mevexlig and mevexwig options.
(md_show_usage): Add description for mevexlig and mevexwig.
* doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
gas/testsuite/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gas/cfi/cfi-i386.s: Add tests for k0-k7.
* gas/cfi/cfi-i386.d: Change to reflect above mentioned changes.
* gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7.
* gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes.
* gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto.
* gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers.
* gas/i386/intel-regs.d: Change correspondingly.
* gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1.
* gas/i386/prefetch.d: Ditto.
* gas/i386/x86-64-prefetch-intel.d: Ditto.
* gas/i386/x86-64-prefetch.d: Ditto.
* gas/i386/avx512f-intel.d: New.
* gas/i386/avx512f-nondef.d: New.
* gas/i386/avx512f-nondef.s: New.
* gas/i386/avx512f-opts-intel.d: New.
* gas/i386/avx512f-opts.d: New.
* gas/i386/avx512f-opts.s: New.
* gas/i386/avx512f.d: New.
* gas/i386/avx512f.s: New.
* gas/i386/avx512cd-intel.d: New.
* gas/i386/avx512cd.d: New.
* gas/i386/avx512cd.s: New.
* gas/i386/avx512er-intel.d: New.
* gas/i386/avx512er.d: New.
* gas/i386/avx512er.s: New.
* gas/i386/avx512pf-intel.d: New.
* gas/i386/avx512pf.d: New.
* gas/i386/avx512pf.s: New.
* gas/i386/evex-lig.s: New.
* gas/i386/evex-lig256-intel.d: New.
* gas/i386/evex-lig256.d: New.
* gas/i386/evex-lig512-intel.d: New.
* gas/i386/evex-lig512.d: New.
* gas/i386/evex-wig.s: New.
* gas/i386/evex-wig1-intel.d: New.
* gas/i386/evex-wig1.d: New.
* gas/i386/inval-avx512f.l: New.
* gas/i386/inval-avx512f.s: New.
* gas/i386/x86-64-avx512f-intel.d: New.
* gas/i386/x86-64-avx512f-nondef.d: New.
* gas/i386/x86-64-avx512f-nondef.s: New.
* gas/i386/x86-64-avx512f-opts-intel.d: New.
* gas/i386/x86-64-avx512f-opts.d: New.
* gas/i386/x86-64-avx512f-opts.s: New.
* gas/i386/x86-64-avx512f.d: New.
* gas/i386/x86-64-avx512f.s: New.
* gas/i386/x86-64-avx512cd-intel.d: New.
* gas/i386/x86-64-avx512cd.d: New.
* gas/i386/x86-64-avx512cd.s: New.
* gas/i386/x86-64-avx512er-intel.d: New.
* gas/i386/x86-64-avx512er.d: New.
* gas/i386/x86-64-avx512er.s: New.
* gas/i386/x86-64-avx512pf-intel.d: New.
* gas/i386/x86-64-avx512pf.d: New.
* gas/i386/x86-64-avx512pf.s: New.
* gas/i386/x86-64-evex-lig.s: New.
* gas/i386/x86-64-evex-lig256-intel.d: New.
* gas/i386/x86-64-evex-lig256.d: New.
* gas/i386/x86-64-evex-lig512-intel.d: New.
* gas/i386/x86-64-evex-lig512.d: New.
* gas/i386/x86-64-evex-wig.s: New.
* gas/i386/x86-64-evex-wig1-intel.d: New.
* gas/i386/x86-64-evex-wig1.d: New.
* gas/i386/x86-64-inval-avx512f.l: New.
* gas/i386/x86-64-inval-avx512f.s: New.
* gas/i386/i386.exp: Run new AVX-512 tests.
opcodes/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-dis-evex.h: New.
* i386-dis.c (OP_Rounding): New.
(VPCMP_Fixup): New.
(OP_Mask): New.
(Rdq): New.
(XMxmmq): New.
(EXdScalarS): New.
(EXymm): New.
(EXEvexHalfBcstXmmq): New.
(EXxmm_mdq): New.
(EXEvexXGscat): New.
(EXEvexXNoBcst): New.
(VPCMP): New.
(EXxEVexR): New.
(EXxEVexS): New.
(XMask): New.
(MaskG): New.
(MaskE): New.
(MaskR): New.
(MaskVex): New.
(modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
evex_rounding_mode, evex_sae_mode, mask_mode.
(USE_EVEX_TABLE): New.
(EVEX_TABLE): New.
(EVEX enum): New.
(REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
REG_EVEX_0F38C7.
(MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
MOD_EVEX_0F38C7_REG_6.
(PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
PREFIX_EVEX_0F3A55.
(VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
VEX_W_0F3A32_P_2_LEN_0.
(VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
(struct vex): Add fields evex, r, v, mask_register_specifier,
zeroing, ll, b.
(intel_names_xmm): Add upper 16 registers.
(att_names_xmm): Ditto.
(intel_names_ymm): Ditto.
(att_names_ymm): Ditto.
(names_zmm): New.
(intel_names_zmm): Ditto.
(att_names_zmm): Ditto.
(names_mask): Ditto.
(intel_names_mask): Ditto.
(att_names_mask): Ditto.
(names_rounding): Ditto.
(names_broadcast): Ditto.
(x86_64_table): Add escape to evex-table.
(reg_table): Include reg_table evex-entries from
i386-dis-evex.h. Fix prefetchwt1 instruction.
(prefix_table): Add entries for new instructions.
(vex_table): Ditto.
(vex_len_table): Ditto.
(vex_w_table): Ditto.
(mod_table): Ditto.
(get_valid_dis386): Properly handle new instructions.
(print_insn): Handle zmm and mask registers, print mask operand.
(intel_operand_size): Support EVEX, new modes and sizes.
(OP_E_register): Handle new modes.
(OP_E_memory): Ditto.
(OP_G): Ditto.
(OP_XMM): Ditto.
(OP_EX): Ditto.
(OP_VEX): Ditto.
* i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
(cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
CpuAVX512PF and CpuVREX.
(operand_type_init): Add OPERAND_TYPE_REGZMM,
OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
(opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
StaticRounding, SAE, Disp8MemShift, NoDefMask.
(operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
* i386-init.h: Regenerate.
* i386-opc.h (CpuAVX512F): New.
(CpuAVX512CD): New.
(CpuAVX512ER): New.
(CpuAVX512PF): New.
(CpuVREX): New.
(i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
cpuavx512pf and cpuvrex fields.
(VecSIB): Add VecSIB512.
(EVex): New.
(Masking): New.
(VecESize): New.
(Broadcast): New.
(StaticRounding): New.
(SAE): New.
(Disp8MemShift): New.
(NoDefMask): New.
(i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
staticrounding, sae, disp8memshift and nodefmask.
(RegZMM): New.
(Zmmword): Ditto.
(Vec_Disp8): Ditto.
(i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
fields.
(RegVRex): New.
* i386-opc.tbl: Add AVX512 instructions.
* i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
registers, mask registers.
* i386-tbl.h: Regenerate.
This commit is contained in:
H.J. Lu
parent
6f64ef53c0
commit
43234a1e14
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@ -1,3 +1,19 @@
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2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
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Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Sergey Lega <sergey.s.lega@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and
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numeration in comments.
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(dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to
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dwarf table.
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2013-07-19 Nick Clifton <nickc@redhat.com>
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PR binutils/15745
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@ -4939,19 +4939,26 @@ frame_need_space (Frame_Chunk *fc, unsigned int reg)
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static const char *const dwarf_regnames_i386[] =
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{
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"eax", "ecx", "edx", "ebx",
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"esp", "ebp", "esi", "edi",
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"eip", "eflags", NULL,
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"st0", "st1", "st2", "st3",
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"st4", "st5", "st6", "st7",
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NULL, NULL,
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"xmm0", "xmm1", "xmm2", "xmm3",
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"xmm4", "xmm5", "xmm6", "xmm7",
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"mm0", "mm1", "mm2", "mm3",
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"mm4", "mm5", "mm6", "mm7",
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"fcw", "fsw", "mxcsr",
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"es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
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"tr", "ldtr"
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"eax", "ecx", "edx", "ebx", /* 0 - 3 */
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"esp", "ebp", "esi", "edi", /* 4 - 7 */
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"eip", "eflags", NULL, /* 8 - 10 */
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"st0", "st1", "st2", "st3", /* 11 - 14 */
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"st4", "st5", "st6", "st7", /* 15 - 18 */
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NULL, NULL, /* 19 - 20 */
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"xmm0", "xmm1", "xmm2", "xmm3", /* 21 - 24 */
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"xmm4", "xmm5", "xmm6", "xmm7", /* 25 - 28 */
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"mm0", "mm1", "mm2", "mm3", /* 29 - 32 */
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"mm4", "mm5", "mm6", "mm7", /* 33 - 36 */
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"fcw", "fsw", "mxcsr", /* 37 - 39 */
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"es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, /* 40 - 47 */
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"tr", "ldtr", /* 48 - 49 */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 50 - 57 */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 58 - 65 */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 66 - 73 */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 74 - 81 */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 82 - 89 */
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NULL, NULL, NULL, /* 90 - 92 */
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"k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" /* 93 - 100 */
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};
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void
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@ -4980,7 +4987,17 @@ static const char *const dwarf_regnames_x86_64[] =
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"es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
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"fs.base", "gs.base", NULL, NULL,
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"tr", "ldtr",
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"mxcsr", "fcw", "fsw"
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"mxcsr", "fcw", "fsw",
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"xmm16", "xmm17", "xmm18", "xmm19",
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"xmm20", "xmm21", "xmm22", "xmm23",
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"xmm24", "xmm25", "xmm26", "xmm27",
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"xmm28", "xmm29", "xmm30", "xmm31",
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 83 - 90 */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 91 - 98 */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 99 - 106 */
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 107 - 114 */
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NULL, NULL, NULL, /* 115 - 117 */
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"k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
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};
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void
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@ -1,3 +1,77 @@
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2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
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Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Sergey Lega <sergey.s.lega@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* config/tc-i386-intel.c (O_zmmword_ptr): New.
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(i386_types): Add zmmword.
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(i386_intel_simplify_register): Allow regzmm.
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(i386_intel_simplify): Handle zmmwords.
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(i386_intel_operand): Handle RC/SAE, vector operations and
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zmmwords.
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* config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
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(struct RC_Operation): New.
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(struct Mask_Operation): New.
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(struct Broadcast_Operation): New.
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(vex_prefix): Size of bytes increased to 4 to support EVEX
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encoding.
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(enum i386_error): Add new error codes: unsupported_broadcast,
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broadcast_not_on_src_operand, broadcast_needed,
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unsupported_masking, mask_not_on_destination, no_default_mask,
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unsupported_rc_sae, rc_sae_operand_not_last_imm,
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invalid_register_operand, try_vector_disp8.
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(struct _i386_insn): Add new fields vrex, need_vrex, mask,
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rounding, broadcast, memshift.
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(struct RC_name): New.
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(RC_NamesTable): New.
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(evexlig): New.
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(evexwig): New.
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(extra_symbol_chars): Add '{'.
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(cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
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(i386_operand_type): Add regzmm, regmask and vec_disp8.
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(match_mem_size): Handle zmmwords.
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(operand_type_match): Handle zmm-registers.
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(mode_from_disp_size): Handle vec_disp8.
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(fits_in_vec_disp8): New.
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(md_begin): Handle {} properly.
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(type_names): Add "rZMM", "Mask reg" and "Vector d8".
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(build_vex_prefix): Handle vrex.
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(build_evex_prefix): New.
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(process_immext): Adjust to properly handle EVEX.
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(md_assemble): Add EVEX encoding support.
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(swap_2_operands): Correctly handle operands with masking,
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broadcasting or RC/SAE.
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(check_VecOperands): Support EVEX features.
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(VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
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(match_template): Support regzmm and handle new error codes.
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(process_suffix): Handle zmmwords and zmm-registers.
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(check_byte_reg): Extend to zmm-registers.
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(process_operands): Extend to zmm-registers.
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(build_modrm_byte): Handle EVEX.
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(output_insn): Adjust to properly handle EVEX case.
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(disp_size): Handle vec_disp8.
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(output_disp): Support compressed disp8*N evex feature.
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(output_imm): Handle RC/SAE immediates properly.
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(check_VecOperations): New.
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(i386_immediate): Handle EVEX features.
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(i386_index_check): Handle zmmwords and zmm-registers.
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(RC_SAE_immediate): New.
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(i386_att_operand): Handle EVEX features.
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(parse_real_register): Add a check for ZMM/Mask registers.
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(OPTION_MEVEXLIG): New.
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(OPTION_MEVEXWIG): New.
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(md_longopts): Add mevexlig and mevexwig.
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(md_parse_option): Handle mevexlig and mevexwig options.
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(md_show_usage): Add description for mevexlig and mevexwig.
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* doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
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avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
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2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* config/tc-i386.c (cpu_arch): Add .sha.
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@ -63,6 +63,8 @@ intel_state;
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#define O_xmmword_ptr O_md21
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/* ymmword ptr X_add_symbol */
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#define O_ymmword_ptr O_md20
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/* zmmword ptr X_add_symbol */
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#define O_zmmword_ptr O_md19
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static struct
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{
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@ -108,6 +110,7 @@ const i386_types[] =
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I386_TYPE(oword, 16),
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I386_TYPE(xmmword, 16),
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I386_TYPE(ymmword, 32),
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I386_TYPE(zmmword, 64),
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#undef I386_TYPE
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{ "near", O_near_ptr, { 0xff04, 0xff02, 0xff08 } },
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{ "far", O_far_ptr, { 0xff06, 0xff05, 0xff06 } },
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@ -280,7 +283,8 @@ i386_intel_simplify_register (expressionS *e)
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}
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else if (!intel_state.index
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&& (i386_regtab[reg_num].reg_type.bitfield.regxmm
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|| i386_regtab[reg_num].reg_type.bitfield.regymm))
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|| i386_regtab[reg_num].reg_type.bitfield.regymm
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|| i386_regtab[reg_num].reg_type.bitfield.regzmm))
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intel_state.index = i386_regtab + reg_num;
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else if (!intel_state.base && !intel_state.in_scale)
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intel_state.base = i386_regtab + reg_num;
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@ -371,6 +375,7 @@ static int i386_intel_simplify (expressionS *e)
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case O_oword_ptr:
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case O_xmmword_ptr:
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case O_ymmword_ptr:
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case O_zmmword_ptr:
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case O_near_ptr:
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case O_far_ptr:
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if (intel_state.op_modifier == O_absent)
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@ -529,6 +534,10 @@ i386_intel_operand (char *operand_string, int got_a_float)
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char suffix = 0;
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int ret;
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/* Handle vector immediates. */
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if (RC_SAE_immediate (operand_string))
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return 1;
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/* Initialize state structure. */
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intel_state.op_modifier = O_absent;
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intel_state.is_mem = 0;
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@ -552,6 +561,17 @@ i386_intel_operand (char *operand_string, int got_a_float)
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intel_syntax = 1;
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SKIP_WHITESPACE ();
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/* Handle vector operations. */
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if (*input_line_pointer == '{')
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{
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char *end = check_VecOperations (input_line_pointer, NULL);
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if (end)
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input_line_pointer = end;
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else
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ret = 0;
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}
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if (!is_end_of_line[(unsigned char) *input_line_pointer])
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{
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as_bad (_("junk `%s' after expression"), input_line_pointer);
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@ -666,6 +686,11 @@ i386_intel_operand (char *operand_string, int got_a_float)
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suffix = YMMWORD_MNEM_SUFFIX;
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break;
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case O_zmmword_ptr:
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i.types[this_operand].bitfield.zmmword = 1;
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suffix = ZMMWORD_MNEM_SUFFIX;
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break;
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case O_far_ptr:
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suffix = LONG_DOUBLE_MNEM_SUFFIX;
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/* FALLTHROUGH */
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1019
gas/config/tc-i386.c
1019
gas/config/tc-i386.c
File diff suppressed because it is too large
Load Diff
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@ -152,6 +152,10 @@ accept various extension mnemonics. For example,
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@code{smap},
|
||||
@code{mpx},
|
||||
@code{sha},
|
||||
@code{avx512f},
|
||||
@code{avx512cd},
|
||||
@code{avx512er},
|
||||
@code{avx512pf},
|
||||
@code{noavx},
|
||||
@code{vmx},
|
||||
@code{vmfunc},
|
||||
|
|
@ -230,6 +234,28 @@ AVX instructions with 128bit vector length, which is the default.
|
|||
@option{-mavxscalar=@var{256}} will encode scalar AVX instructions
|
||||
with 256bit vector length.
|
||||
|
||||
@cindex @samp{-mevexlig=} option, i386
|
||||
@cindex @samp{-mevexlig=} option, x86-64
|
||||
@item -mevexlig=@var{128}
|
||||
@itemx -mevexlig=@var{256}
|
||||
@itemx -mevexlig=@var{512}
|
||||
These options control how the assembler should encode length-ignored
|
||||
(LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
|
||||
EVEX instructions with 128bit vector length, which is the default.
|
||||
@option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
|
||||
encode LIG EVEX instructions with 256bit and 512bit vector length,
|
||||
respectively.
|
||||
|
||||
@cindex @samp{-mevexwig=} option, i386
|
||||
@cindex @samp{-mevexwig=} option, x86-64
|
||||
@item -mevexwig=@var{0}
|
||||
@itemx -mevexwig=@var{1}
|
||||
These options control how the assembler should encode w-ignored (WIG)
|
||||
EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
|
||||
EVEX instructions with evex.w = 0, which is the default.
|
||||
@option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
|
||||
evex.w = 1.
|
||||
|
||||
@cindex @samp{-mmnemonic=} option, i386
|
||||
@cindex @samp{-mmnemonic=} option, x86-64
|
||||
@item -mmnemonic=@var{att}
|
||||
|
|
@ -1042,6 +1068,11 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
|
|||
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
|
||||
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
|
||||
@item @samp{.padlock}
|
||||
@item @samp{.smap} @tab @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er}
|
||||
@item @samp{.avx512pf} @tab @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a}
|
||||
@item @samp{.sse5} @tab @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
|
||||
@item @samp{.abm} @tab @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
|
||||
@item @samp{.cx16} @tab @samp{.padlock}
|
||||
@end multitable
|
||||
|
||||
Apart from the warning, there are only two other effects on
|
||||
|
|
|
|||
|
|
@ -1,3 +1,81 @@
|
|||
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
|
||||
Alexander Ivchenko <alexander.ivchenko@intel.com>
|
||||
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
|
||||
Sergey Lega <sergey.s.lega@intel.com>
|
||||
Anna Tikhonova <anna.tikhonova@intel.com>
|
||||
Ilya Tocar <ilya.tocar@intel.com>
|
||||
Andrey Turetskiy <andrey.turetskiy@intel.com>
|
||||
Ilya Verbin <ilya.verbin@intel.com>
|
||||
Kirill Yukhin <kirill.yukhin@intel.com>
|
||||
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
||||
|
||||
* gas/cfi/cfi-i386.s: Add tests for k0-k7.
|
||||
* gas/cfi/cfi-i386.d: Change to reflect above mentioned changes.
|
||||
* gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7.
|
||||
* gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes.
|
||||
* gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto.
|
||||
* gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers.
|
||||
* gas/i386/intel-regs.d: Change correspondingly.
|
||||
* gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1.
|
||||
* gas/i386/prefetch.d: Ditto.
|
||||
* gas/i386/x86-64-prefetch-intel.d: Ditto.
|
||||
* gas/i386/x86-64-prefetch.d: Ditto.
|
||||
* gas/i386/avx512f-intel.d: New.
|
||||
* gas/i386/avx512f-nondef.d: New.
|
||||
* gas/i386/avx512f-nondef.s: New.
|
||||
* gas/i386/avx512f-opts-intel.d: New.
|
||||
* gas/i386/avx512f-opts.d: New.
|
||||
* gas/i386/avx512f-opts.s: New.
|
||||
* gas/i386/avx512f.d: New.
|
||||
* gas/i386/avx512f.s: New.
|
||||
* gas/i386/avx512cd-intel.d: New.
|
||||
* gas/i386/avx512cd.d: New.
|
||||
* gas/i386/avx512cd.s: New.
|
||||
* gas/i386/avx512er-intel.d: New.
|
||||
* gas/i386/avx512er.d: New.
|
||||
* gas/i386/avx512er.s: New.
|
||||
* gas/i386/avx512pf-intel.d: New.
|
||||
* gas/i386/avx512pf.d: New.
|
||||
* gas/i386/avx512pf.s: New.
|
||||
* gas/i386/evex-lig.s: New.
|
||||
* gas/i386/evex-lig256-intel.d: New.
|
||||
* gas/i386/evex-lig256.d: New.
|
||||
* gas/i386/evex-lig512-intel.d: New.
|
||||
* gas/i386/evex-lig512.d: New.
|
||||
* gas/i386/evex-wig.s: New.
|
||||
* gas/i386/evex-wig1-intel.d: New.
|
||||
* gas/i386/evex-wig1.d: New.
|
||||
* gas/i386/inval-avx512f.l: New.
|
||||
* gas/i386/inval-avx512f.s: New.
|
||||
* gas/i386/x86-64-avx512f-intel.d: New.
|
||||
* gas/i386/x86-64-avx512f-nondef.d: New.
|
||||
* gas/i386/x86-64-avx512f-nondef.s: New.
|
||||
* gas/i386/x86-64-avx512f-opts-intel.d: New.
|
||||
* gas/i386/x86-64-avx512f-opts.d: New.
|
||||
* gas/i386/x86-64-avx512f-opts.s: New.
|
||||
* gas/i386/x86-64-avx512f.d: New.
|
||||
* gas/i386/x86-64-avx512f.s: New.
|
||||
* gas/i386/x86-64-avx512cd-intel.d: New.
|
||||
* gas/i386/x86-64-avx512cd.d: New.
|
||||
* gas/i386/x86-64-avx512cd.s: New.
|
||||
* gas/i386/x86-64-avx512er-intel.d: New.
|
||||
* gas/i386/x86-64-avx512er.d: New.
|
||||
* gas/i386/x86-64-avx512er.s: New.
|
||||
* gas/i386/x86-64-avx512pf-intel.d: New.
|
||||
* gas/i386/x86-64-avx512pf.d: New.
|
||||
* gas/i386/x86-64-avx512pf.s: New.
|
||||
* gas/i386/x86-64-evex-lig.s: New.
|
||||
* gas/i386/x86-64-evex-lig256-intel.d: New.
|
||||
* gas/i386/x86-64-evex-lig256.d: New.
|
||||
* gas/i386/x86-64-evex-lig512-intel.d: New.
|
||||
* gas/i386/x86-64-evex-lig512.d: New.
|
||||
* gas/i386/x86-64-evex-wig.s: New.
|
||||
* gas/i386/x86-64-evex-wig1-intel.d: New.
|
||||
* gas/i386/x86-64-evex-wig1.d: New.
|
||||
* gas/i386/x86-64-inval-avx512f.l: New.
|
||||
* gas/i386/x86-64-inval-avx512f.s: New.
|
||||
* gas/i386/i386.exp: Run new AVX-512 tests.
|
||||
|
||||
2013-07-25 Richard Sandiford <rdsandiford@googlemail.com>
|
||||
|
||||
* gas/mips/loongson-2f.d: Fix expected output for madd.ps,
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ Contents of the .eh_frame section:
|
|||
DW_CFA_undefined: r8 \(eip\)
|
||||
DW_CFA_nop
|
||||
|
||||
000000a0 00000094 00000018 FDE cie=0000008c pc=00000044..00000071
|
||||
000000a0 000000ac 00000018 FDE cie=0000008c pc=00000044..00000079
|
||||
DW_CFA_advance_loc: 1 to 00000045
|
||||
DW_CFA_undefined: r0 \(eax\)
|
||||
DW_CFA_advance_loc: 1 to 00000046
|
||||
|
|
@ -147,6 +147,22 @@ Contents of the .eh_frame section:
|
|||
DW_CFA_undefined: r35 \(mm6\)
|
||||
DW_CFA_advance_loc: 1 to 00000070
|
||||
DW_CFA_undefined: r36 \(mm7\)
|
||||
DW_CFA_advance_loc: 1 to 00000071
|
||||
DW_CFA_undefined: r93 \(k0\)
|
||||
DW_CFA_advance_loc: 1 to 00000072
|
||||
DW_CFA_undefined: r94 \(k1\)
|
||||
DW_CFA_advance_loc: 1 to 00000073
|
||||
DW_CFA_undefined: r95 \(k2\)
|
||||
DW_CFA_advance_loc: 1 to 00000074
|
||||
DW_CFA_undefined: r96 \(k3\)
|
||||
DW_CFA_advance_loc: 1 to 00000075
|
||||
DW_CFA_undefined: r97 \(k4\)
|
||||
DW_CFA_advance_loc: 1 to 00000076
|
||||
DW_CFA_undefined: r98 \(k5\)
|
||||
DW_CFA_advance_loc: 1 to 00000077
|
||||
DW_CFA_undefined: r99 \(k6\)
|
||||
DW_CFA_advance_loc: 1 to 00000078
|
||||
DW_CFA_undefined: r100 \(k7\)
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
|
|
|
|||
|
|
@ -156,4 +156,13 @@ func_all_registers:
|
|||
.cfi_undefined mm6 ; nop
|
||||
.cfi_undefined mm7 ; nop
|
||||
|
||||
.cfi_undefined k0 ; nop
|
||||
.cfi_undefined k1 ; nop
|
||||
.cfi_undefined k2 ; nop
|
||||
.cfi_undefined k3 ; nop
|
||||
.cfi_undefined k4 ; nop
|
||||
.cfi_undefined k5 ; nop
|
||||
.cfi_undefined k6 ; nop
|
||||
.cfi_undefined k7 ; nop
|
||||
|
||||
.cfi_endproc
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ Contents of the .eh_frame section:
|
|||
DW_CFA_undefined: r16 \(rip\)
|
||||
DW_CFA_nop
|
||||
|
||||
000000e8 000000c[8c] 00000018 FDE cie=000000d4 pc=00000058..00000097
|
||||
000000e8 0000011[04] 00000018 FDE cie=000000d4 pc=00000058..000000af
|
||||
DW_CFA_advance_loc: 1 to 00000059
|
||||
DW_CFA_undefined: r0 \(rax\)
|
||||
DW_CFA_advance_loc: 1 to 0000005a
|
||||
|
|
@ -220,5 +220,57 @@ Contents of the .eh_frame section:
|
|||
DW_CFA_undefined: r47 \(mm6\)
|
||||
DW_CFA_advance_loc: 1 to 00000096
|
||||
DW_CFA_undefined: r48 \(mm7\)
|
||||
DW_CFA_advance_loc: 1 to 00000097
|
||||
DW_CFA_undefined: r67 \(xmm16\)
|
||||
DW_CFA_advance_loc: 1 to 00000098
|
||||
DW_CFA_undefined: r68 \(xmm17\)
|
||||
DW_CFA_advance_loc: 1 to 00000099
|
||||
DW_CFA_undefined: r69 \(xmm18\)
|
||||
DW_CFA_advance_loc: 1 to 0000009a
|
||||
DW_CFA_undefined: r70 \(xmm19\)
|
||||
DW_CFA_advance_loc: 1 to 0000009b
|
||||
DW_CFA_undefined: r71 \(xmm20\)
|
||||
DW_CFA_advance_loc: 1 to 0000009c
|
||||
DW_CFA_undefined: r72 \(xmm21\)
|
||||
DW_CFA_advance_loc: 1 to 0000009d
|
||||
DW_CFA_undefined: r73 \(xmm22\)
|
||||
DW_CFA_advance_loc: 1 to 0000009e
|
||||
DW_CFA_undefined: r74 \(xmm23\)
|
||||
DW_CFA_advance_loc: 1 to 0000009f
|
||||
DW_CFA_undefined: r75 \(xmm24\)
|
||||
DW_CFA_advance_loc: 1 to 000000a0
|
||||
DW_CFA_undefined: r76 \(xmm25\)
|
||||
DW_CFA_advance_loc: 1 to 000000a1
|
||||
DW_CFA_undefined: r77 \(xmm26\)
|
||||
DW_CFA_advance_loc: 1 to 000000a2
|
||||
DW_CFA_undefined: r78 \(xmm27\)
|
||||
DW_CFA_advance_loc: 1 to 000000a3
|
||||
DW_CFA_undefined: r79 \(xmm28\)
|
||||
DW_CFA_advance_loc: 1 to 000000a4
|
||||
DW_CFA_undefined: r80 \(xmm29\)
|
||||
DW_CFA_advance_loc: 1 to 000000a5
|
||||
DW_CFA_undefined: r81 \(xmm30\)
|
||||
DW_CFA_advance_loc: 1 to 000000a6
|
||||
DW_CFA_undefined: r82 \(xmm31\)
|
||||
DW_CFA_advance_loc: 1 to 000000a7
|
||||
DW_CFA_undefined: r118 \(k0\)
|
||||
DW_CFA_advance_loc: 1 to 000000a8
|
||||
DW_CFA_undefined: r119 \(k1\)
|
||||
DW_CFA_advance_loc: 1 to 000000a9
|
||||
DW_CFA_undefined: r120 \(k2\)
|
||||
DW_CFA_advance_loc: 1 to 000000aa
|
||||
DW_CFA_undefined: r121 \(k3\)
|
||||
DW_CFA_advance_loc: 1 to 000000ab
|
||||
DW_CFA_undefined: r122 \(k4\)
|
||||
DW_CFA_advance_loc: 1 to 000000ac
|
||||
DW_CFA_undefined: r123 \(k5\)
|
||||
DW_CFA_advance_loc: 1 to 000000ad
|
||||
DW_CFA_undefined: r124 \(k6\)
|
||||
DW_CFA_advance_loc: 1 to 000000ae
|
||||
DW_CFA_undefined: r125 \(k7\)
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
DW_CFA_nop
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -204,4 +204,30 @@ func_all_registers:
|
|||
.cfi_undefined mm6 ; nop
|
||||
.cfi_undefined mm7 ; nop
|
||||
|
||||
.cfi_undefined xmm16 ; nop
|
||||
.cfi_undefined xmm17 ; nop
|
||||
.cfi_undefined xmm18 ; nop
|
||||
.cfi_undefined xmm19 ; nop
|
||||
.cfi_undefined xmm20 ; nop
|
||||
.cfi_undefined xmm21 ; nop
|
||||
.cfi_undefined xmm22 ; nop
|
||||
.cfi_undefined xmm23 ; nop
|
||||
.cfi_undefined xmm24 ; nop
|
||||
.cfi_undefined xmm25 ; nop
|
||||
.cfi_undefined xmm26 ; nop
|
||||
.cfi_undefined xmm27 ; nop
|
||||
.cfi_undefined xmm28 ; nop
|
||||
.cfi_undefined xmm29 ; nop
|
||||
.cfi_undefined xmm30 ; nop
|
||||
.cfi_undefined xmm31 ; nop
|
||||
|
||||
.cfi_undefined k0 ; nop
|
||||
.cfi_undefined k1 ; nop
|
||||
.cfi_undefined k2 ; nop
|
||||
.cfi_undefined k3 ; nop
|
||||
.cfi_undefined k4 ; nop
|
||||
.cfi_undefined k5 ; nop
|
||||
.cfi_undefined k6 ; nop
|
||||
.cfi_undefined k7 ; nop
|
||||
|
||||
.cfi_endproc
|
||||
|
|
|
|||
|
|
@ -0,0 +1,180 @@
|
|||
#as:
|
||||
#objdump: -dwMintel
|
||||
#name: i386 AVX512CD insns (Intel disassembly)
|
||||
#source: avx512cd.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 f5 vpconflictd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f c4 f5 vpconflictd zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf c4 f5 vpconflictd zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 31 vpconflictd zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 b4 f4 c0 1d fe ff vpconflictd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 30 vpconflictd zmm6,DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 72 7f vpconflictd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 b2 00 20 00 00 vpconflictd zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 72 80 vpconflictd zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 b2 c0 df ff ff vpconflictd zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 72 7f vpconflictd zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 b2 00 02 00 00 vpconflictd zmm6,DWORD PTR \[edx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 72 80 vpconflictd zmm6,DWORD PTR \[edx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 b2 fc fd ff ff vpconflictd zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 f5 vpconflictq zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f c4 f5 vpconflictq zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf c4 f5 vpconflictq zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 31 vpconflictq zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 b4 f4 c0 1d fe ff vpconflictq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 30 vpconflictq zmm6,QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 72 7f vpconflictq zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 b2 00 20 00 00 vpconflictq zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 72 80 vpconflictq zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 b2 c0 df ff ff vpconflictq zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 72 7f vpconflictq zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 b2 00 04 00 00 vpconflictq zmm6,QWORD PTR \[edx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 72 80 vpconflictq zmm6,QWORD PTR \[edx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 b2 f8 fb ff ff vpconflictq zmm6,QWORD PTR \[edx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 f5 vplzcntd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f 44 f5 vplzcntd zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf 44 f5 vplzcntd zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 31 vplzcntd zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 b4 f4 c0 1d fe ff vplzcntd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 30 vplzcntd zmm6,DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 72 7f vplzcntd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 b2 00 20 00 00 vplzcntd zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 72 80 vplzcntd zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 b2 c0 df ff ff vplzcntd zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 72 7f vplzcntd zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 b2 00 02 00 00 vplzcntd zmm6,DWORD PTR \[edx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 72 80 vplzcntd zmm6,DWORD PTR \[edx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 b2 fc fd ff ff vplzcntd zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 f5 vplzcntq zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 44 f5 vplzcntq zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 44 f5 vplzcntq zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 31 vplzcntq zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 b4 f4 c0 1d fe ff vplzcntq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 30 vplzcntq zmm6,QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 72 7f vplzcntq zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 b2 00 20 00 00 vplzcntq zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 72 80 vplzcntq zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 b2 c0 df ff ff vplzcntq zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 72 7f vplzcntq zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 00 04 00 00 vplzcntq zmm6,QWORD PTR \[edx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 72 80 vplzcntq zmm6,QWORD PTR \[edx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 f8 fb ff ff vplzcntq zmm6,QWORD PTR \[edx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 ec vptestnmd k5,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 56 4f 27 ec vptestnmd k5\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 29 vptestnmd k5,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 ac f4 c0 1d fe ff vptestnmd k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 28 vptestnmd k5,zmm5,DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 7f vptestnmd k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 aa 00 20 00 00 vptestnmd k5,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 80 vptestnmd k5,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 aa c0 df ff ff vptestnmd k5,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 7f vptestnmd k5,zmm5,DWORD PTR \[edx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 aa 00 02 00 00 vptestnmd k5,zmm5,DWORD PTR \[edx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 80 vptestnmd k5,zmm5,DWORD PTR \[edx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 aa fc fd ff ff vptestnmd k5,zmm5,DWORD PTR \[edx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 ec vptestnmq k5,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 4f 27 ec vptestnmq k5\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 29 vptestnmq k5,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 ac f4 c0 1d fe ff vptestnmq k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 28 vptestnmq k5,zmm5,QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 7f vptestnmq k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa 00 20 00 00 vptestnmq k5,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 80 vptestnmq k5,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa c0 df ff ff vptestnmq k5,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 7f vptestnmq k5,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq k5,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq k5,zmm5,QWORD PTR \[edx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq k5,zmm5,QWORD PTR \[edx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7e 48 3a f6 vpbroadcastmw2d zmm6,k6
|
||||
[ ]*[a-f0-9]+: 62 f2 fe 48 2a f6 vpbroadcastmb2q zmm6,k6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 f5 vpconflictd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f c4 f5 vpconflictd zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf c4 f5 vpconflictd zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 31 vpconflictd zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 b4 f4 c0 1d fe ff vpconflictd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 30 vpconflictd zmm6,DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 72 7f vpconflictd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 b2 00 20 00 00 vpconflictd zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 72 80 vpconflictd zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 b2 c0 df ff ff vpconflictd zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 72 7f vpconflictd zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 b2 00 02 00 00 vpconflictd zmm6,DWORD PTR \[edx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 72 80 vpconflictd zmm6,DWORD PTR \[edx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 b2 fc fd ff ff vpconflictd zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 f5 vpconflictq zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f c4 f5 vpconflictq zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf c4 f5 vpconflictq zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 31 vpconflictq zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 b4 f4 c0 1d fe ff vpconflictq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 30 vpconflictq zmm6,QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 72 7f vpconflictq zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 b2 00 20 00 00 vpconflictq zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 72 80 vpconflictq zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 b2 c0 df ff ff vpconflictq zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 72 7f vpconflictq zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 b2 00 04 00 00 vpconflictq zmm6,QWORD PTR \[edx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 72 80 vpconflictq zmm6,QWORD PTR \[edx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 b2 f8 fb ff ff vpconflictq zmm6,QWORD PTR \[edx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 f5 vplzcntd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f 44 f5 vplzcntd zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf 44 f5 vplzcntd zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 31 vplzcntd zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 b4 f4 c0 1d fe ff vplzcntd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 30 vplzcntd zmm6,DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 72 7f vplzcntd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 b2 00 20 00 00 vplzcntd zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 72 80 vplzcntd zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 b2 c0 df ff ff vplzcntd zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 72 7f vplzcntd zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 b2 00 02 00 00 vplzcntd zmm6,DWORD PTR \[edx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 72 80 vplzcntd zmm6,DWORD PTR \[edx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 b2 fc fd ff ff vplzcntd zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 f5 vplzcntq zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 44 f5 vplzcntq zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 44 f5 vplzcntq zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 31 vplzcntq zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 b4 f4 c0 1d fe ff vplzcntq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 30 vplzcntq zmm6,QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 72 7f vplzcntq zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 b2 00 20 00 00 vplzcntq zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 72 80 vplzcntq zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 b2 c0 df ff ff vplzcntq zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 72 7f vplzcntq zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 00 04 00 00 vplzcntq zmm6,QWORD PTR \[edx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 72 80 vplzcntq zmm6,QWORD PTR \[edx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 f8 fb ff ff vplzcntq zmm6,QWORD PTR \[edx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 ec vptestnmd k5,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 56 4f 27 ec vptestnmd k5\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 29 vptestnmd k5,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 ac f4 c0 1d fe ff vptestnmd k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 28 vptestnmd k5,zmm5,DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 7f vptestnmd k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 aa 00 20 00 00 vptestnmd k5,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 80 vptestnmd k5,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 aa c0 df ff ff vptestnmd k5,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 7f vptestnmd k5,zmm5,DWORD PTR \[edx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 aa 00 02 00 00 vptestnmd k5,zmm5,DWORD PTR \[edx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 80 vptestnmd k5,zmm5,DWORD PTR \[edx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 aa fc fd ff ff vptestnmd k5,zmm5,DWORD PTR \[edx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 ec vptestnmq k5,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 4f 27 ec vptestnmq k5\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 29 vptestnmq k5,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 ac f4 c0 1d fe ff vptestnmq k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 28 vptestnmq k5,zmm5,QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 7f vptestnmq k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa 00 20 00 00 vptestnmq k5,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 80 vptestnmq k5,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa c0 df ff ff vptestnmq k5,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 7f vptestnmq k5,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq k5,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq k5,zmm5,QWORD PTR \[edx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq k5,zmm5,QWORD PTR \[edx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7e 48 3a f6 vpbroadcastmw2d zmm6,k6
|
||||
[ ]*[a-f0-9]+: 62 f2 fe 48 2a f6 vpbroadcastmb2q zmm6,k6
|
||||
#pass
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: i386 AVX512CD insns
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 f5 vpconflictd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f c4 f5 vpconflictd %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf c4 f5 vpconflictd %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 31 vpconflictd \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 b4 f4 c0 1d fe ff vpconflictd -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 30 vpconflictd \(%eax\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 72 7f vpconflictd 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 b2 00 20 00 00 vpconflictd 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 72 80 vpconflictd -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 b2 c0 df ff ff vpconflictd -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 72 7f vpconflictd 0x1fc\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 b2 00 02 00 00 vpconflictd 0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 72 80 vpconflictd -0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 b2 fc fd ff ff vpconflictd -0x204\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 f5 vpconflictq %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f c4 f5 vpconflictq %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf c4 f5 vpconflictq %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 31 vpconflictq \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 b4 f4 c0 1d fe ff vpconflictq -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 30 vpconflictq \(%eax\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 72 7f vpconflictq 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 b2 00 20 00 00 vpconflictq 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 72 80 vpconflictq -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 b2 c0 df ff ff vpconflictq -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 72 7f vpconflictq 0x3f8\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 b2 00 04 00 00 vpconflictq 0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 72 80 vpconflictq -0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 b2 f8 fb ff ff vpconflictq -0x408\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 f5 vplzcntd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f 44 f5 vplzcntd %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf 44 f5 vplzcntd %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 31 vplzcntd \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 b4 f4 c0 1d fe ff vplzcntd -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 30 vplzcntd \(%eax\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 72 7f vplzcntd 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 b2 00 20 00 00 vplzcntd 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 72 80 vplzcntd -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 b2 c0 df ff ff vplzcntd -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 72 7f vplzcntd 0x1fc\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 b2 00 02 00 00 vplzcntd 0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 72 80 vplzcntd -0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 b2 fc fd ff ff vplzcntd -0x204\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 f5 vplzcntq %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 44 f5 vplzcntq %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 44 f5 vplzcntq %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 31 vplzcntq \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 b4 f4 c0 1d fe ff vplzcntq -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 30 vplzcntq \(%eax\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 72 7f vplzcntq 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 b2 00 20 00 00 vplzcntq 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 72 80 vplzcntq -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 b2 c0 df ff ff vplzcntq -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 72 7f vplzcntq 0x3f8\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 00 04 00 00 vplzcntq 0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 72 80 vplzcntq -0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 f8 fb ff ff vplzcntq -0x408\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 ec vptestnmd %zmm4,%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 4f 27 ec vptestnmd %zmm4,%zmm5,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 29 vptestnmd \(%ecx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 ac f4 c0 1d fe ff vptestnmd -0x1e240\(%esp,%esi,8\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 28 vptestnmd \(%eax\)\{1to16\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 7f vptestnmd 0x1fc0\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 aa 00 20 00 00 vptestnmd 0x2000\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 80 vptestnmd -0x2000\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 aa c0 df ff ff vptestnmd -0x2040\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 7f vptestnmd 0x1fc\(%edx\)\{1to16\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 aa 00 02 00 00 vptestnmd 0x200\(%edx\)\{1to16\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 80 vptestnmd -0x200\(%edx\)\{1to16\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 aa fc fd ff ff vptestnmd -0x204\(%edx\)\{1to16\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 ec vptestnmq %zmm4,%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 4f 27 ec vptestnmq %zmm4,%zmm5,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 29 vptestnmq \(%ecx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 ac f4 c0 1d fe ff vptestnmq -0x1e240\(%esp,%esi,8\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 28 vptestnmq \(%eax\)\{1to8\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 7f vptestnmq 0x1fc0\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa 00 20 00 00 vptestnmq 0x2000\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 80 vptestnmq -0x2000\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa c0 df ff ff vptestnmq -0x2040\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 7f vptestnmq 0x3f8\(%edx\)\{1to8\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq 0x400\(%edx\)\{1to8\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq -0x400\(%edx\)\{1to8\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq -0x408\(%edx\)\{1to8\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 7e 48 3a f6 vpbroadcastmw2d %k6,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fe 48 2a f6 vpbroadcastmb2q %k6,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 f5 vpconflictd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f c4 f5 vpconflictd %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf c4 f5 vpconflictd %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 31 vpconflictd \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 b4 f4 c0 1d fe ff vpconflictd -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 30 vpconflictd \(%eax\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 72 7f vpconflictd 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 b2 00 20 00 00 vpconflictd 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 72 80 vpconflictd -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c4 b2 c0 df ff ff vpconflictd -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 72 7f vpconflictd 0x1fc\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 b2 00 02 00 00 vpconflictd 0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 72 80 vpconflictd -0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c4 b2 fc fd ff ff vpconflictd -0x204\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 f5 vpconflictq %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f c4 f5 vpconflictq %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf c4 f5 vpconflictq %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 31 vpconflictq \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 b4 f4 c0 1d fe ff vpconflictq -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 30 vpconflictq \(%eax\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 72 7f vpconflictq 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 b2 00 20 00 00 vpconflictq 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 72 80 vpconflictq -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c4 b2 c0 df ff ff vpconflictq -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 72 7f vpconflictq 0x3f8\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 b2 00 04 00 00 vpconflictq 0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 72 80 vpconflictq -0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c4 b2 f8 fb ff ff vpconflictq -0x408\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 f5 vplzcntd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f 44 f5 vplzcntd %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf 44 f5 vplzcntd %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 31 vplzcntd \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 b4 f4 c0 1d fe ff vplzcntd -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 30 vplzcntd \(%eax\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 72 7f vplzcntd 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 b2 00 20 00 00 vplzcntd 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 72 80 vplzcntd -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 44 b2 c0 df ff ff vplzcntd -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 72 7f vplzcntd 0x1fc\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 b2 00 02 00 00 vplzcntd 0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 72 80 vplzcntd -0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 44 b2 fc fd ff ff vplzcntd -0x204\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 f5 vplzcntq %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 44 f5 vplzcntq %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 44 f5 vplzcntq %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 31 vplzcntq \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 b4 f4 c0 1d fe ff vplzcntq -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 30 vplzcntq \(%eax\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 72 7f vplzcntq 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 b2 00 20 00 00 vplzcntq 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 72 80 vplzcntq -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 44 b2 c0 df ff ff vplzcntq -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 72 7f vplzcntq 0x3f8\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 00 04 00 00 vplzcntq 0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 72 80 vplzcntq -0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 f8 fb ff ff vplzcntq -0x408\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 ec vptestnmd %zmm4,%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 4f 27 ec vptestnmd %zmm4,%zmm5,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 29 vptestnmd \(%ecx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 ac f4 c0 1d fe ff vptestnmd -0x1e240\(%esp,%esi,8\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 28 vptestnmd \(%eax\)\{1to16\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 7f vptestnmd 0x1fc0\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 aa 00 20 00 00 vptestnmd 0x2000\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 80 vptestnmd -0x2000\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 48 27 aa c0 df ff ff vptestnmd -0x2040\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 7f vptestnmd 0x1fc\(%edx\)\{1to16\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 aa 00 02 00 00 vptestnmd 0x200\(%edx\)\{1to16\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 80 vptestnmd -0x200\(%edx\)\{1to16\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 56 58 27 aa fc fd ff ff vptestnmd -0x204\(%edx\)\{1to16\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 ec vptestnmq %zmm4,%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 4f 27 ec vptestnmq %zmm4,%zmm5,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 29 vptestnmq \(%ecx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 ac f4 c0 1d fe ff vptestnmq -0x1e240\(%esp,%esi,8\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 28 vptestnmq \(%eax\)\{1to8\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 7f vptestnmq 0x1fc0\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa 00 20 00 00 vptestnmq 0x2000\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 80 vptestnmq -0x2000\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa c0 df ff ff vptestnmq -0x2040\(%edx\),%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 7f vptestnmq 0x3f8\(%edx\)\{1to8\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq 0x400\(%edx\)\{1to8\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq -0x400\(%edx\)\{1to8\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq -0x408\(%edx\)\{1to8\},%zmm5,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 7e 48 3a f6 vpbroadcastmw2d %k6,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fe 48 2a f6 vpbroadcastmb2q %k6,%zmm6
|
||||
#pass
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
# Check 32bit AVX512CD instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
vpconflictd %zmm5, %zmm6 # AVX512CD
|
||||
vpconflictd %zmm5, %zmm6{%k7} # AVX512CD
|
||||
vpconflictd %zmm5, %zmm6{%k7}{z} # AVX512CD
|
||||
vpconflictd (%ecx), %zmm6 # AVX512CD
|
||||
vpconflictd -123456(%esp,%esi,8), %zmm6 # AVX512CD
|
||||
vpconflictd (%eax){1to16}, %zmm6 # AVX512CD
|
||||
vpconflictd 8128(%edx), %zmm6 # AVX512CD Disp8
|
||||
vpconflictd 8192(%edx), %zmm6 # AVX512CD
|
||||
vpconflictd -8192(%edx), %zmm6 # AVX512CD Disp8
|
||||
vpconflictd -8256(%edx), %zmm6 # AVX512CD
|
||||
vpconflictd 508(%edx){1to16}, %zmm6 # AVX512CD Disp8
|
||||
vpconflictd 512(%edx){1to16}, %zmm6 # AVX512CD
|
||||
vpconflictd -512(%edx){1to16}, %zmm6 # AVX512CD Disp8
|
||||
vpconflictd -516(%edx){1to16}, %zmm6 # AVX512CD
|
||||
|
||||
vpconflictq %zmm5, %zmm6 # AVX512CD
|
||||
vpconflictq %zmm5, %zmm6{%k7} # AVX512CD
|
||||
vpconflictq %zmm5, %zmm6{%k7}{z} # AVX512CD
|
||||
vpconflictq (%ecx), %zmm6 # AVX512CD
|
||||
vpconflictq -123456(%esp,%esi,8), %zmm6 # AVX512CD
|
||||
vpconflictq (%eax){1to8}, %zmm6 # AVX512CD
|
||||
vpconflictq 8128(%edx), %zmm6 # AVX512CD Disp8
|
||||
vpconflictq 8192(%edx), %zmm6 # AVX512CD
|
||||
vpconflictq -8192(%edx), %zmm6 # AVX512CD Disp8
|
||||
vpconflictq -8256(%edx), %zmm6 # AVX512CD
|
||||
vpconflictq 1016(%edx){1to8}, %zmm6 # AVX512CD Disp8
|
||||
vpconflictq 1024(%edx){1to8}, %zmm6 # AVX512CD
|
||||
vpconflictq -1024(%edx){1to8}, %zmm6 # AVX512CD Disp8
|
||||
vpconflictq -1032(%edx){1to8}, %zmm6 # AVX512CD
|
||||
|
||||
vplzcntd %zmm5, %zmm6 # AVX512CD
|
||||
vplzcntd %zmm5, %zmm6{%k7} # AVX512CD
|
||||
vplzcntd %zmm5, %zmm6{%k7}{z} # AVX512CD
|
||||
vplzcntd (%ecx), %zmm6 # AVX512CD
|
||||
vplzcntd -123456(%esp,%esi,8), %zmm6 # AVX512CD
|
||||
vplzcntd (%eax){1to16}, %zmm6 # AVX512CD
|
||||
vplzcntd 8128(%edx), %zmm6 # AVX512CD Disp8
|
||||
vplzcntd 8192(%edx), %zmm6 # AVX512CD
|
||||
vplzcntd -8192(%edx), %zmm6 # AVX512CD Disp8
|
||||
vplzcntd -8256(%edx), %zmm6 # AVX512CD
|
||||
vplzcntd 508(%edx){1to16}, %zmm6 # AVX512CD Disp8
|
||||
vplzcntd 512(%edx){1to16}, %zmm6 # AVX512CD
|
||||
vplzcntd -512(%edx){1to16}, %zmm6 # AVX512CD Disp8
|
||||
vplzcntd -516(%edx){1to16}, %zmm6 # AVX512CD
|
||||
|
||||
vplzcntq %zmm5, %zmm6 # AVX512CD
|
||||
vplzcntq %zmm5, %zmm6{%k7} # AVX512CD
|
||||
vplzcntq %zmm5, %zmm6{%k7}{z} # AVX512CD
|
||||
vplzcntq (%ecx), %zmm6 # AVX512CD
|
||||
vplzcntq -123456(%esp,%esi,8), %zmm6 # AVX512CD
|
||||
vplzcntq (%eax){1to8}, %zmm6 # AVX512CD
|
||||
vplzcntq 8128(%edx), %zmm6 # AVX512CD Disp8
|
||||
vplzcntq 8192(%edx), %zmm6 # AVX512CD
|
||||
vplzcntq -8192(%edx), %zmm6 # AVX512CD Disp8
|
||||
vplzcntq -8256(%edx), %zmm6 # AVX512CD
|
||||
vplzcntq 1016(%edx){1to8}, %zmm6 # AVX512CD Disp8
|
||||
vplzcntq 1024(%edx){1to8}, %zmm6 # AVX512CD
|
||||
vplzcntq -1024(%edx){1to8}, %zmm6 # AVX512CD Disp8
|
||||
vplzcntq -1032(%edx){1to8}, %zmm6 # AVX512CD
|
||||
|
||||
vptestnmd %zmm4, %zmm5, %k5 # AVX512CD
|
||||
vptestnmd %zmm4, %zmm5, %k5{%k7} # AVX512CD
|
||||
vptestnmd (%ecx), %zmm5, %k5 # AVX512CD
|
||||
vptestnmd -123456(%esp,%esi,8), %zmm5, %k5 # AVX512CD
|
||||
vptestnmd (%eax){1to16}, %zmm5, %k5 # AVX512CD
|
||||
vptestnmd 8128(%edx), %zmm5, %k5 # AVX512CD Disp8
|
||||
vptestnmd 8192(%edx), %zmm5, %k5 # AVX512CD
|
||||
vptestnmd -8192(%edx), %zmm5, %k5 # AVX512CD Disp8
|
||||
vptestnmd -8256(%edx), %zmm5, %k5 # AVX512CD
|
||||
vptestnmd 508(%edx){1to16}, %zmm5, %k5 # AVX512CD Disp8
|
||||
vptestnmd 512(%edx){1to16}, %zmm5, %k5 # AVX512CD
|
||||
vptestnmd -512(%edx){1to16}, %zmm5, %k5 # AVX512CD Disp8
|
||||
vptestnmd -516(%edx){1to16}, %zmm5, %k5 # AVX512CD
|
||||
|
||||
vptestnmq %zmm4, %zmm5, %k5 # AVX512CD
|
||||
vptestnmq %zmm4, %zmm5, %k5{%k7} # AVX512CD
|
||||
vptestnmq (%ecx), %zmm5, %k5 # AVX512CD
|
||||
vptestnmq -123456(%esp,%esi,8), %zmm5, %k5 # AVX512CD
|
||||
vptestnmq (%eax){1to8}, %zmm5, %k5 # AVX512CD
|
||||
vptestnmq 8128(%edx), %zmm5, %k5 # AVX512CD Disp8
|
||||
vptestnmq 8192(%edx), %zmm5, %k5 # AVX512CD
|
||||
vptestnmq -8192(%edx), %zmm5, %k5 # AVX512CD Disp8
|
||||
vptestnmq -8256(%edx), %zmm5, %k5 # AVX512CD
|
||||
vptestnmq 1016(%edx){1to8}, %zmm5, %k5 # AVX512CD Disp8
|
||||
vptestnmq 1024(%edx){1to8}, %zmm5, %k5 # AVX512CD
|
||||
vptestnmq -1024(%edx){1to8}, %zmm5, %k5 # AVX512CD Disp8
|
||||
vptestnmq -1032(%edx){1to8}, %zmm5, %k5 # AVX512CD
|
||||
|
||||
vpbroadcastmw2d %k6, %zmm6 # AVX512CD
|
||||
|
||||
vpbroadcastmb2q %k6, %zmm6 # AVX512CD
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpconflictd zmm6, zmm5 # AVX512CD
|
||||
vpconflictd zmm6{k7}, zmm5 # AVX512CD
|
||||
vpconflictd zmm6{k7}{z}, zmm5 # AVX512CD
|
||||
vpconflictd zmm6, ZMMWORD PTR [ecx] # AVX512CD
|
||||
vpconflictd zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512CD
|
||||
vpconflictd zmm6, [eax]{1to16} # AVX512CD
|
||||
vpconflictd zmm6, ZMMWORD PTR [edx+8128] # AVX512CD Disp8
|
||||
vpconflictd zmm6, ZMMWORD PTR [edx+8192] # AVX512CD
|
||||
vpconflictd zmm6, ZMMWORD PTR [edx-8192] # AVX512CD Disp8
|
||||
vpconflictd zmm6, ZMMWORD PTR [edx-8256] # AVX512CD
|
||||
vpconflictd zmm6, [edx+508]{1to16} # AVX512CD Disp8
|
||||
vpconflictd zmm6, [edx+512]{1to16} # AVX512CD
|
||||
vpconflictd zmm6, [edx-512]{1to16} # AVX512CD Disp8
|
||||
vpconflictd zmm6, [edx-516]{1to16} # AVX512CD
|
||||
|
||||
vpconflictq zmm6, zmm5 # AVX512CD
|
||||
vpconflictq zmm6{k7}, zmm5 # AVX512CD
|
||||
vpconflictq zmm6{k7}{z}, zmm5 # AVX512CD
|
||||
vpconflictq zmm6, ZMMWORD PTR [ecx] # AVX512CD
|
||||
vpconflictq zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512CD
|
||||
vpconflictq zmm6, [eax]{1to8} # AVX512CD
|
||||
vpconflictq zmm6, ZMMWORD PTR [edx+8128] # AVX512CD Disp8
|
||||
vpconflictq zmm6, ZMMWORD PTR [edx+8192] # AVX512CD
|
||||
vpconflictq zmm6, ZMMWORD PTR [edx-8192] # AVX512CD Disp8
|
||||
vpconflictq zmm6, ZMMWORD PTR [edx-8256] # AVX512CD
|
||||
vpconflictq zmm6, [edx+1016]{1to8} # AVX512CD Disp8
|
||||
vpconflictq zmm6, [edx+1024]{1to8} # AVX512CD
|
||||
vpconflictq zmm6, [edx-1024]{1to8} # AVX512CD Disp8
|
||||
vpconflictq zmm6, [edx-1032]{1to8} # AVX512CD
|
||||
|
||||
vplzcntd zmm6, zmm5 # AVX512CD
|
||||
vplzcntd zmm6{k7}, zmm5 # AVX512CD
|
||||
vplzcntd zmm6{k7}{z}, zmm5 # AVX512CD
|
||||
vplzcntd zmm6, ZMMWORD PTR [ecx] # AVX512CD
|
||||
vplzcntd zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512CD
|
||||
vplzcntd zmm6, [eax]{1to16} # AVX512CD
|
||||
vplzcntd zmm6, ZMMWORD PTR [edx+8128] # AVX512CD Disp8
|
||||
vplzcntd zmm6, ZMMWORD PTR [edx+8192] # AVX512CD
|
||||
vplzcntd zmm6, ZMMWORD PTR [edx-8192] # AVX512CD Disp8
|
||||
vplzcntd zmm6, ZMMWORD PTR [edx-8256] # AVX512CD
|
||||
vplzcntd zmm6, [edx+508]{1to16} # AVX512CD Disp8
|
||||
vplzcntd zmm6, [edx+512]{1to16} # AVX512CD
|
||||
vplzcntd zmm6, [edx-512]{1to16} # AVX512CD Disp8
|
||||
vplzcntd zmm6, [edx-516]{1to16} # AVX512CD
|
||||
|
||||
vplzcntq zmm6, zmm5 # AVX512CD
|
||||
vplzcntq zmm6{k7}, zmm5 # AVX512CD
|
||||
vplzcntq zmm6{k7}{z}, zmm5 # AVX512CD
|
||||
vplzcntq zmm6, ZMMWORD PTR [ecx] # AVX512CD
|
||||
vplzcntq zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512CD
|
||||
vplzcntq zmm6, [eax]{1to8} # AVX512CD
|
||||
vplzcntq zmm6, ZMMWORD PTR [edx+8128] # AVX512CD Disp8
|
||||
vplzcntq zmm6, ZMMWORD PTR [edx+8192] # AVX512CD
|
||||
vplzcntq zmm6, ZMMWORD PTR [edx-8192] # AVX512CD Disp8
|
||||
vplzcntq zmm6, ZMMWORD PTR [edx-8256] # AVX512CD
|
||||
vplzcntq zmm6, [edx+1016]{1to8} # AVX512CD Disp8
|
||||
vplzcntq zmm6, [edx+1024]{1to8} # AVX512CD
|
||||
vplzcntq zmm6, [edx-1024]{1to8} # AVX512CD Disp8
|
||||
vplzcntq zmm6, [edx-1032]{1to8} # AVX512CD
|
||||
|
||||
vptestnmd k5, zmm5, zmm4 # AVX512CD
|
||||
vptestnmd k5{k7}, zmm5, zmm4 # AVX512CD
|
||||
vptestnmd k5, zmm5, ZMMWORD PTR [ecx] # AVX512CD
|
||||
vptestnmd k5, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512CD
|
||||
vptestnmd k5, zmm5, [eax]{1to16} # AVX512CD
|
||||
vptestnmd k5, zmm5, ZMMWORD PTR [edx+8128] # AVX512CD Disp8
|
||||
vptestnmd k5, zmm5, ZMMWORD PTR [edx+8192] # AVX512CD
|
||||
vptestnmd k5, zmm5, ZMMWORD PTR [edx-8192] # AVX512CD Disp8
|
||||
vptestnmd k5, zmm5, ZMMWORD PTR [edx-8256] # AVX512CD
|
||||
vptestnmd k5, zmm5, [edx+508]{1to16} # AVX512CD Disp8
|
||||
vptestnmd k5, zmm5, [edx+512]{1to16} # AVX512CD
|
||||
vptestnmd k5, zmm5, [edx-512]{1to16} # AVX512CD Disp8
|
||||
vptestnmd k5, zmm5, [edx-516]{1to16} # AVX512CD
|
||||
|
||||
vptestnmq k5, zmm5, zmm4 # AVX512CD
|
||||
vptestnmq k5{k7}, zmm5, zmm4 # AVX512CD
|
||||
vptestnmq k5, zmm5, ZMMWORD PTR [ecx] # AVX512CD
|
||||
vptestnmq k5, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512CD
|
||||
vptestnmq k5, zmm5, [eax]{1to8} # AVX512CD
|
||||
vptestnmq k5, zmm5, ZMMWORD PTR [edx+8128] # AVX512CD Disp8
|
||||
vptestnmq k5, zmm5, ZMMWORD PTR [edx+8192] # AVX512CD
|
||||
vptestnmq k5, zmm5, ZMMWORD PTR [edx-8192] # AVX512CD Disp8
|
||||
vptestnmq k5, zmm5, ZMMWORD PTR [edx-8256] # AVX512CD
|
||||
vptestnmq k5, zmm5, [edx+1016]{1to8} # AVX512CD Disp8
|
||||
vptestnmq k5, zmm5, [edx+1024]{1to8} # AVX512CD
|
||||
vptestnmq k5, zmm5, [edx-1024]{1to8} # AVX512CD Disp8
|
||||
vptestnmq k5, zmm5, [edx-1032]{1to8} # AVX512CD
|
||||
|
||||
vpbroadcastmw2d zmm6, k6 # AVX512CD
|
||||
|
||||
vpbroadcastmb2q zmm6, k6 # AVX512CD
|
||||
|
||||
|
|
@ -0,0 +1,256 @@
|
|||
#as:
|
||||
#objdump: -dwMintel
|
||||
#name: i386 AVX512ER insns (Intel disassembly)
|
||||
#source: avx512er.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 f5 vexp2ps zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 18 c8 f5 vexp2ps zmm6,zmm5,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 31 vexp2ps zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 b4 f4 c0 1d fe ff vexp2ps zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 30 vexp2ps zmm6,DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 72 7f vexp2ps zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 b2 00 20 00 00 vexp2ps zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 72 80 vexp2ps zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 b2 c0 df ff ff vexp2ps zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 72 7f vexp2ps zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 b2 00 02 00 00 vexp2ps zmm6,DWORD PTR \[edx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 72 80 vexp2ps zmm6,DWORD PTR \[edx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 b2 fc fd ff ff vexp2ps zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 f5 vexp2pd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 18 c8 f5 vexp2pd zmm6,zmm5,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 31 vexp2pd zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 b4 f4 c0 1d fe ff vexp2pd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 30 vexp2pd zmm6,QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 72 7f vexp2pd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 b2 00 20 00 00 vexp2pd zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 72 80 vexp2pd zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 b2 c0 df ff ff vexp2pd zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 72 7f vexp2pd zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 b2 00 04 00 00 vexp2pd zmm6,QWORD PTR \[edx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 72 80 vexp2pd zmm6,QWORD PTR \[edx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 b2 f8 fb ff ff vexp2pd zmm6,QWORD PTR \[edx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca f5 vrcp28ps zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f ca f5 vrcp28ps zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf ca f5 vrcp28ps zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 18 ca f5 vrcp28ps zmm6,zmm5,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca 31 vrcp28ps zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca b4 f4 c0 1d fe ff vrcp28ps zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca 30 vrcp28ps zmm6,DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca 72 7f vrcp28ps zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca b2 00 20 00 00 vrcp28ps zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca 72 80 vrcp28ps zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca b2 c0 df ff ff vrcp28ps zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca 72 7f vrcp28ps zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca b2 00 02 00 00 vrcp28ps zmm6,DWORD PTR \[edx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca 72 80 vrcp28ps zmm6,DWORD PTR \[edx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca b2 fc fd ff ff vrcp28ps zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca f5 vrcp28pd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f ca f5 vrcp28pd zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf ca f5 vrcp28pd zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 18 ca f5 vrcp28pd zmm6,zmm5,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca 31 vrcp28pd zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca b4 f4 c0 1d fe ff vrcp28pd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca 30 vrcp28pd zmm6,QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca 72 7f vrcp28pd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca b2 00 20 00 00 vrcp28pd zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca 72 80 vrcp28pd zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca b2 c0 df ff ff vrcp28pd zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca 72 7f vrcp28pd zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca b2 00 04 00 00 vrcp28pd zmm6,QWORD PTR \[edx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca 72 80 vrcp28pd zmm6,QWORD PTR \[edx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca b2 f8 fb ff ff vrcp28pd zmm6,QWORD PTR \[edx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb f4 vrcp28ss xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 55 8f cb f4 vrcp28ss xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 55 1f cb f4 vrcp28ss xmm6\{k7\},xmm5,xmm4,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb 31 vrcp28ss xmm6\{k7\},xmm5,DWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb b4 f4 c0 1d fe ff vrcp28ss xmm6\{k7\},xmm5,DWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb 72 7f vrcp28ss xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x1fc\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb b2 00 02 00 00 vrcp28ss xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x200\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb 72 80 vrcp28ss xmm6\{k7\},xmm5,DWORD PTR \[edx-0x200\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb b2 fc fd ff ff vrcp28ss xmm6\{k7\},xmm5,DWORD PTR \[edx-0x204\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb f4 vrcp28sd xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 8f cb f4 vrcp28sd xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 1f cb f4 vrcp28sd xmm6\{k7\},xmm5,xmm4,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb 31 vrcp28sd xmm6\{k7\},xmm5,QWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb b4 f4 c0 1d fe ff vrcp28sd xmm6\{k7\},xmm5,QWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb 72 7f vrcp28sd xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb b2 00 04 00 00 vrcp28sd xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb 72 80 vrcp28sd xmm6\{k7\},xmm5,QWORD PTR \[edx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb b2 f8 fb ff ff vrcp28sd xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc f5 vrsqrt28ps zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f cc f5 vrsqrt28ps zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf cc f5 vrsqrt28ps zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 18 cc f5 vrsqrt28ps zmm6,zmm5,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc 31 vrsqrt28ps zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc b4 f4 c0 1d fe ff vrsqrt28ps zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc 30 vrsqrt28ps zmm6,DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc 72 7f vrsqrt28ps zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc b2 00 20 00 00 vrsqrt28ps zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc 72 80 vrsqrt28ps zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc b2 c0 df ff ff vrsqrt28ps zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc 72 7f vrsqrt28ps zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc b2 00 02 00 00 vrsqrt28ps zmm6,DWORD PTR \[edx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc 72 80 vrsqrt28ps zmm6,DWORD PTR \[edx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc b2 fc fd ff ff vrsqrt28ps zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc f5 vrsqrt28pd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f cc f5 vrsqrt28pd zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf cc f5 vrsqrt28pd zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 18 cc f5 vrsqrt28pd zmm6,zmm5,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc 31 vrsqrt28pd zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc b4 f4 c0 1d fe ff vrsqrt28pd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc 30 vrsqrt28pd zmm6,QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc 72 7f vrsqrt28pd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc b2 00 20 00 00 vrsqrt28pd zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc 72 80 vrsqrt28pd zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc b2 c0 df ff ff vrsqrt28pd zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc 72 7f vrsqrt28pd zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc b2 00 04 00 00 vrsqrt28pd zmm6,QWORD PTR \[edx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc 72 80 vrsqrt28pd zmm6,QWORD PTR \[edx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc b2 f8 fb ff ff vrsqrt28pd zmm6,QWORD PTR \[edx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd f4 vrsqrt28ss xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 55 8f cd f4 vrsqrt28ss xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 55 1f cd f4 vrsqrt28ss xmm6\{k7\},xmm5,xmm4,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd 31 vrsqrt28ss xmm6\{k7\},xmm5,DWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd b4 f4 c0 1d fe ff vrsqrt28ss xmm6\{k7\},xmm5,DWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd 72 7f vrsqrt28ss xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x1fc\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd b2 00 02 00 00 vrsqrt28ss xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x200\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd 72 80 vrsqrt28ss xmm6\{k7\},xmm5,DWORD PTR \[edx-0x200\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd b2 fc fd ff ff vrsqrt28ss xmm6\{k7\},xmm5,DWORD PTR \[edx-0x204\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd f4 vrsqrt28sd xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 8f cd f4 vrsqrt28sd xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 1f cd f4 vrsqrt28sd xmm6\{k7\},xmm5,xmm4,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd 31 vrsqrt28sd xmm6\{k7\},xmm5,QWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd b4 f4 c0 1d fe ff vrsqrt28sd xmm6\{k7\},xmm5,QWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd 72 7f vrsqrt28sd xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd b2 00 04 00 00 vrsqrt28sd xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd 72 80 vrsqrt28sd xmm6\{k7\},xmm5,QWORD PTR \[edx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd b2 f8 fb ff ff vrsqrt28sd xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 f5 vexp2ps zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 18 c8 f5 vexp2ps zmm6,zmm5,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 31 vexp2ps zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 b4 f4 c0 1d fe ff vexp2ps zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 30 vexp2ps zmm6,DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 72 7f vexp2ps zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 b2 00 20 00 00 vexp2ps zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 72 80 vexp2ps zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 b2 c0 df ff ff vexp2ps zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 72 7f vexp2ps zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 b2 00 02 00 00 vexp2ps zmm6,DWORD PTR \[edx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 72 80 vexp2ps zmm6,DWORD PTR \[edx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 b2 fc fd ff ff vexp2ps zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 f5 vexp2pd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 18 c8 f5 vexp2pd zmm6,zmm5,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 31 vexp2pd zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 b4 f4 c0 1d fe ff vexp2pd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 30 vexp2pd zmm6,QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 72 7f vexp2pd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 b2 00 20 00 00 vexp2pd zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 72 80 vexp2pd zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 b2 c0 df ff ff vexp2pd zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 72 7f vexp2pd zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 b2 00 04 00 00 vexp2pd zmm6,QWORD PTR \[edx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 72 80 vexp2pd zmm6,QWORD PTR \[edx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 b2 f8 fb ff ff vexp2pd zmm6,QWORD PTR \[edx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca f5 vrcp28ps zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f ca f5 vrcp28ps zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf ca f5 vrcp28ps zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 18 ca f5 vrcp28ps zmm6,zmm5,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca 31 vrcp28ps zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca b4 f4 c0 1d fe ff vrcp28ps zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca 30 vrcp28ps zmm6,DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca 72 7f vrcp28ps zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca b2 00 20 00 00 vrcp28ps zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca 72 80 vrcp28ps zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca b2 c0 df ff ff vrcp28ps zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca 72 7f vrcp28ps zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca b2 00 02 00 00 vrcp28ps zmm6,DWORD PTR \[edx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca 72 80 vrcp28ps zmm6,DWORD PTR \[edx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca b2 fc fd ff ff vrcp28ps zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca f5 vrcp28pd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f ca f5 vrcp28pd zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf ca f5 vrcp28pd zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 18 ca f5 vrcp28pd zmm6,zmm5,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca 31 vrcp28pd zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca b4 f4 c0 1d fe ff vrcp28pd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca 30 vrcp28pd zmm6,QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca 72 7f vrcp28pd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca b2 00 20 00 00 vrcp28pd zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca 72 80 vrcp28pd zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca b2 c0 df ff ff vrcp28pd zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca 72 7f vrcp28pd zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca b2 00 04 00 00 vrcp28pd zmm6,QWORD PTR \[edx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca 72 80 vrcp28pd zmm6,QWORD PTR \[edx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca b2 f8 fb ff ff vrcp28pd zmm6,QWORD PTR \[edx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb f4 vrcp28ss xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 55 8f cb f4 vrcp28ss xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 55 1f cb f4 vrcp28ss xmm6\{k7\},xmm5,xmm4,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb 31 vrcp28ss xmm6\{k7\},xmm5,DWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb b4 f4 c0 1d fe ff vrcp28ss xmm6\{k7\},xmm5,DWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb 72 7f vrcp28ss xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x1fc\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb b2 00 02 00 00 vrcp28ss xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x200\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb 72 80 vrcp28ss xmm6\{k7\},xmm5,DWORD PTR \[edx-0x200\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb b2 fc fd ff ff vrcp28ss xmm6\{k7\},xmm5,DWORD PTR \[edx-0x204\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb f4 vrcp28sd xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 8f cb f4 vrcp28sd xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 1f cb f4 vrcp28sd xmm6\{k7\},xmm5,xmm4,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb 31 vrcp28sd xmm6\{k7\},xmm5,QWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb b4 f4 c0 1d fe ff vrcp28sd xmm6\{k7\},xmm5,QWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb 72 7f vrcp28sd xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb b2 00 04 00 00 vrcp28sd xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb 72 80 vrcp28sd xmm6\{k7\},xmm5,QWORD PTR \[edx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb b2 f8 fb ff ff vrcp28sd xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc f5 vrsqrt28ps zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f cc f5 vrsqrt28ps zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf cc f5 vrsqrt28ps zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 18 cc f5 vrsqrt28ps zmm6,zmm5,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc 31 vrsqrt28ps zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc b4 f4 c0 1d fe ff vrsqrt28ps zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc 30 vrsqrt28ps zmm6,DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc 72 7f vrsqrt28ps zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc b2 00 20 00 00 vrsqrt28ps zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc 72 80 vrsqrt28ps zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc b2 c0 df ff ff vrsqrt28ps zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc 72 7f vrsqrt28ps zmm6,DWORD PTR \[edx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc b2 00 02 00 00 vrsqrt28ps zmm6,DWORD PTR \[edx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc 72 80 vrsqrt28ps zmm6,DWORD PTR \[edx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc b2 fc fd ff ff vrsqrt28ps zmm6,DWORD PTR \[edx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc f5 vrsqrt28pd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f cc f5 vrsqrt28pd zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf cc f5 vrsqrt28pd zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 18 cc f5 vrsqrt28pd zmm6,zmm5,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc 31 vrsqrt28pd zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc b4 f4 c0 1d fe ff vrsqrt28pd zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc 30 vrsqrt28pd zmm6,QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc 72 7f vrsqrt28pd zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc b2 00 20 00 00 vrsqrt28pd zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc 72 80 vrsqrt28pd zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc b2 c0 df ff ff vrsqrt28pd zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc 72 7f vrsqrt28pd zmm6,QWORD PTR \[edx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc b2 00 04 00 00 vrsqrt28pd zmm6,QWORD PTR \[edx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc 72 80 vrsqrt28pd zmm6,QWORD PTR \[edx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc b2 f8 fb ff ff vrsqrt28pd zmm6,QWORD PTR \[edx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd f4 vrsqrt28ss xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 55 8f cd f4 vrsqrt28ss xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 55 1f cd f4 vrsqrt28ss xmm6\{k7\},xmm5,xmm4,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd 31 vrsqrt28ss xmm6\{k7\},xmm5,DWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd b4 f4 c0 1d fe ff vrsqrt28ss xmm6\{k7\},xmm5,DWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd 72 7f vrsqrt28ss xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x1fc\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd b2 00 02 00 00 vrsqrt28ss xmm6\{k7\},xmm5,DWORD PTR \[edx\+0x200\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd 72 80 vrsqrt28ss xmm6\{k7\},xmm5,DWORD PTR \[edx-0x200\]
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd b2 fc fd ff ff vrsqrt28ss xmm6\{k7\},xmm5,DWORD PTR \[edx-0x204\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd f4 vrsqrt28sd xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 8f cd f4 vrsqrt28sd xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 1f cd f4 vrsqrt28sd xmm6\{k7\},xmm5,xmm4,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd 31 vrsqrt28sd xmm6\{k7\},xmm5,QWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd b4 f4 c0 1d fe ff vrsqrt28sd xmm6\{k7\},xmm5,QWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd 72 7f vrsqrt28sd xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd b2 00 04 00 00 vrsqrt28sd xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd 72 80 vrsqrt28sd xmm6\{k7\},xmm5,QWORD PTR \[edx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd b2 f8 fb ff ff vrsqrt28sd xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]
|
||||
#pass
|
||||
|
|
@ -0,0 +1,255 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: i386 AVX512ER insns
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 f5 vexp2ps %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 18 c8 f5 vexp2ps \{sae\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 31 vexp2ps \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 b4 f4 c0 1d fe ff vexp2ps -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 30 vexp2ps \(%eax\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 72 7f vexp2ps 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 b2 00 20 00 00 vexp2ps 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 72 80 vexp2ps -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 b2 c0 df ff ff vexp2ps -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 72 7f vexp2ps 0x1fc\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 b2 00 02 00 00 vexp2ps 0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 72 80 vexp2ps -0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 b2 fc fd ff ff vexp2ps -0x204\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 f5 vexp2pd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 18 c8 f5 vexp2pd \{sae\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 31 vexp2pd \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 b4 f4 c0 1d fe ff vexp2pd -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 30 vexp2pd \(%eax\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 72 7f vexp2pd 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 b2 00 20 00 00 vexp2pd 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 72 80 vexp2pd -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 b2 c0 df ff ff vexp2pd -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 72 7f vexp2pd 0x3f8\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 b2 00 04 00 00 vexp2pd 0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 72 80 vexp2pd -0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 b2 f8 fb ff ff vexp2pd -0x408\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca f5 vrcp28ps %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f ca f5 vrcp28ps %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf ca f5 vrcp28ps %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 18 ca f5 vrcp28ps \{sae\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca 31 vrcp28ps \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca b4 f4 c0 1d fe ff vrcp28ps -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca 30 vrcp28ps \(%eax\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca 72 7f vrcp28ps 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca b2 00 20 00 00 vrcp28ps 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca 72 80 vrcp28ps -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca b2 c0 df ff ff vrcp28ps -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca 72 7f vrcp28ps 0x1fc\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca b2 00 02 00 00 vrcp28ps 0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca 72 80 vrcp28ps -0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca b2 fc fd ff ff vrcp28ps -0x204\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca f5 vrcp28pd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f ca f5 vrcp28pd %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf ca f5 vrcp28pd %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 18 ca f5 vrcp28pd \{sae\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca 31 vrcp28pd \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca b4 f4 c0 1d fe ff vrcp28pd -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca 30 vrcp28pd \(%eax\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca 72 7f vrcp28pd 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca b2 00 20 00 00 vrcp28pd 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca 72 80 vrcp28pd -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca b2 c0 df ff ff vrcp28pd -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca 72 7f vrcp28pd 0x3f8\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca b2 00 04 00 00 vrcp28pd 0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca 72 80 vrcp28pd -0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca b2 f8 fb ff ff vrcp28pd -0x408\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb f4 vrcp28ss %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 8f cb f4 vrcp28ss %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 1f cb f4 vrcp28ss \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb 31 vrcp28ss \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb b4 f4 c0 1d fe ff vrcp28ss -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb 72 7f vrcp28ss 0x1fc\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb b2 00 02 00 00 vrcp28ss 0x200\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb 72 80 vrcp28ss -0x200\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb b2 fc fd ff ff vrcp28ss -0x204\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb f4 vrcp28sd %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 8f cb f4 vrcp28sd %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 1f cb f4 vrcp28sd \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb 31 vrcp28sd \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb b4 f4 c0 1d fe ff vrcp28sd -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb 72 7f vrcp28sd 0x3f8\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb b2 00 04 00 00 vrcp28sd 0x400\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb 72 80 vrcp28sd -0x400\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb b2 f8 fb ff ff vrcp28sd -0x408\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc f5 vrsqrt28ps %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f cc f5 vrsqrt28ps %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf cc f5 vrsqrt28ps %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 18 cc f5 vrsqrt28ps \{sae\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc 31 vrsqrt28ps \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc b4 f4 c0 1d fe ff vrsqrt28ps -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc 30 vrsqrt28ps \(%eax\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc 72 7f vrsqrt28ps 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc b2 00 20 00 00 vrsqrt28ps 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc 72 80 vrsqrt28ps -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc b2 c0 df ff ff vrsqrt28ps -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc 72 7f vrsqrt28ps 0x1fc\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc b2 00 02 00 00 vrsqrt28ps 0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc 72 80 vrsqrt28ps -0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc b2 fc fd ff ff vrsqrt28ps -0x204\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc f5 vrsqrt28pd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f cc f5 vrsqrt28pd %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf cc f5 vrsqrt28pd %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 18 cc f5 vrsqrt28pd \{sae\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc 31 vrsqrt28pd \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc b4 f4 c0 1d fe ff vrsqrt28pd -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc 30 vrsqrt28pd \(%eax\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc 72 7f vrsqrt28pd 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc b2 00 20 00 00 vrsqrt28pd 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc 72 80 vrsqrt28pd -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc b2 c0 df ff ff vrsqrt28pd -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc 72 7f vrsqrt28pd 0x3f8\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc b2 00 04 00 00 vrsqrt28pd 0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc 72 80 vrsqrt28pd -0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc b2 f8 fb ff ff vrsqrt28pd -0x408\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd f4 vrsqrt28ss %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 8f cd f4 vrsqrt28ss %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 1f cd f4 vrsqrt28ss \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd 31 vrsqrt28ss \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd b4 f4 c0 1d fe ff vrsqrt28ss -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd 72 7f vrsqrt28ss 0x1fc\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd b2 00 02 00 00 vrsqrt28ss 0x200\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd 72 80 vrsqrt28ss -0x200\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd b2 fc fd ff ff vrsqrt28ss -0x204\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd f4 vrsqrt28sd %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 8f cd f4 vrsqrt28sd %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 1f cd f4 vrsqrt28sd \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd 31 vrsqrt28sd \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd b4 f4 c0 1d fe ff vrsqrt28sd -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd 72 7f vrsqrt28sd 0x3f8\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd b2 00 04 00 00 vrsqrt28sd 0x400\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd 72 80 vrsqrt28sd -0x400\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd b2 f8 fb ff ff vrsqrt28sd -0x408\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 f5 vexp2ps %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 18 c8 f5 vexp2ps \{sae\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 31 vexp2ps \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 b4 f4 c0 1d fe ff vexp2ps -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 30 vexp2ps \(%eax\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 72 7f vexp2ps 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 b2 00 20 00 00 vexp2ps 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 72 80 vexp2ps -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 c8 b2 c0 df ff ff vexp2ps -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 72 7f vexp2ps 0x1fc\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 b2 00 02 00 00 vexp2ps 0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 72 80 vexp2ps -0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 c8 b2 fc fd ff ff vexp2ps -0x204\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 f5 vexp2pd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 18 c8 f5 vexp2pd \{sae\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 31 vexp2pd \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 b4 f4 c0 1d fe ff vexp2pd -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 30 vexp2pd \(%eax\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 72 7f vexp2pd 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 b2 00 20 00 00 vexp2pd 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 72 80 vexp2pd -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 c8 b2 c0 df ff ff vexp2pd -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 72 7f vexp2pd 0x3f8\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 b2 00 04 00 00 vexp2pd 0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 72 80 vexp2pd -0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 c8 b2 f8 fb ff ff vexp2pd -0x408\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca f5 vrcp28ps %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f ca f5 vrcp28ps %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf ca f5 vrcp28ps %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 18 ca f5 vrcp28ps \{sae\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca 31 vrcp28ps \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca b4 f4 c0 1d fe ff vrcp28ps -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca 30 vrcp28ps \(%eax\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca 72 7f vrcp28ps 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca b2 00 20 00 00 vrcp28ps 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca 72 80 vrcp28ps -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 ca b2 c0 df ff ff vrcp28ps -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca 72 7f vrcp28ps 0x1fc\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca b2 00 02 00 00 vrcp28ps 0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca 72 80 vrcp28ps -0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 ca b2 fc fd ff ff vrcp28ps -0x204\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca f5 vrcp28pd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f ca f5 vrcp28pd %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf ca f5 vrcp28pd %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 18 ca f5 vrcp28pd \{sae\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca 31 vrcp28pd \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca b4 f4 c0 1d fe ff vrcp28pd -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca 30 vrcp28pd \(%eax\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca 72 7f vrcp28pd 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca b2 00 20 00 00 vrcp28pd 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca 72 80 vrcp28pd -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 ca b2 c0 df ff ff vrcp28pd -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca 72 7f vrcp28pd 0x3f8\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca b2 00 04 00 00 vrcp28pd 0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca 72 80 vrcp28pd -0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 ca b2 f8 fb ff ff vrcp28pd -0x408\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb f4 vrcp28ss %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 8f cb f4 vrcp28ss %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 1f cb f4 vrcp28ss \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb 31 vrcp28ss \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb b4 f4 c0 1d fe ff vrcp28ss -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb 72 7f vrcp28ss 0x1fc\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb b2 00 02 00 00 vrcp28ss 0x200\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb 72 80 vrcp28ss -0x200\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cb b2 fc fd ff ff vrcp28ss -0x204\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb f4 vrcp28sd %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 8f cb f4 vrcp28sd %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 1f cb f4 vrcp28sd \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb 31 vrcp28sd \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb b4 f4 c0 1d fe ff vrcp28sd -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb 72 7f vrcp28sd 0x3f8\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb b2 00 04 00 00 vrcp28sd 0x400\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb 72 80 vrcp28sd -0x400\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cb b2 f8 fb ff ff vrcp28sd -0x408\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc f5 vrsqrt28ps %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 4f cc f5 vrsqrt28ps %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d cf cc f5 vrsqrt28ps %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 18 cc f5 vrsqrt28ps \{sae\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc 31 vrsqrt28ps \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc b4 f4 c0 1d fe ff vrsqrt28ps -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc 30 vrsqrt28ps \(%eax\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc 72 7f vrsqrt28ps 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc b2 00 20 00 00 vrsqrt28ps 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc 72 80 vrsqrt28ps -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 48 cc b2 c0 df ff ff vrsqrt28ps -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc 72 7f vrsqrt28ps 0x1fc\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc b2 00 02 00 00 vrsqrt28ps 0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc 72 80 vrsqrt28ps -0x200\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 58 cc b2 fc fd ff ff vrsqrt28ps -0x204\(%edx\)\{1to16\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc f5 vrsqrt28pd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f cc f5 vrsqrt28pd %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf cc f5 vrsqrt28pd %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 18 cc f5 vrsqrt28pd \{sae\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc 31 vrsqrt28pd \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc b4 f4 c0 1d fe ff vrsqrt28pd -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc 30 vrsqrt28pd \(%eax\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc 72 7f vrsqrt28pd 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc b2 00 20 00 00 vrsqrt28pd 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc 72 80 vrsqrt28pd -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 48 cc b2 c0 df ff ff vrsqrt28pd -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc 72 7f vrsqrt28pd 0x3f8\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc b2 00 04 00 00 vrsqrt28pd 0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc 72 80 vrsqrt28pd -0x400\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 58 cc b2 f8 fb ff ff vrsqrt28pd -0x408\(%edx\)\{1to8\},%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd f4 vrsqrt28ss %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 8f cd f4 vrsqrt28ss %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 1f cd f4 vrsqrt28ss \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd 31 vrsqrt28ss \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd b4 f4 c0 1d fe ff vrsqrt28ss -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd 72 7f vrsqrt28ss 0x1fc\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd b2 00 02 00 00 vrsqrt28ss 0x200\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd 72 80 vrsqrt28ss -0x200\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 0f cd b2 fc fd ff ff vrsqrt28ss -0x204\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd f4 vrsqrt28sd %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 8f cd f4 vrsqrt28sd %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 1f cd f4 vrsqrt28sd \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd 31 vrsqrt28sd \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd b4 f4 c0 1d fe ff vrsqrt28sd -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd 72 7f vrsqrt28sd 0x3f8\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd b2 00 04 00 00 vrsqrt28sd 0x400\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd 72 80 vrsqrt28sd -0x400\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 d5 0f cd b2 f8 fb ff ff vrsqrt28sd -0x408\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
#pass
|
||||
|
|
@ -0,0 +1,271 @@
|
|||
# Check 32bit AVX512ER instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
vexp2ps %zmm5, %zmm6 # AVX512ER
|
||||
vexp2ps {sae}, %zmm5, %zmm6 # AVX512ER
|
||||
vexp2ps (%ecx), %zmm6 # AVX512ER
|
||||
vexp2ps -123456(%esp,%esi,8), %zmm6 # AVX512ER
|
||||
vexp2ps (%eax){1to16}, %zmm6 # AVX512ER
|
||||
vexp2ps 8128(%edx), %zmm6 # AVX512ER Disp8
|
||||
vexp2ps 8192(%edx), %zmm6 # AVX512ER
|
||||
vexp2ps -8192(%edx), %zmm6 # AVX512ER Disp8
|
||||
vexp2ps -8256(%edx), %zmm6 # AVX512ER
|
||||
vexp2ps 508(%edx){1to16}, %zmm6 # AVX512ER Disp8
|
||||
vexp2ps 512(%edx){1to16}, %zmm6 # AVX512ER
|
||||
vexp2ps -512(%edx){1to16}, %zmm6 # AVX512ER Disp8
|
||||
vexp2ps -516(%edx){1to16}, %zmm6 # AVX512ER
|
||||
|
||||
vexp2pd %zmm5, %zmm6 # AVX512ER
|
||||
vexp2pd {sae}, %zmm5, %zmm6 # AVX512ER
|
||||
vexp2pd (%ecx), %zmm6 # AVX512ER
|
||||
vexp2pd -123456(%esp,%esi,8), %zmm6 # AVX512ER
|
||||
vexp2pd (%eax){1to8}, %zmm6 # AVX512ER
|
||||
vexp2pd 8128(%edx), %zmm6 # AVX512ER Disp8
|
||||
vexp2pd 8192(%edx), %zmm6 # AVX512ER
|
||||
vexp2pd -8192(%edx), %zmm6 # AVX512ER Disp8
|
||||
vexp2pd -8256(%edx), %zmm6 # AVX512ER
|
||||
vexp2pd 1016(%edx){1to8}, %zmm6 # AVX512ER Disp8
|
||||
vexp2pd 1024(%edx){1to8}, %zmm6 # AVX512ER
|
||||
vexp2pd -1024(%edx){1to8}, %zmm6 # AVX512ER Disp8
|
||||
vexp2pd -1032(%edx){1to8}, %zmm6 # AVX512ER
|
||||
|
||||
vrcp28ps %zmm5, %zmm6 # AVX512ER
|
||||
vrcp28ps %zmm5, %zmm6{%k7} # AVX512ER
|
||||
vrcp28ps %zmm5, %zmm6{%k7}{z} # AVX512ER
|
||||
vrcp28ps {sae}, %zmm5, %zmm6 # AVX512ER
|
||||
vrcp28ps (%ecx), %zmm6 # AVX512ER
|
||||
vrcp28ps -123456(%esp,%esi,8), %zmm6 # AVX512ER
|
||||
vrcp28ps (%eax){1to16}, %zmm6 # AVX512ER
|
||||
vrcp28ps 8128(%edx), %zmm6 # AVX512ER Disp8
|
||||
vrcp28ps 8192(%edx), %zmm6 # AVX512ER
|
||||
vrcp28ps -8192(%edx), %zmm6 # AVX512ER Disp8
|
||||
vrcp28ps -8256(%edx), %zmm6 # AVX512ER
|
||||
vrcp28ps 508(%edx){1to16}, %zmm6 # AVX512ER Disp8
|
||||
vrcp28ps 512(%edx){1to16}, %zmm6 # AVX512ER
|
||||
vrcp28ps -512(%edx){1to16}, %zmm6 # AVX512ER Disp8
|
||||
vrcp28ps -516(%edx){1to16}, %zmm6 # AVX512ER
|
||||
|
||||
vrcp28pd %zmm5, %zmm6 # AVX512ER
|
||||
vrcp28pd %zmm5, %zmm6{%k7} # AVX512ER
|
||||
vrcp28pd %zmm5, %zmm6{%k7}{z} # AVX512ER
|
||||
vrcp28pd {sae}, %zmm5, %zmm6 # AVX512ER
|
||||
vrcp28pd (%ecx), %zmm6 # AVX512ER
|
||||
vrcp28pd -123456(%esp,%esi,8), %zmm6 # AVX512ER
|
||||
vrcp28pd (%eax){1to8}, %zmm6 # AVX512ER
|
||||
vrcp28pd 8128(%edx), %zmm6 # AVX512ER Disp8
|
||||
vrcp28pd 8192(%edx), %zmm6 # AVX512ER
|
||||
vrcp28pd -8192(%edx), %zmm6 # AVX512ER Disp8
|
||||
vrcp28pd -8256(%edx), %zmm6 # AVX512ER
|
||||
vrcp28pd 1016(%edx){1to8}, %zmm6 # AVX512ER Disp8
|
||||
vrcp28pd 1024(%edx){1to8}, %zmm6 # AVX512ER
|
||||
vrcp28pd -1024(%edx){1to8}, %zmm6 # AVX512ER Disp8
|
||||
vrcp28pd -1032(%edx){1to8}, %zmm6 # AVX512ER
|
||||
|
||||
vrcp28ss %xmm4, %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrcp28ss %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512ER
|
||||
vrcp28ss {sae}, %xmm4, %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrcp28ss (%ecx), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrcp28ss -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrcp28ss 508(%edx), %xmm5, %xmm6{%k7} # AVX512ER Disp8
|
||||
vrcp28ss 512(%edx), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrcp28ss -512(%edx), %xmm5, %xmm6{%k7} # AVX512ER Disp8
|
||||
vrcp28ss -516(%edx), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
|
||||
vrcp28sd %xmm4, %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrcp28sd %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512ER
|
||||
vrcp28sd {sae}, %xmm4, %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrcp28sd (%ecx), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrcp28sd -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrcp28sd 1016(%edx), %xmm5, %xmm6{%k7} # AVX512ER Disp8
|
||||
vrcp28sd 1024(%edx), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrcp28sd -1024(%edx), %xmm5, %xmm6{%k7} # AVX512ER Disp8
|
||||
vrcp28sd -1032(%edx), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
|
||||
vrsqrt28ps %zmm5, %zmm6 # AVX512ER
|
||||
vrsqrt28ps %zmm5, %zmm6{%k7} # AVX512ER
|
||||
vrsqrt28ps %zmm5, %zmm6{%k7}{z} # AVX512ER
|
||||
vrsqrt28ps {sae}, %zmm5, %zmm6 # AVX512ER
|
||||
vrsqrt28ps (%ecx), %zmm6 # AVX512ER
|
||||
vrsqrt28ps -123456(%esp,%esi,8), %zmm6 # AVX512ER
|
||||
vrsqrt28ps (%eax){1to16}, %zmm6 # AVX512ER
|
||||
vrsqrt28ps 8128(%edx), %zmm6 # AVX512ER Disp8
|
||||
vrsqrt28ps 8192(%edx), %zmm6 # AVX512ER
|
||||
vrsqrt28ps -8192(%edx), %zmm6 # AVX512ER Disp8
|
||||
vrsqrt28ps -8256(%edx), %zmm6 # AVX512ER
|
||||
vrsqrt28ps 508(%edx){1to16}, %zmm6 # AVX512ER Disp8
|
||||
vrsqrt28ps 512(%edx){1to16}, %zmm6 # AVX512ER
|
||||
vrsqrt28ps -512(%edx){1to16}, %zmm6 # AVX512ER Disp8
|
||||
vrsqrt28ps -516(%edx){1to16}, %zmm6 # AVX512ER
|
||||
|
||||
vrsqrt28pd %zmm5, %zmm6 # AVX512ER
|
||||
vrsqrt28pd %zmm5, %zmm6{%k7} # AVX512ER
|
||||
vrsqrt28pd %zmm5, %zmm6{%k7}{z} # AVX512ER
|
||||
vrsqrt28pd {sae}, %zmm5, %zmm6 # AVX512ER
|
||||
vrsqrt28pd (%ecx), %zmm6 # AVX512ER
|
||||
vrsqrt28pd -123456(%esp,%esi,8), %zmm6 # AVX512ER
|
||||
vrsqrt28pd (%eax){1to8}, %zmm6 # AVX512ER
|
||||
vrsqrt28pd 8128(%edx), %zmm6 # AVX512ER Disp8
|
||||
vrsqrt28pd 8192(%edx), %zmm6 # AVX512ER
|
||||
vrsqrt28pd -8192(%edx), %zmm6 # AVX512ER Disp8
|
||||
vrsqrt28pd -8256(%edx), %zmm6 # AVX512ER
|
||||
vrsqrt28pd 1016(%edx){1to8}, %zmm6 # AVX512ER Disp8
|
||||
vrsqrt28pd 1024(%edx){1to8}, %zmm6 # AVX512ER
|
||||
vrsqrt28pd -1024(%edx){1to8}, %zmm6 # AVX512ER Disp8
|
||||
vrsqrt28pd -1032(%edx){1to8}, %zmm6 # AVX512ER
|
||||
|
||||
vrsqrt28ss %xmm4, %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrsqrt28ss %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512ER
|
||||
vrsqrt28ss {sae}, %xmm4, %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrsqrt28ss (%ecx), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrsqrt28ss -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrsqrt28ss 508(%edx), %xmm5, %xmm6{%k7} # AVX512ER Disp8
|
||||
vrsqrt28ss 512(%edx), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrsqrt28ss -512(%edx), %xmm5, %xmm6{%k7} # AVX512ER Disp8
|
||||
vrsqrt28ss -516(%edx), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
|
||||
vrsqrt28sd %xmm4, %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrsqrt28sd %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512ER
|
||||
vrsqrt28sd {sae}, %xmm4, %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrsqrt28sd (%ecx), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrsqrt28sd -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrsqrt28sd 1016(%edx), %xmm5, %xmm6{%k7} # AVX512ER Disp8
|
||||
vrsqrt28sd 1024(%edx), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
vrsqrt28sd -1024(%edx), %xmm5, %xmm6{%k7} # AVX512ER Disp8
|
||||
vrsqrt28sd -1032(%edx), %xmm5, %xmm6{%k7} # AVX512ER
|
||||
|
||||
.intel_syntax noprefix
|
||||
vexp2ps zmm6, zmm5 # AVX512ER
|
||||
vexp2ps zmm6, zmm5, {sae} # AVX512ER
|
||||
vexp2ps zmm6, ZMMWORD PTR [ecx] # AVX512ER
|
||||
vexp2ps zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512ER
|
||||
vexp2ps zmm6, [eax]{1to16} # AVX512ER
|
||||
vexp2ps zmm6, ZMMWORD PTR [edx+8128] # AVX512ER Disp8
|
||||
vexp2ps zmm6, ZMMWORD PTR [edx+8192] # AVX512ER
|
||||
vexp2ps zmm6, ZMMWORD PTR [edx-8192] # AVX512ER Disp8
|
||||
vexp2ps zmm6, ZMMWORD PTR [edx-8256] # AVX512ER
|
||||
vexp2ps zmm6, [edx+508]{1to16} # AVX512ER Disp8
|
||||
vexp2ps zmm6, [edx+512]{1to16} # AVX512ER
|
||||
vexp2ps zmm6, [edx-512]{1to16} # AVX512ER Disp8
|
||||
vexp2ps zmm6, [edx-516]{1to16} # AVX512ER
|
||||
|
||||
vexp2pd zmm6, zmm5 # AVX512ER
|
||||
vexp2pd zmm6, zmm5, {sae} # AVX512ER
|
||||
vexp2pd zmm6, ZMMWORD PTR [ecx] # AVX512ER
|
||||
vexp2pd zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512ER
|
||||
vexp2pd zmm6, [eax]{1to8} # AVX512ER
|
||||
vexp2pd zmm6, ZMMWORD PTR [edx+8128] # AVX512ER Disp8
|
||||
vexp2pd zmm6, ZMMWORD PTR [edx+8192] # AVX512ER
|
||||
vexp2pd zmm6, ZMMWORD PTR [edx-8192] # AVX512ER Disp8
|
||||
vexp2pd zmm6, ZMMWORD PTR [edx-8256] # AVX512ER
|
||||
vexp2pd zmm6, [edx+1016]{1to8} # AVX512ER Disp8
|
||||
vexp2pd zmm6, [edx+1024]{1to8} # AVX512ER
|
||||
vexp2pd zmm6, [edx-1024]{1to8} # AVX512ER Disp8
|
||||
vexp2pd zmm6, [edx-1032]{1to8} # AVX512ER
|
||||
|
||||
vrcp28ps zmm6, zmm5 # AVX512ER
|
||||
vrcp28ps zmm6{k7}, zmm5 # AVX512ER
|
||||
vrcp28ps zmm6{k7}{z}, zmm5 # AVX512ER
|
||||
vrcp28ps zmm6, zmm5, {sae} # AVX512ER
|
||||
vrcp28ps zmm6, ZMMWORD PTR [ecx] # AVX512ER
|
||||
vrcp28ps zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512ER
|
||||
vrcp28ps zmm6, [eax]{1to16} # AVX512ER
|
||||
vrcp28ps zmm6, ZMMWORD PTR [edx+8128] # AVX512ER Disp8
|
||||
vrcp28ps zmm6, ZMMWORD PTR [edx+8192] # AVX512ER
|
||||
vrcp28ps zmm6, ZMMWORD PTR [edx-8192] # AVX512ER Disp8
|
||||
vrcp28ps zmm6, ZMMWORD PTR [edx-8256] # AVX512ER
|
||||
vrcp28ps zmm6, [edx+508]{1to16} # AVX512ER Disp8
|
||||
vrcp28ps zmm6, [edx+512]{1to16} # AVX512ER
|
||||
vrcp28ps zmm6, [edx-512]{1to16} # AVX512ER Disp8
|
||||
vrcp28ps zmm6, [edx-516]{1to16} # AVX512ER
|
||||
|
||||
vrcp28pd zmm6, zmm5 # AVX512ER
|
||||
vrcp28pd zmm6{k7}, zmm5 # AVX512ER
|
||||
vrcp28pd zmm6{k7}{z}, zmm5 # AVX512ER
|
||||
vrcp28pd zmm6, zmm5, {sae} # AVX512ER
|
||||
vrcp28pd zmm6, ZMMWORD PTR [ecx] # AVX512ER
|
||||
vrcp28pd zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512ER
|
||||
vrcp28pd zmm6, [eax]{1to8} # AVX512ER
|
||||
vrcp28pd zmm6, ZMMWORD PTR [edx+8128] # AVX512ER Disp8
|
||||
vrcp28pd zmm6, ZMMWORD PTR [edx+8192] # AVX512ER
|
||||
vrcp28pd zmm6, ZMMWORD PTR [edx-8192] # AVX512ER Disp8
|
||||
vrcp28pd zmm6, ZMMWORD PTR [edx-8256] # AVX512ER
|
||||
vrcp28pd zmm6, [edx+1016]{1to8} # AVX512ER Disp8
|
||||
vrcp28pd zmm6, [edx+1024]{1to8} # AVX512ER
|
||||
vrcp28pd zmm6, [edx-1024]{1to8} # AVX512ER Disp8
|
||||
vrcp28pd zmm6, [edx-1032]{1to8} # AVX512ER
|
||||
|
||||
vrcp28ss xmm6{k7}, xmm5, xmm4 # AVX512ER
|
||||
vrcp28ss xmm6{k7}{z}, xmm5, xmm4 # AVX512ER
|
||||
vrcp28ss xmm6{k7}, xmm5, xmm4, {sae} # AVX512ER
|
||||
vrcp28ss xmm6{k7}, xmm5, DWORD PTR [ecx] # AVX512ER
|
||||
vrcp28ss xmm6{k7}, xmm5, DWORD PTR [esp+esi*8-123456] # AVX512ER
|
||||
vrcp28ss xmm6{k7}, xmm5, DWORD PTR [edx+508] # AVX512ER Disp8
|
||||
vrcp28ss xmm6{k7}, xmm5, DWORD PTR [edx+512] # AVX512ER
|
||||
vrcp28ss xmm6{k7}, xmm5, DWORD PTR [edx-512] # AVX512ER Disp8
|
||||
vrcp28ss xmm6{k7}, xmm5, DWORD PTR [edx-516] # AVX512ER
|
||||
|
||||
vrcp28sd xmm6{k7}, xmm5, xmm4 # AVX512ER
|
||||
vrcp28sd xmm6{k7}{z}, xmm5, xmm4 # AVX512ER
|
||||
vrcp28sd xmm6{k7}, xmm5, xmm4, {sae} # AVX512ER
|
||||
vrcp28sd xmm6{k7}, xmm5, QWORD PTR [ecx] # AVX512ER
|
||||
vrcp28sd xmm6{k7}, xmm5, QWORD PTR [esp+esi*8-123456] # AVX512ER
|
||||
vrcp28sd xmm6{k7}, xmm5, QWORD PTR [edx+1016] # AVX512ER Disp8
|
||||
vrcp28sd xmm6{k7}, xmm5, QWORD PTR [edx+1024] # AVX512ER
|
||||
vrcp28sd xmm6{k7}, xmm5, QWORD PTR [edx-1024] # AVX512ER Disp8
|
||||
vrcp28sd xmm6{k7}, xmm5, QWORD PTR [edx-1032] # AVX512ER
|
||||
|
||||
vrsqrt28ps zmm6, zmm5 # AVX512ER
|
||||
vrsqrt28ps zmm6{k7}, zmm5 # AVX512ER
|
||||
vrsqrt28ps zmm6{k7}{z}, zmm5 # AVX512ER
|
||||
vrsqrt28ps zmm6, zmm5, {sae} # AVX512ER
|
||||
vrsqrt28ps zmm6, ZMMWORD PTR [ecx] # AVX512ER
|
||||
vrsqrt28ps zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512ER
|
||||
vrsqrt28ps zmm6, [eax]{1to16} # AVX512ER
|
||||
vrsqrt28ps zmm6, ZMMWORD PTR [edx+8128] # AVX512ER Disp8
|
||||
vrsqrt28ps zmm6, ZMMWORD PTR [edx+8192] # AVX512ER
|
||||
vrsqrt28ps zmm6, ZMMWORD PTR [edx-8192] # AVX512ER Disp8
|
||||
vrsqrt28ps zmm6, ZMMWORD PTR [edx-8256] # AVX512ER
|
||||
vrsqrt28ps zmm6, [edx+508]{1to16} # AVX512ER Disp8
|
||||
vrsqrt28ps zmm6, [edx+512]{1to16} # AVX512ER
|
||||
vrsqrt28ps zmm6, [edx-512]{1to16} # AVX512ER Disp8
|
||||
vrsqrt28ps zmm6, [edx-516]{1to16} # AVX512ER
|
||||
|
||||
vrsqrt28pd zmm6, zmm5 # AVX512ER
|
||||
vrsqrt28pd zmm6{k7}, zmm5 # AVX512ER
|
||||
vrsqrt28pd zmm6{k7}{z}, zmm5 # AVX512ER
|
||||
vrsqrt28pd zmm6, zmm5, {sae} # AVX512ER
|
||||
vrsqrt28pd zmm6, ZMMWORD PTR [ecx] # AVX512ER
|
||||
vrsqrt28pd zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512ER
|
||||
vrsqrt28pd zmm6, [eax]{1to8} # AVX512ER
|
||||
vrsqrt28pd zmm6, ZMMWORD PTR [edx+8128] # AVX512ER Disp8
|
||||
vrsqrt28pd zmm6, ZMMWORD PTR [edx+8192] # AVX512ER
|
||||
vrsqrt28pd zmm6, ZMMWORD PTR [edx-8192] # AVX512ER Disp8
|
||||
vrsqrt28pd zmm6, ZMMWORD PTR [edx-8256] # AVX512ER
|
||||
vrsqrt28pd zmm6, [edx+1016]{1to8} # AVX512ER Disp8
|
||||
vrsqrt28pd zmm6, [edx+1024]{1to8} # AVX512ER
|
||||
vrsqrt28pd zmm6, [edx-1024]{1to8} # AVX512ER Disp8
|
||||
vrsqrt28pd zmm6, [edx-1032]{1to8} # AVX512ER
|
||||
|
||||
vrsqrt28ss xmm6{k7}, xmm5, xmm4 # AVX512ER
|
||||
vrsqrt28ss xmm6{k7}{z}, xmm5, xmm4 # AVX512ER
|
||||
vrsqrt28ss xmm6{k7}, xmm5, xmm4, {sae} # AVX512ER
|
||||
vrsqrt28ss xmm6{k7}, xmm5, DWORD PTR [ecx] # AVX512ER
|
||||
vrsqrt28ss xmm6{k7}, xmm5, DWORD PTR [esp+esi*8-123456] # AVX512ER
|
||||
vrsqrt28ss xmm6{k7}, xmm5, DWORD PTR [edx+508] # AVX512ER Disp8
|
||||
vrsqrt28ss xmm6{k7}, xmm5, DWORD PTR [edx+512] # AVX512ER
|
||||
vrsqrt28ss xmm6{k7}, xmm5, DWORD PTR [edx-512] # AVX512ER Disp8
|
||||
vrsqrt28ss xmm6{k7}, xmm5, DWORD PTR [edx-516] # AVX512ER
|
||||
|
||||
vrsqrt28sd xmm6{k7}, xmm5, xmm4 # AVX512ER
|
||||
vrsqrt28sd xmm6{k7}{z}, xmm5, xmm4 # AVX512ER
|
||||
vrsqrt28sd xmm6{k7}, xmm5, xmm4, {sae} # AVX512ER
|
||||
vrsqrt28sd xmm6{k7}, xmm5, QWORD PTR [ecx] # AVX512ER
|
||||
vrsqrt28sd xmm6{k7}, xmm5, QWORD PTR [esp+esi*8-123456] # AVX512ER
|
||||
vrsqrt28sd xmm6{k7}, xmm5, QWORD PTR [edx+1016] # AVX512ER Disp8
|
||||
vrsqrt28sd xmm6{k7}, xmm5, QWORD PTR [edx+1024] # AVX512ER
|
||||
vrsqrt28sd xmm6{k7}, xmm5, QWORD PTR [edx-1024] # AVX512ER Disp8
|
||||
vrsqrt28sd xmm6{k7}, xmm5, QWORD PTR [edx-1032] # AVX512ER
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,19 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: i386 AVX512F insns with nondefault values in ignored bits
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <.text>:
|
||||
[ ]*[a-f0-9]+: 62 f3 d5 1f 0b f4 7b vrndscalesd \$0x7b,\{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f3 d5 5f 0b f4 7b vrndscalesd \$0x7b,\{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 1f 3b f4 vpminud %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 c2 55 1f 3b f4 vpminud %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7e 48 31 72 7f vpmovdb %zmm6,0x7f0\(%edx\)
|
||||
[ ]*[a-f0-9]+: 62 vpmovdb %zmm6,\(bad\)
|
||||
[ ]*[a-f0-9]+: f2 7e 58 bnd jle 0x7d
|
||||
[ ]*[a-f0-9]+: 31 72 7f xor %esi,0x7f\(%edx\)
|
||||
#pass
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# Check if objdump works correctly when some bits in instruction
|
||||
# has non-default value
|
||||
|
||||
# vrndscalesd {sae}, $123, %xmm4, %xmm5, %xmm6{%k7} # with null RC
|
||||
.byte 0x62, 0xf3, 0xd5, 0x1f, 0x0b, 0xf4, 0x7b
|
||||
# vrndscalesd {sae}, $123, %xmm4, %xmm5, %xmm6{%k7} # with not-null RC
|
||||
.byte 0x62, 0xf3, 0xd5, 0x5f, 0x0b, 0xf4, 0x7b
|
||||
# vpminud %zmm4, %zmm5, %zmm6{%k7} # with 111 REX
|
||||
.byte 0x62, 0xf2, 0x55, 0x1f, 0x3b, 0xf4
|
||||
# vpminud %zmm4, %zmm5, %zmm6{%k7} # with not-111 REX
|
||||
.byte 0x62, 0xc2, 0x55, 0x1f, 0x3b, 0xf4
|
||||
# vpmovdb %zmm6, 2032(%rdx) # with unset EVEX.B bit
|
||||
.byte 0x62, 0xf2, 0x7e, 0x48, 0x31, 0x72, 0x7f
|
||||
# vpmovdb %zmm6, 2032(%rdx) # with set EVEX.B bit - we should get (bad) operand
|
||||
.byte 0x62, 0xf2, 0x7e, 0x58, 0x31, 0x72, 0x7f
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
#as:
|
||||
#objdump: -dwMintel -Msuffix
|
||||
#name: i386 AVX512F opts insns (Intel disassembly)
|
||||
#source: avx512f-opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 29 ee vmovapd.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 28 f5 vmovapd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 29 ee vmovapd.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 28 f5 vmovapd zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 29 ee vmovapd.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 28 f5 vmovapd zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 29 ee vmovaps.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 28 f5 vmovaps zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 29 ee vmovaps.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 28 f5 vmovaps zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 29 ee vmovaps.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 28 f5 vmovaps zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 48 7f ee vmovdqa32.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 48 6f f5 vmovdqa32 zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 4f 7f ee vmovdqa32.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 4f 6f f5 vmovdqa32 zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7d cf 7f ee vmovdqa32.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7d cf 6f f5 vmovdqa32 zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 7f ee vmovdqa64.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 6f f5 vmovdqa64 zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 7f ee vmovdqa64.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 6f f5 vmovdqa64 zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 7f ee vmovdqa64.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 6f f5 vmovdqa64 zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 48 7f ee vmovdqu32.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 48 6f f5 vmovdqu32 zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 4f 7f ee vmovdqu32.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 4f 6f f5 vmovdqu32 zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7e cf 7f ee vmovdqu32.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7e cf 6f f5 vmovdqu32 zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 48 7f ee vmovdqu64.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 48 6f f5 vmovdqu64 zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 4f 7f ee vmovdqu64.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 4f 6f f5 vmovdqu64 zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fe cf 7f ee vmovdqu64.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fe cf 6f f5 vmovdqu64 zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 0f 11 e6 vmovsd.s xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 0f 10 f4 vmovsd xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 8f 11 e6 vmovsd.s xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 8f 10 f4 vmovsd xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 56 0f 11 e6 vmovss.s xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 56 0f 10 f4 vmovss xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 56 8f 11 e6 vmovss.s xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 56 8f 10 f4 vmovss xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 11 ee vmovupd.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 10 f5 vmovupd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 11 ee vmovupd.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 10 f5 vmovupd zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 11 ee vmovupd.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 10 f5 vmovupd zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 11 ee vmovups.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 10 f5 vmovups zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 11 ee vmovups.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 10 f5 vmovups zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 11 ee vmovups.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 10 f5 vmovups zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 29 ee vmovapd.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 28 f5 vmovapd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 29 ee vmovapd.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 28 f5 vmovapd zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 29 ee vmovapd.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 28 f5 vmovapd zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 29 ee vmovaps.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 28 f5 vmovaps zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 29 ee vmovaps.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 28 f5 vmovaps zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 29 ee vmovaps.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 28 f5 vmovaps zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 48 7f ee vmovdqa32.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 48 6f f5 vmovdqa32 zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 4f 7f ee vmovdqa32.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 4f 6f f5 vmovdqa32 zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7d cf 7f ee vmovdqa32.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7d cf 6f f5 vmovdqa32 zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 7f ee vmovdqa64.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 6f f5 vmovdqa64 zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 7f ee vmovdqa64.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 6f f5 vmovdqa64 zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 7f ee vmovdqa64.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 6f f5 vmovdqa64 zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 48 7f ee vmovdqu32.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 48 6f f5 vmovdqu32 zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 4f 7f ee vmovdqu32.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 4f 6f f5 vmovdqu32 zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7e cf 7f ee vmovdqu32.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7e cf 6f f5 vmovdqu32 zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 48 7f ee vmovdqu64.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 48 6f f5 vmovdqu64 zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 4f 7f ee vmovdqu64.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 4f 6f f5 vmovdqu64 zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fe cf 7f ee vmovdqu64.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fe cf 6f f5 vmovdqu64 zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 0f 11 e6 vmovsd.s xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 0f 10 f4 vmovsd xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 8f 11 e6 vmovsd.s xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 8f 10 f4 vmovsd xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 56 0f 11 e6 vmovss.s xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 56 0f 10 f4 vmovss xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 56 8f 11 e6 vmovss.s xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 56 8f 10 f4 vmovss xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 11 ee vmovupd.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 10 f5 vmovupd zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 11 ee vmovupd.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 10 f5 vmovupd zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 11 ee vmovupd.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 10 f5 vmovupd zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 11 ee vmovups.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 10 f5 vmovups zmm6,zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 11 ee vmovups.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 10 f5 vmovups zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 11 ee vmovups.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 10 f5 vmovups zmm6\{k7\}\{z\},zmm5
|
||||
#pass
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
#as:
|
||||
#objdump: -dw -Msuffix
|
||||
#name: i386 AVX512F opts insns
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 29 ee vmovapd.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 28 f5 vmovapd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 29 ee vmovapd.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 28 f5 vmovapd %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 29 ee vmovapd.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 28 f5 vmovapd %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 29 ee vmovaps.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 28 f5 vmovaps %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 29 ee vmovaps.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 28 f5 vmovaps %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 29 ee vmovaps.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 28 f5 vmovaps %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 48 7f ee vmovdqa32.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 48 6f f5 vmovdqa32 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 4f 7f ee vmovdqa32.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 4f 6f f5 vmovdqa32 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7d cf 7f ee vmovdqa32.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7d cf 6f f5 vmovdqa32 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 7f ee vmovdqa64.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 6f f5 vmovdqa64 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 7f ee vmovdqa64.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 6f f5 vmovdqa64 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 7f ee vmovdqa64.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 6f f5 vmovdqa64 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 48 7f ee vmovdqu32.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 48 6f f5 vmovdqu32 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 4f 7f ee vmovdqu32.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 4f 6f f5 vmovdqu32 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7e cf 7f ee vmovdqu32.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7e cf 6f f5 vmovdqu32 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 48 7f ee vmovdqu64.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 48 6f f5 vmovdqu64 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 4f 7f ee vmovdqu64.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 4f 6f f5 vmovdqu64 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fe cf 7f ee vmovdqu64.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fe cf 6f f5 vmovdqu64 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 0f 11 e6 vmovsd.s %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 0f 10 f4 vmovsd %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 8f 11 e6 vmovsd.s %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 8f 10 f4 vmovsd %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 56 0f 11 e6 vmovss.s %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 56 0f 10 f4 vmovss %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 56 8f 11 e6 vmovss.s %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 56 8f 10 f4 vmovss %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 11 ee vmovupd.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 10 f5 vmovupd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 11 ee vmovupd.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 10 f5 vmovupd %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 11 ee vmovupd.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 10 f5 vmovupd %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 11 ee vmovups.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 10 f5 vmovups %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 11 ee vmovups.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 10 f5 vmovups %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 11 ee vmovups.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 10 f5 vmovups %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 29 ee vmovapd.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 28 f5 vmovapd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 29 ee vmovapd.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 28 f5 vmovapd %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 29 ee vmovapd.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 28 f5 vmovapd %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 29 ee vmovaps.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 28 f5 vmovaps %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 29 ee vmovaps.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 28 f5 vmovaps %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 29 ee vmovaps.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 28 f5 vmovaps %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 48 7f ee vmovdqa32.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 48 6f f5 vmovdqa32 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 4f 7f ee vmovdqa32.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7d 4f 6f f5 vmovdqa32 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7d cf 7f ee vmovdqa32.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7d cf 6f f5 vmovdqa32 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 7f ee vmovdqa64.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 6f f5 vmovdqa64 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 7f ee vmovdqa64.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 6f f5 vmovdqa64 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 7f ee vmovdqa64.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 6f f5 vmovdqa64 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 48 7f ee vmovdqu32.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 48 6f f5 vmovdqu32 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 4f 7f ee vmovdqu32.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7e 4f 6f f5 vmovdqu32 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7e cf 7f ee vmovdqu32.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7e cf 6f f5 vmovdqu32 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 48 7f ee vmovdqu64.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 48 6f f5 vmovdqu64 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 4f 7f ee vmovdqu64.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fe 4f 6f f5 vmovdqu64 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fe cf 7f ee vmovdqu64.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fe cf 6f f5 vmovdqu64 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 0f 11 e6 vmovsd.s %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 0f 10 f4 vmovsd %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 8f 11 e6 vmovsd.s %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 d7 8f 10 f4 vmovsd %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 56 0f 11 e6 vmovss.s %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 56 0f 10 f4 vmovss %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 56 8f 11 e6 vmovss.s %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 56 8f 10 f4 vmovss %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 11 ee vmovupd.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 48 10 f5 vmovupd %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 11 ee vmovupd.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd 4f 10 f5 vmovupd %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 11 ee vmovupd.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 fd cf 10 f5 vmovupd %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 11 ee vmovups.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 48 10 f5 vmovups %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 11 ee vmovups.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c 4f 10 f5 vmovups %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 11 ee vmovups.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f1 7c cf 10 f5 vmovups %zmm5,%zmm6\{%k7\}\{z\}
|
||||
#pass
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
# Check 32bit AVX512F instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
vmovapd.s %zmm5, %zmm6 # AVX512F
|
||||
vmovapd %zmm5, %zmm6 # AVX512F
|
||||
vmovapd.s %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovapd %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovapd.s %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovapd %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovaps.s %zmm5, %zmm6 # AVX512F
|
||||
vmovaps %zmm5, %zmm6 # AVX512F
|
||||
vmovaps.s %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovaps %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovaps.s %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovaps %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovdqa32.s %zmm5, %zmm6 # AVX512F
|
||||
vmovdqa32 %zmm5, %zmm6 # AVX512F
|
||||
vmovdqa32.s %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovdqa32 %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovdqa32.s %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovdqa32 %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovdqa64.s %zmm5, %zmm6 # AVX512F
|
||||
vmovdqa64 %zmm5, %zmm6 # AVX512F
|
||||
vmovdqa64.s %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovdqa64 %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovdqa64.s %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovdqa64 %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovdqu32.s %zmm5, %zmm6 # AVX512F
|
||||
vmovdqu32 %zmm5, %zmm6 # AVX512F
|
||||
vmovdqu32.s %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovdqu32 %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovdqu32.s %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovdqu32 %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovdqu64.s %zmm5, %zmm6 # AVX512F
|
||||
vmovdqu64 %zmm5, %zmm6 # AVX512F
|
||||
vmovdqu64.s %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovdqu64 %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovdqu64.s %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovdqu64 %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovsd.s %xmm4, %xmm5, %xmm6{%k7} # AVX512F
|
||||
vmovsd %xmm4, %xmm5, %xmm6{%k7} # AVX512F
|
||||
vmovsd.s %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512F
|
||||
vmovsd %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512F
|
||||
vmovss.s %xmm4, %xmm5, %xmm6{%k7} # AVX512F
|
||||
vmovss %xmm4, %xmm5, %xmm6{%k7} # AVX512F
|
||||
vmovss.s %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512F
|
||||
vmovss %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512F
|
||||
vmovupd.s %zmm5, %zmm6 # AVX512F
|
||||
vmovupd %zmm5, %zmm6 # AVX512F
|
||||
vmovupd.s %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovupd %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovupd.s %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovupd %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovups.s %zmm5, %zmm6 # AVX512F
|
||||
vmovups %zmm5, %zmm6 # AVX512F
|
||||
vmovups.s %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovups %zmm5, %zmm6{%k7} # AVX512F
|
||||
vmovups.s %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
vmovups %zmm5, %zmm6{%k7}{z} # AVX512F
|
||||
.intel_syntax noprefix
|
||||
vmovapd.s zmm6, zmm5 # AVX512F
|
||||
vmovapd zmm6, zmm5 # AVX512F
|
||||
vmovapd.s zmm6{k7}, zmm5 # AVX512F
|
||||
vmovapd zmm6{k7}, zmm5 # AVX512F
|
||||
vmovapd.s zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovapd zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovaps.s zmm6, zmm5 # AVX512F
|
||||
vmovaps zmm6, zmm5 # AVX512F
|
||||
vmovaps.s zmm6{k7}, zmm5 # AVX512F
|
||||
vmovaps zmm6{k7}, zmm5 # AVX512F
|
||||
vmovaps.s zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovaps zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovdqa32.s zmm6, zmm5 # AVX512F
|
||||
vmovdqa32 zmm6, zmm5 # AVX512F
|
||||
vmovdqa32.s zmm6{k7}, zmm5 # AVX512F
|
||||
vmovdqa32 zmm6{k7}, zmm5 # AVX512F
|
||||
vmovdqa32.s zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovdqa32 zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovdqa64.s zmm6, zmm5 # AVX512F
|
||||
vmovdqa64 zmm6, zmm5 # AVX512F
|
||||
vmovdqa64.s zmm6{k7}, zmm5 # AVX512F
|
||||
vmovdqa64 zmm6{k7}, zmm5 # AVX512F
|
||||
vmovdqa64.s zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovdqa64 zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovdqu32.s zmm6, zmm5 # AVX512F
|
||||
vmovdqu32 zmm6, zmm5 # AVX512F
|
||||
vmovdqu32.s zmm6{k7}, zmm5 # AVX512F
|
||||
vmovdqu32 zmm6{k7}, zmm5 # AVX512F
|
||||
vmovdqu32.s zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovdqu32 zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovdqu64.s zmm6, zmm5 # AVX512F
|
||||
vmovdqu64 zmm6, zmm5 # AVX512F
|
||||
vmovdqu64.s zmm6{k7}, zmm5 # AVX512F
|
||||
vmovdqu64 zmm6{k7}, zmm5 # AVX512F
|
||||
vmovdqu64.s zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovdqu64 zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovsd.s xmm6{k7}, xmm5, xmm4 # AVX512F
|
||||
vmovsd xmm6{k7}, xmm5, xmm4 # AVX512F
|
||||
vmovsd.s xmm6{k7}{z}, xmm5, xmm4 # AVX512F
|
||||
vmovsd xmm6{k7}{z}, xmm5, xmm4 # AVX512F
|
||||
vmovss.s xmm6{k7}, xmm5, xmm4 # AVX512F
|
||||
vmovss xmm6{k7}, xmm5, xmm4 # AVX512F
|
||||
vmovss.s xmm6{k7}{z}, xmm5, xmm4 # AVX512F
|
||||
vmovss xmm6{k7}{z}, xmm5, xmm4 # AVX512F
|
||||
vmovupd.s zmm6, zmm5 # AVX512F
|
||||
vmovupd zmm6, zmm5 # AVX512F
|
||||
vmovupd.s zmm6{k7}, zmm5 # AVX512F
|
||||
vmovupd zmm6{k7}, zmm5 # AVX512F
|
||||
vmovupd.s zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovupd zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovups.s zmm6, zmm5 # AVX512F
|
||||
vmovups zmm6, zmm5 # AVX512F
|
||||
vmovups.s zmm6{k7}, zmm5 # AVX512F
|
||||
vmovups zmm6{k7}, zmm5 # AVX512F
|
||||
vmovups.s zmm6{k7}{z}, zmm5 # AVX512F
|
||||
vmovups zmm6{k7}{z}, zmm5 # AVX512F
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,144 @@
|
|||
#as:
|
||||
#objdump: -dwMintel
|
||||
#name: i386 AVX512PF insns (Intel disassembly)
|
||||
#source: avx512pf.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 4c 38 20 vgatherpf0dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c b9 00 04 00 00 vgatherpf0dpd ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 4c 38 40 vgatherpf0dps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c b9 00 04 00 00 vgatherpf0dps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 4c 38 20 vgatherpf0qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c b9 00 04 00 00 vgatherpf0qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 7b 00 00 00 vgatherpf0qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 7b 00 00 00 vgatherpf0qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 4c 38 40 vgatherpf0qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c b9 00 04 00 00 vgatherpf0qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 7b 00 00 00 vgatherpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 7b 00 00 00 vgatherpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 54 38 20 vgatherpf1dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 b9 00 04 00 00 vgatherpf1dpd ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 94 fd 7b 00 00 00 vgatherpf1dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 94 fd 7b 00 00 00 vgatherpf1dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 54 38 40 vgatherpf1dps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 94 b9 00 04 00 00 vgatherpf1dps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 fd 7b 00 00 00 vgatherpf1qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 fd 7b 00 00 00 vgatherpf1qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 54 38 20 vgatherpf1qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 b9 00 04 00 00 vgatherpf1qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 7b 00 00 00 vgatherpf1qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 7b 00 00 00 vgatherpf1qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 54 38 40 vgatherpf1qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 b9 00 04 00 00 vgatherpf1qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac fd 7b 00 00 00 vscatterpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac fd 7b 00 00 00 vscatterpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 6c 38 20 vscatterpf0dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac b9 00 04 00 00 vscatterpf0dpd ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 ac fd 7b 00 00 00 vscatterpf0dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 ac fd 7b 00 00 00 vscatterpf0dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 6c 38 40 vscatterpf0dps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 ac b9 00 04 00 00 vscatterpf0dps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac fd 7b 00 00 00 vscatterpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac fd 7b 00 00 00 vscatterpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 6c 38 20 vscatterpf0qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac b9 00 04 00 00 vscatterpf0qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 7b 00 00 00 vscatterpf0qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 7b 00 00 00 vscatterpf0qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 6c 38 40 vscatterpf0qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac b9 00 04 00 00 vscatterpf0qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 fd 7b 00 00 00 vscatterpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 fd 7b 00 00 00 vscatterpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 74 38 20 vscatterpf1dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 b9 00 04 00 00 vscatterpf1dpd ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 b4 fd 7b 00 00 00 vscatterpf1dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 b4 fd 7b 00 00 00 vscatterpf1dps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 74 38 40 vscatterpf1dps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 b4 b9 00 04 00 00 vscatterpf1dps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 fd 7b 00 00 00 vscatterpf1qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 fd 7b 00 00 00 vscatterpf1qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 74 38 20 vscatterpf1qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 b9 00 04 00 00 vscatterpf1qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 7b 00 00 00 vscatterpf1qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 7b 00 00 00 vscatterpf1qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 74 38 40 vscatterpf1qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 b9 00 04 00 00 vscatterpf1qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 BYTE PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 0f 0d 94 f4 c0 1d fe ff prefetchwt1 BYTE PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 85 ff ff ff vgatherpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 85 ff ff ff vgatherpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 4c 38 20 vgatherpf0dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c b9 00 04 00 00 vgatherpf0dpd ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 85 ff ff ff vgatherpf0dps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 85 ff ff ff vgatherpf0dps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 4c 38 40 vgatherpf0dps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c b9 00 04 00 00 vgatherpf0dps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 85 ff ff ff vgatherpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 85 ff ff ff vgatherpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 4c 38 20 vgatherpf0qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c b9 00 04 00 00 vgatherpf0qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 85 ff ff ff vgatherpf0qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 85 ff ff ff vgatherpf0qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 4c 38 40 vgatherpf0qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c b9 00 04 00 00 vgatherpf0qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 85 ff ff ff vgatherpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 85 ff ff ff vgatherpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 54 38 20 vgatherpf1dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 b9 00 04 00 00 vgatherpf1dpd ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 94 fd 85 ff ff ff vgatherpf1dps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 94 fd 85 ff ff ff vgatherpf1dps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 54 38 40 vgatherpf1dps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 94 b9 00 04 00 00 vgatherpf1dps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 fd 85 ff ff ff vgatherpf1qpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 fd 85 ff ff ff vgatherpf1qpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 54 38 20 vgatherpf1qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 b9 00 04 00 00 vgatherpf1qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 85 ff ff ff vgatherpf1qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 85 ff ff ff vgatherpf1qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 54 38 40 vgatherpf1qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 b9 00 04 00 00 vgatherpf1qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac fd 85 ff ff ff vscatterpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac fd 85 ff ff ff vscatterpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 6c 38 20 vscatterpf0dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac b9 00 04 00 00 vscatterpf0dpd ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 ac fd 85 ff ff ff vscatterpf0dps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 ac fd 85 ff ff ff vscatterpf0dps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 6c 38 40 vscatterpf0dps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 ac b9 00 04 00 00 vscatterpf0dps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac fd 85 ff ff ff vscatterpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac fd 85 ff ff ff vscatterpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 6c 38 20 vscatterpf0qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac b9 00 04 00 00 vscatterpf0qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 85 ff ff ff vscatterpf0qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 85 ff ff ff vscatterpf0qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 6c 38 40 vscatterpf0qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac b9 00 04 00 00 vscatterpf0qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 fd 85 ff ff ff vscatterpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 fd 85 ff ff ff vscatterpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 74 38 20 vscatterpf1dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 b9 00 04 00 00 vscatterpf1dpd ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 b4 fd 85 ff ff ff vscatterpf1dps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 b4 fd 85 ff ff ff vscatterpf1dps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 74 38 40 vscatterpf1dps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 b4 b9 00 04 00 00 vscatterpf1dps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 fd 85 ff ff ff vscatterpf1qpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 fd 85 ff ff ff vscatterpf1qpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 74 38 20 vscatterpf1qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 b9 00 04 00 00 vscatterpf1qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 85 ff ff ff vscatterpf1qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 85 ff ff ff vscatterpf1qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 74 38 40 vscatterpf1qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 b9 00 04 00 00 vscatterpf1qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 BYTE PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 0f 0d 94 f4 c0 1d fe ff prefetchwt1 BYTE PTR \[esp\+esi\*8-0x1e240\]
|
||||
#pass
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: i386 AVX512PF insns
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 7b 00 00 00 vgatherpf0dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 4c 38 20 vgatherpf0dpd 0x100\(%eax,%ymm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c b9 00 04 00 00 vgatherpf0dpd 0x400\(%ecx,%ymm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 7b 00 00 00 vgatherpf0dps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 4c 38 40 vgatherpf0dps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c b9 00 04 00 00 vgatherpf0dps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 4c 38 20 vgatherpf0qpd 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c b9 00 04 00 00 vgatherpf0qpd 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 7b 00 00 00 vgatherpf0qps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 7b 00 00 00 vgatherpf0qps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 4c 38 40 vgatherpf0qps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c b9 00 04 00 00 vgatherpf0qps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 7b 00 00 00 vgatherpf1dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 7b 00 00 00 vgatherpf1dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 54 38 20 vgatherpf1dpd 0x100\(%eax,%ymm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 b9 00 04 00 00 vgatherpf1dpd 0x400\(%ecx,%ymm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 94 fd 7b 00 00 00 vgatherpf1dps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 94 fd 7b 00 00 00 vgatherpf1dps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 54 38 40 vgatherpf1dps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 94 b9 00 04 00 00 vgatherpf1dps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 fd 7b 00 00 00 vgatherpf1qpd 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 fd 7b 00 00 00 vgatherpf1qpd 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 54 38 20 vgatherpf1qpd 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 b9 00 04 00 00 vgatherpf1qpd 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 7b 00 00 00 vgatherpf1qps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 7b 00 00 00 vgatherpf1qps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 54 38 40 vgatherpf1qps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 b9 00 04 00 00 vgatherpf1qps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac fd 7b 00 00 00 vscatterpf0dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac fd 7b 00 00 00 vscatterpf0dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 6c 38 20 vscatterpf0dpd 0x100\(%eax,%ymm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac b9 00 04 00 00 vscatterpf0dpd 0x400\(%ecx,%ymm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 ac fd 7b 00 00 00 vscatterpf0dps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 ac fd 7b 00 00 00 vscatterpf0dps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 6c 38 40 vscatterpf0dps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 ac b9 00 04 00 00 vscatterpf0dps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac fd 7b 00 00 00 vscatterpf0qpd 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac fd 7b 00 00 00 vscatterpf0qpd 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 6c 38 20 vscatterpf0qpd 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac b9 00 04 00 00 vscatterpf0qpd 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 7b 00 00 00 vscatterpf0qps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 7b 00 00 00 vscatterpf0qps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 6c 38 40 vscatterpf0qps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac b9 00 04 00 00 vscatterpf0qps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 fd 7b 00 00 00 vscatterpf1dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 fd 7b 00 00 00 vscatterpf1dpd 0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 74 38 20 vscatterpf1dpd 0x100\(%eax,%ymm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 b9 00 04 00 00 vscatterpf1dpd 0x400\(%ecx,%ymm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 b4 fd 7b 00 00 00 vscatterpf1dps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 b4 fd 7b 00 00 00 vscatterpf1dps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 74 38 40 vscatterpf1dps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 b4 b9 00 04 00 00 vscatterpf1dps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 fd 7b 00 00 00 vscatterpf1qpd 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 fd 7b 00 00 00 vscatterpf1qpd 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 74 38 20 vscatterpf1qpd 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 b9 00 04 00 00 vscatterpf1qpd 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 7b 00 00 00 vscatterpf1qps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 7b 00 00 00 vscatterpf1qps 0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 74 38 40 vscatterpf1qps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 b9 00 04 00 00 vscatterpf1qps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 \(%ecx\)
|
||||
[ ]*[a-f0-9]+: 0f 0d 94 f4 c0 1d fe ff prefetchwt1 -0x1e240\(%esp,%esi,8\)
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 85 ff ff ff vgatherpf0dpd -0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 85 ff ff ff vgatherpf0dpd -0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 4c 38 20 vgatherpf0dpd 0x100\(%eax,%ymm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c b9 00 04 00 00 vgatherpf0dpd 0x400\(%ecx,%ymm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 85 ff ff ff vgatherpf0dps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c fd 85 ff ff ff vgatherpf0dps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 4c 38 40 vgatherpf0dps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 8c b9 00 04 00 00 vgatherpf0dps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 85 ff ff ff vgatherpf0qpd -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 85 ff ff ff vgatherpf0qpd -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 4c 38 20 vgatherpf0qpd 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c b9 00 04 00 00 vgatherpf0qpd 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 85 ff ff ff vgatherpf0qps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 85 ff ff ff vgatherpf0qps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 4c 38 40 vgatherpf0qps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c b9 00 04 00 00 vgatherpf0qps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 85 ff ff ff vgatherpf1dpd -0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 85 ff ff ff vgatherpf1dpd -0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 54 38 20 vgatherpf1dpd 0x100\(%eax,%ymm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 b9 00 04 00 00 vgatherpf1dpd 0x400\(%ecx,%ymm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 94 fd 85 ff ff ff vgatherpf1dps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 94 fd 85 ff ff ff vgatherpf1dps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 54 38 40 vgatherpf1dps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 94 b9 00 04 00 00 vgatherpf1dps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 fd 85 ff ff ff vgatherpf1qpd -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 fd 85 ff ff ff vgatherpf1qpd -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 54 38 20 vgatherpf1qpd 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 b9 00 04 00 00 vgatherpf1qpd 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 85 ff ff ff vgatherpf1qps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 85 ff ff ff vgatherpf1qps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 54 38 40 vgatherpf1qps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 b9 00 04 00 00 vgatherpf1qps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac fd 85 ff ff ff vscatterpf0dpd -0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac fd 85 ff ff ff vscatterpf0dpd -0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 6c 38 20 vscatterpf0dpd 0x100\(%eax,%ymm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac b9 00 04 00 00 vscatterpf0dpd 0x400\(%ecx,%ymm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 ac fd 85 ff ff ff vscatterpf0dps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 ac fd 85 ff ff ff vscatterpf0dps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 6c 38 40 vscatterpf0dps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 ac b9 00 04 00 00 vscatterpf0dps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac fd 85 ff ff ff vscatterpf0qpd -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac fd 85 ff ff ff vscatterpf0qpd -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 6c 38 20 vscatterpf0qpd 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac b9 00 04 00 00 vscatterpf0qpd 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 85 ff ff ff vscatterpf0qps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 85 ff ff ff vscatterpf0qps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 6c 38 40 vscatterpf0qps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac b9 00 04 00 00 vscatterpf0qps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 fd 85 ff ff ff vscatterpf1dpd -0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 fd 85 ff ff ff vscatterpf1dpd -0x7b\(%ebp,%ymm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 74 38 20 vscatterpf1dpd 0x100\(%eax,%ymm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 b9 00 04 00 00 vscatterpf1dpd 0x400\(%ecx,%ymm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 b4 fd 85 ff ff ff vscatterpf1dps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 b4 fd 85 ff ff ff vscatterpf1dps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 74 38 40 vscatterpf1dps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c6 b4 b9 00 04 00 00 vscatterpf1dps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 fd 85 ff ff ff vscatterpf1qpd -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 fd 85 ff ff ff vscatterpf1qpd -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 74 38 20 vscatterpf1qpd 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 b9 00 04 00 00 vscatterpf1qpd 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 85 ff ff ff vscatterpf1qps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 85 ff ff ff vscatterpf1qps -0x7b\(%ebp,%zmm7,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 74 38 40 vscatterpf1qps 0x100\(%eax,%zmm7,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 b9 00 04 00 00 vscatterpf1qps 0x400\(%ecx,%zmm7,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 \(%ecx\)
|
||||
[ ]*[a-f0-9]+: 0f 0d 94 f4 c0 1d fe ff prefetchwt1 -0x1e240\(%esp,%esi,8\)
|
||||
#pass
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
# Check 32bit AVX512PF instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
vgatherpf0dpd 123(%ebp,%ymm7,8){%k1} # AVX512PF
|
||||
vgatherpf0dpd 123(%ebp,%ymm7,8){%k1} # AVX512PF
|
||||
vgatherpf0dpd 256(%eax,%ymm7){%k1} # AVX512PF
|
||||
vgatherpf0dpd 1024(%ecx,%ymm7,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf0dps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vgatherpf0dps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vgatherpf0dps 256(%eax,%zmm7){%k1} # AVX512PF
|
||||
vgatherpf0dps 1024(%ecx,%zmm7,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf0qpd 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vgatherpf0qpd 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vgatherpf0qpd 256(%eax,%zmm7){%k1} # AVX512PF
|
||||
vgatherpf0qpd 1024(%ecx,%zmm7,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf0qps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vgatherpf0qps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vgatherpf0qps 256(%eax,%zmm7){%k1} # AVX512PF
|
||||
vgatherpf0qps 1024(%ecx,%zmm7,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf1dpd 123(%ebp,%ymm7,8){%k1} # AVX512PF
|
||||
vgatherpf1dpd 123(%ebp,%ymm7,8){%k1} # AVX512PF
|
||||
vgatherpf1dpd 256(%eax,%ymm7){%k1} # AVX512PF
|
||||
vgatherpf1dpd 1024(%ecx,%ymm7,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf1dps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vgatherpf1dps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vgatherpf1dps 256(%eax,%zmm7){%k1} # AVX512PF
|
||||
vgatherpf1dps 1024(%ecx,%zmm7,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf1qpd 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vgatherpf1qpd 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vgatherpf1qpd 256(%eax,%zmm7){%k1} # AVX512PF
|
||||
vgatherpf1qpd 1024(%ecx,%zmm7,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf1qps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vgatherpf1qps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vgatherpf1qps 256(%eax,%zmm7){%k1} # AVX512PF
|
||||
vgatherpf1qps 1024(%ecx,%zmm7,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf0dpd 123(%ebp,%ymm7,8){%k1} # AVX512PF
|
||||
vscatterpf0dpd 123(%ebp,%ymm7,8){%k1} # AVX512PF
|
||||
vscatterpf0dpd 256(%eax,%ymm7){%k1} # AVX512PF
|
||||
vscatterpf0dpd 1024(%ecx,%ymm7,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf0dps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vscatterpf0dps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vscatterpf0dps 256(%eax,%zmm7){%k1} # AVX512PF
|
||||
vscatterpf0dps 1024(%ecx,%zmm7,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf0qpd 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vscatterpf0qpd 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vscatterpf0qpd 256(%eax,%zmm7){%k1} # AVX512PF
|
||||
vscatterpf0qpd 1024(%ecx,%zmm7,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf0qps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vscatterpf0qps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vscatterpf0qps 256(%eax,%zmm7){%k1} # AVX512PF
|
||||
vscatterpf0qps 1024(%ecx,%zmm7,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf1dpd 123(%ebp,%ymm7,8){%k1} # AVX512PF
|
||||
vscatterpf1dpd 123(%ebp,%ymm7,8){%k1} # AVX512PF
|
||||
vscatterpf1dpd 256(%eax,%ymm7){%k1} # AVX512PF
|
||||
vscatterpf1dpd 1024(%ecx,%ymm7,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf1dps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vscatterpf1dps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vscatterpf1dps 256(%eax,%zmm7){%k1} # AVX512PF
|
||||
vscatterpf1dps 1024(%ecx,%zmm7,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf1qpd 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vscatterpf1qpd 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vscatterpf1qpd 256(%eax,%zmm7){%k1} # AVX512PF
|
||||
vscatterpf1qpd 1024(%ecx,%zmm7,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf1qps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vscatterpf1qps 123(%ebp,%zmm7,8){%k1} # AVX512PF
|
||||
vscatterpf1qps 256(%eax,%zmm7){%k1} # AVX512PF
|
||||
vscatterpf1qps 1024(%ecx,%zmm7,4){%k1} # AVX512PF
|
||||
|
||||
prefetchwt1 (%ecx) # AVX512PF
|
||||
prefetchwt1 -123456(%esp,%esi,8) # AVX512PF
|
||||
|
||||
.intel_syntax noprefix
|
||||
vgatherpf0dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf0dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf0dpd ZMMWORD PTR [eax+ymm7+256]{k1} # AVX512PF
|
||||
vgatherpf0dpd ZMMWORD PTR [ecx+ymm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf0dps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf0dps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf0dps ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF
|
||||
vgatherpf0dps ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf0qpd ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf0qpd ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf0qpd ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF
|
||||
vgatherpf0qpd ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf0qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf0qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf0qps ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF
|
||||
vgatherpf0qps ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf1dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf1dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf1dpd ZMMWORD PTR [eax+ymm7+256]{k1} # AVX512PF
|
||||
vgatherpf1dpd ZMMWORD PTR [ecx+ymm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf1dps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf1dps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf1dps ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF
|
||||
vgatherpf1dps ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf1qpd ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf1qpd ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf1qpd ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF
|
||||
vgatherpf1qpd ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf1qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf1qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vgatherpf1qps ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF
|
||||
vgatherpf1qps ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf0dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf0dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf0dpd ZMMWORD PTR [eax+ymm7+256]{k1} # AVX512PF
|
||||
vscatterpf0dpd ZMMWORD PTR [ecx+ymm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf0dps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf0dps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf0dps ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF
|
||||
vscatterpf0dps ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf0qpd ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf0qpd ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf0qpd ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF
|
||||
vscatterpf0qpd ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf0qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf0qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf0qps ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF
|
||||
vscatterpf0qps ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf1dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf1dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf1dpd ZMMWORD PTR [eax+ymm7+256]{k1} # AVX512PF
|
||||
vscatterpf1dpd ZMMWORD PTR [ecx+ymm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf1dps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf1dps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf1dps ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF
|
||||
vscatterpf1dps ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf1qpd ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf1qpd ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf1qpd ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF
|
||||
vscatterpf1qpd ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf1qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf1qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF
|
||||
vscatterpf1qps ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF
|
||||
vscatterpf1qps ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF
|
||||
|
||||
prefetchwt1 BYTE PTR [ecx] # AVX512PF
|
||||
prefetchwt1 BYTE PTR [esp+esi*8-123456] # AVX512PF
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,151 @@
|
|||
# Check EVEX WIG instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
vpmovsxbd %xmm5, %zmm6{%k7} # AVX512
|
||||
vpmovsxbd %xmm5, %zmm6{%k7}{z} # AVX512
|
||||
vpmovsxbd (%ecx), %zmm6{%k7} # AVX512
|
||||
vpmovsxbd -123456(%esp,%esi,8), %zmm6{%k7} # AVX512
|
||||
vpmovsxbd 2032(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovsxbd 2048(%edx), %zmm6{%k7} # AVX512
|
||||
vpmovsxbd -2048(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovsxbd -2064(%edx), %zmm6{%k7} # AVX512
|
||||
|
||||
vpmovsxbq %xmm5, %zmm6{%k7} # AVX512
|
||||
vpmovsxbq %xmm5, %zmm6{%k7}{z} # AVX512
|
||||
vpmovsxbq (%ecx), %zmm6{%k7} # AVX512
|
||||
vpmovsxbq -123456(%esp,%esi,8), %zmm6{%k7} # AVX512
|
||||
vpmovsxbq 1016(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovsxbq 1024(%edx), %zmm6{%k7} # AVX512
|
||||
vpmovsxbq -1024(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovsxbq -1032(%edx), %zmm6{%k7} # AVX512
|
||||
|
||||
vpmovsxwd %ymm5, %zmm6{%k7} # AVX512
|
||||
vpmovsxwd %ymm5, %zmm6{%k7}{z} # AVX512
|
||||
vpmovsxwd (%ecx), %zmm6{%k7} # AVX512
|
||||
vpmovsxwd -123456(%esp,%esi,8), %zmm6{%k7} # AVX512
|
||||
vpmovsxwd 4064(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovsxwd 4096(%edx), %zmm6{%k7} # AVX512
|
||||
vpmovsxwd -4096(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovsxwd -4128(%edx), %zmm6{%k7} # AVX512
|
||||
|
||||
vpmovsxwq %xmm5, %zmm6{%k7} # AVX512
|
||||
vpmovsxwq %xmm5, %zmm6{%k7}{z} # AVX512
|
||||
vpmovsxwq (%ecx), %zmm6{%k7} # AVX512
|
||||
vpmovsxwq -123456(%esp,%esi,8), %zmm6{%k7} # AVX512
|
||||
vpmovsxwq 2032(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovsxwq 2048(%edx), %zmm6{%k7} # AVX512
|
||||
vpmovsxwq -2048(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovsxwq -2064(%edx), %zmm6{%k7} # AVX512
|
||||
|
||||
vpmovzxbd %xmm5, %zmm6{%k7} # AVX512
|
||||
vpmovzxbd %xmm5, %zmm6{%k7}{z} # AVX512
|
||||
vpmovzxbd (%ecx), %zmm6{%k7} # AVX512
|
||||
vpmovzxbd -123456(%esp,%esi,8), %zmm6{%k7} # AVX512
|
||||
vpmovzxbd 2032(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovzxbd 2048(%edx), %zmm6{%k7} # AVX512
|
||||
vpmovzxbd -2048(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovzxbd -2064(%edx), %zmm6{%k7} # AVX512
|
||||
|
||||
vpmovzxbq %xmm5, %zmm6{%k7} # AVX512
|
||||
vpmovzxbq %xmm5, %zmm6{%k7}{z} # AVX512
|
||||
vpmovzxbq (%ecx), %zmm6{%k7} # AVX512
|
||||
vpmovzxbq -123456(%esp,%esi,8), %zmm6{%k7} # AVX512
|
||||
vpmovzxbq 1016(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovzxbq 1024(%edx), %zmm6{%k7} # AVX512
|
||||
vpmovzxbq -1024(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovzxbq -1032(%edx), %zmm6{%k7} # AVX512
|
||||
|
||||
vpmovzxwd %ymm5, %zmm6{%k7} # AVX512
|
||||
vpmovzxwd %ymm5, %zmm6{%k7}{z} # AVX512
|
||||
vpmovzxwd (%ecx), %zmm6{%k7} # AVX512
|
||||
vpmovzxwd -123456(%esp,%esi,8), %zmm6{%k7} # AVX512
|
||||
vpmovzxwd 4064(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovzxwd 4096(%edx), %zmm6{%k7} # AVX512
|
||||
vpmovzxwd -4096(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovzxwd -4128(%edx), %zmm6{%k7} # AVX512
|
||||
|
||||
vpmovzxwq %xmm5, %zmm6{%k7} # AVX512
|
||||
vpmovzxwq %xmm5, %zmm6{%k7}{z} # AVX512
|
||||
vpmovzxwq (%ecx), %zmm6{%k7} # AVX512
|
||||
vpmovzxwq -123456(%esp,%esi,8), %zmm6{%k7} # AVX512
|
||||
vpmovzxwq 2032(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovzxwq 2048(%edx), %zmm6{%k7} # AVX512
|
||||
vpmovzxwq -2048(%edx), %zmm6{%k7} # AVX512 Disp8
|
||||
vpmovzxwq -2064(%edx), %zmm6{%k7} # AVX512
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpmovsxbd zmm6{k7}, xmm5 # AVX512
|
||||
vpmovsxbd zmm6{k7}{z}, xmm5 # AVX512
|
||||
vpmovsxbd zmm6{k7}, XMMWORD PTR [ecx] # AVX512
|
||||
vpmovsxbd zmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512
|
||||
vpmovsxbd zmm6{k7}, XMMWORD PTR [edx+2032] # AVX512 Disp8
|
||||
vpmovsxbd zmm6{k7}, XMMWORD PTR [edx+2048] # AVX512
|
||||
vpmovsxbd zmm6{k7}, XMMWORD PTR [edx-2048] # AVX512 Disp8
|
||||
vpmovsxbd zmm6{k7}, XMMWORD PTR [edx-2064] # AVX512
|
||||
|
||||
vpmovsxbq zmm6{k7}, xmm5 # AVX512
|
||||
vpmovsxbq zmm6{k7}{z}, xmm5 # AVX512
|
||||
vpmovsxbq zmm6{k7}, QWORD PTR [ecx] # AVX512
|
||||
vpmovsxbq zmm6{k7}, QWORD PTR [esp+esi*8-123456] # AVX512
|
||||
vpmovsxbq zmm6{k7}, QWORD PTR [edx+1016] # AVX512 Disp8
|
||||
vpmovsxbq zmm6{k7}, QWORD PTR [edx+1024] # AVX512
|
||||
vpmovsxbq zmm6{k7}, QWORD PTR [edx-1024] # AVX512 Disp8
|
||||
vpmovsxbq zmm6{k7}, QWORD PTR [edx-1032] # AVX512
|
||||
|
||||
vpmovsxwd zmm6{k7}, ymm5 # AVX512
|
||||
vpmovsxwd zmm6{k7}{z}, ymm5 # AVX512
|
||||
vpmovsxwd zmm6{k7}, YMMWORD PTR [ecx] # AVX512
|
||||
vpmovsxwd zmm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512
|
||||
vpmovsxwd zmm6{k7}, YMMWORD PTR [edx+4064] # AVX512 Disp8
|
||||
vpmovsxwd zmm6{k7}, YMMWORD PTR [edx+4096] # AVX512
|
||||
vpmovsxwd zmm6{k7}, YMMWORD PTR [edx-4096] # AVX512 Disp8
|
||||
vpmovsxwd zmm6{k7}, YMMWORD PTR [edx-4128] # AVX512
|
||||
|
||||
vpmovsxwq zmm6{k7}, xmm5 # AVX512
|
||||
vpmovsxwq zmm6{k7}{z}, xmm5 # AVX512
|
||||
vpmovsxwq zmm6{k7}, XMMWORD PTR [ecx] # AVX512
|
||||
vpmovsxwq zmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512
|
||||
vpmovsxwq zmm6{k7}, XMMWORD PTR [edx+2032] # AVX512 Disp8
|
||||
vpmovsxwq zmm6{k7}, XMMWORD PTR [edx+2048] # AVX512
|
||||
vpmovsxwq zmm6{k7}, XMMWORD PTR [edx-2048] # AVX512 Disp8
|
||||
vpmovsxwq zmm6{k7}, XMMWORD PTR [edx-2064] # AVX512
|
||||
|
||||
vpmovzxbd zmm6{k7}, xmm5 # AVX512
|
||||
vpmovzxbd zmm6{k7}{z}, xmm5 # AVX512
|
||||
vpmovzxbd zmm6{k7}, XMMWORD PTR [ecx] # AVX512
|
||||
vpmovzxbd zmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512
|
||||
vpmovzxbd zmm6{k7}, XMMWORD PTR [edx+2032] # AVX512 Disp8
|
||||
vpmovzxbd zmm6{k7}, XMMWORD PTR [edx+2048] # AVX512
|
||||
vpmovzxbd zmm6{k7}, XMMWORD PTR [edx-2048] # AVX512 Disp8
|
||||
vpmovzxbd zmm6{k7}, XMMWORD PTR [edx-2064] # AVX512
|
||||
|
||||
vpmovzxbq zmm6{k7}, xmm5 # AVX512
|
||||
vpmovzxbq zmm6{k7}{z}, xmm5 # AVX512
|
||||
vpmovzxbq zmm6{k7}, QWORD PTR [ecx] # AVX512
|
||||
vpmovzxbq zmm6{k7}, QWORD PTR [esp+esi*8-123456] # AVX512
|
||||
vpmovzxbq zmm6{k7}, QWORD PTR [edx+1016] # AVX512 Disp8
|
||||
vpmovzxbq zmm6{k7}, QWORD PTR [edx+1024] # AVX512
|
||||
vpmovzxbq zmm6{k7}, QWORD PTR [edx-1024] # AVX512 Disp8
|
||||
vpmovzxbq zmm6{k7}, QWORD PTR [edx-1032] # AVX512
|
||||
|
||||
vpmovzxwd zmm6{k7}, ymm5 # AVX512
|
||||
vpmovzxwd zmm6{k7}{z}, ymm5 # AVX512
|
||||
vpmovzxwd zmm6{k7}, YMMWORD PTR [ecx] # AVX512
|
||||
vpmovzxwd zmm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512
|
||||
vpmovzxwd zmm6{k7}, YMMWORD PTR [edx+4064] # AVX512 Disp8
|
||||
vpmovzxwd zmm6{k7}, YMMWORD PTR [edx+4096] # AVX512
|
||||
vpmovzxwd zmm6{k7}, YMMWORD PTR [edx-4096] # AVX512 Disp8
|
||||
vpmovzxwd zmm6{k7}, YMMWORD PTR [edx-4128] # AVX512
|
||||
|
||||
vpmovzxwq zmm6{k7}, xmm5 # AVX512
|
||||
vpmovzxwq zmm6{k7}{z}, xmm5 # AVX512
|
||||
vpmovzxwq zmm6{k7}, XMMWORD PTR [ecx] # AVX512
|
||||
vpmovzxwq zmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512
|
||||
vpmovzxwq zmm6{k7}, XMMWORD PTR [edx+2032] # AVX512 Disp8
|
||||
vpmovzxwq zmm6{k7}, XMMWORD PTR [edx+2048] # AVX512
|
||||
vpmovzxwq zmm6{k7}, XMMWORD PTR [edx-2048] # AVX512 Disp8
|
||||
vpmovzxwq zmm6{k7}, XMMWORD PTR [edx-2064] # AVX512
|
||||
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
#as: -mevexwig=1
|
||||
#objdump: -dwMintel
|
||||
#name: i386 AVX512 wig insns (Intel disassembly)
|
||||
#source: evex-wig.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd zmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd zmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 b4 f4 c0 1d fe ff vpmovsxbd zmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 7f vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 00 08 00 00 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 80 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 f0 f7 ff ff vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 f5 vpmovsxbq zmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 22 f5 vpmovsxbq zmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 31 vpmovsxbq zmm6\{k7\},QWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 b4 f4 c0 1d fe ff vpmovsxbq zmm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 72 7f vpmovsxbq zmm6\{k7\},QWORD PTR \[edx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 b2 00 04 00 00 vpmovsxbq zmm6\{k7\},QWORD PTR \[edx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 72 80 vpmovsxbq zmm6\{k7\},QWORD PTR \[edx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 b2 f8 fb ff ff vpmovsxbq zmm6\{k7\},QWORD PTR \[edx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 f5 vpmovsxwd zmm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 23 f5 vpmovsxwd zmm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 31 vpmovsxwd zmm6\{k7\},YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 b4 f4 c0 1d fe ff vpmovsxwd zmm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 72 7f vpmovsxwd zmm6\{k7\},YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 b2 00 10 00 00 vpmovsxwd zmm6\{k7\},YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 72 80 vpmovsxwd zmm6\{k7\},YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 b2 e0 ef ff ff vpmovsxwd zmm6\{k7\},YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 f5 vpmovsxwq zmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 24 f5 vpmovsxwq zmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 31 vpmovsxwq zmm6\{k7\},XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 b4 f4 c0 1d fe ff vpmovsxwq zmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 72 7f vpmovsxwq zmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 b2 00 08 00 00 vpmovsxwq zmm6\{k7\},XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 72 80 vpmovsxwq zmm6\{k7\},XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 b2 f0 f7 ff ff vpmovsxwq zmm6\{k7\},XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 f5 vpmovzxbd zmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 31 f5 vpmovzxbd zmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 31 vpmovzxbd zmm6\{k7\},XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 b4 f4 c0 1d fe ff vpmovzxbd zmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 72 7f vpmovzxbd zmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 b2 00 08 00 00 vpmovzxbd zmm6\{k7\},XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 72 80 vpmovzxbd zmm6\{k7\},XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 b2 f0 f7 ff ff vpmovzxbd zmm6\{k7\},XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 f5 vpmovzxbq zmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 32 f5 vpmovzxbq zmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 31 vpmovzxbq zmm6\{k7\},QWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 b4 f4 c0 1d fe ff vpmovzxbq zmm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 72 7f vpmovzxbq zmm6\{k7\},QWORD PTR \[edx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 b2 00 04 00 00 vpmovzxbq zmm6\{k7\},QWORD PTR \[edx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 72 80 vpmovzxbq zmm6\{k7\},QWORD PTR \[edx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 b2 f8 fb ff ff vpmovzxbq zmm6\{k7\},QWORD PTR \[edx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 f5 vpmovzxwd zmm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 33 f5 vpmovzxwd zmm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 31 vpmovzxwd zmm6\{k7\},YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 b4 f4 c0 1d fe ff vpmovzxwd zmm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 72 7f vpmovzxwd zmm6\{k7\},YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 b2 00 10 00 00 vpmovzxwd zmm6\{k7\},YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 72 80 vpmovzxwd zmm6\{k7\},YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 b2 e0 ef ff ff vpmovzxwd zmm6\{k7\},YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 f5 vpmovzxwq zmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 34 f5 vpmovzxwq zmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 31 vpmovzxwq zmm6\{k7\},XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 b4 f4 c0 1d fe ff vpmovzxwq zmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 72 7f vpmovzxwq zmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 b2 00 08 00 00 vpmovzxwq zmm6\{k7\},XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 72 80 vpmovzxwq zmm6\{k7\},XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 b2 f0 f7 ff ff vpmovzxwq zmm6\{k7\},XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd zmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd zmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 b4 f4 c0 1d fe ff vpmovsxbd zmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 7f vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 00 08 00 00 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 80 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 f0 f7 ff ff vpmovsxbd zmm6\{k7\},XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 f5 vpmovsxbq zmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 22 f5 vpmovsxbq zmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 31 vpmovsxbq zmm6\{k7\},QWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 b4 f4 c0 1d fe ff vpmovsxbq zmm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 72 7f vpmovsxbq zmm6\{k7\},QWORD PTR \[edx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 b2 00 04 00 00 vpmovsxbq zmm6\{k7\},QWORD PTR \[edx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 72 80 vpmovsxbq zmm6\{k7\},QWORD PTR \[edx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 b2 f8 fb ff ff vpmovsxbq zmm6\{k7\},QWORD PTR \[edx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 f5 vpmovsxwd zmm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 23 f5 vpmovsxwd zmm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 31 vpmovsxwd zmm6\{k7\},YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 b4 f4 c0 1d fe ff vpmovsxwd zmm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 72 7f vpmovsxwd zmm6\{k7\},YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 b2 00 10 00 00 vpmovsxwd zmm6\{k7\},YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 72 80 vpmovsxwd zmm6\{k7\},YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 b2 e0 ef ff ff vpmovsxwd zmm6\{k7\},YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 f5 vpmovsxwq zmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 24 f5 vpmovsxwq zmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 31 vpmovsxwq zmm6\{k7\},XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 b4 f4 c0 1d fe ff vpmovsxwq zmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 72 7f vpmovsxwq zmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 b2 00 08 00 00 vpmovsxwq zmm6\{k7\},XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 72 80 vpmovsxwq zmm6\{k7\},XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 b2 f0 f7 ff ff vpmovsxwq zmm6\{k7\},XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 f5 vpmovzxbd zmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 31 f5 vpmovzxbd zmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 31 vpmovzxbd zmm6\{k7\},XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 b4 f4 c0 1d fe ff vpmovzxbd zmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 72 7f vpmovzxbd zmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 b2 00 08 00 00 vpmovzxbd zmm6\{k7\},XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 72 80 vpmovzxbd zmm6\{k7\},XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 b2 f0 f7 ff ff vpmovzxbd zmm6\{k7\},XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 f5 vpmovzxbq zmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 32 f5 vpmovzxbq zmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 31 vpmovzxbq zmm6\{k7\},QWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 b4 f4 c0 1d fe ff vpmovzxbq zmm6\{k7\},QWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 72 7f vpmovzxbq zmm6\{k7\},QWORD PTR \[edx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 b2 00 04 00 00 vpmovzxbq zmm6\{k7\},QWORD PTR \[edx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 72 80 vpmovzxbq zmm6\{k7\},QWORD PTR \[edx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 b2 f8 fb ff ff vpmovzxbq zmm6\{k7\},QWORD PTR \[edx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 f5 vpmovzxwd zmm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 33 f5 vpmovzxwd zmm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 31 vpmovzxwd zmm6\{k7\},YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 b4 f4 c0 1d fe ff vpmovzxwd zmm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 72 7f vpmovzxwd zmm6\{k7\},YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 b2 00 10 00 00 vpmovzxwd zmm6\{k7\},YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 72 80 vpmovzxwd zmm6\{k7\},YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 b2 e0 ef ff ff vpmovzxwd zmm6\{k7\},YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 f5 vpmovzxwq zmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 34 f5 vpmovzxwq zmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 31 vpmovzxwq zmm6\{k7\},XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 b4 f4 c0 1d fe ff vpmovzxwq zmm6\{k7\},XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 72 7f vpmovzxwq zmm6\{k7\},XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 b2 00 08 00 00 vpmovzxwq zmm6\{k7\},XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 72 80 vpmovzxwq zmm6\{k7\},XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 b2 f0 f7 ff ff vpmovzxwq zmm6\{k7\},XMMWORD PTR \[edx-0x810\]
|
||||
#pass
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
#as: -mevexwig=1
|
||||
#objdump: -dw
|
||||
#name: i386 AVX512 wig insns
|
||||
#source: evex-wig.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 b4 f4 c0 1d fe ff vpmovsxbd -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 7f vpmovsxbd 0x7f0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 00 08 00 00 vpmovsxbd 0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 80 vpmovsxbd -0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 f0 f7 ff ff vpmovsxbd -0x810\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 f5 vpmovsxbq %xmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 22 f5 vpmovsxbq %xmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 31 vpmovsxbq \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 b4 f4 c0 1d fe ff vpmovsxbq -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 72 7f vpmovsxbq 0x3f8\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 b2 00 04 00 00 vpmovsxbq 0x400\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 72 80 vpmovsxbq -0x400\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 b2 f8 fb ff ff vpmovsxbq -0x408\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 f5 vpmovsxwd %ymm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 23 f5 vpmovsxwd %ymm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 31 vpmovsxwd \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 b4 f4 c0 1d fe ff vpmovsxwd -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 72 7f vpmovsxwd 0xfe0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 b2 00 10 00 00 vpmovsxwd 0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 72 80 vpmovsxwd -0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 b2 e0 ef ff ff vpmovsxwd -0x1020\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 f5 vpmovsxwq %xmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 24 f5 vpmovsxwq %xmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 31 vpmovsxwq \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 b4 f4 c0 1d fe ff vpmovsxwq -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 72 7f vpmovsxwq 0x7f0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 b2 00 08 00 00 vpmovsxwq 0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 72 80 vpmovsxwq -0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 b2 f0 f7 ff ff vpmovsxwq -0x810\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 f5 vpmovzxbd %xmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 31 f5 vpmovzxbd %xmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 31 vpmovzxbd \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 b4 f4 c0 1d fe ff vpmovzxbd -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 72 7f vpmovzxbd 0x7f0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 b2 00 08 00 00 vpmovzxbd 0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 72 80 vpmovzxbd -0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 b2 f0 f7 ff ff vpmovzxbd -0x810\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 f5 vpmovzxbq %xmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 32 f5 vpmovzxbq %xmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 31 vpmovzxbq \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 b4 f4 c0 1d fe ff vpmovzxbq -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 72 7f vpmovzxbq 0x3f8\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 b2 00 04 00 00 vpmovzxbq 0x400\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 72 80 vpmovzxbq -0x400\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 b2 f8 fb ff ff vpmovzxbq -0x408\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 f5 vpmovzxwd %ymm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 33 f5 vpmovzxwd %ymm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 31 vpmovzxwd \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 b4 f4 c0 1d fe ff vpmovzxwd -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 72 7f vpmovzxwd 0xfe0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 b2 00 10 00 00 vpmovzxwd 0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 72 80 vpmovzxwd -0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 b2 e0 ef ff ff vpmovzxwd -0x1020\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 f5 vpmovzxwq %xmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 34 f5 vpmovzxwq %xmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 31 vpmovzxwq \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 b4 f4 c0 1d fe ff vpmovzxwq -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 72 7f vpmovzxwq 0x7f0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 b2 00 08 00 00 vpmovzxwq 0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 72 80 vpmovzxwq -0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 b2 f0 f7 ff ff vpmovzxwq -0x810\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 b4 f4 c0 1d fe ff vpmovsxbd -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 7f vpmovsxbd 0x7f0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 00 08 00 00 vpmovsxbd 0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 72 80 vpmovsxbd -0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 b2 f0 f7 ff ff vpmovsxbd -0x810\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 f5 vpmovsxbq %xmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 22 f5 vpmovsxbq %xmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 31 vpmovsxbq \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 b4 f4 c0 1d fe ff vpmovsxbq -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 72 7f vpmovsxbq 0x3f8\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 b2 00 04 00 00 vpmovsxbq 0x400\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 72 80 vpmovsxbq -0x400\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 22 b2 f8 fb ff ff vpmovsxbq -0x408\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 f5 vpmovsxwd %ymm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 23 f5 vpmovsxwd %ymm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 31 vpmovsxwd \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 b4 f4 c0 1d fe ff vpmovsxwd -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 72 7f vpmovsxwd 0xfe0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 b2 00 10 00 00 vpmovsxwd 0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 72 80 vpmovsxwd -0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 23 b2 e0 ef ff ff vpmovsxwd -0x1020\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 f5 vpmovsxwq %xmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 24 f5 vpmovsxwq %xmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 31 vpmovsxwq \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 b4 f4 c0 1d fe ff vpmovsxwq -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 72 7f vpmovsxwq 0x7f0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 b2 00 08 00 00 vpmovsxwq 0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 72 80 vpmovsxwq -0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 24 b2 f0 f7 ff ff vpmovsxwq -0x810\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 f5 vpmovzxbd %xmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 31 f5 vpmovzxbd %xmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 31 vpmovzxbd \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 b4 f4 c0 1d fe ff vpmovzxbd -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 72 7f vpmovzxbd 0x7f0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 b2 00 08 00 00 vpmovzxbd 0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 72 80 vpmovzxbd -0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 31 b2 f0 f7 ff ff vpmovzxbd -0x810\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 f5 vpmovzxbq %xmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 32 f5 vpmovzxbq %xmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 31 vpmovzxbq \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 b4 f4 c0 1d fe ff vpmovzxbq -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 72 7f vpmovzxbq 0x3f8\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 b2 00 04 00 00 vpmovzxbq 0x400\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 72 80 vpmovzxbq -0x400\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 32 b2 f8 fb ff ff vpmovzxbq -0x408\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 f5 vpmovzxwd %ymm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 33 f5 vpmovzxwd %ymm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 31 vpmovzxwd \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 b4 f4 c0 1d fe ff vpmovzxwd -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 72 7f vpmovzxwd 0xfe0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 b2 00 10 00 00 vpmovzxwd 0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 72 80 vpmovzxwd -0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 33 b2 e0 ef ff ff vpmovzxwd -0x1020\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 f5 vpmovzxwq %xmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd cf 34 f5 vpmovzxwq %xmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 31 vpmovzxwq \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 b4 f4 c0 1d fe ff vpmovzxwq -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 72 7f vpmovzxwq 0x7f0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 b2 00 08 00 00 vpmovzxwq 0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 72 80 vpmovzxwq -0x800\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 fd 4f 34 b2 f0 f7 ff ff vpmovzxwq -0x810\(%edx\),%zmm6\{%k7\}
|
||||
#pass
|
||||
|
|
@ -180,8 +180,26 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||
run_dump_test "avx2-intel"
|
||||
run_dump_test "avx-gather"
|
||||
run_dump_test "avx-gather-intel"
|
||||
run_dump_test "avx512f"
|
||||
run_dump_test "avx512f-intel"
|
||||
run_dump_test "avx512f-opts"
|
||||
run_dump_test "avx512f-opts-intel"
|
||||
run_dump_test "avx512f-nondef"
|
||||
run_dump_test "avx512cd"
|
||||
run_dump_test "avx512cd-intel"
|
||||
run_dump_test "avx512er"
|
||||
run_dump_test "avx512er-intel"
|
||||
run_dump_test "avx512pf"
|
||||
run_dump_test "avx512pf-intel"
|
||||
run_dump_test "evex-lig256"
|
||||
run_dump_test "evex-lig512"
|
||||
run_dump_test "evex-lig256-intel"
|
||||
run_dump_test "evex-lig512-intel"
|
||||
run_dump_test "evex-wig1"
|
||||
run_dump_test "evex-wig1-intel"
|
||||
run_dump_test "sse2avx"
|
||||
run_list_test "inval-avx" "-al"
|
||||
run_list_test "inval-avx512f" "-al"
|
||||
run_dump_test "sse-check"
|
||||
run_dump_test "sse-check-none"
|
||||
run_dump_test "sse-check-warn"
|
||||
|
|
@ -452,8 +470,26 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-avx2-intel"
|
||||
run_dump_test "x86-64-avx-gather"
|
||||
run_dump_test "x86-64-avx-gather-intel"
|
||||
run_dump_test "x86-64-avx512f"
|
||||
run_dump_test "x86-64-avx512f-intel"
|
||||
run_dump_test "x86-64-avx512f-opts"
|
||||
run_dump_test "x86-64-avx512f-opts-intel"
|
||||
run_dump_test "x86-64-avx512f-nondef"
|
||||
run_dump_test "x86-64-avx512cd"
|
||||
run_dump_test "x86-64-avx512cd-intel"
|
||||
run_dump_test "x86-64-avx512er"
|
||||
run_dump_test "x86-64-avx512er-intel"
|
||||
run_dump_test "x86-64-avx512pf"
|
||||
run_dump_test "x86-64-avx512pf-intel"
|
||||
run_dump_test "x86-64-evex-lig256"
|
||||
run_dump_test "x86-64-evex-lig512"
|
||||
run_dump_test "x86-64-evex-lig256-intel"
|
||||
run_dump_test "x86-64-evex-lig512-intel"
|
||||
run_dump_test "x86-64-evex-wig1"
|
||||
run_dump_test "x86-64-evex-wig1-intel"
|
||||
run_dump_test "x86-64-sse2avx"
|
||||
run_list_test "x86-64-inval-avx" "-al"
|
||||
run_list_test "x86-64-inval-avx512f" "-al"
|
||||
run_dump_test "x86-64-sse-check"
|
||||
run_dump_test "x86-64-sse-check-none"
|
||||
run_dump_test "x86-64-sse-check-warn"
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ Contents of the .eh_frame section:
|
|||
DW_CFA_undefined: r16 \(rip\)
|
||||
DW_CFA_nop
|
||||
|
||||
000000e8 000000c8 00000018 FDE cie=000000d4 pc=00000058..00000097
|
||||
000000e8 0000011[04] 00000018 FDE cie=000000d4 pc=00000058..000000af
|
||||
DW_CFA_advance_loc: 1 to 00000059
|
||||
DW_CFA_undefined: r0 \(rax\)
|
||||
DW_CFA_advance_loc: 1 to 0000005a
|
||||
|
|
@ -220,5 +220,53 @@ Contents of the .eh_frame section:
|
|||
DW_CFA_undefined: r47 \(mm6\)
|
||||
DW_CFA_advance_loc: 1 to 00000096
|
||||
DW_CFA_undefined: r48 \(mm7\)
|
||||
DW_CFA_advance_loc: 1 to 00000097
|
||||
DW_CFA_undefined: r67 \(xmm16\)
|
||||
DW_CFA_advance_loc: 1 to 00000098
|
||||
DW_CFA_undefined: r68 \(xmm17\)
|
||||
DW_CFA_advance_loc: 1 to 00000099
|
||||
DW_CFA_undefined: r69 \(xmm18\)
|
||||
DW_CFA_advance_loc: 1 to 0000009a
|
||||
DW_CFA_undefined: r70 \(xmm19\)
|
||||
DW_CFA_advance_loc: 1 to 0000009b
|
||||
DW_CFA_undefined: r71 \(xmm20\)
|
||||
DW_CFA_advance_loc: 1 to 0000009c
|
||||
DW_CFA_undefined: r72 \(xmm21\)
|
||||
DW_CFA_advance_loc: 1 to 0000009d
|
||||
DW_CFA_undefined: r73 \(xmm22\)
|
||||
DW_CFA_advance_loc: 1 to 0000009e
|
||||
DW_CFA_undefined: r74 \(xmm23\)
|
||||
DW_CFA_advance_loc: 1 to 0000009f
|
||||
DW_CFA_undefined: r75 \(xmm24\)
|
||||
DW_CFA_advance_loc: 1 to 000000a0
|
||||
DW_CFA_undefined: r76 \(xmm25\)
|
||||
DW_CFA_advance_loc: 1 to 000000a1
|
||||
DW_CFA_undefined: r77 \(xmm26\)
|
||||
DW_CFA_advance_loc: 1 to 000000a2
|
||||
DW_CFA_undefined: r78 \(xmm27\)
|
||||
DW_CFA_advance_loc: 1 to 000000a3
|
||||
DW_CFA_undefined: r79 \(xmm28\)
|
||||
DW_CFA_advance_loc: 1 to 000000a4
|
||||
DW_CFA_undefined: r80 \(xmm29\)
|
||||
DW_CFA_advance_loc: 1 to 000000a5
|
||||
DW_CFA_undefined: r81 \(xmm30\)
|
||||
DW_CFA_advance_loc: 1 to 000000a6
|
||||
DW_CFA_undefined: r82 \(xmm31\)
|
||||
DW_CFA_advance_loc: 1 to 000000a7
|
||||
DW_CFA_undefined: r118 \(k0\)
|
||||
DW_CFA_advance_loc: 1 to 000000a8
|
||||
DW_CFA_undefined: r119 \(k1\)
|
||||
DW_CFA_advance_loc: 1 to 000000a9
|
||||
DW_CFA_undefined: r120 \(k2\)
|
||||
DW_CFA_advance_loc: 1 to 000000aa
|
||||
DW_CFA_undefined: r121 \(k3\)
|
||||
DW_CFA_advance_loc: 1 to 000000ab
|
||||
DW_CFA_undefined: r122 \(k4\)
|
||||
DW_CFA_advance_loc: 1 to 000000ac
|
||||
DW_CFA_undefined: r123 \(k5\)
|
||||
DW_CFA_advance_loc: 1 to 000000ad
|
||||
DW_CFA_undefined: r124 \(k6\)
|
||||
DW_CFA_advance_loc: 1 to 000000ae
|
||||
DW_CFA_undefined: r125 \(k7\)
|
||||
DW_CFA_nop
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,8 @@ Disassembly of section \.text:
|
|||
.*[ ]+R_386_16[ ]+mm0
|
||||
.*[ ]+R_386_16[ ]+xmm0
|
||||
.*[ ]+R_386_16[ ]+ymm0
|
||||
.*[ ]+R_386_16[ ]+xmm16
|
||||
.*[ ]+R_386_16[ ]+zmm0
|
||||
.*[ ]+R_386_32[ ]+rax
|
||||
.*[ ]+R_386_32[ ]+axl
|
||||
.*[ ]+R_386_32[ ]+r8b
|
||||
|
|
@ -33,6 +35,8 @@ Disassembly of section \.text:
|
|||
.*[ ]+R_386_32[ ]+mm0
|
||||
.*[ ]+R_386_32[ ]+xmm0
|
||||
.*[ ]+R_386_32[ ]+ymm0
|
||||
.*[ ]+R_386_32[ ]+xmm16
|
||||
.*[ ]+R_386_32[ ]+zmm0
|
||||
.*:[ ]+dd c0[ ]+ffree[ ]+%st(\(0\))?
|
||||
.*:[ ]+0f ef c0[ ]+pxor[ ]+%mm0,%mm0
|
||||
.*:[ ]+0f 57 c0[ ]+xorps[ ]+%xmm0,%xmm0
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@
|
|||
mov ax, mm0 ; add [bx+si], al
|
||||
mov ax, xmm0 ; add [bx+si], al
|
||||
mov ax, ymm0 ; add [bx+si], al
|
||||
mov ax, xmm16 ; add [bx+si], al
|
||||
mov ax, zmm0 ; add [bx+si], al
|
||||
|
||||
.arch generic32
|
||||
.code32
|
||||
|
|
@ -34,6 +36,8 @@
|
|||
mov eax, mm0
|
||||
mov eax, xmm0
|
||||
mov eax, ymm0
|
||||
mov eax, xmm16
|
||||
mov eax, zmm0
|
||||
|
||||
.arch .387
|
||||
ffree st
|
||||
|
|
|
|||
|
|
@ -0,0 +1,71 @@
|
|||
.*: Assembler messages:
|
||||
.*:4: Error: .*
|
||||
.*:5: Error: .*
|
||||
.*:6: Error: .*
|
||||
.*:7: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:9: Error: .*
|
||||
.*:11: Error: .*
|
||||
.*:12: Error: .*
|
||||
.*:14: Error: .*
|
||||
.*:15: Error: .*
|
||||
.*:18: Error: .*
|
||||
.*:19: Error: .*
|
||||
.*:20: Error: .*
|
||||
.*:21: Error: .*
|
||||
.*:21: Error: .*
|
||||
.*:22: Error: .*
|
||||
.*:22: Error: .*
|
||||
.*:23: Error: .*
|
||||
.*:23: Error: .*
|
||||
.*:25: Error: .*
|
||||
.*:26: Error: .*
|
||||
.*:28: Error: .*
|
||||
.*:29: Error: .*
|
||||
.*:31: Error: .*
|
||||
.*:32: Error: .*
|
||||
.*:33: Error: .*
|
||||
.*:34: Error: .*
|
||||
.*:35: Error: .*
|
||||
.*:36: Error: .*
|
||||
.*:37: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+# Check illegal AVX512F instructions
|
||||
[ ]*2[ ]+\.text
|
||||
[ ]*3[ ]+_start:
|
||||
[ ]*4[ ]+mov \{sae\}, %eax\{%k1\}
|
||||
[ ]*5[ ]+mov \{sae\}, %eax
|
||||
[ ]*6[ ]+mov %ebx, %eax\{%k2\}
|
||||
[ ]*7[ ]+vaddps %zmm3, %zmm1, %zmm2\{z\}\{%k1\}\{z\}
|
||||
[ ]*8[ ]+vaddps %zmm3, %zmm1\{%k3\}, %zmm2\{z\}
|
||||
[ ]*9[ ]+vaddps %zmm3, %zmm1\{%k1\}, %zmm2\{%k2\}
|
||||
[ ]*10[ ]+
|
||||
[ ]*11[ ]+vcvtps2pd \(%eax\), %zmm1\{1to8\}
|
||||
[ ]*12[ ]+vcvtps2pd \(%eax\)\{1to16\}, %zmm1
|
||||
[ ]*13[ ]+
|
||||
[ ]*14[ ]+vcvtps2pd \(%eax\)\{%k1\}, %zmm1
|
||||
[ ]*15[ ]+vcvtps2pd \(%eax\)\{z\}, %zmm1
|
||||
[ ]*16[ ]+
|
||||
[ ]*17[ ]+\.intel_syntax noprefix
|
||||
[ ]*18[ ]+mov eax\{k1\}, \{sae\}
|
||||
[ ]*19[ ]+mov eax, \{sae\}
|
||||
[ ]*20[ ]+mov eax\{k2\}, ebx
|
||||
[ ]*21[ ]+vaddps zmm2\{z\}\{k1\}\{z\}, zmm1, zmm3
|
||||
[ ]*22[ ]+vaddps zmm2\{z\}, zmm1\{k3\}, zmm3
|
||||
[ ]*23[ ]+vaddps zmm2\{k2\}, zmm1\{k1\}, zmm3
|
||||
[ ]*24[ ]+
|
||||
[ ]*25[ ]+vcvtps2pd zmm1\{1to8\}, \[eax\]
|
||||
[ ]*26[ ]+vcvtps2pd zmm1, \[eax\]\{1to16\}
|
||||
[ ]*27[ ]+
|
||||
[ ]*28[ ]+vcvtps2pd zmm1, \[eax\]\{k1\}
|
||||
[ ]*29[ ]+vcvtps2pd zmm1, \[eax\]\{z\}
|
||||
[ ]*30[ ]+
|
||||
[ ]*31[ ]+vaddps zmm2, zmm1, QWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*32[ ]+vaddps zmm2, zmm1, QWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*33[ ]+vaddpd zmm2, zmm1, DWORD PTR \[eax\]\{1to8\}
|
||||
[ ]*34[ ]+vaddpd zmm2, zmm1, DWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*35[ ]+vaddps zmm2, zmm1, ZMMWORD PTR \[eax\]\{1to16\}
|
||||
[ ]*36[ ]+vaddps zmm2, zmm1, DWORD PTR \[eax\]
|
||||
[ ]*37[ ]+vaddpd zmm2, zmm1, QWORD PTR \[eax\]
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
# Check illegal AVX512F instructions
|
||||
.text
|
||||
_start:
|
||||
mov {sae}, %eax{%k1}
|
||||
mov {sae}, %eax
|
||||
mov %ebx, %eax{%k2}
|
||||
vaddps %zmm3, %zmm1, %zmm2{z}{%k1}{z}
|
||||
vaddps %zmm3, %zmm1{%k3}, %zmm2{z}
|
||||
vaddps %zmm3, %zmm1{%k1}, %zmm2{%k2}
|
||||
|
||||
vcvtps2pd (%eax), %zmm1{1to8}
|
||||
vcvtps2pd (%eax){1to16}, %zmm1
|
||||
|
||||
vcvtps2pd (%eax){%k1}, %zmm1
|
||||
vcvtps2pd (%eax){z}, %zmm1
|
||||
|
||||
.intel_syntax noprefix
|
||||
mov eax{k1}, {sae}
|
||||
mov eax, {sae}
|
||||
mov eax{k2}, ebx
|
||||
vaddps zmm2{z}{k1}{z}, zmm1, zmm3
|
||||
vaddps zmm2{z}, zmm1{k3}, zmm3
|
||||
vaddps zmm2{k2}, zmm1{k1}, zmm3
|
||||
|
||||
vcvtps2pd zmm1{1to8}, [eax]
|
||||
vcvtps2pd zmm1, [eax]{1to16}
|
||||
|
||||
vcvtps2pd zmm1, [eax]{k1}
|
||||
vcvtps2pd zmm1, [eax]{z}
|
||||
|
||||
vaddps zmm2, zmm1, QWORD PTR [eax]{1to8}
|
||||
vaddps zmm2, zmm1, QWORD PTR [eax]{1to16}
|
||||
vaddpd zmm2, zmm1, DWORD PTR [eax]{1to8}
|
||||
vaddpd zmm2, zmm1, DWORD PTR [eax]{1to16}
|
||||
vaddps zmm2, zmm1, ZMMWORD PTR [eax]{1to16}
|
||||
vaddps zmm2, zmm1, DWORD PTR [eax]
|
||||
vaddpd zmm2, zmm1, QWORD PTR [eax]
|
||||
|
|
@ -9,7 +9,7 @@ Disassembly of section .text:
|
|||
0+ <amd_prefetch>:
|
||||
\s*[a-f0-9]+: 0f 0d 00 prefetch BYTE PTR \[eax\]
|
||||
\s*[a-f0-9]+: 0f 0d 08 prefetchw BYTE PTR \[eax\]
|
||||
\s*[a-f0-9]+: 0f 0d 10 prefetch BYTE PTR \[eax\]
|
||||
\s*[a-f0-9]+: 0f 0d 10 prefetchwt1 BYTE PTR \[eax\]
|
||||
\s*[a-f0-9]+: 0f 0d 18 prefetch BYTE PTR \[eax\]
|
||||
\s*[a-f0-9]+: 0f 0d 20 prefetch BYTE PTR \[eax\]
|
||||
\s*[a-f0-9]+: 0f 0d 28 prefetch BYTE PTR \[eax\]
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ Disassembly of section .text:
|
|||
0+ <amd_prefetch>:
|
||||
\s*[a-f0-9]+: 0f 0d 00 prefetch \(%eax\)
|
||||
\s*[a-f0-9]+: 0f 0d 08 prefetchw \(%eax\)
|
||||
\s*[a-f0-9]+: 0f 0d 10 prefetch \(%eax\)
|
||||
\s*[a-f0-9]+: 0f 0d 10 prefetchwt1 \(%eax\)
|
||||
\s*[a-f0-9]+: 0f 0d 18 prefetch \(%eax\)
|
||||
\s*[a-f0-9]+: 0f 0d 20 prefetch \(%eax\)
|
||||
\s*[a-f0-9]+: 0f 0d 28 prefetch \(%eax\)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,180 @@
|
|||
#as:
|
||||
#objdump: -dwMintel
|
||||
#name: x86_64 AVX512CD insns (Intel disassembly)
|
||||
#source: x86-64-avx512cd.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 c4 f5 vpconflictd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f c4 f5 vpconflictd zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf c4 f5 vpconflictd zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 31 vpconflictd zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 c4 b4 f0 23 01 00 00 vpconflictd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 31 vpconflictd zmm30,DWORD PTR \[rcx\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 72 7f vpconflictd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 b2 00 20 00 00 vpconflictd zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 72 80 vpconflictd zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 b2 c0 df ff ff vpconflictd zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 72 7f vpconflictd zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 b2 00 02 00 00 vpconflictd zmm30,DWORD PTR \[rdx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 72 80 vpconflictd zmm30,DWORD PTR \[rdx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 b2 fc fd ff ff vpconflictd zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 c4 f5 vpconflictq zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f c4 f5 vpconflictq zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf c4 f5 vpconflictq zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 31 vpconflictq zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 c4 b4 f0 23 01 00 00 vpconflictq zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 31 vpconflictq zmm30,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 72 7f vpconflictq zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 b2 00 20 00 00 vpconflictq zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 72 80 vpconflictq zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 b2 c0 df ff ff vpconflictq zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 72 7f vpconflictq zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 b2 00 04 00 00 vpconflictq zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 72 80 vpconflictq zmm30,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 b2 f8 fb ff ff vpconflictq zmm30,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 44 f5 vplzcntd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f 44 f5 vplzcntd zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf 44 f5 vplzcntd zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 31 vplzcntd zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 44 b4 f0 23 01 00 00 vplzcntd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 31 vplzcntd zmm30,DWORD PTR \[rcx\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 72 7f vplzcntd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 b2 00 20 00 00 vplzcntd zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 72 80 vplzcntd zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 b2 c0 df ff ff vplzcntd zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 72 7f vplzcntd zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 b2 00 02 00 00 vplzcntd zmm30,DWORD PTR \[rdx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 72 80 vplzcntd zmm30,DWORD PTR \[rdx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 b2 fc fd ff ff vplzcntd zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 44 f5 vplzcntq zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 44 f5 vplzcntq zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 44 f5 vplzcntq zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 31 vplzcntq zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 44 b4 f0 23 01 00 00 vplzcntq zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 31 vplzcntq zmm30,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 72 7f vplzcntq zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 b2 00 20 00 00 vplzcntq zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 72 80 vplzcntq zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 b2 c0 df ff ff vplzcntq zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 72 7f vplzcntq zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 00 04 00 00 vplzcntq zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 72 80 vplzcntq zmm30,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 f8 fb ff ff vplzcntq zmm30,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 92 16 40 27 ec vptestnmd k5,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+: 62 92 16 47 27 ec vptestnmd k5\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 29 vptestnmd k5,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 b2 16 40 27 ac f0 23 01 00 00 vptestnmd k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 29 vptestnmd k5,zmm29,DWORD PTR \[rcx\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 7f vptestnmd k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 aa 00 20 00 00 vptestnmd k5,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 80 vptestnmd k5,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 aa c0 df ff ff vptestnmd k5,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 7f vptestnmd k5,zmm29,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 aa 00 02 00 00 vptestnmd k5,zmm29,DWORD PTR \[rdx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 80 vptestnmd k5,zmm29,DWORD PTR \[rdx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 aa fc fd ff ff vptestnmd k5,zmm29,DWORD PTR \[rdx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 92 96 40 27 ec vptestnmq k5,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+: 62 92 96 47 27 ec vptestnmq k5\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 29 vptestnmq k5,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 b2 96 40 27 ac f0 23 01 00 00 vptestnmq k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 29 vptestnmq k5,zmm29,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 7f vptestnmq k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 aa 00 20 00 00 vptestnmq k5,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 80 vptestnmq k5,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 aa c0 df ff ff vptestnmq k5,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 7f vptestnmq k5,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 aa 00 04 00 00 vptestnmq k5,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 80 vptestnmq k5,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 aa f8 fb ff ff vptestnmq k5,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 7e 48 3a f6 vpbroadcastmw2d zmm30,k6
|
||||
[ ]*[a-f0-9]+: 62 62 fe 48 2a f6 vpbroadcastmb2q zmm30,k6
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 c4 f5 vpconflictd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f c4 f5 vpconflictd zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf c4 f5 vpconflictd zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 31 vpconflictd zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 c4 b4 f0 34 12 00 00 vpconflictd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 31 vpconflictd zmm30,DWORD PTR \[rcx\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 72 7f vpconflictd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 b2 00 20 00 00 vpconflictd zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 72 80 vpconflictd zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 b2 c0 df ff ff vpconflictd zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 72 7f vpconflictd zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 b2 00 02 00 00 vpconflictd zmm30,DWORD PTR \[rdx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 72 80 vpconflictd zmm30,DWORD PTR \[rdx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 b2 fc fd ff ff vpconflictd zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 c4 f5 vpconflictq zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f c4 f5 vpconflictq zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf c4 f5 vpconflictq zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 31 vpconflictq zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 c4 b4 f0 34 12 00 00 vpconflictq zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 31 vpconflictq zmm30,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 72 7f vpconflictq zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 b2 00 20 00 00 vpconflictq zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 72 80 vpconflictq zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 b2 c0 df ff ff vpconflictq zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 72 7f vpconflictq zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 b2 00 04 00 00 vpconflictq zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 72 80 vpconflictq zmm30,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 b2 f8 fb ff ff vpconflictq zmm30,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 44 f5 vplzcntd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f 44 f5 vplzcntd zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf 44 f5 vplzcntd zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 31 vplzcntd zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 44 b4 f0 34 12 00 00 vplzcntd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 31 vplzcntd zmm30,DWORD PTR \[rcx\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 72 7f vplzcntd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 b2 00 20 00 00 vplzcntd zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 72 80 vplzcntd zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 b2 c0 df ff ff vplzcntd zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 72 7f vplzcntd zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 b2 00 02 00 00 vplzcntd zmm30,DWORD PTR \[rdx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 72 80 vplzcntd zmm30,DWORD PTR \[rdx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 b2 fc fd ff ff vplzcntd zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 44 f5 vplzcntq zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 44 f5 vplzcntq zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 44 f5 vplzcntq zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 31 vplzcntq zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 44 b4 f0 34 12 00 00 vplzcntq zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 31 vplzcntq zmm30,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 72 7f vplzcntq zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 b2 00 20 00 00 vplzcntq zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 72 80 vplzcntq zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 b2 c0 df ff ff vplzcntq zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 72 7f vplzcntq zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 00 04 00 00 vplzcntq zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 72 80 vplzcntq zmm30,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 f8 fb ff ff vplzcntq zmm30,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 92 16 40 27 ec vptestnmd k5,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+: 62 92 16 47 27 ec vptestnmd k5\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 29 vptestnmd k5,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 b2 16 40 27 ac f0 34 12 00 00 vptestnmd k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 29 vptestnmd k5,zmm29,DWORD PTR \[rcx\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 7f vptestnmd k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 aa 00 20 00 00 vptestnmd k5,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 80 vptestnmd k5,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 aa c0 df ff ff vptestnmd k5,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 7f vptestnmd k5,zmm29,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 aa 00 02 00 00 vptestnmd k5,zmm29,DWORD PTR \[rdx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 80 vptestnmd k5,zmm29,DWORD PTR \[rdx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 aa fc fd ff ff vptestnmd k5,zmm29,DWORD PTR \[rdx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 92 96 40 27 ec vptestnmq k5,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+: 62 92 96 47 27 ec vptestnmq k5\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 29 vptestnmq k5,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 b2 96 40 27 ac f0 34 12 00 00 vptestnmq k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 29 vptestnmq k5,zmm29,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 7f vptestnmq k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 aa 00 20 00 00 vptestnmq k5,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 80 vptestnmq k5,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 aa c0 df ff ff vptestnmq k5,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 7f vptestnmq k5,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 aa 00 04 00 00 vptestnmq k5,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 80 vptestnmq k5,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 aa f8 fb ff ff vptestnmq k5,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 7e 48 3a f6 vpbroadcastmw2d zmm30,k6
|
||||
[ ]*[a-f0-9]+: 62 62 fe 48 2a f6 vpbroadcastmb2q zmm30,k6
|
||||
#pass
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86_64 AVX512CD insns
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 c4 f5 vpconflictd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f c4 f5 vpconflictd %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf c4 f5 vpconflictd %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 31 vpconflictd \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 c4 b4 f0 23 01 00 00 vpconflictd 0x123\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 31 vpconflictd \(%rcx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 72 7f vpconflictd 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 b2 00 20 00 00 vpconflictd 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 72 80 vpconflictd -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 b2 c0 df ff ff vpconflictd -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 72 7f vpconflictd 0x1fc\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 b2 00 02 00 00 vpconflictd 0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 72 80 vpconflictd -0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 b2 fc fd ff ff vpconflictd -0x204\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 c4 f5 vpconflictq %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f c4 f5 vpconflictq %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf c4 f5 vpconflictq %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 31 vpconflictq \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 c4 b4 f0 23 01 00 00 vpconflictq 0x123\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 31 vpconflictq \(%rcx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 72 7f vpconflictq 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 b2 00 20 00 00 vpconflictq 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 72 80 vpconflictq -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 b2 c0 df ff ff vpconflictq -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 72 7f vpconflictq 0x3f8\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 b2 00 04 00 00 vpconflictq 0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 72 80 vpconflictq -0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 b2 f8 fb ff ff vpconflictq -0x408\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 44 f5 vplzcntd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f 44 f5 vplzcntd %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf 44 f5 vplzcntd %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 31 vplzcntd \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 44 b4 f0 23 01 00 00 vplzcntd 0x123\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 31 vplzcntd \(%rcx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 72 7f vplzcntd 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 b2 00 20 00 00 vplzcntd 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 72 80 vplzcntd -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 b2 c0 df ff ff vplzcntd -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 72 7f vplzcntd 0x1fc\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 b2 00 02 00 00 vplzcntd 0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 72 80 vplzcntd -0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 b2 fc fd ff ff vplzcntd -0x204\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 44 f5 vplzcntq %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 44 f5 vplzcntq %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 44 f5 vplzcntq %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 31 vplzcntq \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 44 b4 f0 23 01 00 00 vplzcntq 0x123\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 31 vplzcntq \(%rcx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 72 7f vplzcntq 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 b2 00 20 00 00 vplzcntq 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 72 80 vplzcntq -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 b2 c0 df ff ff vplzcntq -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 72 7f vplzcntq 0x3f8\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 00 04 00 00 vplzcntq 0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 72 80 vplzcntq -0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 f8 fb ff ff vplzcntq -0x408\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 92 16 40 27 ec vptestnmd %zmm28,%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 92 16 47 27 ec vptestnmd %zmm28,%zmm29,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 29 vptestnmd \(%rcx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 b2 16 40 27 ac f0 23 01 00 00 vptestnmd 0x123\(%rax,%r14,8\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 29 vptestnmd \(%rcx\)\{1to16\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 7f vptestnmd 0x1fc0\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 aa 00 20 00 00 vptestnmd 0x2000\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 80 vptestnmd -0x2000\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 aa c0 df ff ff vptestnmd -0x2040\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 7f vptestnmd 0x1fc\(%rdx\)\{1to16\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 aa 00 02 00 00 vptestnmd 0x200\(%rdx\)\{1to16\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 80 vptestnmd -0x200\(%rdx\)\{1to16\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 aa fc fd ff ff vptestnmd -0x204\(%rdx\)\{1to16\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 92 96 40 27 ec vptestnmq %zmm28,%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 92 96 47 27 ec vptestnmq %zmm28,%zmm29,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 29 vptestnmq \(%rcx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 b2 96 40 27 ac f0 23 01 00 00 vptestnmq 0x123\(%rax,%r14,8\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 29 vptestnmq \(%rcx\)\{1to8\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 7f vptestnmq 0x1fc0\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 aa 00 20 00 00 vptestnmq 0x2000\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 80 vptestnmq -0x2000\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 aa c0 df ff ff vptestnmq -0x2040\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 7f vptestnmq 0x3f8\(%rdx\)\{1to8\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 aa 00 04 00 00 vptestnmq 0x400\(%rdx\)\{1to8\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 80 vptestnmq -0x400\(%rdx\)\{1to8\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 aa f8 fb ff ff vptestnmq -0x408\(%rdx\)\{1to8\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 62 7e 48 3a f6 vpbroadcastmw2d %k6,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fe 48 2a f6 vpbroadcastmb2q %k6,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 c4 f5 vpconflictd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f c4 f5 vpconflictd %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf c4 f5 vpconflictd %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 31 vpconflictd \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 c4 b4 f0 34 12 00 00 vpconflictd 0x1234\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 31 vpconflictd \(%rcx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 72 7f vpconflictd 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 b2 00 20 00 00 vpconflictd 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 72 80 vpconflictd -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c4 b2 c0 df ff ff vpconflictd -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 72 7f vpconflictd 0x1fc\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 b2 00 02 00 00 vpconflictd 0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 72 80 vpconflictd -0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c4 b2 fc fd ff ff vpconflictd -0x204\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 c4 f5 vpconflictq %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f c4 f5 vpconflictq %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf c4 f5 vpconflictq %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 31 vpconflictq \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 c4 b4 f0 34 12 00 00 vpconflictq 0x1234\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 31 vpconflictq \(%rcx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 72 7f vpconflictq 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 b2 00 20 00 00 vpconflictq 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 72 80 vpconflictq -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c4 b2 c0 df ff ff vpconflictq -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 72 7f vpconflictq 0x3f8\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 b2 00 04 00 00 vpconflictq 0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 72 80 vpconflictq -0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c4 b2 f8 fb ff ff vpconflictq -0x408\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 44 f5 vplzcntd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f 44 f5 vplzcntd %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf 44 f5 vplzcntd %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 31 vplzcntd \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 44 b4 f0 34 12 00 00 vplzcntd 0x1234\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 31 vplzcntd \(%rcx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 72 7f vplzcntd 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 b2 00 20 00 00 vplzcntd 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 72 80 vplzcntd -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 44 b2 c0 df ff ff vplzcntd -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 72 7f vplzcntd 0x1fc\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 b2 00 02 00 00 vplzcntd 0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 72 80 vplzcntd -0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 44 b2 fc fd ff ff vplzcntd -0x204\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 44 f5 vplzcntq %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 44 f5 vplzcntq %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 44 f5 vplzcntq %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 31 vplzcntq \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 44 b4 f0 34 12 00 00 vplzcntq 0x1234\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 31 vplzcntq \(%rcx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 72 7f vplzcntq 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 b2 00 20 00 00 vplzcntq 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 72 80 vplzcntq -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 44 b2 c0 df ff ff vplzcntq -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 72 7f vplzcntq 0x3f8\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 00 04 00 00 vplzcntq 0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 72 80 vplzcntq -0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 f8 fb ff ff vplzcntq -0x408\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 92 16 40 27 ec vptestnmd %zmm28,%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 92 16 47 27 ec vptestnmd %zmm28,%zmm29,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 29 vptestnmd \(%rcx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 b2 16 40 27 ac f0 34 12 00 00 vptestnmd 0x1234\(%rax,%r14,8\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 29 vptestnmd \(%rcx\)\{1to16\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 7f vptestnmd 0x1fc0\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 aa 00 20 00 00 vptestnmd 0x2000\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 80 vptestnmd -0x2000\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 40 27 aa c0 df ff ff vptestnmd -0x2040\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 7f vptestnmd 0x1fc\(%rdx\)\{1to16\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 aa 00 02 00 00 vptestnmd 0x200\(%rdx\)\{1to16\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 80 vptestnmd -0x200\(%rdx\)\{1to16\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 16 50 27 aa fc fd ff ff vptestnmd -0x204\(%rdx\)\{1to16\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 92 96 40 27 ec vptestnmq %zmm28,%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 92 96 47 27 ec vptestnmq %zmm28,%zmm29,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 29 vptestnmq \(%rcx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 b2 96 40 27 ac f0 34 12 00 00 vptestnmq 0x1234\(%rax,%r14,8\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 29 vptestnmq \(%rcx\)\{1to8\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 7f vptestnmq 0x1fc0\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 aa 00 20 00 00 vptestnmq 0x2000\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 80 vptestnmq -0x2000\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 40 27 aa c0 df ff ff vptestnmq -0x2040\(%rdx\),%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 7f vptestnmq 0x3f8\(%rdx\)\{1to8\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 aa 00 04 00 00 vptestnmq 0x400\(%rdx\)\{1to8\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 80 vptestnmq -0x400\(%rdx\)\{1to8\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 f2 96 50 27 aa f8 fb ff ff vptestnmq -0x408\(%rdx\)\{1to8\},%zmm29,%k5
|
||||
[ ]*[a-f0-9]+: 62 62 7e 48 3a f6 vpbroadcastmw2d %k6,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fe 48 2a f6 vpbroadcastmb2q %k6,%zmm30
|
||||
#pass
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
# Check 64bit AVX512CD instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
vpconflictd %zmm29, %zmm30 # AVX512CD
|
||||
vpconflictd %zmm29, %zmm30{%k7} # AVX512CD
|
||||
vpconflictd %zmm29, %zmm30{%k7}{z} # AVX512CD
|
||||
vpconflictd (%rcx), %zmm30 # AVX512CD
|
||||
vpconflictd 0x123(%rax,%r14,8), %zmm30 # AVX512CD
|
||||
vpconflictd (%rcx){1to16}, %zmm30 # AVX512CD
|
||||
vpconflictd 8128(%rdx), %zmm30 # AVX512CD Disp8
|
||||
vpconflictd 8192(%rdx), %zmm30 # AVX512CD
|
||||
vpconflictd -8192(%rdx), %zmm30 # AVX512CD Disp8
|
||||
vpconflictd -8256(%rdx), %zmm30 # AVX512CD
|
||||
vpconflictd 508(%rdx){1to16}, %zmm30 # AVX512CD Disp8
|
||||
vpconflictd 512(%rdx){1to16}, %zmm30 # AVX512CD
|
||||
vpconflictd -512(%rdx){1to16}, %zmm30 # AVX512CD Disp8
|
||||
vpconflictd -516(%rdx){1to16}, %zmm30 # AVX512CD
|
||||
|
||||
vpconflictq %zmm29, %zmm30 # AVX512CD
|
||||
vpconflictq %zmm29, %zmm30{%k7} # AVX512CD
|
||||
vpconflictq %zmm29, %zmm30{%k7}{z} # AVX512CD
|
||||
vpconflictq (%rcx), %zmm30 # AVX512CD
|
||||
vpconflictq 0x123(%rax,%r14,8), %zmm30 # AVX512CD
|
||||
vpconflictq (%rcx){1to8}, %zmm30 # AVX512CD
|
||||
vpconflictq 8128(%rdx), %zmm30 # AVX512CD Disp8
|
||||
vpconflictq 8192(%rdx), %zmm30 # AVX512CD
|
||||
vpconflictq -8192(%rdx), %zmm30 # AVX512CD Disp8
|
||||
vpconflictq -8256(%rdx), %zmm30 # AVX512CD
|
||||
vpconflictq 1016(%rdx){1to8}, %zmm30 # AVX512CD Disp8
|
||||
vpconflictq 1024(%rdx){1to8}, %zmm30 # AVX512CD
|
||||
vpconflictq -1024(%rdx){1to8}, %zmm30 # AVX512CD Disp8
|
||||
vpconflictq -1032(%rdx){1to8}, %zmm30 # AVX512CD
|
||||
|
||||
vplzcntd %zmm29, %zmm30 # AVX512CD
|
||||
vplzcntd %zmm29, %zmm30{%k7} # AVX512CD
|
||||
vplzcntd %zmm29, %zmm30{%k7}{z} # AVX512CD
|
||||
vplzcntd (%rcx), %zmm30 # AVX512CD
|
||||
vplzcntd 0x123(%rax,%r14,8), %zmm30 # AVX512CD
|
||||
vplzcntd (%rcx){1to16}, %zmm30 # AVX512CD
|
||||
vplzcntd 8128(%rdx), %zmm30 # AVX512CD Disp8
|
||||
vplzcntd 8192(%rdx), %zmm30 # AVX512CD
|
||||
vplzcntd -8192(%rdx), %zmm30 # AVX512CD Disp8
|
||||
vplzcntd -8256(%rdx), %zmm30 # AVX512CD
|
||||
vplzcntd 508(%rdx){1to16}, %zmm30 # AVX512CD Disp8
|
||||
vplzcntd 512(%rdx){1to16}, %zmm30 # AVX512CD
|
||||
vplzcntd -512(%rdx){1to16}, %zmm30 # AVX512CD Disp8
|
||||
vplzcntd -516(%rdx){1to16}, %zmm30 # AVX512CD
|
||||
|
||||
vplzcntq %zmm29, %zmm30 # AVX512CD
|
||||
vplzcntq %zmm29, %zmm30{%k7} # AVX512CD
|
||||
vplzcntq %zmm29, %zmm30{%k7}{z} # AVX512CD
|
||||
vplzcntq (%rcx), %zmm30 # AVX512CD
|
||||
vplzcntq 0x123(%rax,%r14,8), %zmm30 # AVX512CD
|
||||
vplzcntq (%rcx){1to8}, %zmm30 # AVX512CD
|
||||
vplzcntq 8128(%rdx), %zmm30 # AVX512CD Disp8
|
||||
vplzcntq 8192(%rdx), %zmm30 # AVX512CD
|
||||
vplzcntq -8192(%rdx), %zmm30 # AVX512CD Disp8
|
||||
vplzcntq -8256(%rdx), %zmm30 # AVX512CD
|
||||
vplzcntq 1016(%rdx){1to8}, %zmm30 # AVX512CD Disp8
|
||||
vplzcntq 1024(%rdx){1to8}, %zmm30 # AVX512CD
|
||||
vplzcntq -1024(%rdx){1to8}, %zmm30 # AVX512CD Disp8
|
||||
vplzcntq -1032(%rdx){1to8}, %zmm30 # AVX512CD
|
||||
|
||||
vptestnmd %zmm28, %zmm29, %k5 # AVX512CD
|
||||
vptestnmd %zmm28, %zmm29, %k5{%k7} # AVX512CD
|
||||
vptestnmd (%rcx), %zmm29, %k5 # AVX512CD
|
||||
vptestnmd 0x123(%rax,%r14,8), %zmm29, %k5 # AVX512CD
|
||||
vptestnmd (%rcx){1to16}, %zmm29, %k5 # AVX512CD
|
||||
vptestnmd 8128(%rdx), %zmm29, %k5 # AVX512CD Disp8
|
||||
vptestnmd 8192(%rdx), %zmm29, %k5 # AVX512CD
|
||||
vptestnmd -8192(%rdx), %zmm29, %k5 # AVX512CD Disp8
|
||||
vptestnmd -8256(%rdx), %zmm29, %k5 # AVX512CD
|
||||
vptestnmd 508(%rdx){1to16}, %zmm29, %k5 # AVX512CD Disp8
|
||||
vptestnmd 512(%rdx){1to16}, %zmm29, %k5 # AVX512CD
|
||||
vptestnmd -512(%rdx){1to16}, %zmm29, %k5 # AVX512CD Disp8
|
||||
vptestnmd -516(%rdx){1to16}, %zmm29, %k5 # AVX512CD
|
||||
|
||||
vptestnmq %zmm28, %zmm29, %k5 # AVX512CD
|
||||
vptestnmq %zmm28, %zmm29, %k5{%k7} # AVX512CD
|
||||
vptestnmq (%rcx), %zmm29, %k5 # AVX512CD
|
||||
vptestnmq 0x123(%rax,%r14,8), %zmm29, %k5 # AVX512CD
|
||||
vptestnmq (%rcx){1to8}, %zmm29, %k5 # AVX512CD
|
||||
vptestnmq 8128(%rdx), %zmm29, %k5 # AVX512CD Disp8
|
||||
vptestnmq 8192(%rdx), %zmm29, %k5 # AVX512CD
|
||||
vptestnmq -8192(%rdx), %zmm29, %k5 # AVX512CD Disp8
|
||||
vptestnmq -8256(%rdx), %zmm29, %k5 # AVX512CD
|
||||
vptestnmq 1016(%rdx){1to8}, %zmm29, %k5 # AVX512CD Disp8
|
||||
vptestnmq 1024(%rdx){1to8}, %zmm29, %k5 # AVX512CD
|
||||
vptestnmq -1024(%rdx){1to8}, %zmm29, %k5 # AVX512CD Disp8
|
||||
vptestnmq -1032(%rdx){1to8}, %zmm29, %k5 # AVX512CD
|
||||
|
||||
vpbroadcastmw2d %k6, %zmm30 # AVX512CD
|
||||
|
||||
vpbroadcastmb2q %k6, %zmm30 # AVX512CD
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpconflictd zmm30, zmm29 # AVX512CD
|
||||
vpconflictd zmm30{k7}, zmm29 # AVX512CD
|
||||
vpconflictd zmm30{k7}{z}, zmm29 # AVX512CD
|
||||
vpconflictd zmm30, ZMMWORD PTR [rcx] # AVX512CD
|
||||
vpconflictd zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512CD
|
||||
vpconflictd zmm30, [rcx]{1to16} # AVX512CD
|
||||
vpconflictd zmm30, ZMMWORD PTR [rdx+8128] # AVX512CD Disp8
|
||||
vpconflictd zmm30, ZMMWORD PTR [rdx+8192] # AVX512CD
|
||||
vpconflictd zmm30, ZMMWORD PTR [rdx-8192] # AVX512CD Disp8
|
||||
vpconflictd zmm30, ZMMWORD PTR [rdx-8256] # AVX512CD
|
||||
vpconflictd zmm30, [rdx+508]{1to16} # AVX512CD Disp8
|
||||
vpconflictd zmm30, [rdx+512]{1to16} # AVX512CD
|
||||
vpconflictd zmm30, [rdx-512]{1to16} # AVX512CD Disp8
|
||||
vpconflictd zmm30, [rdx-516]{1to16} # AVX512CD
|
||||
|
||||
vpconflictq zmm30, zmm29 # AVX512CD
|
||||
vpconflictq zmm30{k7}, zmm29 # AVX512CD
|
||||
vpconflictq zmm30{k7}{z}, zmm29 # AVX512CD
|
||||
vpconflictq zmm30, ZMMWORD PTR [rcx] # AVX512CD
|
||||
vpconflictq zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512CD
|
||||
vpconflictq zmm30, [rcx]{1to8} # AVX512CD
|
||||
vpconflictq zmm30, ZMMWORD PTR [rdx+8128] # AVX512CD Disp8
|
||||
vpconflictq zmm30, ZMMWORD PTR [rdx+8192] # AVX512CD
|
||||
vpconflictq zmm30, ZMMWORD PTR [rdx-8192] # AVX512CD Disp8
|
||||
vpconflictq zmm30, ZMMWORD PTR [rdx-8256] # AVX512CD
|
||||
vpconflictq zmm30, [rdx+1016]{1to8} # AVX512CD Disp8
|
||||
vpconflictq zmm30, [rdx+1024]{1to8} # AVX512CD
|
||||
vpconflictq zmm30, [rdx-1024]{1to8} # AVX512CD Disp8
|
||||
vpconflictq zmm30, [rdx-1032]{1to8} # AVX512CD
|
||||
|
||||
vplzcntd zmm30, zmm29 # AVX512CD
|
||||
vplzcntd zmm30{k7}, zmm29 # AVX512CD
|
||||
vplzcntd zmm30{k7}{z}, zmm29 # AVX512CD
|
||||
vplzcntd zmm30, ZMMWORD PTR [rcx] # AVX512CD
|
||||
vplzcntd zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512CD
|
||||
vplzcntd zmm30, [rcx]{1to16} # AVX512CD
|
||||
vplzcntd zmm30, ZMMWORD PTR [rdx+8128] # AVX512CD Disp8
|
||||
vplzcntd zmm30, ZMMWORD PTR [rdx+8192] # AVX512CD
|
||||
vplzcntd zmm30, ZMMWORD PTR [rdx-8192] # AVX512CD Disp8
|
||||
vplzcntd zmm30, ZMMWORD PTR [rdx-8256] # AVX512CD
|
||||
vplzcntd zmm30, [rdx+508]{1to16} # AVX512CD Disp8
|
||||
vplzcntd zmm30, [rdx+512]{1to16} # AVX512CD
|
||||
vplzcntd zmm30, [rdx-512]{1to16} # AVX512CD Disp8
|
||||
vplzcntd zmm30, [rdx-516]{1to16} # AVX512CD
|
||||
|
||||
vplzcntq zmm30, zmm29 # AVX512CD
|
||||
vplzcntq zmm30{k7}, zmm29 # AVX512CD
|
||||
vplzcntq zmm30{k7}{z}, zmm29 # AVX512CD
|
||||
vplzcntq zmm30, ZMMWORD PTR [rcx] # AVX512CD
|
||||
vplzcntq zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512CD
|
||||
vplzcntq zmm30, [rcx]{1to8} # AVX512CD
|
||||
vplzcntq zmm30, ZMMWORD PTR [rdx+8128] # AVX512CD Disp8
|
||||
vplzcntq zmm30, ZMMWORD PTR [rdx+8192] # AVX512CD
|
||||
vplzcntq zmm30, ZMMWORD PTR [rdx-8192] # AVX512CD Disp8
|
||||
vplzcntq zmm30, ZMMWORD PTR [rdx-8256] # AVX512CD
|
||||
vplzcntq zmm30, [rdx+1016]{1to8} # AVX512CD Disp8
|
||||
vplzcntq zmm30, [rdx+1024]{1to8} # AVX512CD
|
||||
vplzcntq zmm30, [rdx-1024]{1to8} # AVX512CD Disp8
|
||||
vplzcntq zmm30, [rdx-1032]{1to8} # AVX512CD
|
||||
|
||||
vptestnmd k5, zmm29, zmm28 # AVX512CD
|
||||
vptestnmd k5{k7}, zmm29, zmm28 # AVX512CD
|
||||
vptestnmd k5, zmm29, ZMMWORD PTR [rcx] # AVX512CD
|
||||
vptestnmd k5, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512CD
|
||||
vptestnmd k5, zmm29, [rcx]{1to16} # AVX512CD
|
||||
vptestnmd k5, zmm29, ZMMWORD PTR [rdx+8128] # AVX512CD Disp8
|
||||
vptestnmd k5, zmm29, ZMMWORD PTR [rdx+8192] # AVX512CD
|
||||
vptestnmd k5, zmm29, ZMMWORD PTR [rdx-8192] # AVX512CD Disp8
|
||||
vptestnmd k5, zmm29, ZMMWORD PTR [rdx-8256] # AVX512CD
|
||||
vptestnmd k5, zmm29, [rdx+508]{1to16} # AVX512CD Disp8
|
||||
vptestnmd k5, zmm29, [rdx+512]{1to16} # AVX512CD
|
||||
vptestnmd k5, zmm29, [rdx-512]{1to16} # AVX512CD Disp8
|
||||
vptestnmd k5, zmm29, [rdx-516]{1to16} # AVX512CD
|
||||
|
||||
vptestnmq k5, zmm29, zmm28 # AVX512CD
|
||||
vptestnmq k5{k7}, zmm29, zmm28 # AVX512CD
|
||||
vptestnmq k5, zmm29, ZMMWORD PTR [rcx] # AVX512CD
|
||||
vptestnmq k5, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512CD
|
||||
vptestnmq k5, zmm29, [rcx]{1to8} # AVX512CD
|
||||
vptestnmq k5, zmm29, ZMMWORD PTR [rdx+8128] # AVX512CD Disp8
|
||||
vptestnmq k5, zmm29, ZMMWORD PTR [rdx+8192] # AVX512CD
|
||||
vptestnmq k5, zmm29, ZMMWORD PTR [rdx-8192] # AVX512CD Disp8
|
||||
vptestnmq k5, zmm29, ZMMWORD PTR [rdx-8256] # AVX512CD
|
||||
vptestnmq k5, zmm29, [rdx+1016]{1to8} # AVX512CD Disp8
|
||||
vptestnmq k5, zmm29, [rdx+1024]{1to8} # AVX512CD
|
||||
vptestnmq k5, zmm29, [rdx-1024]{1to8} # AVX512CD Disp8
|
||||
vptestnmq k5, zmm29, [rdx-1032]{1to8} # AVX512CD
|
||||
|
||||
vpbroadcastmw2d zmm30, k6 # AVX512CD
|
||||
|
||||
vpbroadcastmb2q zmm30, k6 # AVX512CD
|
||||
|
||||
|
|
@ -0,0 +1,256 @@
|
|||
#as:
|
||||
#objdump: -dwMintel
|
||||
#name: x86_64 AVX512ER insns (Intel disassembly)
|
||||
#source: x86-64-avx512er.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 c8 f5 vexp2ps zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 18 c8 f5 vexp2ps zmm30,zmm29,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 31 vexp2ps zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 c8 b4 f0 23 01 00 00 vexp2ps zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 31 vexp2ps zmm30,DWORD PTR \[rcx\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 72 7f vexp2ps zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 b2 00 20 00 00 vexp2ps zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 72 80 vexp2ps zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 b2 c0 df ff ff vexp2ps zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 72 7f vexp2ps zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 b2 00 02 00 00 vexp2ps zmm30,DWORD PTR \[rdx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 72 80 vexp2ps zmm30,DWORD PTR \[rdx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 b2 fc fd ff ff vexp2ps zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 c8 f5 vexp2pd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 18 c8 f5 vexp2pd zmm30,zmm29,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 31 vexp2pd zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 c8 b4 f0 23 01 00 00 vexp2pd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 31 vexp2pd zmm30,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 72 7f vexp2pd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 b2 00 20 00 00 vexp2pd zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 72 80 vexp2pd zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 b2 c0 df ff ff vexp2pd zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 72 7f vexp2pd zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 b2 00 04 00 00 vexp2pd zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 72 80 vexp2pd zmm30,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 b2 f8 fb ff ff vexp2pd zmm30,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 ca f5 vrcp28ps zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f ca f5 vrcp28ps zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf ca f5 vrcp28ps zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 18 ca f5 vrcp28ps zmm30,zmm29,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca 31 vrcp28ps zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 ca b4 f0 23 01 00 00 vrcp28ps zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca 31 vrcp28ps zmm30,DWORD PTR \[rcx\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca 72 7f vrcp28ps zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca b2 00 20 00 00 vrcp28ps zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca 72 80 vrcp28ps zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca b2 c0 df ff ff vrcp28ps zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca 72 7f vrcp28ps zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca b2 00 02 00 00 vrcp28ps zmm30,DWORD PTR \[rdx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca 72 80 vrcp28ps zmm30,DWORD PTR \[rdx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca b2 fc fd ff ff vrcp28ps zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 ca f5 vrcp28pd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f ca f5 vrcp28pd zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf ca f5 vrcp28pd zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 18 ca f5 vrcp28pd zmm30,zmm29,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca 31 vrcp28pd zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 ca b4 f0 23 01 00 00 vrcp28pd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca 31 vrcp28pd zmm30,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca 72 7f vrcp28pd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca b2 00 20 00 00 vrcp28pd zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca 72 80 vrcp28pd zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca b2 c0 df ff ff vrcp28pd zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca 72 7f vrcp28pd zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca b2 00 04 00 00 vrcp28pd zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca 72 80 vrcp28pd zmm30,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca b2 f8 fb ff ff vrcp28pd zmm30,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 02 15 07 cb f4 vrcp28ss xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 15 87 cb f4 vrcp28ss xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 15 17 cb f4 vrcp28ss xmm30\{k7\},xmm29,xmm28,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb 31 vrcp28ss xmm30\{k7\},xmm29,DWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 15 07 cb b4 f0 23 01 00 00 vrcp28ss xmm30\{k7\},xmm29,DWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb 72 7f vrcp28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx\+0x1fc\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb b2 00 02 00 00 vrcp28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx\+0x200\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb 72 80 vrcp28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx-0x200\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb b2 fc fd ff ff vrcp28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx-0x204\]
|
||||
[ ]*[a-f0-9]+: 62 02 95 07 cb f4 vrcp28sd xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 95 87 cb f4 vrcp28sd xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 95 17 cb f4 vrcp28sd xmm30\{k7\},xmm29,xmm28,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb 31 vrcp28sd xmm30\{k7\},xmm29,QWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 95 07 cb b4 f0 23 01 00 00 vrcp28sd xmm30\{k7\},xmm29,QWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb 72 7f vrcp28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb b2 00 04 00 00 vrcp28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb 72 80 vrcp28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb b2 f8 fb ff ff vrcp28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 cc f5 vrsqrt28ps zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f cc f5 vrsqrt28ps zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf cc f5 vrsqrt28ps zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 18 cc f5 vrsqrt28ps zmm30,zmm29,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc 31 vrsqrt28ps zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 cc b4 f0 23 01 00 00 vrsqrt28ps zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc 31 vrsqrt28ps zmm30,DWORD PTR \[rcx\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc 72 7f vrsqrt28ps zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc b2 00 20 00 00 vrsqrt28ps zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc 72 80 vrsqrt28ps zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc b2 c0 df ff ff vrsqrt28ps zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc 72 7f vrsqrt28ps zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc b2 00 02 00 00 vrsqrt28ps zmm30,DWORD PTR \[rdx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc 72 80 vrsqrt28ps zmm30,DWORD PTR \[rdx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc b2 fc fd ff ff vrsqrt28ps zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 cc f5 vrsqrt28pd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f cc f5 vrsqrt28pd zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf cc f5 vrsqrt28pd zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 18 cc f5 vrsqrt28pd zmm30,zmm29,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc 31 vrsqrt28pd zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 cc b4 f0 23 01 00 00 vrsqrt28pd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc 31 vrsqrt28pd zmm30,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc 72 7f vrsqrt28pd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc b2 00 20 00 00 vrsqrt28pd zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc 72 80 vrsqrt28pd zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc b2 c0 df ff ff vrsqrt28pd zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc 72 7f vrsqrt28pd zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc b2 00 04 00 00 vrsqrt28pd zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc 72 80 vrsqrt28pd zmm30,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc b2 f8 fb ff ff vrsqrt28pd zmm30,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 02 15 07 cd f4 vrsqrt28ss xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 15 87 cd f4 vrsqrt28ss xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 15 17 cd f4 vrsqrt28ss xmm30\{k7\},xmm29,xmm28,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd 31 vrsqrt28ss xmm30\{k7\},xmm29,DWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 15 07 cd b4 f0 23 01 00 00 vrsqrt28ss xmm30\{k7\},xmm29,DWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd 72 7f vrsqrt28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx\+0x1fc\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd b2 00 02 00 00 vrsqrt28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx\+0x200\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd 72 80 vrsqrt28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx-0x200\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd b2 fc fd ff ff vrsqrt28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx-0x204\]
|
||||
[ ]*[a-f0-9]+: 62 02 95 07 cd f4 vrsqrt28sd xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 95 87 cd f4 vrsqrt28sd xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 95 17 cd f4 vrsqrt28sd xmm30\{k7\},xmm29,xmm28,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd 31 vrsqrt28sd xmm30\{k7\},xmm29,QWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 95 07 cd b4 f0 23 01 00 00 vrsqrt28sd xmm30\{k7\},xmm29,QWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd 72 7f vrsqrt28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd b2 00 04 00 00 vrsqrt28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd 72 80 vrsqrt28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd b2 f8 fb ff ff vrsqrt28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 c8 f5 vexp2ps zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 18 c8 f5 vexp2ps zmm30,zmm29,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 31 vexp2ps zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 c8 b4 f0 34 12 00 00 vexp2ps zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 31 vexp2ps zmm30,DWORD PTR \[rcx\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 72 7f vexp2ps zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 b2 00 20 00 00 vexp2ps zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 72 80 vexp2ps zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 b2 c0 df ff ff vexp2ps zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 72 7f vexp2ps zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 b2 00 02 00 00 vexp2ps zmm30,DWORD PTR \[rdx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 72 80 vexp2ps zmm30,DWORD PTR \[rdx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 b2 fc fd ff ff vexp2ps zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 c8 f5 vexp2pd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 18 c8 f5 vexp2pd zmm30,zmm29,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 31 vexp2pd zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 c8 b4 f0 34 12 00 00 vexp2pd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 31 vexp2pd zmm30,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 72 7f vexp2pd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 b2 00 20 00 00 vexp2pd zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 72 80 vexp2pd zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 b2 c0 df ff ff vexp2pd zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 72 7f vexp2pd zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 b2 00 04 00 00 vexp2pd zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 72 80 vexp2pd zmm30,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 b2 f8 fb ff ff vexp2pd zmm30,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 ca f5 vrcp28ps zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f ca f5 vrcp28ps zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf ca f5 vrcp28ps zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 18 ca f5 vrcp28ps zmm30,zmm29,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca 31 vrcp28ps zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 ca b4 f0 34 12 00 00 vrcp28ps zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca 31 vrcp28ps zmm30,DWORD PTR \[rcx\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca 72 7f vrcp28ps zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca b2 00 20 00 00 vrcp28ps zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca 72 80 vrcp28ps zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca b2 c0 df ff ff vrcp28ps zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca 72 7f vrcp28ps zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca b2 00 02 00 00 vrcp28ps zmm30,DWORD PTR \[rdx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca 72 80 vrcp28ps zmm30,DWORD PTR \[rdx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca b2 fc fd ff ff vrcp28ps zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 ca f5 vrcp28pd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f ca f5 vrcp28pd zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf ca f5 vrcp28pd zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 18 ca f5 vrcp28pd zmm30,zmm29,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca 31 vrcp28pd zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 ca b4 f0 34 12 00 00 vrcp28pd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca 31 vrcp28pd zmm30,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca 72 7f vrcp28pd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca b2 00 20 00 00 vrcp28pd zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca 72 80 vrcp28pd zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca b2 c0 df ff ff vrcp28pd zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca 72 7f vrcp28pd zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca b2 00 04 00 00 vrcp28pd zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca 72 80 vrcp28pd zmm30,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca b2 f8 fb ff ff vrcp28pd zmm30,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 02 15 07 cb f4 vrcp28ss xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 15 87 cb f4 vrcp28ss xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 15 17 cb f4 vrcp28ss xmm30\{k7\},xmm29,xmm28,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb 31 vrcp28ss xmm30\{k7\},xmm29,DWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 15 07 cb b4 f0 34 12 00 00 vrcp28ss xmm30\{k7\},xmm29,DWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb 72 7f vrcp28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx\+0x1fc\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb b2 00 02 00 00 vrcp28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx\+0x200\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb 72 80 vrcp28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx-0x200\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb b2 fc fd ff ff vrcp28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx-0x204\]
|
||||
[ ]*[a-f0-9]+: 62 02 95 07 cb f4 vrcp28sd xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 95 87 cb f4 vrcp28sd xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 95 17 cb f4 vrcp28sd xmm30\{k7\},xmm29,xmm28,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb 31 vrcp28sd xmm30\{k7\},xmm29,QWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 95 07 cb b4 f0 34 12 00 00 vrcp28sd xmm30\{k7\},xmm29,QWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb 72 7f vrcp28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb b2 00 04 00 00 vrcp28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb 72 80 vrcp28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb b2 f8 fb ff ff vrcp28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 cc f5 vrsqrt28ps zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f cc f5 vrsqrt28ps zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf cc f5 vrsqrt28ps zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 7d 18 cc f5 vrsqrt28ps zmm30,zmm29,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc 31 vrsqrt28ps zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 cc b4 f0 34 12 00 00 vrsqrt28ps zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc 31 vrsqrt28ps zmm30,DWORD PTR \[rcx\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc 72 7f vrsqrt28ps zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc b2 00 20 00 00 vrsqrt28ps zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc 72 80 vrsqrt28ps zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc b2 c0 df ff ff vrsqrt28ps zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc 72 7f vrsqrt28ps zmm30,DWORD PTR \[rdx\+0x1fc\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc b2 00 02 00 00 vrsqrt28ps zmm30,DWORD PTR \[rdx\+0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc 72 80 vrsqrt28ps zmm30,DWORD PTR \[rdx-0x200\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc b2 fc fd ff ff vrsqrt28ps zmm30,DWORD PTR \[rdx-0x204\]\{1to16\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 cc f5 vrsqrt28pd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f cc f5 vrsqrt28pd zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf cc f5 vrsqrt28pd zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd 18 cc f5 vrsqrt28pd zmm30,zmm29,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc 31 vrsqrt28pd zmm30,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 cc b4 f0 34 12 00 00 vrsqrt28pd zmm30,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc 31 vrsqrt28pd zmm30,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc 72 7f vrsqrt28pd zmm30,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc b2 00 20 00 00 vrsqrt28pd zmm30,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc 72 80 vrsqrt28pd zmm30,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc b2 c0 df ff ff vrsqrt28pd zmm30,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc 72 7f vrsqrt28pd zmm30,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc b2 00 04 00 00 vrsqrt28pd zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc 72 80 vrsqrt28pd zmm30,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc b2 f8 fb ff ff vrsqrt28pd zmm30,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+: 62 02 15 07 cd f4 vrsqrt28ss xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 15 87 cd f4 vrsqrt28ss xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 15 17 cd f4 vrsqrt28ss xmm30\{k7\},xmm29,xmm28,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd 31 vrsqrt28ss xmm30\{k7\},xmm29,DWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 15 07 cd b4 f0 34 12 00 00 vrsqrt28ss xmm30\{k7\},xmm29,DWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd 72 7f vrsqrt28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx\+0x1fc\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd b2 00 02 00 00 vrsqrt28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx\+0x200\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd 72 80 vrsqrt28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx-0x200\]
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd b2 fc fd ff ff vrsqrt28ss xmm30\{k7\},xmm29,DWORD PTR \[rdx-0x204\]
|
||||
[ ]*[a-f0-9]+: 62 02 95 07 cd f4 vrsqrt28sd xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 95 87 cd f4 vrsqrt28sd xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 02 95 17 cd f4 vrsqrt28sd xmm30\{k7\},xmm29,xmm28,\{sae\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd 31 vrsqrt28sd xmm30\{k7\},xmm29,QWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 95 07 cd b4 f0 34 12 00 00 vrsqrt28sd xmm30\{k7\},xmm29,QWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd 72 7f vrsqrt28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd b2 00 04 00 00 vrsqrt28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd 72 80 vrsqrt28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd b2 f8 fb ff ff vrsqrt28sd xmm30\{k7\},xmm29,QWORD PTR \[rdx-0x408\]
|
||||
#pass
|
||||
|
|
@ -0,0 +1,255 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86_64 AVX512ER insns
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 c8 f5 vexp2ps %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 18 c8 f5 vexp2ps \{sae\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 31 vexp2ps \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 c8 b4 f0 23 01 00 00 vexp2ps 0x123\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 31 vexp2ps \(%rcx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 72 7f vexp2ps 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 b2 00 20 00 00 vexp2ps 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 72 80 vexp2ps -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 b2 c0 df ff ff vexp2ps -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 72 7f vexp2ps 0x1fc\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 b2 00 02 00 00 vexp2ps 0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 72 80 vexp2ps -0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 b2 fc fd ff ff vexp2ps -0x204\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 c8 f5 vexp2pd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 18 c8 f5 vexp2pd \{sae\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 31 vexp2pd \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 c8 b4 f0 23 01 00 00 vexp2pd 0x123\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 31 vexp2pd \(%rcx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 72 7f vexp2pd 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 b2 00 20 00 00 vexp2pd 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 72 80 vexp2pd -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 b2 c0 df ff ff vexp2pd -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 72 7f vexp2pd 0x3f8\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 b2 00 04 00 00 vexp2pd 0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 72 80 vexp2pd -0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 b2 f8 fb ff ff vexp2pd -0x408\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 ca f5 vrcp28ps %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f ca f5 vrcp28ps %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf ca f5 vrcp28ps %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d 18 ca f5 vrcp28ps \{sae\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca 31 vrcp28ps \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 ca b4 f0 23 01 00 00 vrcp28ps 0x123\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca 31 vrcp28ps \(%rcx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca 72 7f vrcp28ps 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca b2 00 20 00 00 vrcp28ps 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca 72 80 vrcp28ps -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca b2 c0 df ff ff vrcp28ps -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca 72 7f vrcp28ps 0x1fc\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca b2 00 02 00 00 vrcp28ps 0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca 72 80 vrcp28ps -0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca b2 fc fd ff ff vrcp28ps -0x204\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 ca f5 vrcp28pd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f ca f5 vrcp28pd %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf ca f5 vrcp28pd %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 18 ca f5 vrcp28pd \{sae\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca 31 vrcp28pd \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 ca b4 f0 23 01 00 00 vrcp28pd 0x123\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca 31 vrcp28pd \(%rcx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca 72 7f vrcp28pd 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca b2 00 20 00 00 vrcp28pd 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca 72 80 vrcp28pd -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca b2 c0 df ff ff vrcp28pd -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca 72 7f vrcp28pd 0x3f8\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca b2 00 04 00 00 vrcp28pd 0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca 72 80 vrcp28pd -0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca b2 f8 fb ff ff vrcp28pd -0x408\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 15 07 cb f4 vrcp28ss %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 15 87 cb f4 vrcp28ss %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 15 17 cb f4 vrcp28ss \{sae\},%xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb 31 vrcp28ss \(%rcx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 15 07 cb b4 f0 23 01 00 00 vrcp28ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb 72 7f vrcp28ss 0x1fc\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb b2 00 02 00 00 vrcp28ss 0x200\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb 72 80 vrcp28ss -0x200\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb b2 fc fd ff ff vrcp28ss -0x204\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 95 07 cb f4 vrcp28sd %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 95 87 cb f4 vrcp28sd %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 95 17 cb f4 vrcp28sd \{sae\},%xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb 31 vrcp28sd \(%rcx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 95 07 cb b4 f0 23 01 00 00 vrcp28sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb 72 7f vrcp28sd 0x3f8\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb b2 00 04 00 00 vrcp28sd 0x400\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb 72 80 vrcp28sd -0x400\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb b2 f8 fb ff ff vrcp28sd -0x408\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 cc f5 vrsqrt28ps %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f cc f5 vrsqrt28ps %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf cc f5 vrsqrt28ps %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d 18 cc f5 vrsqrt28ps \{sae\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc 31 vrsqrt28ps \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 cc b4 f0 23 01 00 00 vrsqrt28ps 0x123\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc 31 vrsqrt28ps \(%rcx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc 72 7f vrsqrt28ps 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc b2 00 20 00 00 vrsqrt28ps 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc 72 80 vrsqrt28ps -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc b2 c0 df ff ff vrsqrt28ps -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc 72 7f vrsqrt28ps 0x1fc\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc b2 00 02 00 00 vrsqrt28ps 0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc 72 80 vrsqrt28ps -0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc b2 fc fd ff ff vrsqrt28ps -0x204\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 cc f5 vrsqrt28pd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f cc f5 vrsqrt28pd %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf cc f5 vrsqrt28pd %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 18 cc f5 vrsqrt28pd \{sae\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc 31 vrsqrt28pd \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 cc b4 f0 23 01 00 00 vrsqrt28pd 0x123\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc 31 vrsqrt28pd \(%rcx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc 72 7f vrsqrt28pd 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc b2 00 20 00 00 vrsqrt28pd 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc 72 80 vrsqrt28pd -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc b2 c0 df ff ff vrsqrt28pd -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc 72 7f vrsqrt28pd 0x3f8\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc b2 00 04 00 00 vrsqrt28pd 0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc 72 80 vrsqrt28pd -0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc b2 f8 fb ff ff vrsqrt28pd -0x408\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 15 07 cd f4 vrsqrt28ss %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 15 87 cd f4 vrsqrt28ss %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 15 17 cd f4 vrsqrt28ss \{sae\},%xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd 31 vrsqrt28ss \(%rcx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 15 07 cd b4 f0 23 01 00 00 vrsqrt28ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd 72 7f vrsqrt28ss 0x1fc\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd b2 00 02 00 00 vrsqrt28ss 0x200\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd 72 80 vrsqrt28ss -0x200\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd b2 fc fd ff ff vrsqrt28ss -0x204\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 95 07 cd f4 vrsqrt28sd %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 95 87 cd f4 vrsqrt28sd %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 95 17 cd f4 vrsqrt28sd \{sae\},%xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd 31 vrsqrt28sd \(%rcx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 95 07 cd b4 f0 23 01 00 00 vrsqrt28sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd 72 7f vrsqrt28sd 0x3f8\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd b2 00 04 00 00 vrsqrt28sd 0x400\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd 72 80 vrsqrt28sd -0x400\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd b2 f8 fb ff ff vrsqrt28sd -0x408\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 c8 f5 vexp2ps %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 18 c8 f5 vexp2ps \{sae\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 31 vexp2ps \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 c8 b4 f0 34 12 00 00 vexp2ps 0x1234\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 31 vexp2ps \(%rcx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 72 7f vexp2ps 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 b2 00 20 00 00 vexp2ps 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 72 80 vexp2ps -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 c8 b2 c0 df ff ff vexp2ps -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 72 7f vexp2ps 0x1fc\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 b2 00 02 00 00 vexp2ps 0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 72 80 vexp2ps -0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 c8 b2 fc fd ff ff vexp2ps -0x204\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 c8 f5 vexp2pd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 18 c8 f5 vexp2pd \{sae\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 31 vexp2pd \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 c8 b4 f0 34 12 00 00 vexp2pd 0x1234\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 31 vexp2pd \(%rcx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 72 7f vexp2pd 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 b2 00 20 00 00 vexp2pd 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 72 80 vexp2pd -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 c8 b2 c0 df ff ff vexp2pd -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 72 7f vexp2pd 0x3f8\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 b2 00 04 00 00 vexp2pd 0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 72 80 vexp2pd -0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 c8 b2 f8 fb ff ff vexp2pd -0x408\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 ca f5 vrcp28ps %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f ca f5 vrcp28ps %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf ca f5 vrcp28ps %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d 18 ca f5 vrcp28ps \{sae\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca 31 vrcp28ps \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 ca b4 f0 34 12 00 00 vrcp28ps 0x1234\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca 31 vrcp28ps \(%rcx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca 72 7f vrcp28ps 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca b2 00 20 00 00 vrcp28ps 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca 72 80 vrcp28ps -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 ca b2 c0 df ff ff vrcp28ps -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca 72 7f vrcp28ps 0x1fc\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca b2 00 02 00 00 vrcp28ps 0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca 72 80 vrcp28ps -0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 ca b2 fc fd ff ff vrcp28ps -0x204\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 ca f5 vrcp28pd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f ca f5 vrcp28pd %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf ca f5 vrcp28pd %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 18 ca f5 vrcp28pd \{sae\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca 31 vrcp28pd \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 ca b4 f0 34 12 00 00 vrcp28pd 0x1234\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca 31 vrcp28pd \(%rcx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca 72 7f vrcp28pd 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca b2 00 20 00 00 vrcp28pd 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca 72 80 vrcp28pd -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 ca b2 c0 df ff ff vrcp28pd -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca 72 7f vrcp28pd 0x3f8\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca b2 00 04 00 00 vrcp28pd 0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca 72 80 vrcp28pd -0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 ca b2 f8 fb ff ff vrcp28pd -0x408\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 15 07 cb f4 vrcp28ss %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 15 87 cb f4 vrcp28ss %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 15 17 cb f4 vrcp28ss \{sae\},%xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb 31 vrcp28ss \(%rcx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 15 07 cb b4 f0 34 12 00 00 vrcp28ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb 72 7f vrcp28ss 0x1fc\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb b2 00 02 00 00 vrcp28ss 0x200\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb 72 80 vrcp28ss -0x200\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cb b2 fc fd ff ff vrcp28ss -0x204\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 95 07 cb f4 vrcp28sd %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 95 87 cb f4 vrcp28sd %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 95 17 cb f4 vrcp28sd \{sae\},%xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb 31 vrcp28sd \(%rcx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 95 07 cb b4 f0 34 12 00 00 vrcp28sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb 72 7f vrcp28sd 0x3f8\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb b2 00 04 00 00 vrcp28sd 0x400\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb 72 80 vrcp28sd -0x400\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cb b2 f8 fb ff ff vrcp28sd -0x408\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d 48 cc f5 vrsqrt28ps %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 7d 4f cc f5 vrsqrt28ps %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d cf cc f5 vrsqrt28ps %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 7d 18 cc f5 vrsqrt28ps \{sae\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc 31 vrsqrt28ps \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 7d 48 cc b4 f0 34 12 00 00 vrsqrt28ps 0x1234\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc 31 vrsqrt28ps \(%rcx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc 72 7f vrsqrt28ps 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc b2 00 20 00 00 vrsqrt28ps 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc 72 80 vrsqrt28ps -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 48 cc b2 c0 df ff ff vrsqrt28ps -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc 72 7f vrsqrt28ps 0x1fc\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc b2 00 02 00 00 vrsqrt28ps 0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc 72 80 vrsqrt28ps -0x200\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 7d 58 cc b2 fc fd ff ff vrsqrt28ps -0x204\(%rdx\)\{1to16\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 48 cc f5 vrsqrt28pd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f cc f5 vrsqrt28pd %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf cc f5 vrsqrt28pd %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 18 cc f5 vrsqrt28pd \{sae\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc 31 vrsqrt28pd \(%rcx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 22 fd 48 cc b4 f0 34 12 00 00 vrsqrt28pd 0x1234\(%rax,%r14,8\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc 31 vrsqrt28pd \(%rcx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc 72 7f vrsqrt28pd 0x1fc0\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc b2 00 20 00 00 vrsqrt28pd 0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc 72 80 vrsqrt28pd -0x2000\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 48 cc b2 c0 df ff ff vrsqrt28pd -0x2040\(%rdx\),%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc 72 7f vrsqrt28pd 0x3f8\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc b2 00 04 00 00 vrsqrt28pd 0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc 72 80 vrsqrt28pd -0x400\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 62 fd 58 cc b2 f8 fb ff ff vrsqrt28pd -0x408\(%rdx\)\{1to8\},%zmm30
|
||||
[ ]*[a-f0-9]+: 62 02 15 07 cd f4 vrsqrt28ss %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 15 87 cd f4 vrsqrt28ss %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 15 17 cd f4 vrsqrt28ss \{sae\},%xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd 31 vrsqrt28ss \(%rcx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 15 07 cd b4 f0 34 12 00 00 vrsqrt28ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd 72 7f vrsqrt28ss 0x1fc\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd b2 00 02 00 00 vrsqrt28ss 0x200\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd 72 80 vrsqrt28ss -0x200\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 15 07 cd b2 fc fd ff ff vrsqrt28ss -0x204\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 95 07 cd f4 vrsqrt28sd %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 95 87 cd f4 vrsqrt28sd %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 02 95 17 cd f4 vrsqrt28sd \{sae\},%xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd 31 vrsqrt28sd \(%rcx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 95 07 cd b4 f0 34 12 00 00 vrsqrt28sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd 72 7f vrsqrt28sd 0x3f8\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd b2 00 04 00 00 vrsqrt28sd 0x400\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd 72 80 vrsqrt28sd -0x400\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 95 07 cd b2 f8 fb ff ff vrsqrt28sd -0x408\(%rdx\),%xmm29,%xmm30\{%k7\}
|
||||
#pass
|
||||
|
|
@ -0,0 +1,271 @@
|
|||
# Check 64bit AVX512ER instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
vexp2ps %zmm29, %zmm30 # AVX512ER
|
||||
vexp2ps {sae}, %zmm29, %zmm30 # AVX512ER
|
||||
vexp2ps (%rcx), %zmm30 # AVX512ER
|
||||
vexp2ps 0x123(%rax,%r14,8), %zmm30 # AVX512ER
|
||||
vexp2ps (%rcx){1to16}, %zmm30 # AVX512ER
|
||||
vexp2ps 8128(%rdx), %zmm30 # AVX512ER Disp8
|
||||
vexp2ps 8192(%rdx), %zmm30 # AVX512ER
|
||||
vexp2ps -8192(%rdx), %zmm30 # AVX512ER Disp8
|
||||
vexp2ps -8256(%rdx), %zmm30 # AVX512ER
|
||||
vexp2ps 508(%rdx){1to16}, %zmm30 # AVX512ER Disp8
|
||||
vexp2ps 512(%rdx){1to16}, %zmm30 # AVX512ER
|
||||
vexp2ps -512(%rdx){1to16}, %zmm30 # AVX512ER Disp8
|
||||
vexp2ps -516(%rdx){1to16}, %zmm30 # AVX512ER
|
||||
|
||||
vexp2pd %zmm29, %zmm30 # AVX512ER
|
||||
vexp2pd {sae}, %zmm29, %zmm30 # AVX512ER
|
||||
vexp2pd (%rcx), %zmm30 # AVX512ER
|
||||
vexp2pd 0x123(%rax,%r14,8), %zmm30 # AVX512ER
|
||||
vexp2pd (%rcx){1to8}, %zmm30 # AVX512ER
|
||||
vexp2pd 8128(%rdx), %zmm30 # AVX512ER Disp8
|
||||
vexp2pd 8192(%rdx), %zmm30 # AVX512ER
|
||||
vexp2pd -8192(%rdx), %zmm30 # AVX512ER Disp8
|
||||
vexp2pd -8256(%rdx), %zmm30 # AVX512ER
|
||||
vexp2pd 1016(%rdx){1to8}, %zmm30 # AVX512ER Disp8
|
||||
vexp2pd 1024(%rdx){1to8}, %zmm30 # AVX512ER
|
||||
vexp2pd -1024(%rdx){1to8}, %zmm30 # AVX512ER Disp8
|
||||
vexp2pd -1032(%rdx){1to8}, %zmm30 # AVX512ER
|
||||
|
||||
vrcp28ps %zmm29, %zmm30 # AVX512ER
|
||||
vrcp28ps %zmm29, %zmm30{%k7} # AVX512ER
|
||||
vrcp28ps %zmm29, %zmm30{%k7}{z} # AVX512ER
|
||||
vrcp28ps {sae}, %zmm29, %zmm30 # AVX512ER
|
||||
vrcp28ps (%rcx), %zmm30 # AVX512ER
|
||||
vrcp28ps 0x123(%rax,%r14,8), %zmm30 # AVX512ER
|
||||
vrcp28ps (%rcx){1to16}, %zmm30 # AVX512ER
|
||||
vrcp28ps 8128(%rdx), %zmm30 # AVX512ER Disp8
|
||||
vrcp28ps 8192(%rdx), %zmm30 # AVX512ER
|
||||
vrcp28ps -8192(%rdx), %zmm30 # AVX512ER Disp8
|
||||
vrcp28ps -8256(%rdx), %zmm30 # AVX512ER
|
||||
vrcp28ps 508(%rdx){1to16}, %zmm30 # AVX512ER Disp8
|
||||
vrcp28ps 512(%rdx){1to16}, %zmm30 # AVX512ER
|
||||
vrcp28ps -512(%rdx){1to16}, %zmm30 # AVX512ER Disp8
|
||||
vrcp28ps -516(%rdx){1to16}, %zmm30 # AVX512ER
|
||||
|
||||
vrcp28pd %zmm29, %zmm30 # AVX512ER
|
||||
vrcp28pd %zmm29, %zmm30{%k7} # AVX512ER
|
||||
vrcp28pd %zmm29, %zmm30{%k7}{z} # AVX512ER
|
||||
vrcp28pd {sae}, %zmm29, %zmm30 # AVX512ER
|
||||
vrcp28pd (%rcx), %zmm30 # AVX512ER
|
||||
vrcp28pd 0x123(%rax,%r14,8), %zmm30 # AVX512ER
|
||||
vrcp28pd (%rcx){1to8}, %zmm30 # AVX512ER
|
||||
vrcp28pd 8128(%rdx), %zmm30 # AVX512ER Disp8
|
||||
vrcp28pd 8192(%rdx), %zmm30 # AVX512ER
|
||||
vrcp28pd -8192(%rdx), %zmm30 # AVX512ER Disp8
|
||||
vrcp28pd -8256(%rdx), %zmm30 # AVX512ER
|
||||
vrcp28pd 1016(%rdx){1to8}, %zmm30 # AVX512ER Disp8
|
||||
vrcp28pd 1024(%rdx){1to8}, %zmm30 # AVX512ER
|
||||
vrcp28pd -1024(%rdx){1to8}, %zmm30 # AVX512ER Disp8
|
||||
vrcp28pd -1032(%rdx){1to8}, %zmm30 # AVX512ER
|
||||
|
||||
vrcp28ss %xmm28, %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrcp28ss %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512ER
|
||||
vrcp28ss {sae}, %xmm28, %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrcp28ss (%rcx), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrcp28ss 0x123(%rax,%r14,8), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrcp28ss 508(%rdx), %xmm29, %xmm30{%k7} # AVX512ER Disp8
|
||||
vrcp28ss 512(%rdx), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrcp28ss -512(%rdx), %xmm29, %xmm30{%k7} # AVX512ER Disp8
|
||||
vrcp28ss -516(%rdx), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
|
||||
vrcp28sd %xmm28, %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrcp28sd %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512ER
|
||||
vrcp28sd {sae}, %xmm28, %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrcp28sd (%rcx), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrcp28sd 0x123(%rax,%r14,8), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrcp28sd 1016(%rdx), %xmm29, %xmm30{%k7} # AVX512ER Disp8
|
||||
vrcp28sd 1024(%rdx), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrcp28sd -1024(%rdx), %xmm29, %xmm30{%k7} # AVX512ER Disp8
|
||||
vrcp28sd -1032(%rdx), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
|
||||
vrsqrt28ps %zmm29, %zmm30 # AVX512ER
|
||||
vrsqrt28ps %zmm29, %zmm30{%k7} # AVX512ER
|
||||
vrsqrt28ps %zmm29, %zmm30{%k7}{z} # AVX512ER
|
||||
vrsqrt28ps {sae}, %zmm29, %zmm30 # AVX512ER
|
||||
vrsqrt28ps (%rcx), %zmm30 # AVX512ER
|
||||
vrsqrt28ps 0x123(%rax,%r14,8), %zmm30 # AVX512ER
|
||||
vrsqrt28ps (%rcx){1to16}, %zmm30 # AVX512ER
|
||||
vrsqrt28ps 8128(%rdx), %zmm30 # AVX512ER Disp8
|
||||
vrsqrt28ps 8192(%rdx), %zmm30 # AVX512ER
|
||||
vrsqrt28ps -8192(%rdx), %zmm30 # AVX512ER Disp8
|
||||
vrsqrt28ps -8256(%rdx), %zmm30 # AVX512ER
|
||||
vrsqrt28ps 508(%rdx){1to16}, %zmm30 # AVX512ER Disp8
|
||||
vrsqrt28ps 512(%rdx){1to16}, %zmm30 # AVX512ER
|
||||
vrsqrt28ps -512(%rdx){1to16}, %zmm30 # AVX512ER Disp8
|
||||
vrsqrt28ps -516(%rdx){1to16}, %zmm30 # AVX512ER
|
||||
|
||||
vrsqrt28pd %zmm29, %zmm30 # AVX512ER
|
||||
vrsqrt28pd %zmm29, %zmm30{%k7} # AVX512ER
|
||||
vrsqrt28pd %zmm29, %zmm30{%k7}{z} # AVX512ER
|
||||
vrsqrt28pd {sae}, %zmm29, %zmm30 # AVX512ER
|
||||
vrsqrt28pd (%rcx), %zmm30 # AVX512ER
|
||||
vrsqrt28pd 0x123(%rax,%r14,8), %zmm30 # AVX512ER
|
||||
vrsqrt28pd (%rcx){1to8}, %zmm30 # AVX512ER
|
||||
vrsqrt28pd 8128(%rdx), %zmm30 # AVX512ER Disp8
|
||||
vrsqrt28pd 8192(%rdx), %zmm30 # AVX512ER
|
||||
vrsqrt28pd -8192(%rdx), %zmm30 # AVX512ER Disp8
|
||||
vrsqrt28pd -8256(%rdx), %zmm30 # AVX512ER
|
||||
vrsqrt28pd 1016(%rdx){1to8}, %zmm30 # AVX512ER Disp8
|
||||
vrsqrt28pd 1024(%rdx){1to8}, %zmm30 # AVX512ER
|
||||
vrsqrt28pd -1024(%rdx){1to8}, %zmm30 # AVX512ER Disp8
|
||||
vrsqrt28pd -1032(%rdx){1to8}, %zmm30 # AVX512ER
|
||||
|
||||
vrsqrt28ss %xmm28, %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrsqrt28ss %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512ER
|
||||
vrsqrt28ss {sae}, %xmm28, %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrsqrt28ss (%rcx), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrsqrt28ss 0x123(%rax,%r14,8), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrsqrt28ss 508(%rdx), %xmm29, %xmm30{%k7} # AVX512ER Disp8
|
||||
vrsqrt28ss 512(%rdx), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrsqrt28ss -512(%rdx), %xmm29, %xmm30{%k7} # AVX512ER Disp8
|
||||
vrsqrt28ss -516(%rdx), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
|
||||
vrsqrt28sd %xmm28, %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrsqrt28sd %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512ER
|
||||
vrsqrt28sd {sae}, %xmm28, %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrsqrt28sd (%rcx), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrsqrt28sd 0x123(%rax,%r14,8), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrsqrt28sd 1016(%rdx), %xmm29, %xmm30{%k7} # AVX512ER Disp8
|
||||
vrsqrt28sd 1024(%rdx), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
vrsqrt28sd -1024(%rdx), %xmm29, %xmm30{%k7} # AVX512ER Disp8
|
||||
vrsqrt28sd -1032(%rdx), %xmm29, %xmm30{%k7} # AVX512ER
|
||||
|
||||
.intel_syntax noprefix
|
||||
vexp2ps zmm30, zmm29 # AVX512ER
|
||||
vexp2ps zmm30, zmm29, {sae} # AVX512ER
|
||||
vexp2ps zmm30, ZMMWORD PTR [rcx] # AVX512ER
|
||||
vexp2ps zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512ER
|
||||
vexp2ps zmm30, [rcx]{1to16} # AVX512ER
|
||||
vexp2ps zmm30, ZMMWORD PTR [rdx+8128] # AVX512ER Disp8
|
||||
vexp2ps zmm30, ZMMWORD PTR [rdx+8192] # AVX512ER
|
||||
vexp2ps zmm30, ZMMWORD PTR [rdx-8192] # AVX512ER Disp8
|
||||
vexp2ps zmm30, ZMMWORD PTR [rdx-8256] # AVX512ER
|
||||
vexp2ps zmm30, [rdx+508]{1to16} # AVX512ER Disp8
|
||||
vexp2ps zmm30, [rdx+512]{1to16} # AVX512ER
|
||||
vexp2ps zmm30, [rdx-512]{1to16} # AVX512ER Disp8
|
||||
vexp2ps zmm30, [rdx-516]{1to16} # AVX512ER
|
||||
|
||||
vexp2pd zmm30, zmm29 # AVX512ER
|
||||
vexp2pd zmm30, zmm29, {sae} # AVX512ER
|
||||
vexp2pd zmm30, ZMMWORD PTR [rcx] # AVX512ER
|
||||
vexp2pd zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512ER
|
||||
vexp2pd zmm30, [rcx]{1to8} # AVX512ER
|
||||
vexp2pd zmm30, ZMMWORD PTR [rdx+8128] # AVX512ER Disp8
|
||||
vexp2pd zmm30, ZMMWORD PTR [rdx+8192] # AVX512ER
|
||||
vexp2pd zmm30, ZMMWORD PTR [rdx-8192] # AVX512ER Disp8
|
||||
vexp2pd zmm30, ZMMWORD PTR [rdx-8256] # AVX512ER
|
||||
vexp2pd zmm30, [rdx+1016]{1to8} # AVX512ER Disp8
|
||||
vexp2pd zmm30, [rdx+1024]{1to8} # AVX512ER
|
||||
vexp2pd zmm30, [rdx-1024]{1to8} # AVX512ER Disp8
|
||||
vexp2pd zmm30, [rdx-1032]{1to8} # AVX512ER
|
||||
|
||||
vrcp28ps zmm30, zmm29 # AVX512ER
|
||||
vrcp28ps zmm30{k7}, zmm29 # AVX512ER
|
||||
vrcp28ps zmm30{k7}{z}, zmm29 # AVX512ER
|
||||
vrcp28ps zmm30, zmm29, {sae} # AVX512ER
|
||||
vrcp28ps zmm30, ZMMWORD PTR [rcx] # AVX512ER
|
||||
vrcp28ps zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512ER
|
||||
vrcp28ps zmm30, [rcx]{1to16} # AVX512ER
|
||||
vrcp28ps zmm30, ZMMWORD PTR [rdx+8128] # AVX512ER Disp8
|
||||
vrcp28ps zmm30, ZMMWORD PTR [rdx+8192] # AVX512ER
|
||||
vrcp28ps zmm30, ZMMWORD PTR [rdx-8192] # AVX512ER Disp8
|
||||
vrcp28ps zmm30, ZMMWORD PTR [rdx-8256] # AVX512ER
|
||||
vrcp28ps zmm30, [rdx+508]{1to16} # AVX512ER Disp8
|
||||
vrcp28ps zmm30, [rdx+512]{1to16} # AVX512ER
|
||||
vrcp28ps zmm30, [rdx-512]{1to16} # AVX512ER Disp8
|
||||
vrcp28ps zmm30, [rdx-516]{1to16} # AVX512ER
|
||||
|
||||
vrcp28pd zmm30, zmm29 # AVX512ER
|
||||
vrcp28pd zmm30{k7}, zmm29 # AVX512ER
|
||||
vrcp28pd zmm30{k7}{z}, zmm29 # AVX512ER
|
||||
vrcp28pd zmm30, zmm29, {sae} # AVX512ER
|
||||
vrcp28pd zmm30, ZMMWORD PTR [rcx] # AVX512ER
|
||||
vrcp28pd zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512ER
|
||||
vrcp28pd zmm30, [rcx]{1to8} # AVX512ER
|
||||
vrcp28pd zmm30, ZMMWORD PTR [rdx+8128] # AVX512ER Disp8
|
||||
vrcp28pd zmm30, ZMMWORD PTR [rdx+8192] # AVX512ER
|
||||
vrcp28pd zmm30, ZMMWORD PTR [rdx-8192] # AVX512ER Disp8
|
||||
vrcp28pd zmm30, ZMMWORD PTR [rdx-8256] # AVX512ER
|
||||
vrcp28pd zmm30, [rdx+1016]{1to8} # AVX512ER Disp8
|
||||
vrcp28pd zmm30, [rdx+1024]{1to8} # AVX512ER
|
||||
vrcp28pd zmm30, [rdx-1024]{1to8} # AVX512ER Disp8
|
||||
vrcp28pd zmm30, [rdx-1032]{1to8} # AVX512ER
|
||||
|
||||
vrcp28ss xmm30{k7}, xmm29, xmm28 # AVX512ER
|
||||
vrcp28ss xmm30{k7}{z}, xmm29, xmm28 # AVX512ER
|
||||
vrcp28ss xmm30{k7}, xmm29, xmm28, {sae} # AVX512ER
|
||||
vrcp28ss xmm30{k7}, xmm29, DWORD PTR [rcx] # AVX512ER
|
||||
vrcp28ss xmm30{k7}, xmm29, DWORD PTR [rax+r14*8+0x1234] # AVX512ER
|
||||
vrcp28ss xmm30{k7}, xmm29, DWORD PTR [rdx+508] # AVX512ER Disp8
|
||||
vrcp28ss xmm30{k7}, xmm29, DWORD PTR [rdx+512] # AVX512ER
|
||||
vrcp28ss xmm30{k7}, xmm29, DWORD PTR [rdx-512] # AVX512ER Disp8
|
||||
vrcp28ss xmm30{k7}, xmm29, DWORD PTR [rdx-516] # AVX512ER
|
||||
|
||||
vrcp28sd xmm30{k7}, xmm29, xmm28 # AVX512ER
|
||||
vrcp28sd xmm30{k7}{z}, xmm29, xmm28 # AVX512ER
|
||||
vrcp28sd xmm30{k7}, xmm29, xmm28, {sae} # AVX512ER
|
||||
vrcp28sd xmm30{k7}, xmm29, QWORD PTR [rcx] # AVX512ER
|
||||
vrcp28sd xmm30{k7}, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512ER
|
||||
vrcp28sd xmm30{k7}, xmm29, QWORD PTR [rdx+1016] # AVX512ER Disp8
|
||||
vrcp28sd xmm30{k7}, xmm29, QWORD PTR [rdx+1024] # AVX512ER
|
||||
vrcp28sd xmm30{k7}, xmm29, QWORD PTR [rdx-1024] # AVX512ER Disp8
|
||||
vrcp28sd xmm30{k7}, xmm29, QWORD PTR [rdx-1032] # AVX512ER
|
||||
|
||||
vrsqrt28ps zmm30, zmm29 # AVX512ER
|
||||
vrsqrt28ps zmm30{k7}, zmm29 # AVX512ER
|
||||
vrsqrt28ps zmm30{k7}{z}, zmm29 # AVX512ER
|
||||
vrsqrt28ps zmm30, zmm29, {sae} # AVX512ER
|
||||
vrsqrt28ps zmm30, ZMMWORD PTR [rcx] # AVX512ER
|
||||
vrsqrt28ps zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512ER
|
||||
vrsqrt28ps zmm30, [rcx]{1to16} # AVX512ER
|
||||
vrsqrt28ps zmm30, ZMMWORD PTR [rdx+8128] # AVX512ER Disp8
|
||||
vrsqrt28ps zmm30, ZMMWORD PTR [rdx+8192] # AVX512ER
|
||||
vrsqrt28ps zmm30, ZMMWORD PTR [rdx-8192] # AVX512ER Disp8
|
||||
vrsqrt28ps zmm30, ZMMWORD PTR [rdx-8256] # AVX512ER
|
||||
vrsqrt28ps zmm30, [rdx+508]{1to16} # AVX512ER Disp8
|
||||
vrsqrt28ps zmm30, [rdx+512]{1to16} # AVX512ER
|
||||
vrsqrt28ps zmm30, [rdx-512]{1to16} # AVX512ER Disp8
|
||||
vrsqrt28ps zmm30, [rdx-516]{1to16} # AVX512ER
|
||||
|
||||
vrsqrt28pd zmm30, zmm29 # AVX512ER
|
||||
vrsqrt28pd zmm30{k7}, zmm29 # AVX512ER
|
||||
vrsqrt28pd zmm30{k7}{z}, zmm29 # AVX512ER
|
||||
vrsqrt28pd zmm30, zmm29, {sae} # AVX512ER
|
||||
vrsqrt28pd zmm30, ZMMWORD PTR [rcx] # AVX512ER
|
||||
vrsqrt28pd zmm30, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512ER
|
||||
vrsqrt28pd zmm30, [rcx]{1to8} # AVX512ER
|
||||
vrsqrt28pd zmm30, ZMMWORD PTR [rdx+8128] # AVX512ER Disp8
|
||||
vrsqrt28pd zmm30, ZMMWORD PTR [rdx+8192] # AVX512ER
|
||||
vrsqrt28pd zmm30, ZMMWORD PTR [rdx-8192] # AVX512ER Disp8
|
||||
vrsqrt28pd zmm30, ZMMWORD PTR [rdx-8256] # AVX512ER
|
||||
vrsqrt28pd zmm30, [rdx+1016]{1to8} # AVX512ER Disp8
|
||||
vrsqrt28pd zmm30, [rdx+1024]{1to8} # AVX512ER
|
||||
vrsqrt28pd zmm30, [rdx-1024]{1to8} # AVX512ER Disp8
|
||||
vrsqrt28pd zmm30, [rdx-1032]{1to8} # AVX512ER
|
||||
|
||||
vrsqrt28ss xmm30{k7}, xmm29, xmm28 # AVX512ER
|
||||
vrsqrt28ss xmm30{k7}{z}, xmm29, xmm28 # AVX512ER
|
||||
vrsqrt28ss xmm30{k7}, xmm29, xmm28, {sae} # AVX512ER
|
||||
vrsqrt28ss xmm30{k7}, xmm29, DWORD PTR [rcx] # AVX512ER
|
||||
vrsqrt28ss xmm30{k7}, xmm29, DWORD PTR [rax+r14*8+0x1234] # AVX512ER
|
||||
vrsqrt28ss xmm30{k7}, xmm29, DWORD PTR [rdx+508] # AVX512ER Disp8
|
||||
vrsqrt28ss xmm30{k7}, xmm29, DWORD PTR [rdx+512] # AVX512ER
|
||||
vrsqrt28ss xmm30{k7}, xmm29, DWORD PTR [rdx-512] # AVX512ER Disp8
|
||||
vrsqrt28ss xmm30{k7}, xmm29, DWORD PTR [rdx-516] # AVX512ER
|
||||
|
||||
vrsqrt28sd xmm30{k7}, xmm29, xmm28 # AVX512ER
|
||||
vrsqrt28sd xmm30{k7}{z}, xmm29, xmm28 # AVX512ER
|
||||
vrsqrt28sd xmm30{k7}, xmm29, xmm28, {sae} # AVX512ER
|
||||
vrsqrt28sd xmm30{k7}, xmm29, QWORD PTR [rcx] # AVX512ER
|
||||
vrsqrt28sd xmm30{k7}, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512ER
|
||||
vrsqrt28sd xmm30{k7}, xmm29, QWORD PTR [rdx+1016] # AVX512ER Disp8
|
||||
vrsqrt28sd xmm30{k7}, xmm29, QWORD PTR [rdx+1024] # AVX512ER
|
||||
vrsqrt28sd xmm30{k7}, xmm29, QWORD PTR [rdx-1024] # AVX512ER Disp8
|
||||
vrsqrt28sd xmm30{k7}, xmm29, QWORD PTR [rdx-1032] # AVX512ER
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,19 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86-64 AVX512F insns with nondefault values in ignored bits
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <.text>:
|
||||
[ ]*[a-f0-9]+: 62 f3 d5 1f 0b f4 7b vrndscalesd \$0x7b,\{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f3 d5 5f 0b f4 7b vrndscalesd \$0x7b,\{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 55 1f 3b f4 vpminud %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 c2 55 1f 3b f4 vpminud %zmm12,%zmm5,%zmm22\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 f2 7e 48 31 72 7f vpmovdb %zmm6,0x7f0\(%rdx\)
|
||||
[ ]*[a-f0-9]+: 62 vpmovdb %zmm6,\(bad\)
|
||||
[ ]*[a-f0-9]+: f2 7e 58 bnd jle 0x7d
|
||||
[ ]*[a-f0-9]+: 31 72 7f xor %esi,0x7f\(%rdx\)
|
||||
#pass
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# Check if objdump works correctly when some bits in instruction
|
||||
# has non-default value
|
||||
|
||||
# vrndscalesd {sae}, $123, %xmm4, %xmm5, %xmm6{%k7} # with null RC
|
||||
.byte 0x62, 0xf3, 0xd5, 0x1f, 0x0b, 0xf4, 0x7b
|
||||
# vrndscalesd {sae}, $123, %xmm4, %xmm5, %xmm6{%k7} # with not-null RC
|
||||
.byte 0x62, 0xf3, 0xd5, 0x5f, 0x0b, 0xf4, 0x7b
|
||||
# vpminud %zmm4, %zmm5, %zmm6{%k7} # with 111 REX
|
||||
.byte 0x62, 0xf2, 0x55, 0x1f, 0x3b, 0xf4
|
||||
# vpminud %zmm4, %zmm5, %zmm6{%k7} # with not-111 REX
|
||||
.byte 0x62, 0xc2, 0x55, 0x1f, 0x3b, 0xf4
|
||||
# vpmovdb %zmm6, 2032(%rdx) # with unset EVEX.B bit
|
||||
.byte 0x62, 0xf2, 0x7e, 0x48, 0x31, 0x72, 0x7f
|
||||
# vpmovdb %zmm6, 2032(%rdx) # with set EVEX.B bit - we should get (bad) operand
|
||||
.byte 0x62, 0xf2, 0x7e, 0x58, 0x31, 0x72, 0x7f
|
||||
|
|
@ -0,0 +1,148 @@
|
|||
#as:
|
||||
#objdump: -dwMintel -Msuffix
|
||||
#name: x86_64 AVX512F opts insns (Intel disassembly)
|
||||
#source: x86-64-avx512f-opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 29 ee vmovapd.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 28 f5 vmovapd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 29 ee vmovapd.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 28 f5 vmovapd zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 29 ee vmovapd.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 28 f5 vmovapd zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 29 ee vmovaps.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 28 f5 vmovaps zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 29 ee vmovaps.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 28 f5 vmovaps zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 29 ee vmovaps.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 28 f5 vmovaps zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f0 vmovd eax,xmm30
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f0 vmovd eax,xmm30
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f5 vmovd ebp,xmm30
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f5 vmovd ebp,xmm30
|
||||
[ ]*[a-f0-9]+: 62 41 7d 08 7e f5 vmovd r13d,xmm30
|
||||
[ ]*[a-f0-9]+: 62 41 7d 08 7e f5 vmovd r13d,xmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7d 48 7f ee vmovdqa32.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7d 48 6f f5 vmovdqa32 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7d 4f 7f ee vmovdqa32.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7d 4f 6f f5 vmovdqa32 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7d cf 7f ee vmovdqa32.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7d cf 6f f5 vmovdqa32 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 7f ee vmovdqa64.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 6f f5 vmovdqa64 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 7f ee vmovdqa64.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 6f f5 vmovdqa64 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 7f ee vmovdqa64.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 6f f5 vmovdqa64 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7e 48 7f ee vmovdqu32.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7e 48 6f f5 vmovdqu32 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7e 4f 7f ee vmovdqu32.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7e 4f 6f f5 vmovdqu32 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7e cf 7f ee vmovdqu32.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7e cf 6f f5 vmovdqu32 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe 48 7f ee vmovdqu64.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe 48 6f f5 vmovdqu64 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe 4f 7f ee vmovdqu64.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe 4f 6f f5 vmovdqu64 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe cf 7f ee vmovdqu64.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe cf 6f f5 vmovdqu64 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 61 fd 08 7e f0 vmovq rax,xmm30
|
||||
[ ]*[a-f0-9]+: 62 61 fd 08 7e f0 vmovq rax,xmm30
|
||||
[ ]*[a-f0-9]+: 62 41 fd 08 7e f0 vmovq r8,xmm30
|
||||
[ ]*[a-f0-9]+: 62 41 fd 08 7e f0 vmovq r8,xmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 08 d6 ee vmovq xmm30,xmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe 08 7e f5 vmovq xmm30,xmm29
|
||||
[ ]*[a-f0-9]+: 62 01 97 07 11 e6 vmovsd.s xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 97 07 10 f4 vmovsd xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 97 87 11 e6 vmovsd.s xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 97 87 10 f4 vmovsd xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 16 07 11 e6 vmovss.s xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 16 07 10 f4 vmovss xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 16 87 11 e6 vmovss.s xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 16 87 10 f4 vmovss xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 11 ee vmovupd.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 10 f5 vmovupd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 11 ee vmovupd.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 10 f5 vmovupd zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 11 ee vmovupd.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 10 f5 vmovupd zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 11 ee vmovups.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 10 f5 vmovups zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 11 ee vmovups.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 10 f5 vmovups zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 11 ee vmovups.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 10 f5 vmovups zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 29 ee vmovapd.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 28 f5 vmovapd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 29 ee vmovapd.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 28 f5 vmovapd zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 29 ee vmovapd.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 28 f5 vmovapd zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 29 ee vmovaps.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 28 f5 vmovaps zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 29 ee vmovaps.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 28 f5 vmovaps zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 29 ee vmovaps.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 28 f5 vmovaps zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f0 vmovd eax,xmm30
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f0 vmovd eax,xmm30
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f5 vmovd ebp,xmm30
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f5 vmovd ebp,xmm30
|
||||
[ ]*[a-f0-9]+: 62 41 7d 08 7e f5 vmovd r13d,xmm30
|
||||
[ ]*[a-f0-9]+: 62 41 7d 08 7e f5 vmovd r13d,xmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7d 48 7f ee vmovdqa32.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7d 48 6f f5 vmovdqa32 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7d 4f 7f ee vmovdqa32.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7d 4f 6f f5 vmovdqa32 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7d cf 7f ee vmovdqa32.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7d cf 6f f5 vmovdqa32 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 7f ee vmovdqa64.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 6f f5 vmovdqa64 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 7f ee vmovdqa64.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 6f f5 vmovdqa64 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 7f ee vmovdqa64.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 6f f5 vmovdqa64 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7e 48 7f ee vmovdqu32.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7e 48 6f f5 vmovdqu32 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7e 4f 7f ee vmovdqu32.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7e 4f 6f f5 vmovdqu32 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7e cf 7f ee vmovdqu32.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7e cf 6f f5 vmovdqu32 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe 48 7f ee vmovdqu64.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe 48 6f f5 vmovdqu64 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe 4f 7f ee vmovdqu64.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe 4f 6f f5 vmovdqu64 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe cf 7f ee vmovdqu64.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe cf 6f f5 vmovdqu64 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 61 fd 08 7e f0 vmovq rax,xmm30
|
||||
[ ]*[a-f0-9]+: 62 61 fd 08 7e f0 vmovq rax,xmm30
|
||||
[ ]*[a-f0-9]+: 62 41 fd 08 7e f0 vmovq r8,xmm30
|
||||
[ ]*[a-f0-9]+: 62 41 fd 08 7e f0 vmovq r8,xmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 08 d6 ee vmovq xmm30,xmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fe 08 7e f5 vmovq xmm30,xmm29
|
||||
[ ]*[a-f0-9]+: 62 01 97 07 11 e6 vmovsd.s xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 97 07 10 f4 vmovsd xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 97 87 11 e6 vmovsd.s xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 97 87 10 f4 vmovsd xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 16 07 11 e6 vmovss.s xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 16 07 10 f4 vmovss xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 16 87 11 e6 vmovss.s xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 16 87 10 f4 vmovss xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 11 ee vmovupd.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 10 f5 vmovupd zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 11 ee vmovupd.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 10 f5 vmovupd zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 11 ee vmovupd.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 10 f5 vmovupd zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 11 ee vmovups.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 10 f5 vmovups zmm30,zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 11 ee vmovups.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 10 f5 vmovups zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 11 ee vmovups.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 10 f5 vmovups zmm30\{k7\}\{z\},zmm29
|
||||
#pass
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
#as:
|
||||
#objdump: -dw -Msuffix
|
||||
#name: x86_64 AVX512F opts insns
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 29 ee vmovapd.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 28 f5 vmovapd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 29 ee vmovapd.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 28 f5 vmovapd %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 29 ee vmovapd.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 28 f5 vmovapd %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 29 ee vmovaps.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 28 f5 vmovaps %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 29 ee vmovaps.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 28 f5 vmovaps %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 29 ee vmovaps.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 28 f5 vmovaps %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f0 vmovd %xmm30,%eax
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f0 vmovd %xmm30,%eax
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f5 vmovd %xmm30,%ebp
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f5 vmovd %xmm30,%ebp
|
||||
[ ]*[a-f0-9]+: 62 41 7d 08 7e f5 vmovd %xmm30,%r13d
|
||||
[ ]*[a-f0-9]+: 62 41 7d 08 7e f5 vmovd %xmm30,%r13d
|
||||
[ ]*[a-f0-9]+: 62 01 7d 48 7f ee vmovdqa32.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7d 48 6f f5 vmovdqa32 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7d 4f 7f ee vmovdqa32.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7d 4f 6f f5 vmovdqa32 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7d cf 7f ee vmovdqa32.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7d cf 6f f5 vmovdqa32 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 7f ee vmovdqa64.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 6f f5 vmovdqa64 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 7f ee vmovdqa64.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 6f f5 vmovdqa64 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 7f ee vmovdqa64.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 6f f5 vmovdqa64 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7e 48 7f ee vmovdqu32.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7e 48 6f f5 vmovdqu32 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7e 4f 7f ee vmovdqu32.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7e 4f 6f f5 vmovdqu32 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7e cf 7f ee vmovdqu32.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7e cf 6f f5 vmovdqu32 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fe 48 7f ee vmovdqu64.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fe 48 6f f5 vmovdqu64 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fe 4f 7f ee vmovdqu64.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fe 4f 6f f5 vmovdqu64 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fe cf 7f ee vmovdqu64.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fe cf 6f f5 vmovdqu64 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 61 fd 08 7e f0 vmovq %xmm30,%rax
|
||||
[ ]*[a-f0-9]+: 62 61 fd 08 7e f0 vmovq %xmm30,%rax
|
||||
[ ]*[a-f0-9]+: 62 41 fd 08 7e f0 vmovq %xmm30,%r8
|
||||
[ ]*[a-f0-9]+: 62 41 fd 08 7e f0 vmovq %xmm30,%r8
|
||||
[ ]*[a-f0-9]+: 62 01 fd 08 d6 ee vmovq %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fe 08 7e f5 vmovq %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+: 62 01 97 07 11 e6 vmovsd.s %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 97 07 10 f4 vmovsd %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 97 87 11 e6 vmovsd.s %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 97 87 10 f4 vmovsd %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 16 07 11 e6 vmovss.s %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 16 07 10 f4 vmovss %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 16 87 11 e6 vmovss.s %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 16 87 10 f4 vmovss %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 11 ee vmovupd.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 10 f5 vmovupd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 11 ee vmovupd.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 10 f5 vmovupd %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 11 ee vmovupd.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 10 f5 vmovupd %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 11 ee vmovups.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 10 f5 vmovups %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 11 ee vmovups.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 10 f5 vmovups %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 11 ee vmovups.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 10 f5 vmovups %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 29 ee vmovapd.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 28 f5 vmovapd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 29 ee vmovapd.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 28 f5 vmovapd %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 29 ee vmovapd.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 28 f5 vmovapd %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 29 ee vmovaps.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 28 f5 vmovaps %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 29 ee vmovaps.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 28 f5 vmovaps %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 29 ee vmovaps.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 28 f5 vmovaps %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f0 vmovd %xmm30,%eax
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f0 vmovd %xmm30,%eax
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f5 vmovd %xmm30,%ebp
|
||||
[ ]*[a-f0-9]+: 62 61 7d 08 7e f5 vmovd %xmm30,%ebp
|
||||
[ ]*[a-f0-9]+: 62 41 7d 08 7e f5 vmovd %xmm30,%r13d
|
||||
[ ]*[a-f0-9]+: 62 41 7d 08 7e f5 vmovd %xmm30,%r13d
|
||||
[ ]*[a-f0-9]+: 62 01 7d 48 7f ee vmovdqa32.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7d 48 6f f5 vmovdqa32 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7d 4f 7f ee vmovdqa32.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7d 4f 6f f5 vmovdqa32 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7d cf 7f ee vmovdqa32.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7d cf 6f f5 vmovdqa32 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 7f ee vmovdqa64.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 6f f5 vmovdqa64 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 7f ee vmovdqa64.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 6f f5 vmovdqa64 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 7f ee vmovdqa64.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 6f f5 vmovdqa64 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7e 48 7f ee vmovdqu32.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7e 48 6f f5 vmovdqu32 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7e 4f 7f ee vmovdqu32.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7e 4f 6f f5 vmovdqu32 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7e cf 7f ee vmovdqu32.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7e cf 6f f5 vmovdqu32 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fe 48 7f ee vmovdqu64.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fe 48 6f f5 vmovdqu64 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fe 4f 7f ee vmovdqu64.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fe 4f 6f f5 vmovdqu64 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fe cf 7f ee vmovdqu64.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fe cf 6f f5 vmovdqu64 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 61 fd 08 7e f0 vmovq %xmm30,%rax
|
||||
[ ]*[a-f0-9]+: 62 61 fd 08 7e f0 vmovq %xmm30,%rax
|
||||
[ ]*[a-f0-9]+: 62 41 fd 08 7e f0 vmovq %xmm30,%r8
|
||||
[ ]*[a-f0-9]+: 62 41 fd 08 7e f0 vmovq %xmm30,%r8
|
||||
[ ]*[a-f0-9]+: 62 01 fd 08 d6 ee vmovq %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fe 08 7e f5 vmovq %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+: 62 01 97 07 11 e6 vmovsd.s %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 97 07 10 f4 vmovsd %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 97 87 11 e6 vmovsd.s %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 97 87 10 f4 vmovsd %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 16 07 11 e6 vmovss.s %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 16 07 10 f4 vmovss %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 16 87 11 e6 vmovss.s %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 16 87 10 f4 vmovss %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 11 ee vmovupd.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 48 10 f5 vmovupd %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 11 ee vmovupd.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd 4f 10 f5 vmovupd %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 11 ee vmovupd.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 fd cf 10 f5 vmovupd %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 11 ee vmovups.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7c 48 10 f5 vmovups %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 11 ee vmovups.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c 4f 10 f5 vmovups %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 11 ee vmovups.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 01 7c cf 10 f5 vmovups %zmm29,%zmm30\{%k7\}\{z\}
|
||||
#pass
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
# Check 64bit AVX512F instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
vmovapd.s %zmm29, %zmm30 # AVX512F
|
||||
vmovapd %zmm29, %zmm30 # AVX512F
|
||||
vmovapd.s %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovapd %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovapd.s %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovapd %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovaps.s %zmm29, %zmm30 # AVX512F
|
||||
vmovaps %zmm29, %zmm30 # AVX512F
|
||||
vmovaps.s %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovaps %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovaps.s %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovaps %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovd.s %xmm30, %eax # AVX512F
|
||||
vmovd %xmm30, %eax # AVX512F
|
||||
vmovd.s %xmm30, %ebp # AVX512F
|
||||
vmovd %xmm30, %ebp # AVX512F
|
||||
vmovd.s %xmm30, %r13d # AVX512F
|
||||
vmovd %xmm30, %r13d # AVX512F
|
||||
vmovdqa32.s %zmm29, %zmm30 # AVX512F
|
||||
vmovdqa32 %zmm29, %zmm30 # AVX512F
|
||||
vmovdqa32.s %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovdqa32 %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovdqa32.s %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovdqa32 %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovdqa64.s %zmm29, %zmm30 # AVX512F
|
||||
vmovdqa64 %zmm29, %zmm30 # AVX512F
|
||||
vmovdqa64.s %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovdqa64 %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovdqa64.s %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovdqa64 %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovdqu32.s %zmm29, %zmm30 # AVX512F
|
||||
vmovdqu32 %zmm29, %zmm30 # AVX512F
|
||||
vmovdqu32.s %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovdqu32 %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovdqu32.s %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovdqu32 %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovdqu64.s %zmm29, %zmm30 # AVX512F
|
||||
vmovdqu64 %zmm29, %zmm30 # AVX512F
|
||||
vmovdqu64.s %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovdqu64 %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovdqu64.s %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovdqu64 %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovq.s %xmm30, %rax # AVX512F
|
||||
vmovq %xmm30, %rax # AVX512F
|
||||
vmovq.s %xmm30, %r8 # AVX512F
|
||||
vmovq %xmm30, %r8 # AVX512F
|
||||
vmovq.s %xmm29, %xmm30 # AVX512F
|
||||
vmovq %xmm29, %xmm30 # AVX512F
|
||||
vmovsd.s %xmm28, %xmm29, %xmm30{%k7} # AVX512F
|
||||
vmovsd %xmm28, %xmm29, %xmm30{%k7} # AVX512F
|
||||
vmovsd.s %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512F
|
||||
vmovsd %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512F
|
||||
vmovss.s %xmm28, %xmm29, %xmm30{%k7} # AVX512F
|
||||
vmovss %xmm28, %xmm29, %xmm30{%k7} # AVX512F
|
||||
vmovss.s %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512F
|
||||
vmovss %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512F
|
||||
vmovupd.s %zmm29, %zmm30 # AVX512F
|
||||
vmovupd %zmm29, %zmm30 # AVX512F
|
||||
vmovupd.s %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovupd %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovupd.s %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovupd %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovups.s %zmm29, %zmm30 # AVX512F
|
||||
vmovups %zmm29, %zmm30 # AVX512F
|
||||
vmovups.s %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovups %zmm29, %zmm30{%k7} # AVX512F
|
||||
vmovups.s %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
vmovups %zmm29, %zmm30{%k7}{z} # AVX512F
|
||||
.intel_syntax noprefix
|
||||
vmovapd.s zmm30, zmm29 # AVX512F
|
||||
vmovapd zmm30, zmm29 # AVX512F
|
||||
vmovapd.s zmm30{k7}, zmm29 # AVX512F
|
||||
vmovapd zmm30{k7}, zmm29 # AVX512F
|
||||
vmovapd.s zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovapd zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovaps.s zmm30, zmm29 # AVX512F
|
||||
vmovaps zmm30, zmm29 # AVX512F
|
||||
vmovaps.s zmm30{k7}, zmm29 # AVX512F
|
||||
vmovaps zmm30{k7}, zmm29 # AVX512F
|
||||
vmovaps.s zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovaps zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovd.s eax, xmm30 # AVX512F
|
||||
vmovd eax, xmm30 # AVX512F
|
||||
vmovd.s ebp, xmm30 # AVX512F
|
||||
vmovd ebp, xmm30 # AVX512F
|
||||
vmovd.s r13d, xmm30 # AVX512F
|
||||
vmovd r13d, xmm30 # AVX512F
|
||||
vmovdqa32.s zmm30, zmm29 # AVX512F
|
||||
vmovdqa32 zmm30, zmm29 # AVX512F
|
||||
vmovdqa32.s zmm30{k7}, zmm29 # AVX512F
|
||||
vmovdqa32 zmm30{k7}, zmm29 # AVX512F
|
||||
vmovdqa32.s zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovdqa32 zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovdqa64.s zmm30, zmm29 # AVX512F
|
||||
vmovdqa64 zmm30, zmm29 # AVX512F
|
||||
vmovdqa64.s zmm30{k7}, zmm29 # AVX512F
|
||||
vmovdqa64 zmm30{k7}, zmm29 # AVX512F
|
||||
vmovdqa64.s zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovdqa64 zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovdqu32.s zmm30, zmm29 # AVX512F
|
||||
vmovdqu32 zmm30, zmm29 # AVX512F
|
||||
vmovdqu32.s zmm30{k7}, zmm29 # AVX512F
|
||||
vmovdqu32 zmm30{k7}, zmm29 # AVX512F
|
||||
vmovdqu32.s zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovdqu32 zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovdqu64.s zmm30, zmm29 # AVX512F
|
||||
vmovdqu64 zmm30, zmm29 # AVX512F
|
||||
vmovdqu64.s zmm30{k7}, zmm29 # AVX512F
|
||||
vmovdqu64 zmm30{k7}, zmm29 # AVX512F
|
||||
vmovdqu64.s zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovdqu64 zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovq.s rax, xmm30 # AVX512F
|
||||
vmovq rax, xmm30 # AVX512F
|
||||
vmovq.s r8, xmm30 # AVX512F
|
||||
vmovq r8, xmm30 # AVX512F
|
||||
vmovq.s xmm30, xmm29 # AVX512F
|
||||
vmovq xmm30, xmm29 # AVX512F
|
||||
vmovsd.s xmm30{k7}, xmm29, xmm28 # AVX512F
|
||||
vmovsd xmm30{k7}, xmm29, xmm28 # AVX512F
|
||||
vmovsd.s xmm30{k7}{z}, xmm29, xmm28 # AVX512F
|
||||
vmovsd xmm30{k7}{z}, xmm29, xmm28 # AVX512F
|
||||
vmovss.s xmm30{k7}, xmm29, xmm28 # AVX512F
|
||||
vmovss xmm30{k7}, xmm29, xmm28 # AVX512F
|
||||
vmovss.s xmm30{k7}{z}, xmm29, xmm28 # AVX512F
|
||||
vmovss xmm30{k7}{z}, xmm29, xmm28 # AVX512F
|
||||
vmovupd.s zmm30, zmm29 # AVX512F
|
||||
vmovupd zmm30, zmm29 # AVX512F
|
||||
vmovupd.s zmm30{k7}, zmm29 # AVX512F
|
||||
vmovupd zmm30{k7}, zmm29 # AVX512F
|
||||
vmovupd.s zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovupd zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovups.s zmm30, zmm29 # AVX512F
|
||||
vmovups zmm30, zmm29 # AVX512F
|
||||
vmovups.s zmm30{k7}, zmm29 # AVX512F
|
||||
vmovups zmm30{k7}, zmm29 # AVX512F
|
||||
vmovups.s zmm30{k7}{z}, zmm29 # AVX512F
|
||||
vmovups zmm30{k7}{z}, zmm29 # AVX512F
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,144 @@
|
|||
#as:
|
||||
#objdump: -dwMintel
|
||||
#name: x86_64 AVX512PF insns (Intel disassembly)
|
||||
#source: x86-64-avx512pf.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 7b 00 00 00 vgatherpf0dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 7b 00 00 00 vgatherpf0dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 4c 39 20 vgatherpf0dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 8c b9 00 04 00 00 vgatherpf0dpd ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 8c fe 7b 00 00 00 vgatherpf0dps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 8c fe 7b 00 00 00 vgatherpf0dps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 4c 39 40 vgatherpf0dps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 8c b9 00 04 00 00 vgatherpf0dps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 8c fe 7b 00 00 00 vgatherpf0qpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 8c fe 7b 00 00 00 vgatherpf0qpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 4c 39 20 vgatherpf0qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 8c b9 00 04 00 00 vgatherpf0qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 7b 00 00 00 vgatherpf0qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 7b 00 00 00 vgatherpf0qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 4c 39 40 vgatherpf0qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 8c b9 00 04 00 00 vgatherpf0qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 7b 00 00 00 vgatherpf1dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 7b 00 00 00 vgatherpf1dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 54 39 20 vgatherpf1dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 94 b9 00 04 00 00 vgatherpf1dpd ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 94 fe 7b 00 00 00 vgatherpf1dps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 94 fe 7b 00 00 00 vgatherpf1dps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 54 39 40 vgatherpf1dps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 94 b9 00 04 00 00 vgatherpf1dps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 94 fe 7b 00 00 00 vgatherpf1qpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 94 fe 7b 00 00 00 vgatherpf1qpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 54 39 20 vgatherpf1qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 94 b9 00 04 00 00 vgatherpf1qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 7b 00 00 00 vgatherpf1qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 7b 00 00 00 vgatherpf1qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 54 39 40 vgatherpf1qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 94 b9 00 04 00 00 vgatherpf1qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 ac fe 7b 00 00 00 vscatterpf0dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 ac fe 7b 00 00 00 vscatterpf0dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 6c 39 20 vscatterpf0dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 ac b9 00 04 00 00 vscatterpf0dpd ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 ac fe 7b 00 00 00 vscatterpf0dps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 ac fe 7b 00 00 00 vscatterpf0dps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 6c 39 40 vscatterpf0dps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 ac b9 00 04 00 00 vscatterpf0dps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 ac fe 7b 00 00 00 vscatterpf0qpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 ac fe 7b 00 00 00 vscatterpf0qpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 6c 39 20 vscatterpf0qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 ac b9 00 04 00 00 vscatterpf0qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 7b 00 00 00 vscatterpf0qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 7b 00 00 00 vscatterpf0qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 6c 39 40 vscatterpf0qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 ac b9 00 04 00 00 vscatterpf0qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 b4 fe 7b 00 00 00 vscatterpf1dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 b4 fe 7b 00 00 00 vscatterpf1dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 74 39 20 vscatterpf1dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 b4 b9 00 04 00 00 vscatterpf1dpd ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 b4 fe 7b 00 00 00 vscatterpf1dps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 b4 fe 7b 00 00 00 vscatterpf1dps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 74 39 40 vscatterpf1dps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 b4 b9 00 04 00 00 vscatterpf1dps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 b4 fe 7b 00 00 00 vscatterpf1qpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 b4 fe 7b 00 00 00 vscatterpf1qpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 74 39 20 vscatterpf1qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 b4 b9 00 04 00 00 vscatterpf1qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 7b 00 00 00 vscatterpf1qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 7b 00 00 00 vscatterpf1qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 74 39 40 vscatterpf1qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 b4 b9 00 04 00 00 vscatterpf1qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 BYTE PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 42 0f 0d 94 f0 23 01 00 00 prefetchwt1 BYTE PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 85 ff ff ff vgatherpf0dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 85 ff ff ff vgatherpf0dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 4c 39 20 vgatherpf0dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 8c b9 00 04 00 00 vgatherpf0dpd ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 8c fe 85 ff ff ff vgatherpf0dps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 8c fe 85 ff ff ff vgatherpf0dps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 4c 39 40 vgatherpf0dps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 8c b9 00 04 00 00 vgatherpf0dps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 8c fe 85 ff ff ff vgatherpf0qpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 8c fe 85 ff ff ff vgatherpf0qpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 4c 39 20 vgatherpf0qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 8c b9 00 04 00 00 vgatherpf0qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 85 ff ff ff vgatherpf0qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 85 ff ff ff vgatherpf0qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 4c 39 40 vgatherpf0qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 8c b9 00 04 00 00 vgatherpf0qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 85 ff ff ff vgatherpf1dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 85 ff ff ff vgatherpf1dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 54 39 20 vgatherpf1dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 94 b9 00 04 00 00 vgatherpf1dpd ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 94 fe 85 ff ff ff vgatherpf1dps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 94 fe 85 ff ff ff vgatherpf1dps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 54 39 40 vgatherpf1dps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 94 b9 00 04 00 00 vgatherpf1dps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 94 fe 85 ff ff ff vgatherpf1qpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 94 fe 85 ff ff ff vgatherpf1qpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 54 39 20 vgatherpf1qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 94 b9 00 04 00 00 vgatherpf1qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 85 ff ff ff vgatherpf1qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 85 ff ff ff vgatherpf1qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 54 39 40 vgatherpf1qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 94 b9 00 04 00 00 vgatherpf1qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 ac fe 85 ff ff ff vscatterpf0dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 ac fe 85 ff ff ff vscatterpf0dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 6c 39 20 vscatterpf0dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 ac b9 00 04 00 00 vscatterpf0dpd ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 ac fe 85 ff ff ff vscatterpf0dps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 ac fe 85 ff ff ff vscatterpf0dps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 6c 39 40 vscatterpf0dps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 ac b9 00 04 00 00 vscatterpf0dps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 ac fe 85 ff ff ff vscatterpf0qpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 ac fe 85 ff ff ff vscatterpf0qpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 6c 39 20 vscatterpf0qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 ac b9 00 04 00 00 vscatterpf0qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 85 ff ff ff vscatterpf0qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 85 ff ff ff vscatterpf0qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 6c 39 40 vscatterpf0qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 ac b9 00 04 00 00 vscatterpf0qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 b4 fe 85 ff ff ff vscatterpf1dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 b4 fe 85 ff ff ff vscatterpf1dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 74 39 20 vscatterpf1dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 b4 b9 00 04 00 00 vscatterpf1dpd ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 b4 fe 85 ff ff ff vscatterpf1dps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 b4 fe 85 ff ff ff vscatterpf1dps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 74 39 40 vscatterpf1dps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 b4 b9 00 04 00 00 vscatterpf1dps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 b4 fe 85 ff ff ff vscatterpf1qpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 b4 fe 85 ff ff ff vscatterpf1qpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 74 39 20 vscatterpf1qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 b4 b9 00 04 00 00 vscatterpf1qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 85 ff ff ff vscatterpf1qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 85 ff ff ff vscatterpf1qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 74 39 40 vscatterpf1qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 b4 b9 00 04 00 00 vscatterpf1qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\}
|
||||
[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 BYTE PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 42 0f 0d 94 f0 34 12 00 00 prefetchwt1 BYTE PTR \[rax\+r14\*8\+0x1234\]
|
||||
#pass
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86_64 AVX512PF insns
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 7b 00 00 00 vgatherpf0dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 7b 00 00 00 vgatherpf0dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 4c 39 20 vgatherpf0dpd 0x100\(%r9,%ymm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 8c b9 00 04 00 00 vgatherpf0dpd 0x400\(%rcx,%ymm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 8c fe 7b 00 00 00 vgatherpf0dps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 8c fe 7b 00 00 00 vgatherpf0dps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 4c 39 40 vgatherpf0dps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 8c b9 00 04 00 00 vgatherpf0dps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 8c fe 7b 00 00 00 vgatherpf0qpd 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 8c fe 7b 00 00 00 vgatherpf0qpd 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 4c 39 20 vgatherpf0qpd 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 8c b9 00 04 00 00 vgatherpf0qpd 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 7b 00 00 00 vgatherpf0qps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 7b 00 00 00 vgatherpf0qps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 4c 39 40 vgatherpf0qps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 8c b9 00 04 00 00 vgatherpf0qps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 7b 00 00 00 vgatherpf1dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 7b 00 00 00 vgatherpf1dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 54 39 20 vgatherpf1dpd 0x100\(%r9,%ymm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 94 b9 00 04 00 00 vgatherpf1dpd 0x400\(%rcx,%ymm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 94 fe 7b 00 00 00 vgatherpf1dps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 94 fe 7b 00 00 00 vgatherpf1dps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 54 39 40 vgatherpf1dps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 94 b9 00 04 00 00 vgatherpf1dps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 94 fe 7b 00 00 00 vgatherpf1qpd 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 94 fe 7b 00 00 00 vgatherpf1qpd 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 54 39 20 vgatherpf1qpd 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 94 b9 00 04 00 00 vgatherpf1qpd 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 7b 00 00 00 vgatherpf1qps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 7b 00 00 00 vgatherpf1qps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 54 39 40 vgatherpf1qps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 94 b9 00 04 00 00 vgatherpf1qps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 ac fe 7b 00 00 00 vscatterpf0dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 ac fe 7b 00 00 00 vscatterpf0dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 6c 39 20 vscatterpf0dpd 0x100\(%r9,%ymm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 ac b9 00 04 00 00 vscatterpf0dpd 0x400\(%rcx,%ymm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 ac fe 7b 00 00 00 vscatterpf0dps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 ac fe 7b 00 00 00 vscatterpf0dps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 6c 39 40 vscatterpf0dps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 ac b9 00 04 00 00 vscatterpf0dps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 ac fe 7b 00 00 00 vscatterpf0qpd 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 ac fe 7b 00 00 00 vscatterpf0qpd 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 6c 39 20 vscatterpf0qpd 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 ac b9 00 04 00 00 vscatterpf0qpd 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 7b 00 00 00 vscatterpf0qps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 7b 00 00 00 vscatterpf0qps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 6c 39 40 vscatterpf0qps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 ac b9 00 04 00 00 vscatterpf0qps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 b4 fe 7b 00 00 00 vscatterpf1dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 b4 fe 7b 00 00 00 vscatterpf1dpd 0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 74 39 20 vscatterpf1dpd 0x100\(%r9,%ymm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 b4 b9 00 04 00 00 vscatterpf1dpd 0x400\(%rcx,%ymm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 b4 fe 7b 00 00 00 vscatterpf1dps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 b4 fe 7b 00 00 00 vscatterpf1dps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 74 39 40 vscatterpf1dps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 b4 b9 00 04 00 00 vscatterpf1dps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 b4 fe 7b 00 00 00 vscatterpf1qpd 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 b4 fe 7b 00 00 00 vscatterpf1qpd 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 74 39 20 vscatterpf1qpd 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 b4 b9 00 04 00 00 vscatterpf1qpd 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 7b 00 00 00 vscatterpf1qps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 7b 00 00 00 vscatterpf1qps 0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 74 39 40 vscatterpf1qps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 b4 b9 00 04 00 00 vscatterpf1qps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 \(%rcx\)
|
||||
[ ]*[a-f0-9]+: 42 0f 0d 94 f0 23 01 00 00 prefetchwt1 0x123\(%rax,%r14,8\)
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 85 ff ff ff vgatherpf0dpd -0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 85 ff ff ff vgatherpf0dpd -0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 4c 39 20 vgatherpf0dpd 0x100\(%r9,%ymm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 8c b9 00 04 00 00 vgatherpf0dpd 0x400\(%rcx,%ymm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 8c fe 85 ff ff ff vgatherpf0dps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 8c fe 85 ff ff ff vgatherpf0dps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 4c 39 40 vgatherpf0dps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 8c b9 00 04 00 00 vgatherpf0dps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 8c fe 85 ff ff ff vgatherpf0qpd -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 8c fe 85 ff ff ff vgatherpf0qpd -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 4c 39 20 vgatherpf0qpd 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 8c b9 00 04 00 00 vgatherpf0qpd 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 85 ff ff ff vgatherpf0qps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 85 ff ff ff vgatherpf0qps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 4c 39 40 vgatherpf0qps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 8c b9 00 04 00 00 vgatherpf0qps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 85 ff ff ff vgatherpf1dpd -0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 85 ff ff ff vgatherpf1dpd -0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 54 39 20 vgatherpf1dpd 0x100\(%r9,%ymm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 94 b9 00 04 00 00 vgatherpf1dpd 0x400\(%rcx,%ymm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 94 fe 85 ff ff ff vgatherpf1dps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 94 fe 85 ff ff ff vgatherpf1dps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 54 39 40 vgatherpf1dps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 94 b9 00 04 00 00 vgatherpf1dps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 94 fe 85 ff ff ff vgatherpf1qpd -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 94 fe 85 ff ff ff vgatherpf1qpd -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 54 39 20 vgatherpf1qpd 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 94 b9 00 04 00 00 vgatherpf1qpd 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 85 ff ff ff vgatherpf1qps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 85 ff ff ff vgatherpf1qps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 54 39 40 vgatherpf1qps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 94 b9 00 04 00 00 vgatherpf1qps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 ac fe 85 ff ff ff vscatterpf0dpd -0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 ac fe 85 ff ff ff vscatterpf0dpd -0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 6c 39 20 vscatterpf0dpd 0x100\(%r9,%ymm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 ac b9 00 04 00 00 vscatterpf0dpd 0x400\(%rcx,%ymm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 ac fe 85 ff ff ff vscatterpf0dps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 ac fe 85 ff ff ff vscatterpf0dps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 6c 39 40 vscatterpf0dps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 ac b9 00 04 00 00 vscatterpf0dps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 ac fe 85 ff ff ff vscatterpf0qpd -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 ac fe 85 ff ff ff vscatterpf0qpd -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 6c 39 20 vscatterpf0qpd 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 ac b9 00 04 00 00 vscatterpf0qpd 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 85 ff ff ff vscatterpf0qps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 85 ff ff ff vscatterpf0qps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 6c 39 40 vscatterpf0qps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 ac b9 00 04 00 00 vscatterpf0qps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 b4 fe 85 ff ff ff vscatterpf1dpd -0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 b4 fe 85 ff ff ff vscatterpf1dpd -0x7b\(%r14,%ymm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c6 74 39 20 vscatterpf1dpd 0x100\(%r9,%ymm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c6 b4 b9 00 04 00 00 vscatterpf1dpd 0x400\(%rcx,%ymm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 b4 fe 85 ff ff ff vscatterpf1dps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 b4 fe 85 ff ff ff vscatterpf1dps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c6 74 39 40 vscatterpf1dps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c6 b4 b9 00 04 00 00 vscatterpf1dps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 b4 fe 85 ff ff ff vscatterpf1qpd -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 b4 fe 85 ff ff ff vscatterpf1qpd -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 fd 41 c7 74 39 20 vscatterpf1qpd 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 fd 41 c7 b4 b9 00 04 00 00 vscatterpf1qpd 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 85 ff ff ff vscatterpf1qps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 85 ff ff ff vscatterpf1qps -0x7b\(%r14,%zmm31,8\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 92 7d 41 c7 74 39 40 vscatterpf1qps 0x100\(%r9,%zmm31,1\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 62 b2 7d 41 c7 b4 b9 00 04 00 00 vscatterpf1qps 0x400\(%rcx,%zmm31,4\)\{%k1\}
|
||||
[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 \(%rcx\)
|
||||
[ ]*[a-f0-9]+: 42 0f 0d 94 f0 34 12 00 00 prefetchwt1 0x1234\(%rax,%r14,8\)
|
||||
#pass
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
# Check 64bit AVX512PF instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
vgatherpf0dpd 123(%r14,%ymm31,8){%k1} # AVX512PF
|
||||
vgatherpf0dpd 123(%r14,%ymm31,8){%k1} # AVX512PF
|
||||
vgatherpf0dpd 256(%r9,%ymm31){%k1} # AVX512PF
|
||||
vgatherpf0dpd 1024(%rcx,%ymm31,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf0dps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vgatherpf0dps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vgatherpf0dps 256(%r9,%zmm31){%k1} # AVX512PF
|
||||
vgatherpf0dps 1024(%rcx,%zmm31,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf0qpd 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vgatherpf0qpd 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vgatherpf0qpd 256(%r9,%zmm31){%k1} # AVX512PF
|
||||
vgatherpf0qpd 1024(%rcx,%zmm31,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf0qps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vgatherpf0qps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vgatherpf0qps 256(%r9,%zmm31){%k1} # AVX512PF
|
||||
vgatherpf0qps 1024(%rcx,%zmm31,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf1dpd 123(%r14,%ymm31,8){%k1} # AVX512PF
|
||||
vgatherpf1dpd 123(%r14,%ymm31,8){%k1} # AVX512PF
|
||||
vgatherpf1dpd 256(%r9,%ymm31){%k1} # AVX512PF
|
||||
vgatherpf1dpd 1024(%rcx,%ymm31,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf1dps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vgatherpf1dps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vgatherpf1dps 256(%r9,%zmm31){%k1} # AVX512PF
|
||||
vgatherpf1dps 1024(%rcx,%zmm31,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf1qpd 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vgatherpf1qpd 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vgatherpf1qpd 256(%r9,%zmm31){%k1} # AVX512PF
|
||||
vgatherpf1qpd 1024(%rcx,%zmm31,4){%k1} # AVX512PF
|
||||
|
||||
vgatherpf1qps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vgatherpf1qps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vgatherpf1qps 256(%r9,%zmm31){%k1} # AVX512PF
|
||||
vgatherpf1qps 1024(%rcx,%zmm31,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf0dpd 123(%r14,%ymm31,8){%k1} # AVX512PF
|
||||
vscatterpf0dpd 123(%r14,%ymm31,8){%k1} # AVX512PF
|
||||
vscatterpf0dpd 256(%r9,%ymm31){%k1} # AVX512PF
|
||||
vscatterpf0dpd 1024(%rcx,%ymm31,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf0dps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vscatterpf0dps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vscatterpf0dps 256(%r9,%zmm31){%k1} # AVX512PF
|
||||
vscatterpf0dps 1024(%rcx,%zmm31,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf0qpd 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vscatterpf0qpd 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vscatterpf0qpd 256(%r9,%zmm31){%k1} # AVX512PF
|
||||
vscatterpf0qpd 1024(%rcx,%zmm31,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf0qps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vscatterpf0qps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vscatterpf0qps 256(%r9,%zmm31){%k1} # AVX512PF
|
||||
vscatterpf0qps 1024(%rcx,%zmm31,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf1dpd 123(%r14,%ymm31,8){%k1} # AVX512PF
|
||||
vscatterpf1dpd 123(%r14,%ymm31,8){%k1} # AVX512PF
|
||||
vscatterpf1dpd 256(%r9,%ymm31){%k1} # AVX512PF
|
||||
vscatterpf1dpd 1024(%rcx,%ymm31,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf1dps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vscatterpf1dps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vscatterpf1dps 256(%r9,%zmm31){%k1} # AVX512PF
|
||||
vscatterpf1dps 1024(%rcx,%zmm31,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf1qpd 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vscatterpf1qpd 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vscatterpf1qpd 256(%r9,%zmm31){%k1} # AVX512PF
|
||||
vscatterpf1qpd 1024(%rcx,%zmm31,4){%k1} # AVX512PF
|
||||
|
||||
vscatterpf1qps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vscatterpf1qps 123(%r14,%zmm31,8){%k1} # AVX512PF
|
||||
vscatterpf1qps 256(%r9,%zmm31){%k1} # AVX512PF
|
||||
vscatterpf1qps 1024(%rcx,%zmm31,4){%k1} # AVX512PF
|
||||
|
||||
prefetchwt1 (%rcx) # AVX512PF
|
||||
prefetchwt1 0x123(%rax,%r14,8) # AVX512PF
|
||||
|
||||
.intel_syntax noprefix
|
||||
vgatherpf0dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf0dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf0dpd ZMMWORD PTR [r9+ymm31+256]{k1} # AVX512PF
|
||||
vgatherpf0dpd ZMMWORD PTR [rcx+ymm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf0dps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf0dps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf0dps ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF
|
||||
vgatherpf0dps ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf0qpd ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf0qpd ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf0qpd ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF
|
||||
vgatherpf0qpd ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf0qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf0qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf0qps ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF
|
||||
vgatherpf0qps ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf1dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf1dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf1dpd ZMMWORD PTR [r9+ymm31+256]{k1} # AVX512PF
|
||||
vgatherpf1dpd ZMMWORD PTR [rcx+ymm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf1dps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf1dps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf1dps ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF
|
||||
vgatherpf1dps ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf1qpd ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf1qpd ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf1qpd ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF
|
||||
vgatherpf1qpd ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vgatherpf1qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf1qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vgatherpf1qps ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF
|
||||
vgatherpf1qps ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf0dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf0dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf0dpd ZMMWORD PTR [r9+ymm31+256]{k1} # AVX512PF
|
||||
vscatterpf0dpd ZMMWORD PTR [rcx+ymm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf0dps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf0dps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf0dps ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF
|
||||
vscatterpf0dps ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf0qpd ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf0qpd ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf0qpd ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF
|
||||
vscatterpf0qpd ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf0qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf0qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf0qps ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF
|
||||
vscatterpf0qps ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf1dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf1dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf1dpd ZMMWORD PTR [r9+ymm31+256]{k1} # AVX512PF
|
||||
vscatterpf1dpd ZMMWORD PTR [rcx+ymm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf1dps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf1dps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf1dps ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF
|
||||
vscatterpf1dps ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf1qpd ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf1qpd ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf1qpd ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF
|
||||
vscatterpf1qpd ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
vscatterpf1qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf1qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF
|
||||
vscatterpf1qps ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF
|
||||
vscatterpf1qps ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF
|
||||
|
||||
prefetchwt1 BYTE PTR [rcx] # AVX512PF
|
||||
prefetchwt1 BYTE PTR [rax+r14*8+0x1234] # AVX512PF
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,171 @@
|
|||
# Check EVEX WIG instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
vextractps $0xab, %xmm29, %rax # AVX512
|
||||
vextractps $123, %xmm29, %rax # AVX512
|
||||
vextractps $123, %xmm29, %r8 # AVX512
|
||||
vextractps $123, %xmm29, (%rcx) # AVX512
|
||||
vextractps $123, %xmm29, 0x123(%rax,%r14,8) # AVX512
|
||||
vextractps $123, %xmm29, 508(%rdx) # AVX512 Disp8
|
||||
vextractps $123, %xmm29, 512(%rdx) # AVX512
|
||||
vextractps $123, %xmm29, -512(%rdx) # AVX512 Disp8
|
||||
vextractps $123, %xmm29, -516(%rdx) # AVX512
|
||||
|
||||
vpmovsxbd %xmm29, %zmm30{%k7} # AVX512
|
||||
vpmovsxbd %xmm29, %zmm30{%k7}{z} # AVX512
|
||||
vpmovsxbd (%rcx), %zmm30{%k7} # AVX512
|
||||
vpmovsxbd 0x123(%rax,%r14,8), %zmm30{%k7} # AVX512
|
||||
vpmovsxbd 2032(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovsxbd 2048(%rdx), %zmm30{%k7} # AVX512
|
||||
vpmovsxbd -2048(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovsxbd -2064(%rdx), %zmm30{%k7} # AVX512
|
||||
|
||||
vpmovsxbq %xmm29, %zmm30{%k7} # AVX512
|
||||
vpmovsxbq %xmm29, %zmm30{%k7}{z} # AVX512
|
||||
vpmovsxbq (%rcx), %zmm30{%k7} # AVX512
|
||||
vpmovsxbq 0x123(%rax,%r14,8), %zmm30{%k7} # AVX512
|
||||
vpmovsxbq 1016(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovsxbq 1024(%rdx), %zmm30{%k7} # AVX512
|
||||
vpmovsxbq -1024(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovsxbq -1032(%rdx), %zmm30{%k7} # AVX512
|
||||
|
||||
vpmovsxwd %ymm29, %zmm30{%k7} # AVX512
|
||||
vpmovsxwd %ymm29, %zmm30{%k7}{z} # AVX512
|
||||
vpmovsxwd (%rcx), %zmm30{%k7} # AVX512
|
||||
vpmovsxwd 0x123(%rax,%r14,8), %zmm30{%k7} # AVX512
|
||||
vpmovsxwd 4064(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovsxwd 4096(%rdx), %zmm30{%k7} # AVX512
|
||||
vpmovsxwd -4096(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovsxwd -4128(%rdx), %zmm30{%k7} # AVX512
|
||||
|
||||
vpmovsxwq %xmm29, %zmm30{%k7} # AVX512
|
||||
vpmovsxwq %xmm29, %zmm30{%k7}{z} # AVX512
|
||||
vpmovsxwq (%rcx), %zmm30{%k7} # AVX512
|
||||
vpmovsxwq 0x123(%rax,%r14,8), %zmm30{%k7} # AVX512
|
||||
vpmovsxwq 2032(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovsxwq 2048(%rdx), %zmm30{%k7} # AVX512
|
||||
vpmovsxwq -2048(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovsxwq -2064(%rdx), %zmm30{%k7} # AVX512
|
||||
|
||||
vpmovzxbd %xmm29, %zmm30{%k7} # AVX512
|
||||
vpmovzxbd %xmm29, %zmm30{%k7}{z} # AVX512
|
||||
vpmovzxbd (%rcx), %zmm30{%k7} # AVX512
|
||||
vpmovzxbd 0x123(%rax,%r14,8), %zmm30{%k7} # AVX512
|
||||
vpmovzxbd 2032(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovzxbd 2048(%rdx), %zmm30{%k7} # AVX512
|
||||
vpmovzxbd -2048(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovzxbd -2064(%rdx), %zmm30{%k7} # AVX512
|
||||
|
||||
vpmovzxbq %xmm29, %zmm30{%k7} # AVX512
|
||||
vpmovzxbq %xmm29, %zmm30{%k7}{z} # AVX512
|
||||
vpmovzxbq (%rcx), %zmm30{%k7} # AVX512
|
||||
vpmovzxbq 0x123(%rax,%r14,8), %zmm30{%k7} # AVX512
|
||||
vpmovzxbq 1016(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovzxbq 1024(%rdx), %zmm30{%k7} # AVX512
|
||||
vpmovzxbq -1024(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovzxbq -1032(%rdx), %zmm30{%k7} # AVX512
|
||||
|
||||
vpmovzxwd %ymm29, %zmm30{%k7} # AVX512
|
||||
vpmovzxwd %ymm29, %zmm30{%k7}{z} # AVX512
|
||||
vpmovzxwd (%rcx), %zmm30{%k7} # AVX512
|
||||
vpmovzxwd 0x123(%rax,%r14,8), %zmm30{%k7} # AVX512
|
||||
vpmovzxwd 4064(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovzxwd 4096(%rdx), %zmm30{%k7} # AVX512
|
||||
vpmovzxwd -4096(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovzxwd -4128(%rdx), %zmm30{%k7} # AVX512
|
||||
|
||||
vpmovzxwq %xmm29, %zmm30{%k7} # AVX512
|
||||
vpmovzxwq %xmm29, %zmm30{%k7}{z} # AVX512
|
||||
vpmovzxwq (%rcx), %zmm30{%k7} # AVX512
|
||||
vpmovzxwq 0x123(%rax,%r14,8), %zmm30{%k7} # AVX512
|
||||
vpmovzxwq 2032(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovzxwq 2048(%rdx), %zmm30{%k7} # AVX512
|
||||
vpmovzxwq -2048(%rdx), %zmm30{%k7} # AVX512 Disp8
|
||||
vpmovzxwq -2064(%rdx), %zmm30{%k7} # AVX512
|
||||
|
||||
.intel_syntax noprefix
|
||||
vextractps rax, xmm29, 0xab # AVX512
|
||||
vextractps rax, xmm29, 123 # AVX512
|
||||
vextractps r8, xmm29, 123 # AVX512
|
||||
vextractps DWORD PTR [rcx], xmm29, 123 # AVX512
|
||||
vextractps DWORD PTR [rax+r14*8+0x1234], xmm29, 123 # AVX512
|
||||
vextractps DWORD PTR [rdx+508], xmm29, 123 # AVX512 Disp8
|
||||
vextractps DWORD PTR [rdx+512], xmm29, 123 # AVX512
|
||||
vextractps DWORD PTR [rdx-512], xmm29, 123 # AVX512 Disp8
|
||||
vextractps DWORD PTR [rdx-516], xmm29, 123 # AVX512
|
||||
|
||||
vpmovsxbd zmm30{k7}, xmm29 # AVX512
|
||||
vpmovsxbd zmm30{k7}{z}, xmm29 # AVX512
|
||||
vpmovsxbd zmm30{k7}, XMMWORD PTR [rcx] # AVX512
|
||||
vpmovsxbd zmm30{k7}, XMMWORD PTR [rax+r14*8+0x1234] # AVX512
|
||||
vpmovsxbd zmm30{k7}, XMMWORD PTR [rdx+2032] # AVX512 Disp8
|
||||
vpmovsxbd zmm30{k7}, XMMWORD PTR [rdx+2048] # AVX512
|
||||
vpmovsxbd zmm30{k7}, XMMWORD PTR [rdx-2048] # AVX512 Disp8
|
||||
vpmovsxbd zmm30{k7}, XMMWORD PTR [rdx-2064] # AVX512
|
||||
|
||||
vpmovsxbq zmm30{k7}, xmm29 # AVX512
|
||||
vpmovsxbq zmm30{k7}{z}, xmm29 # AVX512
|
||||
vpmovsxbq zmm30{k7}, QWORD PTR [rcx] # AVX512
|
||||
vpmovsxbq zmm30{k7}, QWORD PTR [rax+r14*8+0x1234] # AVX512
|
||||
vpmovsxbq zmm30{k7}, QWORD PTR [rdx+1016] # AVX512 Disp8
|
||||
vpmovsxbq zmm30{k7}, QWORD PTR [rdx+1024] # AVX512
|
||||
vpmovsxbq zmm30{k7}, QWORD PTR [rdx-1024] # AVX512 Disp8
|
||||
vpmovsxbq zmm30{k7}, QWORD PTR [rdx-1032] # AVX512
|
||||
|
||||
vpmovsxwd zmm30{k7}, ymm29 # AVX512
|
||||
vpmovsxwd zmm30{k7}{z}, ymm29 # AVX512
|
||||
vpmovsxwd zmm30{k7}, YMMWORD PTR [rcx] # AVX512
|
||||
vpmovsxwd zmm30{k7}, YMMWORD PTR [rax+r14*8+0x1234] # AVX512
|
||||
vpmovsxwd zmm30{k7}, YMMWORD PTR [rdx+4064] # AVX512 Disp8
|
||||
vpmovsxwd zmm30{k7}, YMMWORD PTR [rdx+4096] # AVX512
|
||||
vpmovsxwd zmm30{k7}, YMMWORD PTR [rdx-4096] # AVX512 Disp8
|
||||
vpmovsxwd zmm30{k7}, YMMWORD PTR [rdx-4128] # AVX512
|
||||
|
||||
vpmovsxwq zmm30{k7}, xmm29 # AVX512
|
||||
vpmovsxwq zmm30{k7}{z}, xmm29 # AVX512
|
||||
vpmovsxwq zmm30{k7}, XMMWORD PTR [rcx] # AVX512
|
||||
vpmovsxwq zmm30{k7}, XMMWORD PTR [rax+r14*8+0x1234] # AVX512
|
||||
vpmovsxwq zmm30{k7}, XMMWORD PTR [rdx+2032] # AVX512 Disp8
|
||||
vpmovsxwq zmm30{k7}, XMMWORD PTR [rdx+2048] # AVX512
|
||||
vpmovsxwq zmm30{k7}, XMMWORD PTR [rdx-2048] # AVX512 Disp8
|
||||
vpmovsxwq zmm30{k7}, XMMWORD PTR [rdx-2064] # AVX512
|
||||
|
||||
vpmovzxbd zmm30{k7}, xmm29 # AVX512
|
||||
vpmovzxbd zmm30{k7}{z}, xmm29 # AVX512
|
||||
vpmovzxbd zmm30{k7}, XMMWORD PTR [rcx] # AVX512
|
||||
vpmovzxbd zmm30{k7}, XMMWORD PTR [rax+r14*8+0x1234] # AVX512
|
||||
vpmovzxbd zmm30{k7}, XMMWORD PTR [rdx+2032] # AVX512 Disp8
|
||||
vpmovzxbd zmm30{k7}, XMMWORD PTR [rdx+2048] # AVX512
|
||||
vpmovzxbd zmm30{k7}, XMMWORD PTR [rdx-2048] # AVX512 Disp8
|
||||
vpmovzxbd zmm30{k7}, XMMWORD PTR [rdx-2064] # AVX512
|
||||
|
||||
vpmovzxbq zmm30{k7}, xmm29 # AVX512
|
||||
vpmovzxbq zmm30{k7}{z}, xmm29 # AVX512
|
||||
vpmovzxbq zmm30{k7}, QWORD PTR [rcx] # AVX512
|
||||
vpmovzxbq zmm30{k7}, QWORD PTR [rax+r14*8+0x1234] # AVX512
|
||||
vpmovzxbq zmm30{k7}, QWORD PTR [rdx+1016] # AVX512 Disp8
|
||||
vpmovzxbq zmm30{k7}, QWORD PTR [rdx+1024] # AVX512
|
||||
vpmovzxbq zmm30{k7}, QWORD PTR [rdx-1024] # AVX512 Disp8
|
||||
vpmovzxbq zmm30{k7}, QWORD PTR [rdx-1032] # AVX512
|
||||
|
||||
vpmovzxwd zmm30{k7}, ymm29 # AVX512
|
||||
vpmovzxwd zmm30{k7}{z}, ymm29 # AVX512
|
||||
vpmovzxwd zmm30{k7}, YMMWORD PTR [rcx] # AVX512
|
||||
vpmovzxwd zmm30{k7}, YMMWORD PTR [rax+r14*8+0x1234] # AVX512
|
||||
vpmovzxwd zmm30{k7}, YMMWORD PTR [rdx+4064] # AVX512 Disp8
|
||||
vpmovzxwd zmm30{k7}, YMMWORD PTR [rdx+4096] # AVX512
|
||||
vpmovzxwd zmm30{k7}, YMMWORD PTR [rdx-4096] # AVX512 Disp8
|
||||
vpmovzxwd zmm30{k7}, YMMWORD PTR [rdx-4128] # AVX512
|
||||
|
||||
vpmovzxwq zmm30{k7}, xmm29 # AVX512
|
||||
vpmovzxwq zmm30{k7}{z}, xmm29 # AVX512
|
||||
vpmovzxwq zmm30{k7}, XMMWORD PTR [rcx] # AVX512
|
||||
vpmovzxwq zmm30{k7}, XMMWORD PTR [rax+r14*8+0x1234] # AVX512
|
||||
vpmovzxwq zmm30{k7}, XMMWORD PTR [rdx+2032] # AVX512 Disp8
|
||||
vpmovzxwq zmm30{k7}, XMMWORD PTR [rdx+2048] # AVX512
|
||||
vpmovzxwq zmm30{k7}, XMMWORD PTR [rdx-2048] # AVX512 Disp8
|
||||
vpmovzxwq zmm30{k7}, XMMWORD PTR [rdx-2064] # AVX512
|
||||
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
#as: -mevexwig=1
|
||||
#objdump: -dwMintel
|
||||
#name: x86_64 AVX512 wig insns (Intel disassembly)
|
||||
#source: x86-64-evex-wig.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps rax,xmm29,0xab
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps rax,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps DWORD PTR \[rcx\],xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 23 01 00 00 7b vextractps DWORD PTR \[rax\+r14\*8\+0x123\],xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps DWORD PTR \[rdx\+0x1fc\],xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa 00 02 00 00 7b vextractps DWORD PTR \[rdx\+0x200\],xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 80 7b vextractps DWORD PTR \[rdx-0x200\],xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa fc fd ff ff 7b vextractps DWORD PTR \[rdx-0x204\],xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 21 f5 vpmovsxbd zmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 21 f5 vpmovsxbd zmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 31 vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 21 b4 f0 23 01 00 00 vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 72 7f vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 b2 00 08 00 00 vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 72 80 vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 b2 f0 f7 ff ff vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 22 f5 vpmovsxbq zmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 22 f5 vpmovsxbq zmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 31 vpmovsxbq zmm30\{k7\},QWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 22 b4 f0 23 01 00 00 vpmovsxbq zmm30\{k7\},QWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 72 7f vpmovsxbq zmm30\{k7\},QWORD PTR \[rdx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 b2 00 04 00 00 vpmovsxbq zmm30\{k7\},QWORD PTR \[rdx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 72 80 vpmovsxbq zmm30\{k7\},QWORD PTR \[rdx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 b2 f8 fb ff ff vpmovsxbq zmm30\{k7\},QWORD PTR \[rdx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 23 f5 vpmovsxwd zmm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 23 f5 vpmovsxwd zmm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 31 vpmovsxwd zmm30\{k7\},YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 23 b4 f0 23 01 00 00 vpmovsxwd zmm30\{k7\},YMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 72 7f vpmovsxwd zmm30\{k7\},YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 b2 00 10 00 00 vpmovsxwd zmm30\{k7\},YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 72 80 vpmovsxwd zmm30\{k7\},YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 b2 e0 ef ff ff vpmovsxwd zmm30\{k7\},YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 24 f5 vpmovsxwq zmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 24 f5 vpmovsxwq zmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 31 vpmovsxwq zmm30\{k7\},XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 24 b4 f0 23 01 00 00 vpmovsxwq zmm30\{k7\},XMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 72 7f vpmovsxwq zmm30\{k7\},XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 b2 00 08 00 00 vpmovsxwq zmm30\{k7\},XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 72 80 vpmovsxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 b2 f0 f7 ff ff vpmovsxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 31 f5 vpmovzxbd zmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 31 f5 vpmovzxbd zmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 31 vpmovzxbd zmm30\{k7\},XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 31 b4 f0 23 01 00 00 vpmovzxbd zmm30\{k7\},XMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 72 7f vpmovzxbd zmm30\{k7\},XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 b2 00 08 00 00 vpmovzxbd zmm30\{k7\},XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 72 80 vpmovzxbd zmm30\{k7\},XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 b2 f0 f7 ff ff vpmovzxbd zmm30\{k7\},XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 32 f5 vpmovzxbq zmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 32 f5 vpmovzxbq zmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 31 vpmovzxbq zmm30\{k7\},QWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 32 b4 f0 23 01 00 00 vpmovzxbq zmm30\{k7\},QWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 72 7f vpmovzxbq zmm30\{k7\},QWORD PTR \[rdx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 b2 00 04 00 00 vpmovzxbq zmm30\{k7\},QWORD PTR \[rdx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 72 80 vpmovzxbq zmm30\{k7\},QWORD PTR \[rdx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 b2 f8 fb ff ff vpmovzxbq zmm30\{k7\},QWORD PTR \[rdx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 33 f5 vpmovzxwd zmm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 33 f5 vpmovzxwd zmm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 31 vpmovzxwd zmm30\{k7\},YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 33 b4 f0 23 01 00 00 vpmovzxwd zmm30\{k7\},YMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 72 7f vpmovzxwd zmm30\{k7\},YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 b2 00 10 00 00 vpmovzxwd zmm30\{k7\},YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 72 80 vpmovzxwd zmm30\{k7\},YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 b2 e0 ef ff ff vpmovzxwd zmm30\{k7\},YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 34 f5 vpmovzxwq zmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 34 f5 vpmovzxwq zmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 31 vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 34 b4 f0 23 01 00 00 vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 72 7f vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 00 08 00 00 vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 72 80 vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 f0 f7 ff ff vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps rax,xmm29,0xab
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps rax,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps r8,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps DWORD PTR \[rcx\],xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 34 12 00 00 7b vextractps DWORD PTR \[rax\+r14\*8\+0x1234\],xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps DWORD PTR \[rdx\+0x1fc\],xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa 00 02 00 00 7b vextractps DWORD PTR \[rdx\+0x200\],xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 80 7b vextractps DWORD PTR \[rdx-0x200\],xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa fc fd ff ff 7b vextractps DWORD PTR \[rdx-0x204\],xmm29,0x7b
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 21 f5 vpmovsxbd zmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 21 f5 vpmovsxbd zmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 31 vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 21 b4 f0 34 12 00 00 vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 72 7f vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 b2 00 08 00 00 vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 72 80 vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 b2 f0 f7 ff ff vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 22 f5 vpmovsxbq zmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 22 f5 vpmovsxbq zmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 31 vpmovsxbq zmm30\{k7\},QWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 22 b4 f0 34 12 00 00 vpmovsxbq zmm30\{k7\},QWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 72 7f vpmovsxbq zmm30\{k7\},QWORD PTR \[rdx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 b2 00 04 00 00 vpmovsxbq zmm30\{k7\},QWORD PTR \[rdx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 72 80 vpmovsxbq zmm30\{k7\},QWORD PTR \[rdx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 b2 f8 fb ff ff vpmovsxbq zmm30\{k7\},QWORD PTR \[rdx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 23 f5 vpmovsxwd zmm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 23 f5 vpmovsxwd zmm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 31 vpmovsxwd zmm30\{k7\},YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 23 b4 f0 34 12 00 00 vpmovsxwd zmm30\{k7\},YMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 72 7f vpmovsxwd zmm30\{k7\},YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 b2 00 10 00 00 vpmovsxwd zmm30\{k7\},YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 72 80 vpmovsxwd zmm30\{k7\},YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 b2 e0 ef ff ff vpmovsxwd zmm30\{k7\},YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 24 f5 vpmovsxwq zmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 24 f5 vpmovsxwq zmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 31 vpmovsxwq zmm30\{k7\},XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 24 b4 f0 34 12 00 00 vpmovsxwq zmm30\{k7\},XMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 72 7f vpmovsxwq zmm30\{k7\},XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 b2 00 08 00 00 vpmovsxwq zmm30\{k7\},XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 72 80 vpmovsxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 b2 f0 f7 ff ff vpmovsxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 31 f5 vpmovzxbd zmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 31 f5 vpmovzxbd zmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 31 vpmovzxbd zmm30\{k7\},XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 31 b4 f0 34 12 00 00 vpmovzxbd zmm30\{k7\},XMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 72 7f vpmovzxbd zmm30\{k7\},XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 b2 00 08 00 00 vpmovzxbd zmm30\{k7\},XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 72 80 vpmovzxbd zmm30\{k7\},XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 b2 f0 f7 ff ff vpmovzxbd zmm30\{k7\},XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 32 f5 vpmovzxbq zmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 32 f5 vpmovzxbq zmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 31 vpmovzxbq zmm30\{k7\},QWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 32 b4 f0 34 12 00 00 vpmovzxbq zmm30\{k7\},QWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 72 7f vpmovzxbq zmm30\{k7\},QWORD PTR \[rdx\+0x3f8\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 b2 00 04 00 00 vpmovzxbq zmm30\{k7\},QWORD PTR \[rdx\+0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 72 80 vpmovzxbq zmm30\{k7\},QWORD PTR \[rdx-0x400\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 b2 f8 fb ff ff vpmovzxbq zmm30\{k7\},QWORD PTR \[rdx-0x408\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 33 f5 vpmovzxwd zmm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 33 f5 vpmovzxwd zmm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 31 vpmovzxwd zmm30\{k7\},YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 33 b4 f0 34 12 00 00 vpmovzxwd zmm30\{k7\},YMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 72 7f vpmovzxwd zmm30\{k7\},YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 b2 00 10 00 00 vpmovzxwd zmm30\{k7\},YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 72 80 vpmovzxwd zmm30\{k7\},YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 b2 e0 ef ff ff vpmovzxwd zmm30\{k7\},YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 34 f5 vpmovzxwq zmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 34 f5 vpmovzxwq zmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 31 vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 34 b4 f0 34 12 00 00 vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 72 7f vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 00 08 00 00 vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 72 80 vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 f0 f7 ff ff vpmovzxwq zmm30\{k7\},XMMWORD PTR \[rdx-0x810\]
|
||||
#pass
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
#as: -mevexwig=1
|
||||
#objdump: -dw
|
||||
#name: x86_64 AVX512 wig insns
|
||||
#source: x86-64-evex-wig.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps \$0x7b,%xmm29,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 23 01 00 00 7b vextractps \$0x7b,%xmm29,0x123\(%rax,%r14,8\)
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps \$0x7b,%xmm29,0x1fc\(%rdx\)
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa 00 02 00 00 7b vextractps \$0x7b,%xmm29,0x200\(%rdx\)
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 80 7b vextractps \$0x7b,%xmm29,-0x200\(%rdx\)
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa fc fd ff ff 7b vextractps \$0x7b,%xmm29,-0x204\(%rdx\)
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 21 f5 vpmovsxbd %xmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 21 f5 vpmovsxbd %xmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 31 vpmovsxbd \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 21 b4 f0 23 01 00 00 vpmovsxbd 0x123\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 72 7f vpmovsxbd 0x7f0\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 b2 00 08 00 00 vpmovsxbd 0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 72 80 vpmovsxbd -0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 b2 f0 f7 ff ff vpmovsxbd -0x810\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 22 f5 vpmovsxbq %xmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 22 f5 vpmovsxbq %xmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 31 vpmovsxbq \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 22 b4 f0 23 01 00 00 vpmovsxbq 0x123\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 72 7f vpmovsxbq 0x3f8\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 b2 00 04 00 00 vpmovsxbq 0x400\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 72 80 vpmovsxbq -0x400\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 b2 f8 fb ff ff vpmovsxbq -0x408\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 23 f5 vpmovsxwd %ymm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 23 f5 vpmovsxwd %ymm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 31 vpmovsxwd \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 23 b4 f0 23 01 00 00 vpmovsxwd 0x123\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 72 7f vpmovsxwd 0xfe0\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 b2 00 10 00 00 vpmovsxwd 0x1000\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 72 80 vpmovsxwd -0x1000\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 b2 e0 ef ff ff vpmovsxwd -0x1020\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 24 f5 vpmovsxwq %xmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 24 f5 vpmovsxwq %xmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 31 vpmovsxwq \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 24 b4 f0 23 01 00 00 vpmovsxwq 0x123\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 72 7f vpmovsxwq 0x7f0\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 b2 00 08 00 00 vpmovsxwq 0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 72 80 vpmovsxwq -0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 b2 f0 f7 ff ff vpmovsxwq -0x810\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 31 f5 vpmovzxbd %xmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 31 f5 vpmovzxbd %xmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 31 vpmovzxbd \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 31 b4 f0 23 01 00 00 vpmovzxbd 0x123\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 72 7f vpmovzxbd 0x7f0\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 b2 00 08 00 00 vpmovzxbd 0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 72 80 vpmovzxbd -0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 b2 f0 f7 ff ff vpmovzxbd -0x810\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 32 f5 vpmovzxbq %xmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 32 f5 vpmovzxbq %xmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 31 vpmovzxbq \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 32 b4 f0 23 01 00 00 vpmovzxbq 0x123\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 72 7f vpmovzxbq 0x3f8\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 b2 00 04 00 00 vpmovzxbq 0x400\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 72 80 vpmovzxbq -0x400\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 b2 f8 fb ff ff vpmovzxbq -0x408\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 33 f5 vpmovzxwd %ymm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 33 f5 vpmovzxwd %ymm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 31 vpmovzxwd \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 33 b4 f0 23 01 00 00 vpmovzxwd 0x123\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 72 7f vpmovzxwd 0xfe0\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 b2 00 10 00 00 vpmovzxwd 0x1000\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 72 80 vpmovzxwd -0x1000\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 b2 e0 ef ff ff vpmovzxwd -0x1020\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 34 f5 vpmovzxwq %xmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 34 f5 vpmovzxwq %xmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 31 vpmovzxwq \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 34 b4 f0 23 01 00 00 vpmovzxwq 0x123\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 72 7f vpmovzxwq 0x7f0\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 00 08 00 00 vpmovzxwq 0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 72 80 vpmovzxwq -0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 f0 f7 ff ff vpmovzxwq -0x810\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 ab vextractps \$0xab,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+: 62 43 fd 08 17 e8 7b vextractps \$0x7b,%xmm29,%r8
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 29 7b vextractps \$0x7b,%xmm29,\(%rcx\)
|
||||
[ ]*[a-f0-9]+: 62 23 fd 08 17 ac f0 34 12 00 00 7b vextractps \$0x7b,%xmm29,0x1234\(%rax,%r14,8\)
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 7f 7b vextractps \$0x7b,%xmm29,0x1fc\(%rdx\)
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa 00 02 00 00 7b vextractps \$0x7b,%xmm29,0x200\(%rdx\)
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 6a 80 7b vextractps \$0x7b,%xmm29,-0x200\(%rdx\)
|
||||
[ ]*[a-f0-9]+: 62 63 fd 08 17 aa fc fd ff ff 7b vextractps \$0x7b,%xmm29,-0x204\(%rdx\)
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 21 f5 vpmovsxbd %xmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 21 f5 vpmovsxbd %xmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 31 vpmovsxbd \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 21 b4 f0 34 12 00 00 vpmovsxbd 0x1234\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 72 7f vpmovsxbd 0x7f0\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 b2 00 08 00 00 vpmovsxbd 0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 72 80 vpmovsxbd -0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 21 b2 f0 f7 ff ff vpmovsxbd -0x810\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 22 f5 vpmovsxbq %xmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 22 f5 vpmovsxbq %xmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 31 vpmovsxbq \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 22 b4 f0 34 12 00 00 vpmovsxbq 0x1234\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 72 7f vpmovsxbq 0x3f8\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 b2 00 04 00 00 vpmovsxbq 0x400\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 72 80 vpmovsxbq -0x400\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 22 b2 f8 fb ff ff vpmovsxbq -0x408\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 23 f5 vpmovsxwd %ymm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 23 f5 vpmovsxwd %ymm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 31 vpmovsxwd \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 23 b4 f0 34 12 00 00 vpmovsxwd 0x1234\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 72 7f vpmovsxwd 0xfe0\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 b2 00 10 00 00 vpmovsxwd 0x1000\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 72 80 vpmovsxwd -0x1000\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 23 b2 e0 ef ff ff vpmovsxwd -0x1020\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 24 f5 vpmovsxwq %xmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 24 f5 vpmovsxwq %xmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 31 vpmovsxwq \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 24 b4 f0 34 12 00 00 vpmovsxwq 0x1234\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 72 7f vpmovsxwq 0x7f0\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 b2 00 08 00 00 vpmovsxwq 0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 72 80 vpmovsxwq -0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 24 b2 f0 f7 ff ff vpmovsxwq -0x810\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 31 f5 vpmovzxbd %xmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 31 f5 vpmovzxbd %xmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 31 vpmovzxbd \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 31 b4 f0 34 12 00 00 vpmovzxbd 0x1234\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 72 7f vpmovzxbd 0x7f0\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 b2 00 08 00 00 vpmovzxbd 0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 72 80 vpmovzxbd -0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 31 b2 f0 f7 ff ff vpmovzxbd -0x810\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 32 f5 vpmovzxbq %xmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 32 f5 vpmovzxbq %xmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 31 vpmovzxbq \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 32 b4 f0 34 12 00 00 vpmovzxbq 0x1234\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 72 7f vpmovzxbq 0x3f8\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 b2 00 04 00 00 vpmovzxbq 0x400\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 72 80 vpmovzxbq -0x400\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 32 b2 f8 fb ff ff vpmovzxbq -0x408\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 33 f5 vpmovzxwd %ymm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 33 f5 vpmovzxwd %ymm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 31 vpmovzxwd \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 33 b4 f0 34 12 00 00 vpmovzxwd 0x1234\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 72 7f vpmovzxwd 0xfe0\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 b2 00 10 00 00 vpmovzxwd 0x1000\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 72 80 vpmovzxwd -0x1000\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 33 b2 e0 ef ff ff vpmovzxwd -0x1020\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd 4f 34 f5 vpmovzxwq %xmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 02 fd cf 34 f5 vpmovzxwq %xmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 31 vpmovzxwq \(%rcx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 22 fd 4f 34 b4 f0 34 12 00 00 vpmovzxwq 0x1234\(%rax,%r14,8\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 72 7f vpmovzxwq 0x7f0\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 00 08 00 00 vpmovzxwq 0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 72 80 vpmovzxwq -0x800\(%rdx\),%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+: 62 62 fd 4f 34 b2 f0 f7 ff ff vpmovzxwq -0x810\(%rdx\),%zmm30\{%k7\}
|
||||
#pass
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
.*: Assembler messages:
|
||||
.*:4: Error: .*
|
||||
.*:5: Error: .*
|
||||
.*:6: Error: .*
|
||||
.*:7: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:9: Error: .*
|
||||
.*:11: Error: .*
|
||||
.*:12: Error: .*
|
||||
.*:14: Error: .*
|
||||
.*:15: Error: .*
|
||||
.*:18: Error: .*
|
||||
.*:19: Error: .*
|
||||
.*:20: Error: .*
|
||||
.*:21: Error: .*
|
||||
.*:21: Error: .*
|
||||
.*:22: Error: .*
|
||||
.*:22: Error: .*
|
||||
.*:23: Error: .*
|
||||
.*:23: Error: .*
|
||||
.*:25: Error: .*
|
||||
.*:26: Error: .*
|
||||
.*:28: Error: .*
|
||||
.*:29: Error: .*
|
||||
.*:31: Error: .*
|
||||
.*:32: Error: .*
|
||||
.*:33: Error: .*
|
||||
.*:34: Error: .*
|
||||
.*:35: Error: .*
|
||||
.*:36: Error: .*
|
||||
.*:37: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+# Check illegal AVX512F instructions
|
||||
[ ]*2[ ]+\.text
|
||||
[ ]*3[ ]+_start:
|
||||
[ ]*4[ ]+mov \{sae\}, %rax\{%k1\}
|
||||
[ ]*5[ ]+mov \{sae\}, %rax
|
||||
[ ]*6[ ]+mov %rbx, %rax\{%k2\}
|
||||
[ ]*7[ ]+vaddps %zmm3, %zmm1, %zmm2\{z\}\{%k1\}\{z\}
|
||||
[ ]*8[ ]+vaddps %zmm3, %zmm1\{%k3\}, %zmm2\{z\}
|
||||
[ ]*9[ ]+vaddps %zmm3, %zmm1\{%k1\}, %zmm2\{%k2\}
|
||||
[ ]*10[ ]+
|
||||
[ ]*11[ ]+vcvtps2pd \(%rax\), %zmm1\{1to8\}
|
||||
[ ]*12[ ]+vcvtps2pd \(%rax\)\{1to16\}, %zmm1
|
||||
[ ]*13[ ]+
|
||||
[ ]*14[ ]+vcvtps2pd \(%rax\)\{%k1\}, %zmm1
|
||||
[ ]*15[ ]+vcvtps2pd \(%rax\)\{z\}, %zmm1
|
||||
[ ]*16[ ]+
|
||||
[ ]*17[ ]+\.intel_syntax noprefix
|
||||
[ ]*18[ ]+mov rax\{k1\}, \{sae\}
|
||||
[ ]*19[ ]+mov rax, \{sae\}
|
||||
[ ]*20[ ]+mov rax\{k2\}, rbx
|
||||
[ ]*21[ ]+vaddps zmm2\{z\}\{k1\}\{z\}, zmm1, zmm3
|
||||
[ ]*22[ ]+vaddps zmm2\{z\}, zmm1\{k3\}, zmm3
|
||||
[ ]*23[ ]+vaddps zmm2\{k2\}, zmm1\{k1\}, zmm3
|
||||
[ ]*24[ ]+
|
||||
[ ]*25[ ]+vcvtps2pd zmm1\{1to8\}, \[rax\]
|
||||
[ ]*26[ ]+vcvtps2pd zmm1, \[rax\]\{1to16\}
|
||||
[ ]*27[ ]+
|
||||
[ ]*28[ ]+vcvtps2pd zmm1, \[rax\]\{k1\}
|
||||
[ ]*29[ ]+vcvtps2pd zmm1, \[rax\]\{z\}
|
||||
[ ]*30[ ]+
|
||||
[ ]*31[ ]+vaddps zmm2, zmm1, QWORD PTR \[rax\]\{1to8\}
|
||||
[ ]*32[ ]+vaddps zmm2, zmm1, QWORD PTR \[rax\]\{1to16\}
|
||||
[ ]*33[ ]+vaddpd zmm2, zmm1, DWORD PTR \[rax\]\{1to8\}
|
||||
[ ]*34[ ]+vaddpd zmm2, zmm1, DWORD PTR \[rax\]\{1to16\}
|
||||
[ ]*35[ ]+vaddps zmm2, zmm1, ZMMWORD PTR \[rax\]\{1to16\}
|
||||
[ ]*36[ ]+vaddps zmm2, zmm1, DWORD PTR \[rax\]
|
||||
[ ]*37[ ]+vaddpd zmm2, zmm1, QWORD PTR \[rax\]
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
# Check illegal AVX512F instructions
|
||||
.text
|
||||
_start:
|
||||
mov {sae}, %rax{%k1}
|
||||
mov {sae}, %rax
|
||||
mov %rbx, %rax{%k2}
|
||||
vaddps %zmm3, %zmm1, %zmm2{z}{%k1}{z}
|
||||
vaddps %zmm3, %zmm1{%k3}, %zmm2{z}
|
||||
vaddps %zmm3, %zmm1{%k1}, %zmm2{%k2}
|
||||
|
||||
vcvtps2pd (%rax), %zmm1{1to8}
|
||||
vcvtps2pd (%rax){1to16}, %zmm1
|
||||
|
||||
vcvtps2pd (%rax){%k1}, %zmm1
|
||||
vcvtps2pd (%rax){z}, %zmm1
|
||||
|
||||
.intel_syntax noprefix
|
||||
mov rax{k1}, {sae}
|
||||
mov rax, {sae}
|
||||
mov rax{k2}, rbx
|
||||
vaddps zmm2{z}{k1}{z}, zmm1, zmm3
|
||||
vaddps zmm2{z}, zmm1{k3}, zmm3
|
||||
vaddps zmm2{k2}, zmm1{k1}, zmm3
|
||||
|
||||
vcvtps2pd zmm1{1to8}, [rax]
|
||||
vcvtps2pd zmm1, [rax]{1to16}
|
||||
|
||||
vcvtps2pd zmm1, [rax]{k1}
|
||||
vcvtps2pd zmm1, [rax]{z}
|
||||
|
||||
vaddps zmm2, zmm1, QWORD PTR [rax]{1to8}
|
||||
vaddps zmm2, zmm1, QWORD PTR [rax]{1to16}
|
||||
vaddpd zmm2, zmm1, DWORD PTR [rax]{1to8}
|
||||
vaddpd zmm2, zmm1, DWORD PTR [rax]{1to16}
|
||||
vaddps zmm2, zmm1, ZMMWORD PTR [rax]{1to16}
|
||||
vaddps zmm2, zmm1, DWORD PTR [rax]
|
||||
vaddpd zmm2, zmm1, QWORD PTR [rax]
|
||||
|
|
@ -9,7 +9,7 @@ Disassembly of section .text:
|
|||
0+ <amd_prefetch>:
|
||||
\s*[a-f0-9]+: 0f 0d 00 prefetch BYTE PTR \[rax\]
|
||||
\s*[a-f0-9]+: 0f 0d 08 prefetchw BYTE PTR \[rax\]
|
||||
\s*[a-f0-9]+: 0f 0d 10 prefetch BYTE PTR \[rax\]
|
||||
\s*[a-f0-9]+: 0f 0d 10 prefetchwt1 BYTE PTR \[rax\]
|
||||
\s*[a-f0-9]+: 0f 0d 18 prefetch BYTE PTR \[rax\]
|
||||
\s*[a-f0-9]+: 0f 0d 20 prefetch BYTE PTR \[rax\]
|
||||
\s*[a-f0-9]+: 0f 0d 28 prefetch BYTE PTR \[rax\]
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ Disassembly of section .text:
|
|||
0+ <amd_prefetch>:
|
||||
\s*[a-f0-9]+: 0f 0d 00 prefetch \(%rax\)
|
||||
\s*[a-f0-9]+: 0f 0d 08 prefetchw \(%rax\)
|
||||
\s*[a-f0-9]+: 0f 0d 10 prefetch \(%rax\)
|
||||
\s*[a-f0-9]+: 0f 0d 10 prefetchwt1 \(%rax\)
|
||||
\s*[a-f0-9]+: 0f 0d 18 prefetch \(%rax\)
|
||||
\s*[a-f0-9]+: 0f 0d 20 prefetch \(%rax\)
|
||||
\s*[a-f0-9]+: 0f 0d 28 prefetch \(%rax\)
|
||||
|
|
|
|||
|
|
@ -1,3 +1,260 @@
|
|||
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
|
||||
Alexander Ivchenko <alexander.ivchenko@intel.com>
|
||||
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
|
||||
Sergey Lega <sergey.s.lega@intel.com>
|
||||
Anna Tikhonova <anna.tikhonova@intel.com>
|
||||
Ilya Tocar <ilya.tocar@intel.com>
|
||||
Andrey Turetskiy <andrey.turetskiy@intel.com>
|
||||
Ilya Verbin <ilya.verbin@intel.com>
|
||||
Kirill Yukhin <kirill.yukhin@intel.com>
|
||||
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
||||
|
||||
* i386-dis-evex.h: New.
|
||||
* i386-dis.c (OP_Rounding): New.
|
||||
(VPCMP_Fixup): New.
|
||||
(OP_Mask): New.
|
||||
(Rdq): New.
|
||||
(XMxmmq): New.
|
||||
(EXdScalarS): New.
|
||||
(EXymm): New.
|
||||
(EXEvexHalfBcstXmmq): New.
|
||||
(EXxmm_mdq): New.
|
||||
(EXEvexXGscat): New.
|
||||
(EXEvexXNoBcst): New.
|
||||
(VPCMP): New.
|
||||
(EXxEVexR): New.
|
||||
(EXxEVexS): New.
|
||||
(XMask): New.
|
||||
(MaskG): New.
|
||||
(MaskE): New.
|
||||
(MaskR): New.
|
||||
(MaskVex): New.
|
||||
(modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
|
||||
evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
|
||||
evex_rounding_mode, evex_sae_mode, mask_mode.
|
||||
(USE_EVEX_TABLE): New.
|
||||
(EVEX_TABLE): New.
|
||||
(EVEX enum): New.
|
||||
(REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
|
||||
REG_EVEX_0F38C7.
|
||||
(MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
|
||||
MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
|
||||
MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
|
||||
MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
|
||||
MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
|
||||
MOD_EVEX_0F38C7_REG_6.
|
||||
(PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
|
||||
PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
|
||||
PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
|
||||
PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
|
||||
PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
|
||||
PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
|
||||
PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
|
||||
PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
|
||||
PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
|
||||
PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
|
||||
PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
|
||||
PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
|
||||
PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
|
||||
PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
|
||||
PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
|
||||
PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
|
||||
PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
|
||||
PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
|
||||
PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
|
||||
PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
|
||||
PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
|
||||
PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
|
||||
PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
|
||||
PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
|
||||
PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
|
||||
PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
|
||||
PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
|
||||
PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
|
||||
PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
|
||||
PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
|
||||
PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
|
||||
PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
|
||||
PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
|
||||
PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
|
||||
PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
|
||||
PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
|
||||
PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
|
||||
PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
|
||||
PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
|
||||
PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
|
||||
PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
|
||||
PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
|
||||
PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
|
||||
PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
|
||||
PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
|
||||
PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
|
||||
PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
|
||||
PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
|
||||
PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
|
||||
PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
|
||||
PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
|
||||
PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
|
||||
PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
|
||||
PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
|
||||
PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
|
||||
PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
|
||||
PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
|
||||
PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
|
||||
PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
|
||||
PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
|
||||
PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
|
||||
PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
|
||||
PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
|
||||
PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
|
||||
PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
|
||||
PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
|
||||
PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
|
||||
PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
|
||||
PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
|
||||
PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
|
||||
PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
|
||||
PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
|
||||
PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
|
||||
PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
|
||||
PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
|
||||
PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
|
||||
PREFIX_EVEX_0F3A55.
|
||||
(VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
|
||||
VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
|
||||
VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
|
||||
VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
|
||||
VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
|
||||
VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
|
||||
VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
|
||||
VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
|
||||
VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
|
||||
VEX_W_0F3A32_P_2_LEN_0.
|
||||
(VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
|
||||
EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
|
||||
EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
|
||||
EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
|
||||
EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
|
||||
EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
|
||||
EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
|
||||
EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
|
||||
EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
|
||||
EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
|
||||
EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
|
||||
EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
|
||||
EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
|
||||
EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
|
||||
EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
|
||||
EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
|
||||
EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
|
||||
EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
|
||||
EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
|
||||
EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
|
||||
EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
|
||||
EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
|
||||
EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
|
||||
EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
|
||||
EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
|
||||
EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
|
||||
EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
|
||||
EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
|
||||
EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
|
||||
EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
|
||||
EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
|
||||
EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
|
||||
EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
|
||||
EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
|
||||
EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
|
||||
EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
|
||||
EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
|
||||
EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
|
||||
EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
|
||||
EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
|
||||
EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
|
||||
EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
|
||||
EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
|
||||
EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
|
||||
EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
|
||||
EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
|
||||
EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
|
||||
EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
|
||||
EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
|
||||
EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
|
||||
EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
|
||||
EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
|
||||
EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
|
||||
EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
|
||||
(struct vex): Add fields evex, r, v, mask_register_specifier,
|
||||
zeroing, ll, b.
|
||||
(intel_names_xmm): Add upper 16 registers.
|
||||
(att_names_xmm): Ditto.
|
||||
(intel_names_ymm): Ditto.
|
||||
(att_names_ymm): Ditto.
|
||||
(names_zmm): New.
|
||||
(intel_names_zmm): Ditto.
|
||||
(att_names_zmm): Ditto.
|
||||
(names_mask): Ditto.
|
||||
(intel_names_mask): Ditto.
|
||||
(att_names_mask): Ditto.
|
||||
(names_rounding): Ditto.
|
||||
(names_broadcast): Ditto.
|
||||
(x86_64_table): Add escape to evex-table.
|
||||
(reg_table): Include reg_table evex-entries from
|
||||
i386-dis-evex.h. Fix prefetchwt1 instruction.
|
||||
(prefix_table): Add entries for new instructions.
|
||||
(vex_table): Ditto.
|
||||
(vex_len_table): Ditto.
|
||||
(vex_w_table): Ditto.
|
||||
(mod_table): Ditto.
|
||||
(get_valid_dis386): Properly handle new instructions.
|
||||
(print_insn): Handle zmm and mask registers, print mask operand.
|
||||
(intel_operand_size): Support EVEX, new modes and sizes.
|
||||
(OP_E_register): Handle new modes.
|
||||
(OP_E_memory): Ditto.
|
||||
(OP_G): Ditto.
|
||||
(OP_XMM): Ditto.
|
||||
(OP_EX): Ditto.
|
||||
(OP_VEX): Ditto.
|
||||
* i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
|
||||
CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
|
||||
CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
|
||||
(cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
|
||||
CpuAVX512PF and CpuVREX.
|
||||
(operand_type_init): Add OPERAND_TYPE_REGZMM,
|
||||
OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
|
||||
(opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
|
||||
StaticRounding, SAE, Disp8MemShift, NoDefMask.
|
||||
(operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
|
||||
* i386-init.h: Regenerate.
|
||||
* i386-opc.h (CpuAVX512F): New.
|
||||
(CpuAVX512CD): New.
|
||||
(CpuAVX512ER): New.
|
||||
(CpuAVX512PF): New.
|
||||
(CpuVREX): New.
|
||||
(i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
|
||||
cpuavx512pf and cpuvrex fields.
|
||||
(VecSIB): Add VecSIB512.
|
||||
(EVex): New.
|
||||
(Masking): New.
|
||||
(VecESize): New.
|
||||
(Broadcast): New.
|
||||
(StaticRounding): New.
|
||||
(SAE): New.
|
||||
(Disp8MemShift): New.
|
||||
(NoDefMask): New.
|
||||
(i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
|
||||
staticrounding, sae, disp8memshift and nodefmask.
|
||||
(RegZMM): New.
|
||||
(Zmmword): Ditto.
|
||||
(Vec_Disp8): Ditto.
|
||||
(i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
|
||||
fields.
|
||||
(RegVRex): New.
|
||||
* i386-opc.tbl: Add AVX512 instructions.
|
||||
* i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
|
||||
registers, mask registers.
|
||||
* i386-tbl.h: Regenerate.
|
||||
|
||||
2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
|
||||
|
||||
PR gas/15220
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
1337
opcodes/i386-dis.c
1337
opcodes/i386-dis.c
File diff suppressed because it is too large
Load Diff
|
|
@ -127,7 +127,7 @@ static initializer cpu_flag_init[] =
|
|||
{ "CPU_SSE4_2_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2" },
|
||||
{ "CPU_ANY_SSE_FLAGS",
|
||||
"CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuAVX|CpuAVX2" },
|
||||
"CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" },
|
||||
{ "CPU_VMX_FLAGS",
|
||||
"CpuVMX" },
|
||||
{ "CPU_SMX_FLAGS",
|
||||
|
|
@ -194,8 +194,16 @@ static initializer cpu_flag_init[] =
|
|||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX" },
|
||||
{ "CPU_AVX2_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2" },
|
||||
{ "CPU_AVX512F_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F" },
|
||||
{ "CPU_AVX512CD_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD" },
|
||||
{ "CPU_AVX512ER_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" },
|
||||
{ "CPU_AVX512PF_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" },
|
||||
{ "CPU_ANY_AVX_FLAGS",
|
||||
"CpuAVX|CpuAVX2" },
|
||||
"CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" },
|
||||
{ "CPU_L1OM_FLAGS",
|
||||
"unknown" },
|
||||
{ "CPU_K1OM_FLAGS",
|
||||
|
|
@ -280,6 +288,10 @@ static initializer operand_type_init[] =
|
|||
"RegXMM" },
|
||||
{ "OPERAND_TYPE_REGYMM",
|
||||
"RegYMM" },
|
||||
{ "OPERAND_TYPE_REGZMM",
|
||||
"RegZMM" },
|
||||
{ "OPERAND_TYPE_REGMASK",
|
||||
"RegMask" },
|
||||
{ "OPERAND_TYPE_ESSEG",
|
||||
"EsSeg" },
|
||||
{ "OPERAND_TYPE_ACC32",
|
||||
|
|
@ -314,6 +326,8 @@ static initializer operand_type_init[] =
|
|||
"Vec_Imm4" },
|
||||
{ "OPERAND_TYPE_REGBND",
|
||||
"RegBND" },
|
||||
{ "OPERAND_TYPE_VEC_DISP8",
|
||||
"Vec_Disp8" },
|
||||
};
|
||||
|
||||
typedef struct bitfield
|
||||
|
|
@ -350,6 +364,10 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (CpuSSE4_2),
|
||||
BITFIELD (CpuAVX),
|
||||
BITFIELD (CpuAVX2),
|
||||
BITFIELD (CpuAVX512F),
|
||||
BITFIELD (CpuAVX512CD),
|
||||
BITFIELD (CpuAVX512ER),
|
||||
BITFIELD (CpuAVX512PF),
|
||||
BITFIELD (CpuL1OM),
|
||||
BITFIELD (CpuK1OM),
|
||||
BITFIELD (CpuSSE4a),
|
||||
|
|
@ -389,6 +407,7 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (CpuPRFCHW),
|
||||
BITFIELD (CpuSMAP),
|
||||
BITFIELD (CpuSHA),
|
||||
BITFIELD (CpuVREX),
|
||||
BITFIELD (Cpu64),
|
||||
BITFIELD (CpuNo64),
|
||||
BITFIELD (CpuMPX),
|
||||
|
|
@ -449,6 +468,14 @@ static bitfield opcode_modifiers[] =
|
|||
BITFIELD (VecSIB),
|
||||
BITFIELD (SSE2AVX),
|
||||
BITFIELD (NoAVX),
|
||||
BITFIELD (EVex),
|
||||
BITFIELD (Masking),
|
||||
BITFIELD (VecESize),
|
||||
BITFIELD (Broadcast),
|
||||
BITFIELD (StaticRounding),
|
||||
BITFIELD (SAE),
|
||||
BITFIELD (Disp8MemShift),
|
||||
BITFIELD (NoDefMask),
|
||||
BITFIELD (OldGcc),
|
||||
BITFIELD (ATTMnemonic),
|
||||
BITFIELD (ATTSyntax),
|
||||
|
|
@ -465,6 +492,8 @@ static bitfield operand_types[] =
|
|||
BITFIELD (RegMMX),
|
||||
BITFIELD (RegXMM),
|
||||
BITFIELD (RegYMM),
|
||||
BITFIELD (RegZMM),
|
||||
BITFIELD (RegMask),
|
||||
BITFIELD (Imm1),
|
||||
BITFIELD (Imm8),
|
||||
BITFIELD (Imm8S),
|
||||
|
|
@ -499,10 +528,12 @@ static bitfield operand_types[] =
|
|||
BITFIELD (Tbyte),
|
||||
BITFIELD (Xmmword),
|
||||
BITFIELD (Ymmword),
|
||||
BITFIELD (Zmmword),
|
||||
BITFIELD (Unspecified),
|
||||
BITFIELD (Anysize),
|
||||
BITFIELD (Vec_Imm4),
|
||||
BITFIELD (RegBND),
|
||||
BITFIELD (Vec_Disp8),
|
||||
#ifdef OTUnused
|
||||
BITFIELD (OTUnused),
|
||||
#endif
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -94,6 +94,15 @@ enum
|
|||
CpuAVX,
|
||||
/* AVX2 support required */
|
||||
CpuAVX2,
|
||||
/* Intel AVX-512 Foundation Instructions support required */
|
||||
CpuAVX512F,
|
||||
/* Intel AVX-512 Conflict Detection Instructions support required */
|
||||
CpuAVX512CD,
|
||||
/* Intel AVX-512 Exponential and Reciprocal Instructions support
|
||||
required */
|
||||
CpuAVX512ER,
|
||||
/* Intel AVX-512 Prefetch Instructions support required */
|
||||
CpuAVX512PF,
|
||||
/* Intel L1OM support required */
|
||||
CpuL1OM,
|
||||
/* Intel K1OM support required */
|
||||
|
|
@ -158,6 +167,8 @@ enum
|
|||
CpuSMAP,
|
||||
/* SHA instructions required. */
|
||||
CpuSHA,
|
||||
/* VREX support required */
|
||||
CpuVREX,
|
||||
/* 64bit support required */
|
||||
Cpu64,
|
||||
/* Not supported in the 64bit mode */
|
||||
|
|
@ -212,6 +223,10 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpusse4_2:1;
|
||||
unsigned int cpuavx:1;
|
||||
unsigned int cpuavx2:1;
|
||||
unsigned int cpuavx512f:1;
|
||||
unsigned int cpuavx512cd:1;
|
||||
unsigned int cpuavx512er:1;
|
||||
unsigned int cpuavx512pf:1;
|
||||
unsigned int cpul1om:1;
|
||||
unsigned int cpuk1om:1;
|
||||
unsigned int cpuxsave:1;
|
||||
|
|
@ -244,6 +259,7 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpuprfchw:1;
|
||||
unsigned int cpusmap:1;
|
||||
unsigned int cpusha:1;
|
||||
unsigned int cpuvrex:1;
|
||||
unsigned int cpu64:1;
|
||||
unsigned int cpuno64:1;
|
||||
#ifdef CpuUnused
|
||||
|
|
@ -415,14 +431,67 @@ enum
|
|||
/* Instruction with vector SIB byte:
|
||||
1: 128bit vector register.
|
||||
2: 256bit vector register.
|
||||
3: 512bit vector register.
|
||||
*/
|
||||
#define VecSIB128 1
|
||||
#define VecSIB256 2
|
||||
#define VecSIB512 3
|
||||
VecSIB,
|
||||
/* SSE to AVX support required */
|
||||
SSE2AVX,
|
||||
/* No AVX equivalent */
|
||||
NoAVX,
|
||||
|
||||
/* insn has EVEX prefix:
|
||||
1: 512bit EVEX prefix.
|
||||
2: 128bit EVEX prefix.
|
||||
3: 256bit EVEX prefix.
|
||||
4: Length-ignored (LIG) EVEX prefix.
|
||||
*/
|
||||
#define EVEX512 1
|
||||
#define EVEX128 2
|
||||
#define EVEX256 3
|
||||
#define EVEXLIG 4
|
||||
EVex,
|
||||
|
||||
/* AVX512 masking support:
|
||||
1: Zeroing-masking.
|
||||
2: Merging-masking.
|
||||
3: Both zeroing and merging masking.
|
||||
*/
|
||||
#define ZEROING_MASKING 1
|
||||
#define MERGING_MASKING 2
|
||||
#define BOTH_MASKING 3
|
||||
Masking,
|
||||
|
||||
/* Input element size of vector insn:
|
||||
0: 32bit.
|
||||
1: 64bit.
|
||||
*/
|
||||
VecESize,
|
||||
|
||||
/* Broadcast factor.
|
||||
0: No broadcast.
|
||||
1: 1to16 broadcast.
|
||||
2: 1to8 broadcast.
|
||||
*/
|
||||
#define NO_BROADCAST 0
|
||||
#define BROADCAST_1TO16 1
|
||||
#define BROADCAST_1TO8 2
|
||||
Broadcast,
|
||||
|
||||
/* Static rounding control is supported. */
|
||||
StaticRounding,
|
||||
|
||||
/* Supress All Exceptions is supported. */
|
||||
SAE,
|
||||
|
||||
/* Copressed Disp8*N attribute. */
|
||||
Disp8MemShift,
|
||||
|
||||
/* Default mask isn't allowed. */
|
||||
NoDefMask,
|
||||
|
||||
/* Compatible with old (<= 2.8.1) versions of gcc */
|
||||
OldGcc,
|
||||
/* AT&T mnemonic. */
|
||||
|
|
@ -487,6 +556,14 @@ typedef struct i386_opcode_modifier
|
|||
unsigned int vecsib:2;
|
||||
unsigned int sse2avx:1;
|
||||
unsigned int noavx:1;
|
||||
unsigned int evex:3;
|
||||
unsigned int masking:2;
|
||||
unsigned int vecesize:1;
|
||||
unsigned int broadcast:3;
|
||||
unsigned int staticrounding:1;
|
||||
unsigned int sae:1;
|
||||
unsigned int disp8memshift:3;
|
||||
unsigned int nodefmask:1;
|
||||
unsigned int oldgcc:1;
|
||||
unsigned int attmnemonic:1;
|
||||
unsigned int attsyntax:1;
|
||||
|
|
@ -513,6 +590,10 @@ enum
|
|||
RegXMM,
|
||||
/* AVX registers */
|
||||
RegYMM,
|
||||
/* AVX512 registers */
|
||||
RegZMM,
|
||||
/* Vector Mask registers */
|
||||
RegMask,
|
||||
/* Control register */
|
||||
Control,
|
||||
/* Debug register */
|
||||
|
|
@ -592,6 +673,8 @@ enum
|
|||
Xmmword,
|
||||
/* YMMWORD memory. */
|
||||
Ymmword,
|
||||
/* ZMMWORD memory. */
|
||||
Zmmword,
|
||||
/* Unspecified memory size. */
|
||||
Unspecified,
|
||||
/* Any memory size. */
|
||||
|
|
@ -603,6 +686,9 @@ enum
|
|||
/* Bound register. */
|
||||
RegBND,
|
||||
|
||||
/* Vector 8bit displacement */
|
||||
Vec_Disp8,
|
||||
|
||||
/* The last bitfield in i386_operand_type. */
|
||||
OTMax
|
||||
};
|
||||
|
|
@ -628,6 +714,8 @@ typedef union i386_operand_type
|
|||
unsigned int regmmx:1;
|
||||
unsigned int regxmm:1;
|
||||
unsigned int regymm:1;
|
||||
unsigned int regzmm:1;
|
||||
unsigned int regmask:1;
|
||||
unsigned int control:1;
|
||||
unsigned int debug:1;
|
||||
unsigned int test:1;
|
||||
|
|
@ -662,10 +750,12 @@ typedef union i386_operand_type
|
|||
unsigned int tbyte:1;
|
||||
unsigned int xmmword:1;
|
||||
unsigned int ymmword:1;
|
||||
unsigned int zmmword:1;
|
||||
unsigned int unspecified:1;
|
||||
unsigned int anysize:1;
|
||||
unsigned int vec_imm4:1;
|
||||
unsigned int regbnd:1;
|
||||
unsigned int vec_disp8:1;
|
||||
#ifdef OTUnused
|
||||
unsigned int unused:(OTNumOfBits - OTUnused);
|
||||
#endif
|
||||
|
|
@ -727,6 +817,7 @@ typedef struct
|
|||
unsigned char reg_flags;
|
||||
#define RegRex 0x1 /* Extended register. */
|
||||
#define RegRex64 0x2 /* Extended 8 bit register. */
|
||||
#define RegVRex 0x4 /* Extended vector register. */
|
||||
unsigned char reg_num;
|
||||
#define RegRip ((unsigned char ) ~0)
|
||||
#define RegEip (RegRip - 1)
|
||||
|
|
|
|||
1209
opcodes/i386-opc.tbl
1209
opcodes/i386-opc.tbl
File diff suppressed because it is too large
Load Diff
|
|
@ -96,6 +96,15 @@ r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12
|
|||
r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13
|
||||
r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14
|
||||
r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15
|
||||
// Vector mask registers.
|
||||
k0, RegMask, 0, 0, 93, 118
|
||||
k1, RegMask, 0, 1, 94, 119
|
||||
k2, RegMask, 0, 2, 95, 120
|
||||
k3, RegMask, 0, 3, 96, 121
|
||||
k4, RegMask, 0, 4, 97, 122
|
||||
k5, RegMask, 0, 5, 98, 123
|
||||
k6, RegMask, 0, 6, 99, 124
|
||||
k7, RegMask, 0, 7, 100, 125
|
||||
// Segment registers.
|
||||
es, SReg2, 0, 0, 40, 50
|
||||
cs, SReg2, 0, 1, 41, 51
|
||||
|
|
@ -188,6 +197,22 @@ xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
|
|||
xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
|
||||
xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
|
||||
xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
|
||||
xmm16, RegXMM, RegVRex, 0, Dw2Inval, 67
|
||||
xmm17, RegXMM, RegVRex, 1, Dw2Inval, 68
|
||||
xmm18, RegXMM, RegVRex, 2, Dw2Inval, 69
|
||||
xmm19, RegXMM, RegVRex, 3, Dw2Inval, 70
|
||||
xmm20, RegXMM, RegVRex, 4, Dw2Inval, 71
|
||||
xmm21, RegXMM, RegVRex, 5, Dw2Inval, 72
|
||||
xmm22, RegXMM, RegVRex, 6, Dw2Inval, 73
|
||||
xmm23, RegXMM, RegVRex, 7, Dw2Inval, 74
|
||||
xmm24, RegXMM, RegVRex|RegRex, 0, Dw2Inval, 75
|
||||
xmm25, RegXMM, RegVRex|RegRex, 1, Dw2Inval, 76
|
||||
xmm26, RegXMM, RegVRex|RegRex, 2, Dw2Inval, 77
|
||||
xmm27, RegXMM, RegVRex|RegRex, 3, Dw2Inval, 78
|
||||
xmm28, RegXMM, RegVRex|RegRex, 4, Dw2Inval, 79
|
||||
xmm29, RegXMM, RegVRex|RegRex, 5, Dw2Inval, 80
|
||||
xmm30, RegXMM, RegVRex|RegRex, 6, Dw2Inval, 81
|
||||
xmm31, RegXMM, RegVRex|RegRex, 7, Dw2Inval, 82
|
||||
// AVX registers.
|
||||
ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval
|
||||
ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval
|
||||
|
|
@ -205,6 +230,55 @@ ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
|
|||
ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
ymm16, RegYMM, RegVRex, 0, Dw2Inval, Dw2Inval
|
||||
ymm17, RegYMM, RegVRex, 1, Dw2Inval, Dw2Inval
|
||||
ymm18, RegYMM, RegVRex, 2, Dw2Inval, Dw2Inval
|
||||
ymm19, RegYMM, RegVRex, 3, Dw2Inval, Dw2Inval
|
||||
ymm20, RegYMM, RegVRex, 4, Dw2Inval, Dw2Inval
|
||||
ymm21, RegYMM, RegVRex, 5, Dw2Inval, Dw2Inval
|
||||
ymm22, RegYMM, RegVRex, 6, Dw2Inval, Dw2Inval
|
||||
ymm23, RegYMM, RegVRex, 7, Dw2Inval, Dw2Inval
|
||||
ymm24, RegYMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
|
||||
ymm25, RegYMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
|
||||
ymm26, RegYMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
|
||||
ymm27, RegYMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
|
||||
ymm28, RegYMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
|
||||
ymm29, RegYMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
||||
ymm30, RegYMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
||||
ymm31, RegYMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
||||
// AVX512 registers.
|
||||
zmm0, RegZMM, 0, 0, Dw2Inval, Dw2Inval
|
||||
zmm1, RegZMM, 0, 1, Dw2Inval, Dw2Inval
|
||||
zmm2, RegZMM, 0, 2, Dw2Inval, Dw2Inval
|
||||
zmm3, RegZMM, 0, 3, Dw2Inval, Dw2Inval
|
||||
zmm4, RegZMM, 0, 4, Dw2Inval, Dw2Inval
|
||||
zmm5, RegZMM, 0, 5, Dw2Inval, Dw2Inval
|
||||
zmm6, RegZMM, 0, 6, Dw2Inval, Dw2Inval
|
||||
zmm7, RegZMM, 0, 7, Dw2Inval, Dw2Inval
|
||||
zmm8, RegZMM, RegRex, 0, Dw2Inval, Dw2Inval
|
||||
zmm9, RegZMM, RegRex, 1, Dw2Inval, Dw2Inval
|
||||
zmm10, RegZMM, RegRex, 2, Dw2Inval, Dw2Inval
|
||||
zmm11, RegZMM, RegRex, 3, Dw2Inval, Dw2Inval
|
||||
zmm12, RegZMM, RegRex, 4, Dw2Inval, Dw2Inval
|
||||
zmm13, RegZMM, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
zmm14, RegZMM, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
zmm15, RegZMM, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
zmm16, RegZMM, RegVRex, 0, Dw2Inval, Dw2Inval
|
||||
zmm17, RegZMM, RegVRex, 1, Dw2Inval, Dw2Inval
|
||||
zmm18, RegZMM, RegVRex, 2, Dw2Inval, Dw2Inval
|
||||
zmm19, RegZMM, RegVRex, 3, Dw2Inval, Dw2Inval
|
||||
zmm20, RegZMM, RegVRex, 4, Dw2Inval, Dw2Inval
|
||||
zmm21, RegZMM, RegVRex, 5, Dw2Inval, Dw2Inval
|
||||
zmm22, RegZMM, RegVRex, 6, Dw2Inval, Dw2Inval
|
||||
zmm23, RegZMM, RegVRex, 7, Dw2Inval, Dw2Inval
|
||||
zmm24, RegZMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
|
||||
zmm25, RegZMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
|
||||
zmm26, RegZMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
|
||||
zmm27, RegZMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
|
||||
zmm28, RegZMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
|
||||
zmm29, RegZMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
||||
zmm30, RegZMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
||||
zmm31, RegZMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
||||
// Bound registers for MPX
|
||||
bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
|
||||
bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
|
||||
|
|
|
|||
51874
opcodes/i386-tbl.h
51874
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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Reference in New Issue