[AArch64] Recognize STR instruction in prologue
This patch teaches GDB AArch64 backend to recognize STR instructions in prologue, like 'str x19, [sp, #-48]!' or 'str w0, [sp, #44]'. The unit test is added too. gdb: 2016-12-02 Yao Qi <yao.qi@linaro.org> Pedro Alves <palves@redhat.com> * aarch64-tdep.c (aarch64_analyze_prologue): Recognize STR instruction. (aarch64_analyze_prologue_test): More tests.
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@ -1,3 +1,10 @@
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2016-12-02 Yao Qi <yao.qi@linaro.org>
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Pedro Alves <palves@redhat.com>
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* aarch64-tdep.c (aarch64_analyze_prologue): Recognize STR
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instruction.
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(aarch64_analyze_prologue_test): More tests.
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2016-12-02 Yao Qi <yao.qi@linaro.org>
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Pedro Alves <palves@redhat.com>
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@ -395,6 +395,35 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
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regs[rn] = pv_add_constant (regs[rn], imm);
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}
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else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
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|| (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
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&& (inst.opcode->op == OP_STR_POS
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|| inst.opcode->op == OP_STRF_POS)))
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&& inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
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&& strcmp ("str", inst.opcode->name) == 0)
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{
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/* STR (immediate) */
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unsigned int rt = inst.operands[0].reg.regno;
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int32_t imm = inst.operands[1].addr.offset.imm;
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unsigned int rn = inst.operands[1].addr.base_regno;
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bool is64
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= (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
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gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
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|| inst.operands[0].type == AARCH64_OPND_Ft);
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if (inst.operands[0].type == AARCH64_OPND_Ft)
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{
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/* Only bottom 64-bit of each V register (D register) need
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to be preserved. */
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gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
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rt += AARCH64_X_REGISTER_COUNT;
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}
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pv_area_store (stack, pv_add_constant (regs[rn], imm),
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is64 ? 8 : 4, regs[rt]);
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if (inst.operands[1].addr.writeback)
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regs[rn] = pv_add_constant (regs[rn], imm);
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}
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else if (inst.opcode->iclass == testbranch)
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{
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/* Stop analysis on branch. */
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@ -545,6 +574,52 @@ aarch64_analyze_prologue_test (void)
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== -1);
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}
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}
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/* Test a prologue in which STR is used and frame pointer is not
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used. */
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{
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struct aarch64_prologue_cache cache;
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cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
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static const uint32_t insns[] = {
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0xf81d0ff3, /* str x19, [sp, #-48]! */
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0xb9002fe0, /* str w0, [sp, #44] */
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0xf90013e1, /* str x1, [sp, #32]*/
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0xfd000fe0, /* str d0, [sp, #24] */
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0xaa0203f3, /* mov x19, x2 */
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0xf94013e0, /* ldr x0, [sp, #32] */
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};
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instruction_reader_test reader (insns);
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CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
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SELF_CHECK (end == 4 * 5);
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SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
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SELF_CHECK (cache.framesize == 48);
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for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
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{
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if (i == 1)
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SELF_CHECK (cache.saved_regs[i].addr == -16);
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else if (i == 19)
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SELF_CHECK (cache.saved_regs[i].addr == -48);
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else
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SELF_CHECK (cache.saved_regs[i].addr == -1);
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}
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for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
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{
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int regnum = gdbarch_num_regs (gdbarch);
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if (i == 0)
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SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
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== -24);
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else
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SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
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== -1);
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}
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}
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}
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} // namespace selftests
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#endif /* GDB_SELF_TEST */
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