Improve MIPS32 support
This commit is contained in:
Nick Clifton
parent
0c92ba5f58
commit
4372b67322
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@ -4,6 +4,15 @@
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don't accept as constant the difference between the
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addresses of symbols in two different sections.
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* config/tc-mips.c (macro_build): Add new 'U' and 'J' operand
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specifiers.
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(validate_mips_insn): Likewise. Also, update 'B' operand
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specifier to use OP_*_CODE20 constants and delete 'm' operand
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specifier.
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(mips_ip): Remove 'm' operand specifier, add 'U' and 'J'
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operand specifiers. Change warning generated by 'B' operand
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specifier to reflect its new multi-purpose usage.
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2000-12-01 Joel Sherrill <joel@OARcorp.com>
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* configure.in (arm-*-rtems*, a29k-*rtems*, h8300-*-rtems*):
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@ -2597,6 +2597,15 @@ macro_build (place, counter, ep, name, fmt, va_alist)
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insn.insn_opcode |= va_arg (args, int) << 11;
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continue;
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case 'U':
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{
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int tmp = va_arg (args, int);
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insn.insn_opcode |= tmp << 16;
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insn.insn_opcode |= tmp << 11;
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continue;
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}
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case 'V':
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case 'S':
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insn.insn_opcode |= va_arg (args, int) << 11;
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@ -2617,6 +2626,10 @@ macro_build (place, counter, ep, name, fmt, va_alist)
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insn.insn_opcode |= va_arg (args, int) << 6;
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continue;
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case 'J':
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insn.insn_opcode |= va_arg (args, int) << 6;
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continue;
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case 'q':
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insn.insn_opcode |= va_arg (args, int) << 6;
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continue;
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@ -6976,7 +6989,7 @@ validate_mips_insn (opc)
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case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
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case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
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case 'A': break;
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case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break;
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case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
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case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
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case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
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case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
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@ -6984,6 +6997,7 @@ validate_mips_insn (opc)
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case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
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case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
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case 'I': break;
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case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
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case 'L': break;
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case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
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case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
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@ -7002,7 +7016,6 @@ validate_mips_insn (opc)
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case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
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case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
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case 'l': break;
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case 'm': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
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case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
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case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
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case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
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@ -7015,6 +7028,8 @@ validate_mips_insn (opc)
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case 'x': break;
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case 'z': break;
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case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
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case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
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USE_BITS (OP_MASK_RT, OP_SH_RT); break;
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default:
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as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
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c, opc->name, opc->args);
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@ -7268,29 +7283,11 @@ mips_ip (str, ip)
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s = expr_end;
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continue;
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case 'm': /* Full 20 bit break code. */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned) imm_expr.X_add_number > 0xfffff)
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{
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as_warn (_("Illegal break code (%ld)"),
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(long) imm_expr.X_add_number);
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imm_expr.X_add_number &= 0xfffff;
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}
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ip->insn_opcode |= imm_expr.X_add_number << 6;
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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case 'B': /* syscall code */
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case 'B': /* 20-bit syscall/break code. */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned) imm_expr.X_add_number > 0xfffff)
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as_warn (_("Illegal syscall code (%ld)"),
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as_warn (_("Illegal 20-bit code (%ld)"),
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(long) imm_expr.X_add_number);
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ip->insn_opcode |= imm_expr.X_add_number << 6;
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imm_expr.X_op = O_absent;
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@ -7311,6 +7308,17 @@ mips_ip (str, ip)
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s = expr_end;
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continue;
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case 'J': /* 19-bit wait code. */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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if ((unsigned) imm_expr.X_add_number > 0x7ffff)
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as_warn (_("Illegal 19-bit code (%ld)"),
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(long) imm_expr.X_add_number);
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ip->insn_opcode |= imm_expr.X_add_number << 6;
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imm_expr.X_op = O_absent;
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s = expr_end;
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continue;
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case 'P': /* Performance register */
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my_getExpression (&imm_expr, s);
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check_absolute_expr (ip, &imm_expr);
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@ -7336,6 +7344,7 @@ mips_ip (str, ip)
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case 'G': /* coprocessor destination register */
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case 'x': /* ignore register name */
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case 'z': /* must be zero register */
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case 'U': /* destination register (clo/clz). */
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s_reset = s;
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if (s[0] == '$')
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{
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@ -7450,6 +7459,10 @@ mips_ip (str, ip)
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case 'G':
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ip->insn_opcode |= regno << 11;
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break;
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case 'U':
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ip->insn_opcode |= regno << 11;
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ip->insn_opcode |= regno << 16;
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break;
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case 'w':
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case 't':
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case 'E':
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@ -1,3 +1,13 @@
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2000-12-01 Chris Demetriou <cgd@sibyte.com>
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mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.
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(OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old
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OP_*_SYSCALL definitions.
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(OP_SH_CODE19, OP_MASK_CODE19): Define, for use as
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19 bit wait codes.
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(MIPS operand specifier comments): Remove 'm', add 'U' and
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'J', and update the meaning of 'B' so that it's more general.
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2000-10-20 Jakub Jelinek <jakub@redhat.com>
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* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
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@ -48,9 +48,11 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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breakpoint instruction are not defined; Kane says the breakpoint
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code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
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only use ten bits). An optional two-operand form of break/sdbbp
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allows the lower ten bits to be set too.
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allows the lower ten bits to be set too, and MIPS32 and later
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architectures allow 20 bits to be set with a signal operand
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(using CODE20).
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The syscall instruction uses SYSCALL.
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The syscall instruction uses CODE20.
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The general coprocessor instructions use COPZ. */
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@ -82,8 +84,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define OP_SH_PREFX 11
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#define OP_MASK_CCC 0x7
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#define OP_SH_CCC 8
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#define OP_MASK_SYSCALL 0xfffff
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#define OP_SH_SYSCALL 6
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#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
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#define OP_SH_CODE20 6
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#define OP_MASK_SHAMT 0x1f
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#define OP_SH_SHAMT 6
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#define OP_MASK_FD 0x1f
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@ -100,17 +102,17 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define OP_SH_FUNCT 0
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#define OP_MASK_SPEC 0x3f
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#define OP_SH_SPEC 0
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#define OP_SH_LOCC 8 /* FP condition code */
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#define OP_SH_HICC 18 /* FP condition code */
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#define OP_SH_LOCC 8 /* FP condition code. */
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#define OP_SH_HICC 18 /* FP condition code. */
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#define OP_MASK_CC 0x7
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#define OP_SH_COP1NORM 25 /* Normal COP1 encoding */
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#define OP_MASK_COP1NORM 0x1 /* a single bit */
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#define OP_SH_COP1SPEC 21 /* COP1 encodings */
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#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
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#define OP_MASK_COP1NORM 0x1 /* a single bit. */
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#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
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#define OP_MASK_COP1SPEC 0xf
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#define OP_MASK_COP1SCLR 0x4
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#define OP_MASK_COP1CMP 0x3
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#define OP_SH_COP1CMP 4
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#define OP_SH_FORMAT 21 /* FP short format field */
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#define OP_SH_FORMAT 21 /* FP short format field. */
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#define OP_MASK_FORMAT 0x7
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#define OP_SH_TRUE 16
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#define OP_MASK_TRUE 0x1
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@ -120,16 +122,17 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define OP_MASK_UNSIGNED 0x1
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#define OP_SH_HINT 16
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#define OP_MASK_HINT 0x1f
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#define OP_SH_MMI 0 /* Multimedia (parallel) op */
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#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
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#define OP_MASK_MMI 0x3f
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#define OP_SH_MMISUB 6
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#define OP_MASK_MMISUB 0x1f
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#define OP_MASK_PERFREG 0x1f /* Performance monitoring */
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#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
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#define OP_SH_PERFREG 1
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#define OP_SH_SEL 0 /* Coprocessor select field */
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#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
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#define OP_SH_CODE20 6 /* 20 bit breakpoint code */
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#define OP_MASK_CODE20 0xfffff
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#define OP_SH_SEL 0 /* Coprocessor select field. */
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#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
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#define OP_SH_CODE19 6 /* 19 bit wait code. */
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#define OP_MASK_CODE19 0x7ffff
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/* This structure holds information for a particular instruction. */
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@ -176,7 +179,6 @@ struct mips_opcode
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"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
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"j" 16 bit signed immediate (OP_*_DELTA)
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"k" 5 bit cache opcode in target register position (OP_*_CACHE)
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"m" 20 bit breakpoint code (OP_*_CODE20)
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"o" 16 bit signed offset (OP_*_DELTA)
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"p" 16 bit PC relative branch target address (OP_*_DELTA)
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"q" 10 bit extra breakpoint code (OP_*_CODE2)
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@ -186,8 +188,11 @@ struct mips_opcode
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"u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
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"v" 5 bit same register used as both source and destination (OP_*_RS)
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"w" 5 bit same register used as both target and destination (OP_*_RT)
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"U" 5 bit same destination register in both OP_*_RD and OP_*_RT
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(used by clo and clz)
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"C" 25 bit coprocessor function code (OP_*_COPZ)
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"B" 20 bit syscall function code (OP_*_SYSCALL)
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"B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
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"J" 19 bit wait function code (OP_*_CODE19)
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"x" accept and ignore register name
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"z" must be zero register
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@ -221,8 +226,8 @@ struct mips_opcode
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Characters used so far, for quick reference when adding more:
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"<>(),"
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"ABCDEFGHILMNPSTRVW"
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"abcdfhijklmopqrstuvwxz"
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"ABCDEFGHIJLMNPRSTUVW"
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"abcdfhijklopqrstuvwxz"
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*/
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/* These are the bits which may be set in the pinfo field of an
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@ -1,3 +1,17 @@
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2000-12-01 Chris Demetriou <cgd@sibyte.com>
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mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument
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specifiers. Update 'B' for new constant names, and remove
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'm'.
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mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop"
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near the top of the array, so they are disassembled properly.
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Enable "ssnop" for MIPS32. Add "break" variant with 20 bit
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code for MIPS32. Update "clo" and "clz" to use 'U' operand
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specifier. Add 'H' format specifier variants for "mfc1,"
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"mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update
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MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32
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"wait" variant which uses 'J' operand specifier.
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2000-11-28 Hans-Peter Nilsson <hp@bitrange.com>
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* sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned.
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@ -157,6 +157,30 @@ print_insn_arg (d, l, pc, info)
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reg_names[(l >> OP_SH_RD) & OP_MASK_RD]);
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break;
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case 'U':
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{
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/* First check for both rd and rt being equal. */
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int reg = (l >> OP_SH_RD) & OP_MASK_RD;
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if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
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(*info->fprintf_func) (info->stream, "$%s",
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reg_names[reg]);
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else
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{
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/* If one is zero use the other. */
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if (reg == 0)
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(*info->fprintf_func) (info->stream, "$%s",
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reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
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else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
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(*info->fprintf_func) (info->stream, "$%s",
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reg_names[reg]);
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else /* Bogus, result depends on processor. */
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(*info->fprintf_func) (info->stream, "$%s or $%s",
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reg_names[reg],
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reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
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}
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}
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break;
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case 'z':
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(*info->fprintf_func) (info->stream, "$%s", reg_names[0]);
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break;
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@ -171,17 +195,11 @@ print_insn_arg (d, l, pc, info)
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(l >> OP_SH_CODE) & OP_MASK_CODE);
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break;
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case 'q':
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_CODE2) & OP_MASK_CODE2);
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break;
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case 'm':
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_CODE20) & OP_MASK_CODE20);
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break;
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case 'C':
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_COPZ) & OP_MASK_COPZ);
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@ -189,7 +207,12 @@ print_insn_arg (d, l, pc, info)
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case 'B':
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_SYSCALL) & OP_MASK_SYSCALL);
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(l >> OP_SH_CODE20) & OP_MASK_CODE20);
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break;
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case 'J':
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(*info->fprintf_func) (info->stream, "0x%x",
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(l >> OP_SH_CODE19) & OP_MASK_CODE19);
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break;
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case 'S':
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@ -198,7 +221,6 @@ print_insn_arg (d, l, pc, info)
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(l >> OP_SH_FS) & OP_MASK_FS);
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break;
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case 'T':
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case 'W':
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(*info->fprintf_func) (info->stream, "$f%d",
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@ -107,12 +107,15 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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Many instructions are short hand for other instructions (i.e., The
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jal <register> instruction is short for jalr <register>). */
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const struct mips_opcode mips_builtin_opcodes[] = {
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const struct mips_opcode mips_builtin_opcodes[] =
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{
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/* These instructions appear first so that the disassembler will find
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them first. The assemblers uses a hash table based on the
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instruction name anyhow. */
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/* name, args, match, mask, pinfo, membership */
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{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
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{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|P4},
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{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
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{"ssnop", "", 0x00000040, 0xffffffff, 0, M1|P4 },
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{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
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{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
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{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
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@ -220,6 +223,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
|
||||
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 },
|
||||
{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 },
|
||||
{"break", "B", 0x0000000d, 0xfc00003f, TRAP, P4 },
|
||||
{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 },
|
||||
{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 },
|
||||
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
|
|
@ -328,8 +332,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {
|
|||
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
|
||||
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
|
||||
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
|
||||
{"clo", "d,s", 0x70000021, 0xfc1f07ff, WR_d|RD_s, P4 },
|
||||
{"clz", "d,s", 0x70000020, 0xfc1f07ff, WR_d|RD_s, P4 },
|
||||
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|RD_s, P4 },
|
||||
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|RD_s, P4 },
|
||||
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
|
||||
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
|
||||
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
|
||||
|
|
@ -545,8 +549,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {
|
|||
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, P4 },
|
||||
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
|
||||
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
|
||||
{"mfc1", "t,G,H", 0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, P4},
|
||||
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
|
||||
{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, P4 },
|
||||
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
|
||||
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, P4 },
|
||||
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
|
||||
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
|
||||
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
|
||||
|
|
@ -580,8 +587,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {
|
|||
{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, P4 },
|
||||
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
|
||||
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
|
||||
{"mtc1", "t,G,H", 0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S, P4 },
|
||||
{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
|
||||
{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, P4 },
|
||||
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
|
||||
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, P4 },
|
||||
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
|
||||
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
|
||||
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
|
||||
|
|
@ -620,7 +630,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
|
|||
{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
|
||||
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
|
||||
|
||||
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|P4 },
|
||||
/* pref is at the start of the table. */
|
||||
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
|
||||
|
||||
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
|
||||
|
|
@ -657,7 +667,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
|
|||
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|M1 },
|
||||
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1 },
|
||||
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1 },
|
||||
{"sdbbp", "m", 0x7000003f, 0xfc00003f, TRAP, P4 },
|
||||
{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, P4 },
|
||||
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
|
||||
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
|
||||
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
|
||||
|
|
@ -711,7 +721,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
|
|||
{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
|
||||
{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */
|
||||
{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
|
||||
{"ssnop", "", 0x00000040, 0xffffffff, 0, M1 },
|
||||
/* ssnop is at the start of the table. */
|
||||
{"standby", "", 0x42000021, 0xffffffff, 0, V1 },
|
||||
{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
|
||||
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 },
|
||||
|
|
@ -810,6 +820,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
|
|||
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
|
||||
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
|
||||
{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|M1|P4 },
|
||||
{"wait", "J", 0x42000020, 0xfe00003f, TRAP, P4 },
|
||||
{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
|
||||
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
|
||||
/* No hazard protection on coprocessor instructions--they shouldn't
|
||||
|
|
|
|||
Loading…
Reference in New Issue