[binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This patch adds the BF instruction.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bf.
(do_t_branch_future): New.
(insns): New instruction for bf.
* testsuite/gas/arm/armv8_1-m-bf.d: New.
* testsuite/gas/arm/armv8_1-m-bf.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.l: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bf.s: New.
* testsuite/ld-arm/bf.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instructions for bf.
This commit is contained in:
Andre Vieira
parent
e5d6e09ee6
commit
4389b29a5a
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@ -1,3 +1,17 @@
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (T16_32_TAB): New entries for bf.
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(do_t_branch_future): New.
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(insns): New instruction for bf.
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* testsuite/gas/arm/armv8_1-m-bf.d: New.
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* testsuite/gas/arm/armv8_1-m-bf.s: New.
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* testsuite/gas/arm/armv8_1-m-bf-bad.s: New.
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* testsuite/gas/arm/armv8_1-m-bf-bad.l: New.
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* testsuite/gas/arm/armv8_1-m-bf-bad.d: New.
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* testsuite/gas/arm/armv8_1-m-bf-rel.d: New.
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* testsuite/gas/arm/armv8_1-m-bf-rel.s: New.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* config/tc-arm.c (md_pcrel_from_section): New switch case for
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@ -10505,6 +10505,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
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X(_asrs, 1000, fa50f000), \
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X(_b, e000, f000b000), \
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X(_bcond, d000, f0008000), \
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X(_bf, 0000, f040e001), \
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X(_bic, 4380, ea200000), \
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X(_bics, 4380, ea300000), \
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X(_cmn, 42c0, eb100f00), \
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@ -13320,6 +13321,51 @@ v8_1_branch_value_check (int val, int nbits, int is_signed)
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return SUCCESS;
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}
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/* For branches in Armv8.1-M Mainline. */
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static void
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do_t_branch_future (void)
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{
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unsigned long insn = inst.instruction;
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inst.instruction = THUMB_OP32 (inst.instruction);
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if (inst.operands[0].hasreloc == 0)
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{
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if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
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as_bad (BAD_BRANCH_OFF);
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inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
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}
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else
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{
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inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
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inst.relocs[0].pc_rel = 1;
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}
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switch (insn)
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{
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case T_MNEM_bf:
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if (inst.operands[1].hasreloc == 0)
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{
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int val = inst.operands[1].imm;
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if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
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as_bad (BAD_BRANCH_OFF);
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int immA = (val & 0x0001f000) >> 12;
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int immB = (val & 0x00000ffc) >> 2;
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int immC = (val & 0x00000002) >> 1;
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inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
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}
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else
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{
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inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
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inst.relocs[1].pc_rel = 1;
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}
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break;
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default: abort ();
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}
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}
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/* Neon instruction encoder helpers. */
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/* Encodings for the different types for various Neon opcodes. */
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@ -19538,6 +19584,11 @@ static struct asm_barrier_opt barrier_opt_names[] =
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{ mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
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NULL, do_##te }
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/* T_MNEM_xyz enumerator variants of ToC. */
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#define toC(mnem, top, nops, ops, te) \
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{ mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
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do_##te }
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/* Legacy mnemonics that always have conditional infix after the third
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character. */
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#define CL(mnem, op, nops, ops, ae) \
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@ -21623,6 +21674,11 @@ static const struct asm_opcode insns[] =
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#define THUMB_VARIANT & arm_ext_v8m_main
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ToC("vlldm", ec300a00, 1, (RRnpc), rn),
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ToC("vlstm", ec200a00, 1, (RRnpc), rn),
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/* Armv8.1-M Mainline instructions. */
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_v8_1m_main
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toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
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};
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#undef ARM_VARIANT
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#undef THUMB_VARIANT
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@ -21633,8 +21689,10 @@ static const struct asm_opcode insns[] =
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#undef cCE
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#undef cCL
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#undef C3E
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#undef C3
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#undef CE
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#undef CM
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#undef CL
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#undef UE
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#undef UF
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#undef UT
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@ -21650,6 +21708,9 @@ static const struct asm_opcode insns[] =
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#undef OPS5
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#undef OPS6
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#undef do_0
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#undef ToC
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#undef toC
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#undef ToU
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/* MD interface: bits in the object file. */
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@ -0,0 +1,4 @@
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#name: Invalid Armv8.1-M Mainline BF instructions
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#source: armv8_1-m-bf-bad.s
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#as: -march=armv8.1-m.main
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#error_output: armv8_1-m-bf-bad.l
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@ -0,0 +1,9 @@
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.*: Assembler messages:
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.*:6: Error: branch out of range or not a multiple of 2
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.*:7: Error: branch out of range or not a multiple of 2
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.*:8: Error: branch out of range or not a multiple of 2
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.*:9: Error: branch out of range or not a multiple of 2
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.*:11: Error: branch out of range or not a multiple of 2
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.*:12: Error: branch out of range or not a multiple of 2
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.*:13: Error: branch out of range or not a multiple of 2
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.*:14: Error: branch out of range or not a multiple of 2
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@ -0,0 +1,14 @@
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.syntax unified
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.text
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.thumb
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foo:
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# OP0 : Unsigned, 5-bit, even
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bf 0, 36
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bf -2, 36
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bf 3, 36
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bf 32, 36
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# OP1 : signed, 17-bit, even
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bf 2, -5
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bf 2, 5
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bf 2, 65536
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bf 2, -65538
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@ -0,0 +1,10 @@
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#name: Valid Armv8.1-M Mainline BF instruction with relocation
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#as: -march=armv8.1-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn
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#skip: *-*-pe *-wince-*
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f0df e7ff bf 2, 00000000 <.target>
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0: R_ARM_THM_BF16 .target
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@ -0,0 +1,5 @@
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.syntax unified
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.text
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.thumb
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foo:
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bf 2, .target
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@ -0,0 +1,13 @@
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#name: Valid Armv8.1-M Mainline BF instruction
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#as: -march=armv8.1-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a <foo\+0xa>
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0[0-9a-f]+ <[^>]+> 4609 mov r1, r1
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0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 0000000c <foo\+0xc>
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0[0-9a-f]+ <[^>]+> 460a mov r2, r1
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0[0-9a-f]+ <[^>]+> 4613 mov r3, r2
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0[0-9a-f]+ <[^>]+> 4614 mov r4, r2
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@ -0,0 +1,12 @@
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.syntax unified
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.text
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.thumb
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foo:
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bf 2, 6
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mov r1, r1
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bf .LBranch, .LB2
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mov r2, r1
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.LB2:
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mov r3, r2
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.LBranch:
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mov r4, r2
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@ -1,3 +1,9 @@
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* testsuite/ld-arm/bf.s: New.
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* testsuite/ld-arm/bf.d: New.
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* testsuite/ld-arm/arm-elf.exp: Add above test.
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* testsuite/ld-arm/attr-merge-13.attr: New test.
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@ -667,6 +667,10 @@ set armeabitests_nonacl {
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{{objdump -d armv4-bx.d}}
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"armv4-bx"}
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{"Armv8.1-M Mainline BF" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bf.s}
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{{objdump -dr bf.d}}
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"bf"}
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{"R_ARM_THM_JUMP24 Relocation veneers: Short 1"
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"--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000" ""
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"-march=armv7-a -mthumb"
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@ -0,0 +1,14 @@
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.*: file format elf32-.*arm
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Disassembly of section .text:
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00001000 <_start>:
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1000: f0df e7ff bf 2, 1001000 <bar>
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1000: R_ARM_THM_BF16 bar
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Disassembly of section .foo:
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01001000 <bar>:
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1001000: 4770 bx lr
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@ -0,0 +1,19 @@
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.global _start
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.syntax unified
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@ We will place the section .text at 0x1000.
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.text
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.thumb_func
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_start:
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bf 2, bar
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@ We will place the section .foo at 0x1001000.
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.section .foo, "xa"
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.thumb_func
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bar:
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bx lr
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@ -1,3 +1,7 @@
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (thumb32_opcodes): New instructions for bf.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
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@ -2746,6 +2746,11 @@ static const struct opcode16 thumb_opcodes[] =
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makes heavy use of special-case bit patterns. */
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static const struct opcode32 thumb32_opcodes[] =
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{
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/* Armv8.1-M Mainline instructions. */
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
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/* ARMv8-M and ARMv8-M Security Extensions instructions. */
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
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