* simops.c: Fix register references when computing Z and N bits
for lsr imm8,dn. Bug exposed by c-torture testing of the mn10300.
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@ -2154,7 +2154,7 @@ void OP_F2A0 (insn, extension)
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
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}
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}
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/* lsr dm, dn */
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/* lsr imm8, dn */
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void OP_F8C400 (insn, extension)
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void OP_F8C400 (insn, extension)
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unsigned long insn, extension;
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unsigned long insn, extension;
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{
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{
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@ -2162,8 +2162,8 @@ void OP_F8C400 (insn, extension)
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c = State.regs[REG_D0 + REG0_8 (insn)] & 1;
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c = State.regs[REG_D0 + REG0_8 (insn)] & 1;
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State.regs[REG_D0 + REG0_8 (insn)] >>= (insn & 0xff);
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State.regs[REG_D0 + REG0_8 (insn)] >>= (insn & 0xff);
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z = (State.regs[REG_D0 + (REG0 (insn) >> 8)] == 0);
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z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
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n = (State.regs[REG_D0 + (REG0 (insn) >> 8)] & 0x80000000) != 0;
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n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
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PSW &= ~(PSW_Z | PSW_N | PSW_C);
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PSW &= ~(PSW_Z | PSW_N | PSW_C);
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
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PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
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}
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}
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