[PATCH 33/57][Arm][GAS] Add support for MVE instructions: vshr, vrshr, vsli, vsri, vrev16, vrev32 and vrev64
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_sli): Accept MVE variants. (do_neon_sri): Likewise. (do_neon_rev): Likewise. (do_neon_rshift_round_imm): Likewise. (insns): Likewise. * testsuite/gas/arm/mve-vrev-bad.d: New test. * testsuite/gas/arm/mve-vrev-bad.l: New test. * testsuite/gas/arm/mve-vrev-bad.s: New test. * testsuite/gas/arm/mve-vshr-bad.d: New test. * testsuite/gas/arm/mve-vshr-bad.l: New test. * testsuite/gas/arm/mve-vshr-bad.s: New test. * testsuite/gas/arm/mve-vsli-bad.d: New test. * testsuite/gas/arm/mve-vsli-bad.l: New test. * testsuite/gas/arm/mve-vsli-bad.s: New test. * testsuite/gas/arm/mve-vsri-bad.d: New test. * testsuite/gas/arm/mve-vsri-bad.l: New test. * testsuite/gas/arm/mve-vsri-bad.s: New test.
This commit is contained in:
Andre Vieira
parent
a710b305c5
commit
4401c2414d
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@ -1,3 +1,23 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_neon_sli): Accept MVE variants.
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(do_neon_sri): Likewise.
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(do_neon_rev): Likewise.
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(do_neon_rshift_round_imm): Likewise.
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(insns): Likewise.
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* testsuite/gas/arm/mve-vrev-bad.d: New test.
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* testsuite/gas/arm/mve-vrev-bad.l: New test.
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* testsuite/gas/arm/mve-vrev-bad.s: New test.
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* testsuite/gas/arm/mve-vshr-bad.d: New test.
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* testsuite/gas/arm/mve-vshr-bad.l: New test.
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* testsuite/gas/arm/mve-vshr-bad.s: New test.
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* testsuite/gas/arm/mve-vsli-bad.d: New test.
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* testsuite/gas/arm/mve-vsli-bad.l: New test.
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* testsuite/gas/arm/mve-vsli-bad.s: New test.
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* testsuite/gas/arm/mve-vsri-bad.d: New test.
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* testsuite/gas/arm/mve-vsri-bad.l: New test.
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* testsuite/gas/arm/mve-vsri-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_vrint_1): Accept MVE variants.
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@ -17873,9 +17873,23 @@ do_neon_abs_neg (void)
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static void
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do_neon_sli (void)
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{
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enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
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struct neon_type_el et = neon_check_type (2, rs,
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N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
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if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
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return;
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enum neon_shape rs;
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struct neon_type_el et;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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{
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rs = neon_select_shape (NS_QQI, NS_NULL);
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et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
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}
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else
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{
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rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
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et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
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}
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int imm = inst.operands[2].imm;
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constraint (imm < 0 || (unsigned)imm >= et.size,
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_("immediate out of range for insert"));
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@ -17885,9 +17899,22 @@ do_neon_sli (void)
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static void
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do_neon_sri (void)
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{
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enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
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struct neon_type_el et = neon_check_type (2, rs,
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N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
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if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
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return;
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enum neon_shape rs;
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struct neon_type_el et;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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{
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rs = neon_select_shape (NS_QQI, NS_NULL);
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et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
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}
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else
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{
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rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
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et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
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}
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int imm = inst.operands[2].imm;
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constraint (imm < 1 || (unsigned)imm > et.size,
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_("immediate out of range for insert"));
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@ -19112,14 +19139,29 @@ do_neon_ext (void)
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static void
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do_neon_rev (void)
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{
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enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
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if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
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return;
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enum neon_shape rs;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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rs = neon_select_shape (NS_QQ, NS_NULL);
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else
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rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
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struct neon_type_el et = neon_check_type (2, rs,
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N_EQK, N_8 | N_16 | N_32 | N_KEY);
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unsigned op = (inst.instruction >> 7) & 3;
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/* N (width of reversed regions) is encoded as part of the bitmask. We
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extract it here to check the elements to be reversed are smaller.
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Otherwise we'd get a reserved instruction. */
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unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) && elsize == 64
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&& inst.operands[0].reg == inst.operands[1].reg)
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as_tsktsk (_("Warning: 64-bit element size and same destination and source"
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" operands makes instruction UNPREDICTABLE"));
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gas_assert (elsize != 0);
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constraint (et.size >= elsize,
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_("elements must be smaller than reversal region"));
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@ -19663,8 +19705,22 @@ do_mve_movl (void)
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static void
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do_neon_rshift_round_imm (void)
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{
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enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
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struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
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if (check_simd_pred_availability (0, NEON_CHECK_ARCH | NEON_CHECK_CC))
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return;
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enum neon_shape rs;
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struct neon_type_el et;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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{
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rs = neon_select_shape (NS_QQI, NS_NULL);
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et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
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}
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else
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{
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rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
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et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
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}
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int imm = inst.operands[2].imm;
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/* imm == 0 case is encoded as VMOV for V{R}SHR. */
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@ -24323,18 +24379,14 @@ static const struct asm_opcode insns[] =
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/* Data processing with two registers and a shift amount. */
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/* Right shifts, and variants with rounding.
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Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
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NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
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NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
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NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
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NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
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NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
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NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
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NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
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NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
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/* Shift and insert. Sizes accepted 8 16 32 64. */
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NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
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NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
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NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
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NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
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/* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
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NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
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@ -24385,11 +24437,8 @@ static const struct asm_opcode insns[] =
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/* Two registers, miscellaneous. */
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/* Reverse. Sizes 8 16 32 (must be < size in opcode). */
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NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
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NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
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NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
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NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
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NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
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NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
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/* Vector replicate. Sizes 8 16 32. */
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nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
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@ -25109,6 +25158,13 @@ static const struct asm_opcode insns[] =
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mnUF(vqrdmulh, _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
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MNUF(vqrshl, 0000510, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
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MNUF(vrshl, 0000500, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
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MNUF(vshr, 0800010, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
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MNUF(vrshr, 0800210, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
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MNUF(vsli, 1800510, 3, (RNDQMQ, oRNDQMQ, I63), neon_sli),
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MNUF(vsri, 1800410, 3, (RNDQMQ, oRNDQMQ, I64z), neon_sri),
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MNUF(vrev64, 1b00000, 2, (RNDQMQ, RNDQMQ), neon_rev),
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MNUF(vrev32, 1b00080, 2, (RNDQMQ, RNDQMQ), neon_rev),
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MNUF(vrev16, 1b00100, 2, (RNDQMQ, RNDQMQ), neon_rev),
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#undef ARM_VARIANT
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#define ARM_VARIANT & arm_ext_v8_3
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@ -0,0 +1,5 @@
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#name: bad MVE VREV16, VREV32 and VREV64 instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vrev-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,38 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: elements must be smaller than reversal region -- `vrev16.16 q0,q1'
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[^:]*:11: Error: elements must be smaller than reversal region -- `vrev32.32 q0,q1'
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[^:]*:12: Error: elements must be smaller than reversal region -- `vrev64.64 q0,q1'
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[^:]*:13: Warning: 64-bit element size and same destination and source operands makes instruction UNPREDICTABLE
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Error: syntax error -- `vrev16eq.8 q0,q1'
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[^:]*:19: Error: syntax error -- `vrev16eq.8 q0,q1'
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[^:]*:21: Error: syntax error -- `vrev16eq.8 q0,q1'
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[^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrev16t.8 q0,q1'
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[^:]*:24: Error: instruction missing MVE vector predication code -- `vrev16.8 q0,q1'
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[^:]*:26: Error: syntax error -- `vrev32eq.8 q0,q1'
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[^:]*:27: Error: syntax error -- `vrev32eq.8 q0,q1'
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[^:]*:29: Error: syntax error -- `vrev32eq.8 q0,q1'
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[^:]*:30: Error: vector predicated instruction should be in VPT/VPST block -- `vrev32t.8 q0,q1'
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[^:]*:32: Error: instruction missing MVE vector predication code -- `vrev32.8 q0,q1'
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[^:]*:34: Error: syntax error -- `vrev64eq.8 q0,q1'
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[^:]*:35: Error: syntax error -- `vrev64eq.8 q0,q1'
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[^:]*:37: Error: syntax error -- `vrev64eq.8 q0,q1'
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[^:]*:38: Error: vector predicated instruction should be in VPT/VPST block -- `vrev64t.8 q0,q1'
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[^:]*:40: Error: instruction missing MVE vector predication code -- `vrev64.8 q0,q1'
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@ -0,0 +1,40 @@
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.macro cond op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().8 q0, q1
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.endr
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.endm
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.syntax unified
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.thumb
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vrev16.16 q0, q1
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vrev32.32 q0, q1
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vrev64.64 q0, q1
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vrev64.8 q0, q0
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cond vrev16
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cond vrev32
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cond vrev64
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it eq
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vrev16eq.8 q0, q1
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vrev16eq.8 q0, q1
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vpst
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vrev16eq.8 q0, q1
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vrev16t.8 q0, q1
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vpst
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vrev16.8 q0, q1
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it eq
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vrev32eq.8 q0, q1
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vrev32eq.8 q0, q1
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vpst
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vrev32eq.8 q0, q1
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vrev32t.8 q0, q1
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vpst
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vrev32.8 q0, q1
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it eq
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vrev64eq.8 q0, q1
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vrev64eq.8 q0, q1
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vpst
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vrev64eq.8 q0, q1
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vrev64t.8 q0, q1
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vpst
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vrev64.8 q0, q1
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@ -0,0 +1,5 @@
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#name: bad MVE VSHR and VRSHR instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vshr-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,33 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vshr.s64 q0,q1,#1'
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[^:]*:11: Error: bad type in SIMD instruction -- `vshr.i32 q0,q1,#1'
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[^:]*:12: Error: bad type in SIMD instruction -- `vrshr.u64 q0,q1,#1'
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[^:]*:13: Error: bad type in SIMD instruction -- `vrshr.i32 q0,q1,#1'
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[^:]*:14: Error: immediate out of range for shift -- `vshr.s8 q0,q1,#9'
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[^:]*:15: Error: immediate out of range for shift -- `vshr.u8 q0,q1,#9'
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[^:]*:16: Error: immediate out of range for shift -- `vshr.s16 q0,q1,#17'
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[^:]*:17: Error: immediate out of range for shift -- `vshr.u16 q0,q1,#17'
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[^:]*:18: Error: immediate out of range for shift -- `vshr.s32 q0,q1,#33'
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[^:]*:19: Error: immediate out of range for shift -- `vshr.u32 q0,q1,#33'
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:23: Error: syntax error -- `vshreq.s32 q0,q1,#1'
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[^:]*:24: Error: syntax error -- `vshreq.s32 q0,q1,#1'
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[^:]*:26: Error: syntax error -- `vshreq.s32 q0,q1,#1'
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[^:]*:27: Error: vector predicated instruction should be in VPT/VPST block -- `vshrt.s32 q0,q1,#1'
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[^:]*:29: Error: instruction missing MVE vector predication code -- `vshr.s32 q0,q1,#1'
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[^:]*:31: Error: syntax error -- `vrshreq.s32 q0,q1,#1'
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[^:]*:32: Error: syntax error -- `vrshreq.s32 q0,q1,#1'
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[^:]*:34: Error: syntax error -- `vrshreq.s32 q0,q1,#1'
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[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vrshrt.s32 q0,q1,#1'
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[^:]*:37: Error: instruction missing MVE vector predication code -- `vrshr.s32 q0,q1,#1'
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@ -0,0 +1,37 @@
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.macro cond op
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\().s32 q0, q1, #1
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vshr.s64 q0, q1, #1
|
||||
vshr.i32 q0, q1, #1
|
||||
vrshr.u64 q0, q1, #1
|
||||
vrshr.i32 q0, q1, #1
|
||||
vshr.s8 q0, q1, #9
|
||||
vshr.u8 q0, q1, #9
|
||||
vshr.s16 q0, q1, #17
|
||||
vshr.u16 q0, q1, #17
|
||||
vshr.s32 q0, q1, #33
|
||||
vshr.u32 q0, q1, #33
|
||||
cond vshr
|
||||
cond vrshr
|
||||
it eq
|
||||
vshreq.s32 q0, q1, #1
|
||||
vshreq.s32 q0, q1, #1
|
||||
vpst
|
||||
vshreq.s32 q0, q1, #1
|
||||
vshrt.s32 q0, q1, #1
|
||||
vpst
|
||||
vshr.s32 q0, q1, #1
|
||||
it eq
|
||||
vrshreq.s32 q0, q1, #1
|
||||
vrshreq.s32 q0, q1, #1
|
||||
vpst
|
||||
vrshreq.s32 q0, q1, #1
|
||||
vrshrt.s32 q0, q1, #1
|
||||
vpst
|
||||
vrshr.s32 q0, q1, #1
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#name: bad MVE VSLI instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vsli-bad.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:10: Error: bad type in SIMD instruction -- `vsli.64 q0,q1,#1'
|
||||
[^:]*:11: Error: immediate out of range for insert -- `vsli.8 q0,q1,#8'
|
||||
[^:]*:12: Error: immediate out of range for insert -- `vsli.16 q0,q1,#16'
|
||||
[^:]*:13: Error: immediate out of range for insert -- `vsli.32 q0,q1,#32'
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Error: syntax error -- `vslieq.8 q0,q1,#2'
|
||||
[^:]*:17: Error: syntax error -- `vslieq.8 q0,q1,#2'
|
||||
[^:]*:19: Error: syntax error -- `vslieq.8 q0,q1,#2'
|
||||
[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vslit.8 q0,q1,#2'
|
||||
[^:]*:22: Error: instruction missing MVE vector predication code -- `vsli.8 q0,q1,#2'
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
.macro cond
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
vsli.16 q0, q1, #4
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vsli.64 q0, q1, #1
|
||||
vsli.8 q0, q1, #8
|
||||
vsli.16 q0, q1, #16
|
||||
vsli.32 q0, q1, #32
|
||||
cond
|
||||
it eq
|
||||
vslieq.8 q0, q1, #2
|
||||
vslieq.8 q0, q1, #2
|
||||
vpst
|
||||
vslieq.8 q0, q1, #2
|
||||
vslit.8 q0, q1, #2
|
||||
vpst
|
||||
vsli.8 q0, q1, #2
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#name: bad MVE VSRI instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vsri-bad.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:10: Error: bad type in SIMD instruction -- `vsri.64 q0,q1,#1'
|
||||
[^:]*:11: Error: immediate out of range for insert -- `vsri.8 q0,q1,#0'
|
||||
[^:]*:12: Error: immediate out of range for insert -- `vsri.8 q0,q1,#9'
|
||||
[^:]*:13: Error: immediate out of range for insert -- `vsri.16 q0,q1,#0'
|
||||
[^:]*:14: Error: immediate out of range for insert -- `vsri.16 q0,q1,#17'
|
||||
[^:]*:15: Error: immediate out of range for insert -- `vsri.32 q0,q1,#0'
|
||||
[^:]*:16: Error: immediate out of range for insert -- `vsri.32 q0,q1,#33'
|
||||
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:19: Error: syntax error -- `vsrieq.8 q0,q1,#2'
|
||||
[^:]*:20: Error: syntax error -- `vsrieq.8 q0,q1,#2'
|
||||
[^:]*:22: Error: syntax error -- `vsrieq.8 q0,q1,#2'
|
||||
[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vsrit.8 q0,q1,#2'
|
||||
[^:]*:25: Error: instruction missing MVE vector predication code -- `vsri.8 q0,q1,#2'
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
.macro cond
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
vsri.16 q0, q1, #4
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vsri.64 q0, q1, #1
|
||||
vsri.8 q0, q1, #0
|
||||
vsri.8 q0, q1, #9
|
||||
vsri.16 q0, q1, #0
|
||||
vsri.16 q0, q1, #17
|
||||
vsri.32 q0, q1, #0
|
||||
vsri.32 q0, q1, #33
|
||||
cond
|
||||
it eq
|
||||
vsrieq.8 q0, q1, #2
|
||||
vsrieq.8 q0, q1, #2
|
||||
vpst
|
||||
vsrieq.8 q0, q1, #2
|
||||
vsrit.8 q0, q1, #2
|
||||
vpst
|
||||
vsri.8 q0, q1, #2
|
||||
|
||||
Loading…
Reference in New Issue