2002-03-16 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (M3D): Tweak comment. (mips_builtin_op): Add comment indicating that opcodes of the same name must be placed together in the table, and sort the "recip.fmt", "recip1.fmt", "recip2.fmt", "rsqrt.fmt", "rsqrt1.fmt", and "rsqrt2.fmt" opcodes by name.
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@ -1,3 +1,11 @@
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2002-03-16 Chris Demetriou <cgd@broadcom.com>
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* mips-opc.c (M3D): Tweak comment.
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(mips_builtin_op): Add comment indicating that opcodes of the
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same name must be placed together in the table, and sort
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the "recip.fmt", "recip1.fmt", "recip2.fmt", "rsqrt.fmt",
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"rsqrt1.fmt", and "rsqrt2.fmt" opcodes by name.
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2002-03-16 Nick Clifton <nickc@cambridge.redhat.com>
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* Makefile.am: Tidy up sh64 rules.
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@ -83,7 +83,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define I32 INSN_ISA32
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#define I64 INSN_ISA64
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/* MIPS-3D support. */
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/* MIPS64 MIPS-3D ASE support. */
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#define M3D INSN_MIPS3D
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#define P3 INSN_4650
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@ -109,6 +109,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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immediate operands must apear after the same instruction with
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registers.
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Because of the lookup algorithm used, entries with the same opcode
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name must be contiguous.
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Many instructions are short hand for other instructions (i.e., The
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jal <register> instruction is short for jalr <register>). */
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@ -715,14 +718,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
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{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 },
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{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 },
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{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, SB1 },
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{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 },
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{"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, M3D },
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{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, M3D },
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{"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, M3D },
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{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, M3D },
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{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
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{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
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{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
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{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
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{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
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{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 },
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{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 },
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@ -739,14 +742,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 },
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{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 },
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{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 },
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{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 },
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{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, SB1 },
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{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, M3D },
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{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, M3D },
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{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 },
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{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, M3D },
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{"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, M3D },
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{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, M3D },
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{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
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{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
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{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
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{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
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{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 },
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{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 },
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{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 },
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