[AArch64] Record instruction alignment for .inst directive
2015-05-06 Renlin Li <renlin.li@arm.com> gas/ * config/tc-aarch64.c (mapping_state): Recording alignment before exit. gas/testsuite/ * gas/aarch64/codealign_1.s: New. * gas/aarch64/codealign_1.d: New.
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2015-05-06 Renlin Li <renlin.li@arm.com>
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* config/tc-aarch64.c (mapping_state): Recording alignment before exit.
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2015-05-05 Renlin Li <renlin.li@arm.com>
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* config/tc-aarch64.c (aarch64_init_frag): Always generate mapping
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@ -1460,17 +1460,17 @@ mapping_state (enum mstate state)
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{
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enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
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if (mapstate == state)
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/* The mapping symbol has already been emitted.
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There is nothing else to do. */
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return;
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if (state == MAP_INSN)
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/* AArch64 instructions require 4-byte alignment. When emitting
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instructions into any section, record the appropriate section
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alignment. */
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record_alignment (now_seg, 2);
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if (mapstate == state)
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/* The mapping symbol has already been emitted.
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There is nothing else to do. */
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return;
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#define TRANSITION(from, to) (mapstate == (from) && state == (to))
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if (TRANSITION (MAP_UNDEFINED, MAP_DATA) && !subseg_text_p (now_seg))
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/* Emit MAP_DATA within executable section in order. Otherwise, it will be
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@ -1,3 +1,8 @@
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2015-05-06 Renlin Li <renlin.li@arm.com>
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* gas/aarch64/codealign_1.s: New.
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* gas/aarch64/codealign_1.d: New.
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2015-05-05 Renlin Li <renlin.li@arm.com>
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* gas/aarch64/mapping_5.d: New.
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#objdump: --section-headers
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# Minimum code alignment should be set.
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.*: +file format.*aarch64.*
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 \.text .* .* .* .* 2\*\*2
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.*CODE.*
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1 \.data .* .* .* .* 2\*\*0
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.*DATA.*
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2 \.bss .* .* .* .* 2\*\*0
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.*
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@ -0,0 +1,3 @@
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.text
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.byte 0xf
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.inst 0xd503201f
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