revert previous delta
This commit is contained in:
Nick Clifton
parent
9cac79d30b
commit
452a37f009
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@ -1,9 +1,3 @@
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1999-10-25 Nick Clifton <nickc@cygnus.com>
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* config/tc-mcore.c (parse_psrmod): New function: Parse the psr
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flag specifiers of a psrclr/psrset instruction.
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(md_assemble): Parse instructions of class OPSR.
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Mon Oct 18 18:11:10 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
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* tc_d10v.c (find_opcode): Allow ATSIGN to match expressions of the
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@ -48,7 +48,6 @@ static char * parse_exp PARAMS ((char *, expressionS *));
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static char * parse_rt PARAMS ((char *, char **, int, expressionS *));
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static char * parse_imm PARAMS ((char *, unsigned *, unsigned, unsigned));
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static char * parse_mem PARAMS ((char *, unsigned *, unsigned *, unsigned));
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static char * parse_psrmod PARAMS ((char *, unsigned *));
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static void make_name PARAMS ((char *, char *, int));
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static int enter_literal PARAMS ((expressionS *, int));
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static void dump_literals PARAMS ((int));
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@ -589,46 +588,6 @@ parse_creg (s, reg)
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return s;
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}
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static char *
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parse_psrmod (s, reg)
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char * s;
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unsigned * reg;
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{
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int i;
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char buf[10];
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static struct psrmods
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{
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char * name;
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unsigned int value;
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}
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psrmods[] =
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{
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{ "ie", 1 },
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{ "fe", 2 },
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{ "ee", 4 },
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{ "af", 8 } /* really 0 and non-combinable */
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};
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for (i = 0; i < 2; i++)
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buf[i] = isascii (s[i]) ? tolower (s[i]) : 0;
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for (i = sizeof (psrmods) / sizeof (psrmods[0]); i--;)
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{
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if (! strncmp (psrmods[i].name, buf, 2))
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{
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* reg = psrmods[i].value;
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return s + 2;
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}
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}
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as_bad (_("bad/missing psr specifier"));
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* reg = 0;
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return s;
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}
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static char *
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parse_exp (s, e)
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char * s;
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@ -1635,29 +1594,6 @@ md_assemble (str)
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output = frag_more (2);
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break;
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case OPSR:
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op_end = parse_psrmod (op_end + 1, & reg);
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/* Look for further selectors. */
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while (* op_end == ',')
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{
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unsigned value;
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op_end = parse_psrmod (op_end + 1, & value);
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if (value & reg)
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as_bad (_("duplicated psr bit specifier"));
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reg |= value;
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}
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if (reg > 8)
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as_bad (_("`af' must appear alone"));
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inst |= (reg & 0x7);
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output = frag_more (2);
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break;
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default:
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as_bad (_("unimplemented opcode \"%s\""), name);
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}
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@ -1,11 +1,3 @@
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1999-10-25 Nick Clifton <nickc@cygnus.com>
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* mcore-opc.h (enum mcore_opclass): Add class OPSR.
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(mcore_table): Add psrclr and psrset instructions.
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* mcore-dis.c (array imsk): Add mask for OPSR class.
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(print_insn_mcore): Add decode for OPSR class insns.
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1999-10-18 Michael Meissner <meissner@cygnus.com>
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* alpha-opc.c (alpha_operands): Fill in missing initializer.
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@ -101,8 +101,6 @@ static const unsigned short imsk[] =
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/* OMc */ 0xFF00,
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/* SIa */ 0xFE00,
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/* OPSR */ 0xFFF8, /* psrset/psrclr */
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/* JC */ 0, /* JC,JU,JL don't appear in object */
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/* JU */ 0,
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/* JL */ 0,
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@ -283,18 +281,6 @@ print_insn_mcore (memaddr, info)
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}
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break;
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case OPSR:
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{
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static char * fields[] =
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{
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"af", "ie", "fe", "fe,ie",
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"ee", "ee,ie", "ee,fe", "ee,fe,ie"
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};
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fprintf (stream, "\t%s", fields[inst & 0x7]);
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}
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break;
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default:
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/* if the disassembler lags the instruction set */
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fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
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@ -23,7 +23,7 @@ typedef enum
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O0, OT, O1, OC, O2, X1, OI, OB,
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OMa, SI, I7, LS, BR, BL, LR, LJ,
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RM, RQ, JSR, JMP, OBRa, OBRb, OBRc, OBR2,
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O1R1, OMb, OMc, SIa, OPSR,
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O1R1, OMb, OMc, SIa,
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JC, JU, JL, RSI, DO21, OB2
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}
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mcore_opclass;
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@ -99,8 +99,6 @@ mcore_opcode_info mcore_table[] =
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{ "tst", O2, 0, 0x0E00 },
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{ "cmpne", O2, 0, 0x0F00 },
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{ "mfcr", OC, 0, 0x1000 },
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{ "psrclr", OPSR, 0, 0x11F0 },
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{ "psrset", OPSR, 0, 0x11F8 },
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{ "mov", O2, 0, 0x1200 },
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{ "bgenr", O2, 0, 0x1300 },
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{ "rsub", O2, 0, 0x1400 },
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