Add support for ARC instruction relaxation in the assembler.
gas/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS) (MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE): Define. (arc_flags, arc_relax_type): New structure. * config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY) (RELAX_TABLE_ENTRY_MAX): New define. (relaxation_state, md_relax_table, arc_relaxable_insns) (arc_num_relaxable_ins): New variable. (rlx_operand_type, arc_rlx_types): New enums. (arc_relaxable_ins): New structure. (OPTION_RELAX): New option. (arc_insn): New relax member. (arc_flags): Remove. (relax_insn_p): New function. (apply_fixups): Likewise. (relaxable_operand): Likewise. (may_relax_expr): Likewise. (relaxable_flag): Likewise. (arc_pcrel_adjust): Likewise. (md_estimate_size_before_relax): Implement. (md_convert_frag): Likewise. (md_parse_option): Handle new mrelax option. (md_show_usage): Likewise. (assemble_insn): Set relax member. (emit_insn0): New function. (emit_insn1): Likewise. (emit_insn): Handle relaxation case. * NEWS: Mention the new relaxation option. * doc/c-arc.texi (ARC Options): Document new mrelax option. gas/testsuite 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> * gas/arc/relax-avoid1.d: New file. * gas/arc/relax-avoid1.s: Likewise. * gas/arc/relax-avoid2.d: Likewise. * gas/arc/relax-avoid2.s: Likewise. * gas/arc/relax-avoid3.d: Likewise. * gas/arc/relax-avoid3.s: Likewise. * gas/arc/relax-b.d: Likewise. * gas/arc/relax-b.s: Likewise. include/opcode/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes): Declare. opcodes/ 2016-01-26 Claudiu Zissulescu <claziss@synopsys.com> Janek van Oirschot <jvanoirs@synopsys.com> * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New variable.
This commit is contained in:
parent
83da6e748c
commit
4670103e86
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@ -1,3 +1,45 @@
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2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
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Janek van Oirschot <jvanoirs@synopsys.com>
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* config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
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(MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
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Define.
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(arc_flags, arc_relax_type): New structure.
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* config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
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(RELAX_TABLE_ENTRY_MAX): New define.
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(relaxation_state, md_relax_table, arc_relaxable_insns)
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(arc_num_relaxable_ins): New variable.
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(rlx_operand_type, arc_rlx_types): New enums.
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(arc_relaxable_ins): New structure.
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(OPTION_RELAX): New option.
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(arc_insn): New relax member.
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(arc_flags): Remove.
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(relax_insn_p): New function.
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(apply_fixups): Likewise.
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(relaxable_operand): Likewise.
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(may_relax_expr): Likewise.
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(relaxable_flag): Likewise.
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(arc_pcrel_adjust): Likewise.
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(md_estimate_size_before_relax): Implement.
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(md_convert_frag): Likewise.
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(md_parse_option): Handle new mrelax option.
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(md_show_usage): Likewise.
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(assemble_insn): Set relax member.
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(emit_insn0): New function.
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(emit_insn1): Likewise.
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(emit_insn): Handle relaxation case.
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* NEWS: Mention the new relaxation option.
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* doc/c-arc.texi (ARC Options): Document new mrelax option.
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* doc/as.texinfo (Target ARC Options): Likewise.
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* testsuite/gas/arc/relax-avoid1.d: New file.
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* testsuite/gas/arc/relax-avoid1.s: Likewise.
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* testsuite/gas/arc/relax-avoid2.d: Likewise.
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* testsuite/gas/arc/relax-avoid2.s: Likewise.
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* testsuite/gas/arc/relax-avoid3.d: Likewise.
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* testsuite/gas/arc/relax-avoid3.s: Likewise.
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* testsuite/gas/arc/relax-b.d: Likewise.
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* testsuite/gas/arc/relax-b.s: Likewise.
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2016-02-08 Nick Clifton <nickc@redhat.com>
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* config/tc-ia64.c (dot_prologue): Fix formatting.
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2
gas/NEWS
2
gas/NEWS
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@ -10,6 +10,8 @@
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* New command line option -mfence-as-lock-add=yes for x86 target to encode
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lfence, mfence and sfence as "lock addl $0x0, (%[re]sp)".
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* Add assembly-time relaxation option for ARC cpus.
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Changes in 2.26:
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* Add a configure option --enable-compressed-debug-sections={all,gas} to
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3369
gas/config/tc-arc.c
3369
gas/config/tc-arc.c
File diff suppressed because it is too large
Load Diff
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@ -177,6 +177,14 @@ extern long md_pcrel_from_section (struct fix *, segT);
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/* This hook is required to parse register names as operands. */
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#define md_parse_name(name, exp, m, c) arc_parse_name (name, exp)
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/* Used within frags to pass some information to some relaxation
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machine dependent values. */
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#define TC_FRAG_TYPE struct arc_relax_type
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/* Adjust non PC-rel values at relaxation time. */
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#define TC_PCREL_ADJUST(F) arc_pcrel_adjust (F)
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extern int arc_pcrel_adjust (fragS *);
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extern bfd_boolean arc_parse_name (const char *, struct expressionS *);
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extern int tc_arc_fix_adjustable (struct fix *);
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extern void arc_handle_align (fragS *);
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@ -193,3 +201,51 @@ extern void arc_frob_label (symbolS *);
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#define NOP_OPCODE_S 0x000078E0
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#define NOP_OPCODE_L 0x264A7000 /* mov 0,0. */
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#define MAX_FLAG_NAME_LENGHT 3
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struct arc_flags
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{
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/* Name of the parsed flag. */
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char name[MAX_FLAG_NAME_LENGHT + 1];
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/* The code of the parsed flag. Valid when is not zero. */
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unsigned char code;
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};
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#ifndef MAX_INSN_ARGS
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#define MAX_INSN_ARGS 6
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#endif
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#ifndef MAX_INSN_FLGS
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#define MAX_INSN_FLGS 3
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#endif
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extern const relax_typeS md_relax_table[];
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#define TC_GENERIC_RELAX_TABLE md_relax_table
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/* Used to construct instructions at md_convert_frag stage of
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relaxation. */
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struct arc_relax_type
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{
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/* Dictates whether the pc-relativity should be kept in mind when
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relax_frag is called or whether the pc-relativity should be
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solved outside of relaxation. For clarification: BL(_S) and
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B(_S) use pcrel == 1 and ADD with a solvable expression as 3rd
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operand use pcrel == 0. */
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unsigned char pcrel;
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/* Expressions that dictate the operands. Used for re-assembling in
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md_convert_frag. */
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expressionS tok[MAX_INSN_ARGS];
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/* Number of tok (i.e. number of operands). Used for re-assembling
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in md_convert_frag. */
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int ntok;
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/* Flags of instruction. Used for re-assembling in
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md_convert_frag. */
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struct arc_flags pflags[MAX_INSN_FLGS];
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/* Number of flags. Used for re-assembling in md_convert_frag. */
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int nflg;
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};
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@ -268,6 +268,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
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[@b{-mcpu=@var{cpu}}]
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[@b{-mA6}|@b{-mARC600}|@b{-mARC601}|@b{-mA7}|@b{-mARC700}|@b{-mEM}|@b{-mHS}]
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[@b{-mcode-density}]
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[@b{-mrelax}]
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[@b{-EB}|@b{-EL}]
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@end ifset
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@ifset ARM
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@ -85,6 +85,12 @@ default.
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This option turns on Code Density instructions. Only valid for ARC EM
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processors.
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@cindex @code{-mrelax} command line option, ARC
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@item -mrelax
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Enable support for assembly-time relaxation. The assembler will
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replace a longer version of an instruction with a shorter one,
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whenever it is possible.
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@end table
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@node ARC Syntax
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@ -0,0 +1,13 @@
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#as: -mcpu=archs -mrelax
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#objdump: -dr
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.*: +file format .*arc.*
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Disassembly of section .text:
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00000000 <.text>:
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0: 78e0 nop_s
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2: 240a 0f80 0000 0000 mov r4,0
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6: R_ARC_32_ME .LC2
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a: 78e0 nop_s
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@ -0,0 +1,11 @@
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.section .rodata
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.align 4
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.LC2:
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.word 0x01
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.word 0x02
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.word 0x03
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.section .text
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.align 4
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nop_s
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mov r4,@.LC2
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@ -0,0 +1,14 @@
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#as: -mcpu=archs -mrelax
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#objdump: -dr
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.*: +file format .*arc.*
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Disassembly of section .text:
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00000000 <test>:
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0: 2000 0000 add r0,r0,r0
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00000004 <main>:
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4: 0802 0000 bl 0 <test>
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4: R_ARC_S25W_PCREL_PLT test
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@ -0,0 +1,4 @@
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test:
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add r0,r0,r0
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main:
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bl @test@plt
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@ -0,0 +1,14 @@
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#as: -mcpu=archs -mrelax
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#objdump: -dr
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.*: +file format .*arc.*
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Disassembly of section .text:
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00000000 <test>:
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0: 2000 0000 add r0,r0,r0
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00000004 <main>:
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4: 0001 0000 b 0 <test>
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4: R_ARC_S25H_PCREL test
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@ -0,0 +1,5 @@
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test:
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add r0,r0,r0
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.weak test
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main:
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b test
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@ -0,0 +1,19 @@
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#as: -mcpu=archs -mrelax
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#objdump: -dr
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.*: +file format .*arc.*
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Disassembly of section .text:
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00000000 <foo-0x4>:
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0: 78e0 nop_s
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2: 78e0 nop_s
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00000004 <foo>:
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4: 2000 0000 add r0,r0,r0
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00000008 <bar>:
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8: ffff bl_s 4 <foo>
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a: 2100 0041 add r1,r1,r1
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e: f1fc b_s 4 <foo>
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@ -0,0 +1,11 @@
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.text
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nop_s
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.align 4
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foo:
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add r0,r0,r0
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.align 4
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bar:
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bl @foo
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add r1,r1,r1
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b @foo
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@ -1,3 +1,9 @@
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2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
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Janek van Oirschot <jvanoirs@synopsys.com>
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* opcode/arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
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Declare.
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2016-02-09 Nick Clifton <nickc@redhat.com>
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* opcode/metag.h (metag_scondtab): Mark as possibly unused.
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@ -24,8 +24,13 @@
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#ifndef OPCODE_ARC_H
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#define OPCODE_ARC_H
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#ifndef MAX_INSN_ARGS
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#define MAX_INSN_ARGS 6
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#endif
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#ifndef MAX_INSN_FLGS
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#define MAX_INSN_FLGS 3
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#endif
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/* Instruction Class. */
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typedef enum
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@ -410,4 +415,7 @@ struct arc_aux_reg
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extern const struct arc_aux_reg arc_aux_regs[];
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extern const unsigned arc_num_aux_regs;
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extern const struct arc_opcode arc_relax_opcodes[];
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extern const unsigned arc_num_relax_opcodes;
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#endif /* OPCODE_ARC_H */
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@ -1,3 +1,9 @@
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2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
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Janek van Oirschot <jvanoirs@synopsys.com>
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* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
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variable.
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2016-02-04 Nick Clifton <nickc@redhat.com>
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PR target/19561
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@ -1359,3 +1359,129 @@ const struct arc_aux_reg arc_aux_regs[] =
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};
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const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
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/* NOTE: The order of this array MUST be consistent with 'enum
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arc_rlx_types' located in tc-arc.h! */
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const struct arc_opcode arc_relax_opcodes[] =
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{
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{ NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
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/* bl_s s13 11111sssssssssss. */
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{ "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
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{ SIMM13_A32_5_S }, { 0 }},
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/* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
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{ "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
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{ SIMM25_A32_5 }, { C_D }},
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/* b_s s10 1111000sssssssss. */
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{ "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
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{ SIMM10_A16_7_S }, { 0 }},
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/* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
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{ "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
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{ SIMM25_A16_5 }, { C_D }},
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/* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
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{ "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
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{ RC_S, RB_S, UIMM3_13_S }, { 0 }},
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/* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
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UIMM6_20_PCREL. */
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{ "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
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{ RA, RB, UIMM6_20 }, { C_F }},
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/* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
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{ "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
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{ RA, RB, LIMM }, { C_F }},
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/* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
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{ "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
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{ RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
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/* ld<.di><.aa><.x><zz> a,b,s9
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00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
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{ "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
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{ RA, BRAKET, RB, SIMM9_8, BRAKETdup },
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{ C_ZZ23, C_DI20, C_AA21, C_X25 }},
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/* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
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{ "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
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{ RA, BRAKET, RB, LIMM, BRAKETdup },
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{ C_ZZ13, C_DI16, C_AA8, C_X15 }},
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/* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
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{ "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
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{ RB_S, UIMM8_8_S }, { 0 }},
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/* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
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SIMM12_20_PCREL. */
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{ "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
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{ RB, SIMM12_20 }, { C_F }},
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/* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
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{ "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
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{ RB, LIMM }, { C_F }},
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/* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
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{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
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{ RC_S, RB_S, UIMM3_13_S }, { 0 }},
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/* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
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UIMM6_20_PCREL. */
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{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
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{ RA, RB, UIMM6_20 }, { C_F }},
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/* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
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{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
|
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{ RA, RB, LIMM }, { C_F }},
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/* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
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UIMM6_20_PCREL. */
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{ "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
|
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| ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
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|
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/* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
|
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{ "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
|
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| ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
|
||||
|
||||
/* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
|
||||
UIMM6_20_PCREL. */
|
||||
{ "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
|
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
|
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{ RB, UIMM6_20 }, { C_F, C_CC }},
|
||||
|
||||
/* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
|
||||
{ "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
|
||||
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
|
||||
{ RB, LIMM }, { C_F, C_CC }},
|
||||
|
||||
/* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
|
||||
UIMM6_20_PCREL. */
|
||||
{ "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
|
||||
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
|
||||
{ RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
|
||||
|
||||
/* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
|
||||
{ "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
|
||||
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
|
||||
{ RB, RBdup, LIMM }, { C_F, C_CC }}
|
||||
};
|
||||
|
||||
const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
|
||||
|
|
Loading…
Reference in New Issue