* mips-opc.c ("macc*","mul*"): Added the 4320 versions
of these.
This commit is contained in:
Gavin Romig-Koch
parent
d843d7ca34
commit
46bb89f0d2
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@ -1,3 +1,10 @@
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start-sanitize-vr4320
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Mon Mar 9 15:22:06 1998 Gavin Koch <gavin@cygnus.com>
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* mips-opc.c ("macc*","mul*"): Added the 4320 versions
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of these.
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end-sanitize-vr4320
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start-sanitize-sky
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Fri Mar 6 11:27:53 1998 Doug Evans <devans@canuck.cygnus.com>
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@ -57,16 +57,19 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define WR_C1 INSN_COP
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#define WR_C2 INSN_COP
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#define WR_C3 INSN_COP
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#define WR_HI INSN_WRITE_HI
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#define WR_LO INSN_WRITE_LO
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#define RD_HI INSN_READ_HI
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#define RD_LO INSN_READ_LO
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/* start-sanitize-vr5400 */
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#define WR_HI INSN_WRITE_HI
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#define RD_HI INSN_READ_HI
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#define MOD_HI WR_HI|RD_HI
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#define WR_LO INSN_WRITE_LO
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#define RD_LO INSN_READ_LO
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#define MOD_LO WR_LO|RD_LO
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#define WR_HILO WR_HI|WR_LO
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#define RD_HILO RD_HI|RD_LO
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#define MOD_HILO WR_HILO|RD_HILO
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/* end-sanitize-vr5400 */
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#define I1 INSN_ISA1
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#define I2 INSN_ISA2
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@ -525,13 +528,31 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
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/* start-sanitize-vr4320 */
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{"mac", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, N4},
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{"dmac", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO, N4},
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{"dmac", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr4320 */
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{"macc", "d,s,t", 0x000000A8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr5400 */
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{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d, N5 },
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{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d, N5 },
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{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d, N5 },
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{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d, N5 },
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{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N5},
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/* end-sanitize-vr5400 */
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/* start-sanitize-vr4320 */
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{"maccu", "d,s,t", 0x000000E8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr5400 */
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{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N5},
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/* end-sanitize-vr5400 */
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/* start-sanitize-vr4320 */
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{"macchi", "d,s,t", 0x000002A8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr5400 */
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{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N5},
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/* end-sanitize-vr5400 */
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/* start-sanitize-vr4320 */
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{"macchiu", "d,s,t", 0x000002E8, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr5400 */
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{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|MOD_HILO|WR_d,N5},
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/* end-sanitize-vr5400 */
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{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
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{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
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@ -676,19 +697,37 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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/* end-sanitize-r5900 */
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{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
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{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
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/* start-sanitize-vr5400 */
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{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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/* end-sanitize-vr5400 */
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{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3},
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/* start-sanitize-vr4320 */
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{"mul", "d,s,t", 0x00000128, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr5400 */
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{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5},
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/* end-sanitize-vr5400 */
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{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
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{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
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{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
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{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 },
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{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 },
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{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 },
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/* start-sanitize-vr4320 */
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{"mulu", "d,s,t", 0x00000168, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr5400 */
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{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5},
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/* end-sanitize-vr5400 */
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/* start-sanitize-vr4320 */
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{"mulhi", "d,s,t", 0x00000328, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr5400 */
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{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5},
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/* end-sanitize-vr5400 */
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/* start-sanitize-vr4320 */
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{"mulhiu", "d,s,t", 0x00000368, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N4},
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/* end-sanitize-vr4320 */
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/* start-sanitize-vr5400 */
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{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5},
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/* end-sanitize-vr5400 */
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/* start-sanitize-vr5400 */
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{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
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