gas/testsuite/
2002-02-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run xsave, xsave-intel, x86-64-xsave and x86-64-xsave-intel. * gas/i386/x86-64-xsave-intel.d: New file. * gas/i386/x86-64-xsave.d: Likewise. * gas/i386/x86-64-xsave.s: Likewise. * gas/i386/xsave-intel.d: Likewise. * gas/i386/xsave.d: Likewise. * gas/i386/xsave.s: Likewise. opcodes/ 2008-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flags): Add CpuXsave. * i386-opc.h (CpuXsave): New. (Cpu64): Updated. (i386_cpu_flags): Add cpuxsave. * i386-dis.c (MOD_0FAE_REG_4): New. (RM_0F01_REG_2): Likewise. (MOD_0FAE_REG_5): Updated. (RM_0F01_REG_3): Likewise. (reg_table): Use MOD_0FAE_REG_4. (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated for xrstor. (rm_table): Add RM_0F01_REG_2. * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu
parent
86ed6051f7
commit
475a2301db
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@ -1,3 +1,15 @@
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2002-02-11 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run xsave, xsave-intel, x86-64-xsave
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and x86-64-xsave-intel.
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* gas/i386/x86-64-xsave-intel.d: New file.
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* gas/i386/x86-64-xsave.d: Likewise.
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* gas/i386/x86-64-xsave.s: Likewise.
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* gas/i386/xsave-intel.d: Likewise.
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* gas/i386/xsave.d: Likewise.
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* gas/i386/xsave.s: Likewise.
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2008-02-05 Adam Nemet <anemet@caviumnetworks.com>
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* gas/mips/mips.exp: Invoke the tests smartmips, mips32-dsp,
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@ -114,6 +114,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_list_test "arch-10-4" "-march=i686+sse4+vmx+smx -I${srcdir}/$subdir -al"
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run_dump_test "arch-11"
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run_dump_test "arch-12"
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run_dump_test "xsave"
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run_dump_test "xsave-intel"
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# These tests require support for 8 and 16 bit relocs,
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# so we only run them for ELF and COFF targets.
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@ -226,6 +228,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "rexw"
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run_dump_test "x86-64-arch-1"
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run_dump_test "x86-64-arch-10"
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run_dump_test "x86-64-xsave"
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run_dump_test "x86-64-xsave-intel"
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if { ![istarget "*-*-aix*"]
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&& ![istarget "*-*-beos*"]
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@ -0,0 +1,17 @@
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#source: x86-64-xsave.s
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#as: -J
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#objdump: -dw -Mintel
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#name: x86-64 xsave (Intel mode)
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 41 0f ae 29 xrstor \[r9\]
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[ ]*[a-f0-9]+: 41 0f ae 21 xsave \[r9\]
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[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
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[ ]*[a-f0-9]+: 0f 01 d1 xsetbv
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[ ]*[a-f0-9]+: 0f ae 29 xrstor \[rcx\]
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[ ]*[a-f0-9]+: 0f ae 21 xsave \[rcx\]
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#pass
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@ -0,0 +1,15 @@
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#objdump: -dw
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#name: x86-64 xsave prefix
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 41 0f ae 29 xrstor \(%r9\)
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[ ]*[a-f0-9]+: 41 0f ae 21 xsave \(%r9\)
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[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
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[ ]*[a-f0-9]+: 0f 01 d1 xsetbv
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[ ]*[a-f0-9]+: 0f ae 29 xrstor \(%rcx\)
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[ ]*[a-f0-9]+: 0f ae 21 xsave \(%rcx\)
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#pass
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@ -0,0 +1,11 @@
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# Check 64bit xsave/xrstor
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.text
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_start:
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xrstor (%r9)
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xsave (%r9)
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xgetbv
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xsetbv
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.intel_syntax noprefix
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xrstor [rcx]
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xsave [rcx]
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@ -0,0 +1,17 @@
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#source: xsave.s
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#as: -J
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#objdump: -dw -Mintel
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#name: i386 xsave (Intel mode)
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 0f ae 2b xrstor \[ebx\]
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[ ]*[a-f0-9]+: 0f ae 23 xsave \[ebx\]
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[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
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[ ]*[a-f0-9]+: 0f 01 d1 xsetbv
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[ ]*[a-f0-9]+: 0f ae 29 xrstor \[ecx\]
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[ ]*[a-f0-9]+: 0f ae 21 xsave \[ecx\]
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#pass
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@ -0,0 +1,15 @@
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#objdump: -dw
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#name: i386 xsave
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.*: file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 0f ae 2b xrstor \(%ebx\)
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[ ]*[a-f0-9]+: 0f ae 23 xsave \(%ebx\)
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[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
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[ ]*[a-f0-9]+: 0f 01 d1 xsetbv
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[ ]*[a-f0-9]+: 0f ae 29 xrstor \(%ecx\)
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[ ]*[a-f0-9]+: 0f ae 21 xsave \(%ecx\)
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#pass
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@ -0,0 +1,11 @@
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# Check xsave/xrstor
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.text
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_start:
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xrstor (%ebx)
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xsave (%ebx)
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xgetbv
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xsetbv
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.intel_syntax noprefix
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xrstor [ecx]
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xsave [ecx]
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@ -1,3 +1,24 @@
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2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flags): Add CpuXsave.
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* i386-opc.h (CpuXsave): New.
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(Cpu64): Updated.
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(i386_cpu_flags): Add cpuxsave.
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* i386-dis.c (MOD_0FAE_REG_4): New.
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(RM_0F01_REG_2): Likewise.
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(MOD_0FAE_REG_5): Updated.
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(RM_0F01_REG_3): Likewise.
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(reg_table): Use MOD_0FAE_REG_4.
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(mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
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for xrstor.
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(rm_table): Add RM_0F01_REG_2.
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* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2008-02-11 Jan Beulich <jbeulich@novell.com>
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* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
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@ -542,7 +542,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
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#define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
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#define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
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#define MOD_0FAE_REG_5 (MOD_0FAE_REG_3 + 1)
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#define MOD_0FAE_REG_4 (MOD_0FAE_REG_3 + 1)
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#define MOD_0FAE_REG_5 (MOD_0FAE_REG_4 + 1)
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#define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
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#define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
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#define MOD_0FB2 (MOD_0FAE_REG_7 + 1)
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@ -560,7 +561,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define RM_0F01_REG_0 0
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#define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
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#define RM_0F01_REG_3 (RM_0F01_REG_1 + 1)
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#define RM_0F01_REG_2 (RM_0F01_REG_1 + 1)
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#define RM_0F01_REG_3 (RM_0F01_REG_2 + 1)
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#define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
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#define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
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#define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
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@ -1764,7 +1766,7 @@ static const struct dis386 reg_table[][8] = {
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{ MOD_TABLE (MOD_0FAE_REG_1) },
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{ MOD_TABLE (MOD_0FAE_REG_2) },
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{ MOD_TABLE (MOD_0FAE_REG_3) },
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{ "(bad)", { XX } },
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{ MOD_TABLE (MOD_0FAE_REG_4) },
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{ MOD_TABLE (MOD_0FAE_REG_5) },
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{ MOD_TABLE (MOD_0FAE_REG_6) },
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{ MOD_TABLE (MOD_0FAE_REG_7) },
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@ -4549,7 +4551,7 @@ static const struct dis386 mod_table[][2] = {
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{
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/* MOD_0F01_REG_2 */
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{ X86_64_TABLE (X86_64_0F01_REG_2) },
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{ "(bad)", { XX } },
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{ RM_TABLE (RM_0F01_REG_2) },
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},
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{
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/* MOD_0F01_REG_3 */
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@ -4727,8 +4729,13 @@ static const struct dis386 mod_table[][2] = {
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{ "(bad)", { XX } },
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},
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{
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/* MOD_0FAE_REG_5 */
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/* MOD_0FAE_REG_4 */
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{ "xsave", { M } },
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{ "(bad)", { XX } },
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},
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{
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/* MOD_0FAE_REG_5 */
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{ "xrstor", { M } },
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{ RM_TABLE (RM_0FAE_REG_5) },
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},
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{
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@ -4826,6 +4833,17 @@ static const struct dis386 rm_table[][8] = {
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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},
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{
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/* RM_0F01_REG_2 */
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{ "xgetbv", { Skip_MODRM } },
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{ "xsetbv", { Skip_MODRM } },
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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},
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{
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/* RM_0F01_REG_3 */
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{ "vmrun", { Skip_MODRM } },
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@ -245,6 +245,7 @@ static bitfield cpu_flags[] =
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BITFIELD (CpuSMX),
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BITFIELD (CpuABM),
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BITFIELD (CpuLM),
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BITFIELD (CpuXsave),
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BITFIELD (Cpu64),
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BITFIELD (CpuNo64),
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#ifdef CpuUnused
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@ -20,151 +20,151 @@
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#define CPU_UNKNOWN_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 0, 1, 1 } }
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1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
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#define CPU_GENERIC32_FLAGS \
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{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_GENERIC64_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_NONE_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I186_FLAGS \
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I286_FLAGS \
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{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I386_FLAGS \
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{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I486_FLAGS \
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{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I586_FLAGS \
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{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I686_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_P2_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_P3_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_P4_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_NOCONA_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_CORE_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_CORE2_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
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0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_K6_FLAGS \
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{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_K6_2_FLAGS \
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{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_ATHLON_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_K8_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_AMDFAM10_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
1, 1, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE5_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
1, 1, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
|
|
|||
|
|
@ -80,8 +80,10 @@
|
|||
#define CpuSSE4_2 (CpuSSE4_1 + 1)
|
||||
/* SSE5 support required */
|
||||
#define CpuSSE5 (CpuSSE4_2 + 1)
|
||||
/* Xsave/xrstor New Instuctions support required */
|
||||
#define CpuXsave (CpuSSE5 + 1)
|
||||
/* 64bit support available, used by -march= in assembler. */
|
||||
#define CpuLM (CpuSSE5 + 1)
|
||||
#define CpuLM (CpuXsave + 1)
|
||||
/* 64bit support required */
|
||||
#define Cpu64 (CpuLM + 1)
|
||||
/* Not supported in the 64bit mode */
|
||||
|
|
@ -129,6 +131,7 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpusse4_1:1;
|
||||
unsigned int cpusse4_2:1;
|
||||
unsigned int cpusse5:1;
|
||||
unsigned int cpuxsave:1;
|
||||
unsigned int cpulm:1;
|
||||
unsigned int cpu64:1;
|
||||
unsigned int cpuno64:1;
|
||||
|
|
|
|||
|
|
@ -1408,6 +1408,13 @@ crc32, 2, 0xf20f38f1, None, 3, CpuSSE4_2|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No
|
|||
crc32, 2, 0xf20f38f0, None, 3, CpuSSE4_2, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
|
||||
crc32, 2, 0xf20f38f0, None, 3, CpuSSE4_2|Cpu64, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
|
||||
|
||||
// xsave/xrstor New Instructions.
|
||||
|
||||
xsave, 1, 0xfae, 0x4, 2, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
xrstor, 1, 0xfae, 0x5, 2, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
xgetbv, 0, 0xf01, 0xd0, 2, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
xsetbv, 0, 0xf01, 0xd1, 2, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
|
||||
|
||||
// AMD 3DNow! instructions.
|
||||
|
||||
prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
|
|
|
|||
2940
opcodes/i386-tbl.h
2940
opcodes/i386-tbl.h
File diff suppressed because it is too large
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Reference in New Issue