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Update function declarations to ISO C90 formatting

This commit is contained in:
Nick Clifton 2005-07-01 11:16:33 +00:00
parent e4e8248d79
commit 47b0e7ad8c
119 changed files with 13365 additions and 15909 deletions
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22
bfd/ChangeLog
View File

@ -1,3 +1,25 @@
2005-07-01 Nick Clifton <nickc@redhat.com>
* cpu-d10v.c: Update to ISO C90 style function declarations and
fix formatting.
* cpu-d30v.c: Likewsie.
* cpu-i370.c: Likewsie.
* cpu-xstormy16.c: Likewsie.
* elf32-arc.c: Likewsie.
* elf32-d10v.c: Likewsie.
* elf32-d30v.c: Likewsie.
* elf32-dlx.c: Likewsie.
* elf32-i370.c: Likewsie.
* elf32-i960.c: Likewsie.
* elf32-ip2k.c: Likewsie.
* elf32-m32r.c: Likewsie.
* elf32-mcore.c: Likewsie.
* elf32-openrisc.c: Likewsie.
* elf32-or32.c: Likewsie.
* elf32-pj.c: Likewsie.
* elf32-v850.c: Likewsie.
* elf32-xstormy16.c: Likewsie.
2005-07-01 Alan Modra <amodra@bigpond.net.au>
* elf64-alpha.c (elf64_alpha_create_got_section): Always create

55
bfd/cpu-d10v.c
View File

@ -1,22 +1,23 @@
/* BFD support for the D10V processor
Copyright 1996, 1999, 2000, 2002 Free Software Foundation, Inc.
Copyright 1996, 1999, 2000, 2002, 2005 Free Software Foundation, Inc.
Contributed by Martin Hunt (hunt@cygnus.com).
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -24,14 +25,14 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
static const bfd_arch_info_type d10v_ts3_info =
{
16, /* 16 bits in a word */
16, /* 16 bits in an address */
8, /* 8 bits in a byte */
16, /* 16 bits in a word. */
16, /* 16 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_d10v,
bfd_mach_d10v_ts3,
"d10v",
"d10v:ts3",
4, /* section alignment power */
4, /* Section alignment power. */
FALSE,
bfd_default_compatible,
bfd_default_scan,
@ -40,32 +41,32 @@ static const bfd_arch_info_type d10v_ts3_info =
static const bfd_arch_info_type d10v_ts2_info =
{
16, /* 16 bits in a word */
16, /* 16 bits in an address */
8, /* 8 bits in a byte */
16, /* 16 bits in a word. */
16, /* 16 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_d10v,
bfd_mach_d10v_ts2,
"d10v",
"d10v:ts2",
4, /* section alignment power */
4, /* Section alignment power. */
FALSE,
bfd_default_compatible,
bfd_default_scan,
&d10v_ts3_info,
& d10v_ts3_info,
};
const bfd_arch_info_type bfd_d10v_arch =
{
16, /* 16 bits in a word */
16, /* 16 bits in an address */
8, /* 8 bits in a byte */
16, /* 16 bits in a word. */
16, /* 16 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_d10v,
bfd_mach_d10v,
"d10v",
"d10v",
4, /* section alignment power */
4, /* Section alignment power. */
TRUE,
bfd_default_compatible,
bfd_default_scan,
&d10v_ts2_info,
& d10v_ts2_info,
};

35
bfd/cpu-d30v.c
View File

@ -1,22 +1,23 @@
/* BFD support for the Mitsubishi D30V processor
Copyright 1997, 2002 Free Software Foundation, Inc.
Copyright 1997, 2002, 2005 Free Software Foundation, Inc.
Contributed by Martin Hunt (hunt@cygnus.com).
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -24,14 +25,14 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
const bfd_arch_info_type bfd_d30v_arch =
{
32, /* bits in a word */
32, /* bits in an address */
8, /* bits in a byte */
32, /* Bits in a word. */
32, /* Bits in an address. */
8, /* Bits in a byte. */
bfd_arch_d30v,
0,
"d30v",
"d30v",
4, /* section alignment power */
4, /* Section alignment power. */
TRUE,
bfd_default_compatible,
bfd_default_scan,

77
bfd/cpu-i370.c
View File

@ -1,24 +1,25 @@
/* BFD i370 CPU definition
Copyright 1994, 1995, 1996, 1998, 1999, 2000, 2002
Copyright 1994, 1995, 1996, 1998, 1999, 2000, 2002, 2005
Free Software Foundation, Inc.
Contributed by Ian Lance Taylor, Cygnus Support.
Hacked by Linas Vepstas <linas@linas.org> in 1998, 1999
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -26,31 +27,31 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
static const bfd_arch_info_type arch_info_struct[] =
{
/* hack alert: old old machines are really 16 and 24 bit arch ... */
/* Hack alert: old old machines are really 16 and 24 bit arch ... */
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
32, /* 32 bits in a word. */
32, /* 32 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_i370,
360, /* for the 360 */
360, /* For the 360. */
"i370",
"i370:360",
3,
FALSE, /* not the default */
FALSE, /* Not the default. */
bfd_default_compatible,
bfd_default_scan,
&arch_info_struct[1]
},
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
32, /* 32 bits in a word. */
32, /* 32 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_i370,
370, /* for the 370 */
370, /* For the 370. */
"i370",
"i370:370",
3,
FALSE, /* not the default */
FALSE, /* Not the default. */
bfd_default_compatible,
bfd_default_scan,
0
@ -58,17 +59,17 @@ static const bfd_arch_info_type arch_info_struct[] =
};
const bfd_arch_info_type bfd_i370_arch =
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_i370,
0, /* for the 360/370 common architecture */
"i370",
"i370:common",
3,
TRUE, /* the default */
bfd_default_compatible,
bfd_default_scan,
&arch_info_struct[0]
};
{
32, /* 32 bits in a word. */
32, /* 32 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_i370,
0, /* For the 360/370 common architecture. */
"i370",
"i370:common",
3,
TRUE, /* The default. */
bfd_default_compatible,
bfd_default_scan,
& arch_info_struct[0]
};

24
bfd/cpu-xstormy16.c
View File

@ -1,21 +1,21 @@
/* BFD support for the XSTORMY16 processor.
Copyright 2001, 2002 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"

208
bfd/elf32-arc.c
View File

@ -1,5 +1,5 @@
/* ARC-specific support for 32-bit ELF
Copyright 1994, 1995, 1997, 1999, 2001, 2002
Copyright 1994, 1995, 1997, 1999, 2001, 2002, 2005
Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
@ -17,7 +17,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -26,83 +27,94 @@
#include "elf/arc.h"
#include "libiberty.h"
static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
PARAMS ((bfd *abfd, bfd_reloc_code_real_type code));
static void arc_info_to_howto_rel
PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
static bfd_boolean arc_elf_object_p
PARAMS ((bfd *));
static void arc_elf_final_write_processing
PARAMS ((bfd *, bfd_boolean));
static bfd_reloc_status_type arc_elf_b22_pcrel
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
/* Try to minimize the amount of space occupied by relocation tables
on the ROM (not that the ROM won't be swamped by other ELF overhead). */
#define USE_REL 1
static bfd_reloc_status_type
arc_elf_b22_pcrel (bfd * abfd,
arelent * reloc_entry,
asymbol * symbol,
void * data,
asection * input_section,
bfd * output_bfd,
char ** error_message)
{
/* If linking, back up the final symbol address by the address of the
reloc. This cannot be accomplished by setting the pcrel_offset
field to TRUE, as bfd_install_relocation will detect this and refuse
to install the offset in the first place, but bfd_perform_relocation
will still insist on removing it. */
if (output_bfd == NULL)
reloc_entry->addend -= reloc_entry->address;
/* Fall through to the default elf reloc handler. */
return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data,
input_section, output_bfd, error_message);
}
static reloc_howto_type elf_arc_howto_table[] =
{
/* This reloc does nothing. */
HOWTO (R_ARC_NONE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARC_NONE", /* name */
TRUE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (R_ARC_NONE, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
32, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_bitfield, /* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_ARC_NONE", /* Name. */
TRUE, /* Partial_inplace. */
0, /* Src_mask. */
0, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* A standard 32 bit relocation. */
HOWTO (R_ARC_32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARC_32", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (R_ARC_32, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
32, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_bitfield, /* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_ARC_32", /* Name. */
TRUE, /* Partial_inplace. */
0xffffffff, /* Src_mask. */
0xffffffff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* A 26 bit absolute branch, right shifted by 2. */
HOWTO (R_ARC_B26, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
26, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARC_B26", /* name */
TRUE, /* partial_inplace */
0x00ffffff, /* src_mask */
0x00ffffff, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (R_ARC_B26, /* Type. */
2, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
26, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_bitfield, /* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_ARC_B26", /* Name. */
TRUE, /* Partial_inplace. */
0x00ffffff, /* Src_mask. */
0x00ffffff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* A relative 22 bit branch; bits 21-2 are stored in bits 26-7. */
HOWTO (R_ARC_B22_PCREL, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
22, /* bitsize */
TRUE, /* pc_relative */
7, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
arc_elf_b22_pcrel, /* special_function */
"R_ARC_B22_PCREL", /* name */
TRUE, /* partial_inplace */
0x07ffff80, /* src_mask */
0x07ffff80, /* dst_mask */
FALSE), /* pcrel_offset */
HOWTO (R_ARC_B22_PCREL, /* Type. */
2, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
22, /* Bitsize. */
TRUE, /* PC_relative. */
7, /* Bitpos. */
complain_overflow_signed, /* Complain_on_overflow. */
arc_elf_b22_pcrel, /* Special_function. */
"R_ARC_B22_PCREL", /* Name. */
TRUE, /* Partial_inplace. */
0x07ffff80, /* Src_mask. */
0x07ffff80, /* Dst_mask. */
FALSE), /* PCrel_offset. */
};
/* Map BFD reloc types to ARC ELF reloc types. */
@ -123,9 +135,8 @@ static const struct arc_reloc_map arc_reloc_map[] =
};
static reloc_howto_type *
bfd_elf32_bfd_reloc_type_lookup (abfd, code)
bfd *abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
@ -139,10 +150,9 @@ bfd_elf32_bfd_reloc_type_lookup (abfd, code)
/* Set the howto pointer for an ARC ELF reloc. */
static void
arc_info_to_howto_rel (abfd, cache_ptr, dst)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *cache_ptr;
Elf_Internal_Rela *dst;
arc_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
arelent *cache_ptr,
Elf_Internal_Rela *dst)
{
unsigned int r_type;
@ -154,8 +164,7 @@ arc_info_to_howto_rel (abfd, cache_ptr, dst)
/* Set the right machine number for an ARC ELF file. */
static bfd_boolean
arc_elf_object_p (abfd)
bfd *abfd;
arc_elf_object_p (bfd *abfd)
{
unsigned int mach = bfd_mach_arc_6;
@ -187,9 +196,8 @@ arc_elf_object_p (abfd)
This gets the ARC architecture right based on the machine number. */
static void
arc_elf_final_write_processing (abfd, linker)
bfd *abfd;
bfd_boolean linker ATTRIBUTE_UNUSED;
arc_elf_final_write_processing (bfd *abfd,
bfd_boolean linker ATTRIBUTE_UNUSED)
{
unsigned long val;
@ -213,41 +221,17 @@ arc_elf_final_write_processing (abfd, linker)
elf_elfheader (abfd)->e_flags |= val;
}
bfd_reloc_status_type
arc_elf_b22_pcrel (abfd, reloc_entry, symbol, data, input_section,
output_bfd, error_message)
bfd * abfd;
arelent * reloc_entry;
asymbol * symbol;
PTR data;
asection * input_section;
bfd * output_bfd;
char ** error_message;
{
/* If linking, back up the final symbol address by the address of the
reloc. This cannot be accomplished by setting the pcrel_offset
field to TRUE, as bfd_install_relocation will detect this and refuse
to install the offset in the first place, but bfd_perform_relocation
will still insist on removing it. */
if (output_bfd == (bfd *) NULL)
reloc_entry->addend -= reloc_entry->address;
#define TARGET_LITTLE_SYM bfd_elf32_littlearc_vec
#define TARGET_LITTLE_NAME "elf32-littlearc"
#define TARGET_BIG_SYM bfd_elf32_bigarc_vec
#define TARGET_BIG_NAME "elf32-bigarc"
#define ELF_ARCH bfd_arch_arc
#define ELF_MACHINE_CODE EM_ARC
#define ELF_MAXPAGESIZE 0x1000
/* Fall through to the default elf reloc handler. */
return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data,
input_section, output_bfd, error_message);
}
#define TARGET_LITTLE_SYM bfd_elf32_littlearc_vec
#define TARGET_LITTLE_NAME "elf32-littlearc"
#define TARGET_BIG_SYM bfd_elf32_bigarc_vec
#define TARGET_BIG_NAME "elf32-bigarc"
#define ELF_ARCH bfd_arch_arc
#define ELF_MACHINE_CODE EM_ARC
#define ELF_MAXPAGESIZE 0x1000
#define elf_info_to_howto 0
#define elf_info_to_howto_rel arc_info_to_howto_rel
#define elf_backend_object_p arc_elf_object_p
#define elf_backend_final_write_processing arc_elf_final_write_processing
#define elf_info_to_howto 0
#define elf_info_to_howto_rel arc_info_to_howto_rel
#define elf_backend_object_p arc_elf_object_p
#define elf_backend_final_write_processing arc_elf_final_write_processing
#include "elf32-target.h"

425
bfd/elf32-d10v.c
View File

@ -1,23 +1,24 @@
/* D10V-specific support for 32-bit ELF
Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004
Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
Free Software Foundation, Inc.
Contributed by Martin Hunt (hunt@cygnus.com).
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -25,206 +26,179 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#include "elf-bfd.h"
#include "elf/d10v.h"
static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
PARAMS ((bfd *abfd, bfd_reloc_code_real_type code));
static void d10v_info_to_howto_rel
PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
static asection * elf32_d10v_gc_mark_hook
PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *,
struct elf_link_hash_entry *, Elf_Internal_Sym *));
static bfd_boolean elf32_d10v_gc_sweep_hook
PARAMS ((bfd *, struct bfd_link_info *, asection *,
const Elf_Internal_Rela *));
static bfd_boolean elf32_d10v_check_relocs
PARAMS ((bfd *, struct bfd_link_info *, asection *,
const Elf_Internal_Rela *));
static bfd_vma extract_rel_addend
PARAMS ((bfd *, bfd_byte *, reloc_howto_type *));
static void insert_rel_addend
PARAMS ((bfd *, bfd_byte *, reloc_howto_type *, bfd_vma));
static bfd_boolean elf32_d10v_relocate_section
PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *,
bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *,
asection **));
/* Use REL instead of RELA to save space. */
#define USE_REL 1
static reloc_howto_type elf_d10v_howto_table[] =
{
/* This reloc does nothing. */
HOWTO (R_D10V_NONE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_D10V_NONE", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
{
/* This reloc does nothing. */
HOWTO (R_D10V_NONE, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
32, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_D10V_NONE", /* Name. */
FALSE, /* Partial_inplace. */
0, /* Src_mask. */
0, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* An PC Relative 10-bit relocation, shifted by 2 */
/* right container */
HOWTO (R_D10V_10_PCREL_R, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
7, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_D10V_10_PCREL_R", /* name */
FALSE, /* partial_inplace */
0xff, /* src_mask */
0xff, /* dst_mask */
TRUE), /* pcrel_offset */
/* An PC Relative 10-bit relocation, shifted by 2, right container. */
HOWTO (R_D10V_10_PCREL_R, /* Type. */
2, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
7, /* Bitsize. */
TRUE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_bitfield, /* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_D10V_10_PCREL_R", /* Name. */
FALSE, /* Partial_inplace. */
0xff, /* Src_mask. */
0xff, /* Dst_mask. */
TRUE), /* PCrel_offset. */
/* An PC Relative 10-bit relocation, shifted by 2 */
/* left container */
HOWTO (R_D10V_10_PCREL_L, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
7, /* bitsize */
TRUE, /* pc_relative */
15, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_D10V_10_PCREL_L", /* name */
FALSE, /* partial_inplace */
0x07f8000, /* src_mask */
0x07f8000, /* dst_mask */
TRUE), /* pcrel_offset */
/* An PC Relative 10-bit relocation, shifted by 2, left container. */
HOWTO (R_D10V_10_PCREL_L, /* Type. */
2, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
7, /* Bitsize. */
TRUE, /* PC_relative. */
15, /* Bitpos. */
complain_overflow_bitfield, /* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_D10V_10_PCREL_L", /* Name. */
FALSE, /* Partial_inplace. */
0x07f8000, /* Src_mask. */
0x07f8000, /* Dst_mask. */
TRUE), /* PCrel_offset. */
/* A 16 bit absolute relocation */
HOWTO (R_D10V_16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_D10V_16", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A 16 bit absolute relocation. */
HOWTO (R_D10V_16, /* Type. */
0, /* Rightshift. */
1, /* Size (0 = byte, 1 = short, 2 = long). */
16, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_D10V_16", /* Name. */
FALSE, /* Partial_inplace. */
0xffff, /* Src_mask. */
0xffff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* An 18 bit absolute relocation, right shifted 2 */
HOWTO (R_D10V_18, /* type */
2, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_D10V_18", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* An 18 bit absolute relocation, right shifted 2. */
HOWTO (R_D10V_18, /* Type. */
2, /* Rightshift. */
1, /* Size (0 = byte, 1 = short, 2 = long). */
16, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont, /* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_D10V_18", /* Name. */
FALSE, /* Partial_inplace. */
0xffff, /* Src_mask. */
0xffff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* A relative 18 bit relocation, right shifted by 2 */
HOWTO (R_D10V_18_PCREL, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
15, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_D10V_18_PCREL", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* A relative 18 bit relocation, right shifted by 2. */
HOWTO (R_D10V_18_PCREL, /* Type. */
2, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
15, /* Bitsize. */
TRUE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_bitfield, /* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_D10V_18_PCREL", /* Name. */
FALSE, /* Partial_inplace. */
0xffff, /* Src_mask. */
0xffff, /* Dst_mask. */
TRUE), /* PCrel_offset. */
/* A 32 bit absolute relocation */
HOWTO (R_D10V_32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_D10V_32", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A 32 bit absolute relocation. */
HOWTO (R_D10V_32, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
32, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_D10V_32", /* Name. */
FALSE, /* Partial_inplace. */
0xffffffff, /* Src_mask. */
0xffffffff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* GNU extension to record C++ vtable hierarchy */
HOWTO (R_D10V_GNU_VTINHERIT, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
NULL, /* special_function */
"R_D10V_GNU_VTINHERIT", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* GNU extension to record C++ vtable hierarchy. */
HOWTO (R_D10V_GNU_VTINHERIT, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
0, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
NULL, /* Special_function. */
"R_D10V_GNU_VTINHERIT",/* Name. */
FALSE, /* Partial_inplace. */
0, /* Src_mask. */
0, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* GNU extension to record C++ vtable member usage */
HOWTO (R_D10V_GNU_VTENTRY, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
_bfd_elf_rel_vtable_reloc_fn, /* special_function */
"R_D10V_GNU_VTENTRY", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
};
/* GNU extension to record C++ vtable member usage. */
HOWTO (R_D10V_GNU_VTENTRY, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
0, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
_bfd_elf_rel_vtable_reloc_fn, /* Special_function. */
"R_D10V_GNU_VTENTRY", /* Name. */
FALSE, /* Partial_inplace. */
0, /* Src_mask. */
0, /* Dst_mask. */
FALSE), /* PCrel_offset. */
};
/* Map BFD reloc types to D10V ELF reloc types. */
struct d10v_reloc_map
{
bfd_reloc_code_real_type bfd_reloc_val;
unsigned char elf_reloc_val;
};
{
bfd_reloc_code_real_type bfd_reloc_val;
unsigned char elf_reloc_val;
};
static const struct d10v_reloc_map d10v_reloc_map[] =
{
{ BFD_RELOC_NONE, R_D10V_NONE, },
{ BFD_RELOC_D10V_10_PCREL_R, R_D10V_10_PCREL_R },
{ BFD_RELOC_D10V_10_PCREL_L, R_D10V_10_PCREL_L },
{ BFD_RELOC_16, R_D10V_16 },
{ BFD_RELOC_D10V_18, R_D10V_18 },
{ BFD_RELOC_D10V_18_PCREL, R_D10V_18_PCREL },
{ BFD_RELOC_32, R_D10V_32 },
{ BFD_RELOC_VTABLE_INHERIT, R_D10V_GNU_VTINHERIT },
{ BFD_RELOC_VTABLE_ENTRY, R_D10V_GNU_VTENTRY },
};
{
{ BFD_RELOC_NONE, R_D10V_NONE, },
{ BFD_RELOC_D10V_10_PCREL_R, R_D10V_10_PCREL_R },
{ BFD_RELOC_D10V_10_PCREL_L, R_D10V_10_PCREL_L },
{ BFD_RELOC_16, R_D10V_16 },
{ BFD_RELOC_D10V_18, R_D10V_18 },
{ BFD_RELOC_D10V_18_PCREL, R_D10V_18_PCREL },
{ BFD_RELOC_32, R_D10V_32 },
{ BFD_RELOC_VTABLE_INHERIT, R_D10V_GNU_VTINHERIT },
{ BFD_RELOC_VTABLE_ENTRY, R_D10V_GNU_VTENTRY },
};
static reloc_howto_type *
bfd_elf32_bfd_reloc_type_lookup (abfd, code)
bfd *abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
for (i = 0;
i < sizeof (d10v_reloc_map) / sizeof (struct d10v_reloc_map);
i++)
{
if (d10v_reloc_map[i].bfd_reloc_val == code)
return &elf_d10v_howto_table[d10v_reloc_map[i].elf_reloc_val];
}
if (d10v_reloc_map[i].bfd_reloc_val == code)
return &elf_d10v_howto_table[d10v_reloc_map[i].elf_reloc_val];
return NULL;
}
@ -232,10 +206,9 @@ bfd_elf32_bfd_reloc_type_lookup (abfd, code)
/* Set the howto pointer for an D10V ELF reloc. */
static void
d10v_info_to_howto_rel (abfd, cache_ptr, dst)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *cache_ptr;
Elf_Internal_Rela *dst;
d10v_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
arelent *cache_ptr,
Elf_Internal_Rela *dst)
{
unsigned int r_type;
@ -245,12 +218,11 @@ d10v_info_to_howto_rel (abfd, cache_ptr, dst)
}
static asection *
elf32_d10v_gc_mark_hook (sec, info, rel, h, sym)
asection *sec;
struct bfd_link_info *info ATTRIBUTE_UNUSED;
Elf_Internal_Rela *rel;
struct elf_link_hash_entry *h;
Elf_Internal_Sym *sym;
elf32_d10v_gc_mark_hook (asection *sec,
struct bfd_link_info *info ATTRIBUTE_UNUSED,
Elf_Internal_Rela *rel,
struct elf_link_hash_entry *h,
Elf_Internal_Sym *sym)
{
if (h != NULL)
{
@ -282,13 +254,12 @@ elf32_d10v_gc_mark_hook (sec, info, rel, h, sym)
}
static bfd_boolean
elf32_d10v_gc_sweep_hook (abfd, info, sec, relocs)
bfd *abfd ATTRIBUTE_UNUSED;
struct bfd_link_info *info ATTRIBUTE_UNUSED;
asection *sec ATTRIBUTE_UNUSED;
const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED;
elf32_d10v_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED,
struct bfd_link_info *info ATTRIBUTE_UNUSED,
asection *sec ATTRIBUTE_UNUSED,
const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED)
{
/* we don't use got and plt entries for d10v */
/* We don't use got and plt entries for d10v. */
return TRUE;
}
@ -297,11 +268,10 @@ elf32_d10v_gc_sweep_hook (abfd, info, sec, relocs)
virtual table relocs for gc. */
static bfd_boolean
elf32_d10v_check_relocs (abfd, info, sec, relocs)
bfd *abfd;
struct bfd_link_info *info;
asection *sec;
const Elf_Internal_Rela *relocs;
elf32_d10v_check_relocs (bfd *abfd,
struct bfd_link_info *info,
asection *sec,
const Elf_Internal_Rela *relocs)
{
Elf_Internal_Shdr *symtab_hdr;
struct elf_link_hash_entry **sym_hashes, **sym_hashes_end;
@ -356,10 +326,9 @@ elf32_d10v_check_relocs (abfd, info, sec, relocs)
}
static bfd_vma
extract_rel_addend (abfd, where, howto)
bfd *abfd;
bfd_byte *where;
reloc_howto_type *howto;
extract_rel_addend (bfd *abfd,
bfd_byte *where,
reloc_howto_type *howto)
{
bfd_vma insn, val;
@ -392,11 +361,10 @@ extract_rel_addend (abfd, where, howto)
}
static void
insert_rel_addend (abfd, where, howto, addend)
bfd *abfd;
bfd_byte *where;
reloc_howto_type *howto;
bfd_vma addend;
insert_rel_addend (bfd *abfd,
bfd_byte *where,
reloc_howto_type *howto,
bfd_vma addend)
{
bfd_vma insn;
@ -425,17 +393,16 @@ insert_rel_addend (abfd, where, howto, addend)
}
/* Relocate a D10V ELF section. */
static bfd_boolean
elf32_d10v_relocate_section (output_bfd, info, input_bfd, input_section,
contents, relocs, local_syms, local_sections)
bfd *output_bfd;
struct bfd_link_info *info;
bfd *input_bfd;
asection *input_section;
bfd_byte *contents;
Elf_Internal_Rela *relocs;
Elf_Internal_Sym *local_syms;
asection **local_sections;
elf32_d10v_relocate_section (bfd *output_bfd,
struct bfd_link_info *info,
bfd *input_bfd,
asection *input_section,
bfd_byte *contents,
Elf_Internal_Rela *relocs,
Elf_Internal_Sym *local_syms,
asection **local_sections)
{
Elf_Internal_Shdr *symtab_hdr;
struct elf_link_hash_entry **sym_hashes;
@ -462,7 +429,7 @@ elf32_d10v_relocate_section (output_bfd, info, input_bfd, input_section,
r_type = ELF32_R_TYPE (rel->r_info);
if (r_type == R_D10V_GNU_VTENTRY
|| r_type == R_D10V_GNU_VTINHERIT )
|| r_type == R_D10V_GNU_VTINHERIT)
continue;
howto = elf_d10v_howto_table + r_type;
@ -552,7 +519,7 @@ elf32_d10v_relocate_section (output_bfd, info, input_bfd, input_section,
{
case bfd_reloc_overflow:
if (!((*info->callbacks->reloc_overflow)
(info, (h ? &h->root : NULL), name, howto->name,
(info, (h ? &h->root : NULL), name, howto->name,
(bfd_vma) 0, input_bfd, input_section,
rel->r_offset)))
return FALSE;

551
bfd/elf32-d30v.c
View File

@ -1,23 +1,24 @@
/* D30V-specific support for 32-bit ELF
Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
Free Software Foundation, Inc.
Contributed by Martin Hunt (hunt@cygnus.com).
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -25,240 +26,17 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#include "elf-bfd.h"
#include "elf/d30v.h"
static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
PARAMS ((bfd *abfd, bfd_reloc_code_real_type code));
static void d30v_info_to_howto_rel
PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
static void d30v_info_to_howto_rela
PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
static bfd_reloc_status_type bfd_elf_d30v_reloc PARAMS ((
bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
PTR data,
asection *input_section,
bfd *output_bfd,
char **error_message));
static bfd_reloc_status_type bfd_elf_d30v_reloc_21 PARAMS ((
bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
PTR data,
asection *input_section,
bfd *output_bfd,
char **error_message));
static reloc_howto_type elf_d30v_howto_table[] =
{
/* This reloc does nothing. */
HOWTO (R_D30V_NONE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_D30V_NONE", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* A 6 bit absolute relocation */
HOWTO (R_D30V_6, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
6, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_D30V_6", /* name */
FALSE, /* partial_inplace */
0x3f, /* src_mask */
0x3f, /* dst_mask */
FALSE), /* pcrel_offset */
/* A relative 9 bit relocation, right shifted by 3 */
HOWTO (R_D30V_9_PCREL, /* type */
3, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
6, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_d30v_reloc_21, /* special_function */
"R_D30V_9_PCREL", /* name */
FALSE, /* partial_inplace */
0x3f, /* src_mask */
0x3f, /* dst_mask */
TRUE), /* pcrel_offset */
/* A relative 9 bit relocation, right shifted by 3 */
HOWTO (R_D30V_9_PCREL_R, /* type */
3, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
6, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_d30v_reloc_21, /* special_function */
"R_D30V_9_PCREL_R", /* name */
FALSE, /* partial_inplace */
0x3f, /* src_mask */
0x3f, /* dst_mask */
TRUE), /* pcrel_offset */
/* An absolute 15 bit relocation, right shifted by 3 */
HOWTO (R_D30V_15, /* type */
3, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
12, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_D30V_15", /* name */
FALSE, /* partial_inplace */
0xfff, /* src_mask */
0xfff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A relative 15 bit relocation, right shifted by 3 */
HOWTO (R_D30V_15_PCREL, /* type */
3, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
12, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_d30v_reloc_21, /* special_function */
"R_D30V_15_PCREL", /* name */
FALSE, /* partial_inplace */
0xfff, /* src_mask */
0xfff, /* dst_mask */
TRUE), /* pcrel_offset */
/* A relative 15 bit relocation, right shifted by 3 */
HOWTO (R_D30V_15_PCREL_R, /* type */
3, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
12, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_d30v_reloc_21, /* special_function */
"R_D30V_15_PCREL_R", /* name */
FALSE, /* partial_inplace */
0xfff, /* src_mask */
0xfff, /* dst_mask */
TRUE), /* pcrel_offset */
/* An absolute 21 bit relocation, right shifted by 3 */
HOWTO (R_D30V_21, /* type */
3, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
18, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_D30V_21", /* name */
FALSE, /* partial_inplace */
0x3ffff, /* src_mask */
0x3ffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A relative 21 bit relocation, right shifted by 3 */
HOWTO (R_D30V_21_PCREL, /* type */
3, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
18, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_d30v_reloc_21, /* special_function */
"R_D30V_21_PCREL", /* name */
FALSE, /* partial_inplace */
0x3ffff, /* src_mask */
0x3ffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* A relative 21 bit relocation, right shifted by 3, in the Right container */
HOWTO (R_D30V_21_PCREL_R, /* type */
3, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
18, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_d30v_reloc_21, /* special_function */
"R_D30V_21_PCREL_R", /* name */
FALSE, /* partial_inplace */
0x3ffff, /* src_mask */
0x3ffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* A D30V 32 bit absolute relocation */
HOWTO (R_D30V_32, /* type */
0, /* rightshift */
4, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_d30v_reloc, /* special_function */
"R_D30V_32", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A relative 32 bit relocation */
HOWTO (R_D30V_32_PCREL, /* type */
0, /* rightshift */
4, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_d30v_reloc, /* special_function */
"R_D30V_32_PCREL", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* A regular 32 bit absolute relocation */
HOWTO (R_D30V_32_NORMAL, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_D30V_32_NORMAL", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
};
#define MAX32 ((bfd_signed_vma) 0x7fffffff)
#define MIN32 (- MAX32 - 1)
static bfd_reloc_status_type
bfd_elf_d30v_reloc (abfd, reloc_entry, symbol, data, input_section, output_bfd, error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message;
bfd_elf_d30v_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message)
{
bfd_signed_vma relocation;
bfd_vma in1, in2, num;
@ -271,7 +49,7 @@ bfd_elf_d30v_reloc (abfd, reloc_entry, symbol, data, input_section, output_bfd,
reloc_howto_type *howto = reloc_entry->howto;
int make_absolute = 0;
if (output_bfd != (bfd *) NULL)
if (output_bfd != NULL)
{
/* Partial linking -- do nothing. */
reloc_entry->address += input_section->output_offset;
@ -283,10 +61,10 @@ bfd_elf_d30v_reloc (abfd, reloc_entry, symbol, data, input_section, output_bfd,
if (r != bfd_reloc_continue)
return r;
/* a hacked-up version of bfd_perform_reloc() follows */
/* A hacked-up version of bfd_perform_reloc() follows. */
if (bfd_is_und_section (symbol->section)
&& (symbol->flags & BSF_WEAK) == 0
&& output_bfd == (bfd *) NULL)
&& output_bfd == NULL)
flag = bfd_reloc_undefined;
/* Is the address of the relocation really within the section? */
@ -313,10 +91,10 @@ bfd_elf_d30v_reloc (abfd, reloc_entry, symbol, data, input_section, output_bfd,
/* Here the variable relocation holds the final address of the
symbol we are relocating against, plus any addend. */
if (howto->pc_relative)
{
tmp_addr = input_section->output_section->vma + input_section->output_offset
tmp_addr = input_section->output_section->vma
+ input_section->output_offset
+ reloc_entry->address;
relocation -= tmp_addr;
}
@ -324,7 +102,7 @@ bfd_elf_d30v_reloc (abfd, reloc_entry, symbol, data, input_section, output_bfd,
in1 = bfd_get_32 (abfd, (bfd_byte *) data + addr);
in2 = bfd_get_32 (abfd, (bfd_byte *) data + addr + 4);
/* extract the addend */
/* Extract the addend. */
num = ((in2 & 0x3FFFF)
| ((in2 & 0xFF00000) >> 2)
| ((in1 & 0x3F) << 26));
@ -345,12 +123,12 @@ bfd_elf_d30v_reloc (abfd, reloc_entry, symbol, data, input_section, output_bfd,
}
}
in1 |= (relocation >> 26) & 0x3F; /* top 6 bits */
in2 |= ((relocation & 0x03FC0000) << 2); /* next 8 bits */
in2 |= relocation & 0x0003FFFF; /* bottom 18 bits */
in1 |= (relocation >> 26) & 0x3F; /* Top 6 bits. */
in2 |= ((relocation & 0x03FC0000) << 2); /* Next 8 bits. */
in2 |= relocation & 0x0003FFFF; /* Bottom 18 bits. */
/* change a PC-relative instruction to its absolute equivalent */
/* with this simple hack */
/* Change a PC-relative instruction to its
absolute equivalent with this simple hack. */
if (make_absolute)
in1 |= 0x00100000;
@ -361,14 +139,13 @@ bfd_elf_d30v_reloc (abfd, reloc_entry, symbol, data, input_section, output_bfd,
}
static bfd_reloc_status_type
bfd_elf_d30v_reloc_21 (abfd, reloc_entry, symbol, data, input_section, output_bfd, error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message;
bfd_elf_d30v_reloc_21 (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message)
{
bfd_vma relocation;
bfd_vma in1, num;
@ -380,7 +157,7 @@ bfd_elf_d30v_reloc_21 (abfd, reloc_entry, symbol, data, input_section, output_bf
reloc_howto_type *howto = reloc_entry->howto;
int mask, max;
if (output_bfd != (bfd *) NULL)
if (output_bfd != NULL)
{
/* Partial linking -- do nothing. */
reloc_entry->address += input_section->output_offset;
@ -392,10 +169,10 @@ bfd_elf_d30v_reloc_21 (abfd, reloc_entry, symbol, data, input_section, output_bf
if (r != bfd_reloc_continue)
return r;
/* a hacked-up version of bfd_perform_reloc() follows */
if (bfd_is_und_section (symbol->section)
/* A hacked-up version of bfd_perform_reloc() follows. */
if (bfd_is_und_section (symbol->section)
&& (symbol->flags & BSF_WEAK) == 0
&& output_bfd == (bfd *) NULL)
&& output_bfd == NULL)
flag = bfd_reloc_undefined;
/* Is the address of the relocation really within the section? */
@ -438,30 +215,30 @@ bfd_elf_d30v_reloc_21 (abfd, reloc_entry, symbol, data, input_section, output_bf
mask <<= 12;
max = (1 << (howto->bitsize + 2)) - 1;
/* extract the addend */
num = in1 & mask; /* 18 bits */
/* Extract the addend. */
num = in1 & mask; /* 18 bits. */
if (howto->bitsize == 6)
num >>= 12;
num <<= 3; /* shift left 3 */
in1 &= ~mask; /* mask out addend */
num <<= 3; /* shift left 3. */
in1 &= ~mask; /* Mask out addend. */
relocation += num;
if (howto->type == R_D30V_21_PCREL_R || howto->type == R_D30V_15_PCREL_R ||
howto->type == R_D30V_9_PCREL_R )
{
relocation += 4;
}
if (howto->type == R_D30V_21_PCREL_R
|| howto->type == R_D30V_15_PCREL_R
|| howto->type == R_D30V_9_PCREL_R)
relocation += 4;
if ((int)relocation < 0 )
if ((int) relocation < 0)
{
if (~(int)relocation > max)
if (~ (int) relocation > max)
flag = bfd_reloc_overflow;
}
else
{
if ((int)relocation > max)
if ((int) relocation > max)
flag = bfd_reloc_overflow;
}
relocation >>= 3;
if (howto->bitsize == 6)
in1 |= ((relocation & (mask >> 12)) << 12);
@ -473,6 +250,205 @@ bfd_elf_d30v_reloc_21 (abfd, reloc_entry, symbol, data, input_section, output_bf
return flag;
}
static reloc_howto_type elf_d30v_howto_table[] =
{
/* This reloc does nothing. */
HOWTO (R_D30V_NONE, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
32, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_bitfield, /* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_D30V_NONE", /* Name. */
FALSE, /* Partial_inplace. */
0, /* Src_mask. */
0, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* A 6 bit absolute relocation. */
HOWTO (R_D30V_6, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
6, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_bitfield, /* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_D30V_6", /* Name. */
FALSE, /* Partial_inplace. */
0x3f, /* Src_mask. */
0x3f, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* A relative 9 bit relocation, right shifted by 3. */
HOWTO (R_D30V_9_PCREL, /* Type. */
3, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
6, /* Bitsize. */
TRUE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_signed, /* Complain_on_overflow. */
bfd_elf_d30v_reloc_21, /* Special_function. */
"R_D30V_9_PCREL", /* Name. */
FALSE, /* Partial_inplace. */
0x3f, /* Src_mask. */
0x3f, /* Dst_mask. */
TRUE), /* PCrel_offset. */
/* A relative 9 bit relocation, right shifted by 3. */
HOWTO (R_D30V_9_PCREL_R, /* Type. */
3, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
6, /* Bitsize. */
TRUE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_signed, /* Complain_on_overflow. */
bfd_elf_d30v_reloc_21, /* Special_function. */
"R_D30V_9_PCREL_R", /* Name. */
FALSE, /* Partial_inplace. */
0x3f, /* Src_mask. */
0x3f, /* Dst_mask. */
TRUE), /* PCrel_offset. */
/* An absolute 15 bit relocation, right shifted by 3. */
HOWTO (R_D30V_15, /* Type. */
3, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
12, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_signed, /* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_D30V_15", /* Name. */
FALSE, /* Partial_inplace. */
0xfff, /* Src_mask. */
0xfff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* A relative 15 bit relocation, right shifted by 3. */
HOWTO (R_D30V_15_PCREL, /* Type. */
3, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
12, /* Bitsize. */
TRUE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_signed, /* Complain_on_overflow. */
bfd_elf_d30v_reloc_21, /* Special_function. */
"R_D30V_15_PCREL", /* Name. */
FALSE, /* Partial_inplace. */
0xfff, /* Src_mask. */
0xfff, /* Dst_mask. */
TRUE), /* PCrel_offset. */
/* A relative 15 bit relocation, right shifted by 3. */
HOWTO (R_D30V_15_PCREL_R, /* Type. */
3, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
12, /* Bitsize. */
TRUE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_signed, /* Complain_on_overflow. */
bfd_elf_d30v_reloc_21, /* Special_function. */
"R_D30V_15_PCREL_R", /* Name. */
FALSE, /* Partial_inplace. */
0xfff, /* Src_mask. */
0xfff, /* Dst_mask. */
TRUE), /* PCrel_offset. */
/* An absolute 21 bit relocation, right shifted by 3. */
HOWTO (R_D30V_21, /* Type. */
3, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
18, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_signed, /* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_D30V_21", /* Name. */
FALSE, /* Partial_inplace. */
0x3ffff, /* Src_mask. */
0x3ffff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* A relative 21 bit relocation, right shifted by 3. */
HOWTO (R_D30V_21_PCREL, /* Type. */
3, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
18, /* Bitsize. */
TRUE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_signed, /* Complain_on_overflow. */
bfd_elf_d30v_reloc_21, /* Special_function. */
"R_D30V_21_PCREL", /* Name. */
FALSE, /* Partial_inplace. */
0x3ffff, /* Src_mask. */
0x3ffff, /* Dst_mask. */
TRUE), /* PCrel_offset. */
/* A relative 21 bit relocation, right shifted by 3, in the Right container. */
HOWTO (R_D30V_21_PCREL_R, /* Type. */
3, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
18, /* Bitsize. */
TRUE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_signed, /* Complain_on_overflow. */
bfd_elf_d30v_reloc_21, /* Special_function. */
"R_D30V_21_PCREL_R", /* Name. */
FALSE, /* Partial_inplace. */
0x3ffff, /* Src_mask. */
0x3ffff, /* Dst_mask. */
TRUE), /* PCrel_offset. */
/* A D30V 32 bit absolute relocation. */
HOWTO (R_D30V_32, /* Type. */
0, /* Rightshift. */
4, /* Size (0 = byte, 1 = short, 2 = long). */
32, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_bitfield, /* Complain_on_overflow. */
bfd_elf_d30v_reloc, /* Special_function. */
"R_D30V_32", /* Name. */
FALSE, /* Partial_inplace. */
0xffffffff, /* Src_mask. */
0xffffffff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* A relative 32 bit relocation. */
HOWTO (R_D30V_32_PCREL, /* Type. */
0, /* Rightshift. */
4, /* Size (0 = byte, 1 = short, 2 = long). */
32, /* Bitsize. */
TRUE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_signed, /* Complain_on_overflow. */
bfd_elf_d30v_reloc, /* Special_function. */
"R_D30V_32_PCREL", /* Name. */
FALSE, /* Partial_inplace. */
0xffffffff, /* Src_mask. */
0xffffffff, /* Dst_mask. */
TRUE), /* PCrel_offset. */
/* A regular 32 bit absolute relocation. */
HOWTO (R_D30V_32_NORMAL, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
32, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_bitfield, /* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_D30V_32_NORMAL", /* Name. */
FALSE, /* Partial_inplace. */
0xffffffff, /* Src_mask. */
0xffffffff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
};
/* Map BFD reloc types to D30V ELF reloc types. */
struct d30v_reloc_map
@ -499,9 +475,8 @@ static const struct d30v_reloc_map d30v_reloc_map[] =
};
static reloc_howto_type *
bfd_elf32_bfd_reloc_type_lookup (abfd, code)
bfd *abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
@ -519,10 +494,9 @@ bfd_elf32_bfd_reloc_type_lookup (abfd, code)
/* Set the howto pointer for an D30V ELF reloc (type REL). */
static void
d30v_info_to_howto_rel (abfd, cache_ptr, dst)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *cache_ptr;
Elf_Internal_Rela *dst;
d30v_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
arelent *cache_ptr,
Elf_Internal_Rela *dst)
{
unsigned int r_type;
@ -534,10 +508,9 @@ d30v_info_to_howto_rel (abfd, cache_ptr, dst)
/* Set the howto pointer for an D30V ELF reloc (type RELA). */
static void
d30v_info_to_howto_rela (abfd, cache_ptr, dst)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *cache_ptr;
Elf_Internal_Rela *dst;
d30v_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED,
arelent *cache_ptr,
Elf_Internal_Rela *dst)
{
unsigned int r_type;

446
bfd/elf32-dlx.c
View File

@ -15,7 +15,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -23,27 +24,6 @@
#include "elf-bfd.h"
#include "elf/dlx.h"
int set_dlx_skip_hi16_flag PARAMS ((int));
static bfd_boolean elf32_dlx_check_relocs
PARAMS ((bfd *, struct bfd_link_info *, asection *,
const Elf_Internal_Rela *));
static void elf32_dlx_info_to_howto
PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
static void elf32_dlx_info_to_howto_rel
PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
static bfd_reloc_status_type elf32_dlx_relocate16
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
static bfd_reloc_status_type elf32_dlx_relocate26
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
static reloc_howto_type *elf32_dlx_reloc_type_lookup
PARAMS ((bfd *, bfd_reloc_code_real_type));
static bfd_reloc_status_type _bfd_dlx_elf_hi16_reloc
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
static reloc_howto_type * dlx_rtype_to_howto
PARAMS ((unsigned int));
#define USE_REL 1
#define bfd_elf32_bfd_reloc_type_lookup elf32_dlx_reloc_type_lookup
@ -51,164 +31,6 @@ static reloc_howto_type * dlx_rtype_to_howto
#define elf_info_to_howto_rel elf32_dlx_info_to_howto_rel
#define elf_backend_check_relocs elf32_dlx_check_relocs
static reloc_howto_type dlx_elf_howto_table[]=
{
/* No relocation. */
HOWTO (R_DLX_NONE, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_DLX_NONE", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* 8 bit relocation. */
HOWTO (R_DLX_RELOC_8, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_DLX_RELOC_8", /* name */
TRUE, /* partial_inplace */
0xff, /* src_mask */
0xff, /* dst_mask */
FALSE), /* pcrel_offset */
/* 16 bit relocation. */
HOWTO (R_DLX_RELOC_16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_DLX_RELOC_16", /* name */
TRUE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* 32 bit relocation. */
HOWTO (R_DLX_RELOC_32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_DLX_RELOC_32", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* GNU extension to record C++ vtable hierarchy */
HOWTO (R_DLX_GNU_VTINHERIT, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
NULL, /* special_function */
"R_DLX_GNU_VTINHERIT", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* GNU extension to record C++ vtable member usage */
HOWTO (R_DLX_GNU_VTENTRY, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
_bfd_elf_rel_vtable_reloc_fn,/* special_function */
"R_DLX_GNU_VTENTRY", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE) /* pcrel_offset */
};
/* 16 bit offset for pc-relative branches. */
static reloc_howto_type elf_dlx_gnu_rel16_s2 =
HOWTO (R_DLX_RELOC_16_PCREL, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
elf32_dlx_relocate16, /* special_function */
"R_DLX_RELOC_16_PCREL",/* name */
TRUE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE); /* pcrel_offset */
/* 26 bit offset for pc-relative branches. */
static reloc_howto_type elf_dlx_gnu_rel26_s2 =
HOWTO (R_DLX_RELOC_26_PCREL, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
26, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
elf32_dlx_relocate26, /* special_function */
"R_DLX_RELOC_26_PCREL",/* name */
TRUE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE); /* pcrel_offset */
/* High 16 bits of symbol value. */
static reloc_howto_type elf_dlx_reloc_16_hi =
HOWTO (R_DLX_RELOC_16_HI, /* type */
16, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
_bfd_dlx_elf_hi16_reloc,/* special_function */
"R_DLX_RELOC_16_HI", /* name */
TRUE, /* partial_inplace */
0xFFFF, /* src_mask */
0xffff, /* dst_mask */
FALSE); /* pcrel_offset */
/* Low 16 bits of symbol value. */
static reloc_howto_type elf_dlx_reloc_16_lo =
HOWTO (R_DLX_RELOC_16_LO, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_DLX_RELOC_16_LO", /* name */
TRUE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
FALSE); /* pcrel_offset */
/* The gas default behavior is not to preform the %hi modifier so that the
GNU assembler can have the lower 16 bits offset placed in the insn, BUT
we do like the gas to indicate it is %hi reloc type so when we in the link
@ -217,24 +39,23 @@ HOWTO (R_DLX_RELOC_16_LO, /* type */
static int skip_dlx_elf_hi16_reloc = 0;
extern int set_dlx_skip_hi16_flag (int);
int
set_dlx_skip_hi16_flag (flag)
int flag;
set_dlx_skip_hi16_flag (int flag)
{
skip_dlx_elf_hi16_reloc = flag;
return flag;
}
static bfd_reloc_status_type
_bfd_dlx_elf_hi16_reloc (abfd, reloc_entry, symbol, data,
input_section, output_bfd, error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message;
_bfd_dlx_elf_hi16_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message)
{
bfd_reloc_status_type ret;
bfd_vma relocation;
@ -288,15 +109,13 @@ _bfd_dlx_elf_hi16_reloc (abfd, reloc_entry, symbol, data,
relocatable output against an external symbol. */
static bfd_reloc_status_type
elf32_dlx_relocate16 (abfd, reloc_entry, symbol, data,
input_section, output_bfd, error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message ATTRIBUTE_UNUSED;
elf32_dlx_relocate16 (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
unsigned long insn, vallo, allignment;
int val;
@ -310,12 +129,12 @@ elf32_dlx_relocate16 (abfd, reloc_entry, symbol, data,
return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data,
input_section, output_bfd, error_message);
/* Check undefined section and undefined symbols */
/* Check undefined section and undefined symbols. */
if (bfd_is_und_section (symbol->section)
&& output_bfd == (bfd *) NULL)
return bfd_reloc_undefined;
/* Can not support a long jump to sections other then .text */
/* Can not support a long jump to sections other then .text. */
if (strcmp (input_section->name, symbol->section->output_section->name) != 0)
{
fprintf (stderr,
@ -353,15 +172,13 @@ elf32_dlx_relocate16 (abfd, reloc_entry, symbol, data,
}
static bfd_reloc_status_type
elf32_dlx_relocate26 (abfd, reloc_entry, symbol, data,
input_section, output_bfd, error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message ATTRIBUTE_UNUSED;
elf32_dlx_relocate26 (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
unsigned long insn, vallo, allignment;
int val;
@ -416,6 +233,163 @@ elf32_dlx_relocate26 (abfd, reloc_entry, symbol, data,
return bfd_reloc_ok;
}
static reloc_howto_type dlx_elf_howto_table[]=
{
/* No relocation. */
HOWTO (R_DLX_NONE, /* Type. */
0, /* Rightshift. */
0, /* size (0 = byte, 1 = short, 2 = long). */
0, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_DLX_NONE", /* Name. */
FALSE, /* Partial_inplace. */
0, /* Src_mask. */
0, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* 8 bit relocation. */
HOWTO (R_DLX_RELOC_8, /* Type. */
0, /* Rightshift. */
0, /* Size (0 = byte, 1 = short, 2 = long). */
8, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_DLX_RELOC_8", /* Name. */
TRUE, /* Partial_inplace. */
0xff, /* Src_mask. */
0xff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* 16 bit relocation. */
HOWTO (R_DLX_RELOC_16, /* Type. */
0, /* Rightshift. */
1, /* Size (0 = byte, 1 = short, 2 = long). */
16, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_DLX_RELOC_16", /* Name. */
TRUE, /* Partial_inplace. */
0xffff, /* Src_mask. */
0xffff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* 32 bit relocation. */
HOWTO (R_DLX_RELOC_32, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
32, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_DLX_RELOC_32", /* Name. */
TRUE, /* Partial_inplace. */
0xffffffff, /* Src_mask. */
0xffffffff, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* GNU extension to record C++ vtable hierarchy. */
HOWTO (R_DLX_GNU_VTINHERIT, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
0, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
NULL, /* Special_function. */
"R_DLX_GNU_VTINHERIT", /* Name. */
FALSE, /* Partial_inplace. */
0, /* Src_mask. */
0, /* Dst_mask. */
FALSE), /* PCrel_offset. */
/* GNU extension to record C++ vtable member usage. */
HOWTO (R_DLX_GNU_VTENTRY, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
0, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
_bfd_elf_rel_vtable_reloc_fn,/* Special_function. */
"R_DLX_GNU_VTENTRY", /* Name. */
FALSE, /* Partial_inplace. */
0, /* Src_mask. */
0, /* Dst_mask. */
FALSE) /* PCrel_offset. */
};
/* 16 bit offset for pc-relative branches. */
static reloc_howto_type elf_dlx_gnu_rel16_s2 =
HOWTO (R_DLX_RELOC_16_PCREL, /* Type. */
0, /* Rightshift. */
1, /* Size (0 = byte, 1 = short, 2 = long). */
16, /* Bitsize. */
TRUE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_signed, /* Complain_on_overflow. */
elf32_dlx_relocate16, /* Special_function. */
"R_DLX_RELOC_16_PCREL",/* Name. */
TRUE, /* Partial_inplace. */
0xffff, /* Src_mask. */
0xffff, /* Dst_mask. */
TRUE); /* PCrel_offset. */
/* 26 bit offset for pc-relative branches. */
static reloc_howto_type elf_dlx_gnu_rel26_s2 =
HOWTO (R_DLX_RELOC_26_PCREL, /* Type. */
0, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
26, /* Bitsize. */
TRUE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
elf32_dlx_relocate26, /* Special_function. */
"R_DLX_RELOC_26_PCREL",/* Name. */
TRUE, /* Partial_inplace. */
0xffff, /* Src_mask. */
0xffff, /* Dst_mask. */
TRUE); /* PCrel_offset. */
/* High 16 bits of symbol value. */
static reloc_howto_type elf_dlx_reloc_16_hi =
HOWTO (R_DLX_RELOC_16_HI, /* Type. */
16, /* Rightshift. */
2, /* Size (0 = byte, 1 = short, 2 = long). */
32, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
_bfd_dlx_elf_hi16_reloc,/* Special_function. */
"R_DLX_RELOC_16_HI", /* Name. */
TRUE, /* Partial_inplace. */
0xFFFF, /* Src_mask. */
0xffff, /* Dst_mask. */
FALSE); /* PCrel_offset. */
/* Low 16 bits of symbol value. */
static reloc_howto_type elf_dlx_reloc_16_lo =
HOWTO (R_DLX_RELOC_16_LO, /* Type. */
0, /* Rightshift. */
1, /* Size (0 = byte, 1 = short, 2 = long). */
16, /* Bitsize. */
FALSE, /* PC_relative. */
0, /* Bitpos. */
complain_overflow_dont,/* Complain_on_overflow. */
bfd_elf_generic_reloc, /* Special_function. */
"R_DLX_RELOC_16_LO", /* Name. */
TRUE, /* Partial_inplace. */
0xffff, /* Src_mask. */
0xffff, /* Dst_mask. */
FALSE); /* PCrel_offset. */
/* A mapping from BFD reloc types to DLX ELF reloc types.
Stolen from elf32-mips.c.
@ -431,27 +405,25 @@ struct elf_reloc_map
};
static const struct elf_reloc_map dlx_reloc_map[] =
{
{ BFD_RELOC_NONE, R_DLX_NONE },
{ BFD_RELOC_16, R_DLX_RELOC_16 },
{ BFD_RELOC_32, R_DLX_RELOC_32 },
{ BFD_RELOC_DLX_HI16_S, R_DLX_RELOC_16_HI },
{ BFD_RELOC_DLX_LO16, R_DLX_RELOC_16_LO },
{ BFD_RELOC_VTABLE_INHERIT, R_DLX_GNU_VTINHERIT },
{ BFD_RELOC_VTABLE_ENTRY, R_DLX_GNU_VTENTRY }
};
{
{ BFD_RELOC_NONE, R_DLX_NONE },
{ BFD_RELOC_16, R_DLX_RELOC_16 },
{ BFD_RELOC_32, R_DLX_RELOC_32 },
{ BFD_RELOC_DLX_HI16_S, R_DLX_RELOC_16_HI },
{ BFD_RELOC_DLX_LO16, R_DLX_RELOC_16_LO },
{ BFD_RELOC_VTABLE_INHERIT, R_DLX_GNU_VTINHERIT },
{ BFD_RELOC_VTABLE_ENTRY, R_DLX_GNU_VTENTRY }
};
/* Look through the relocs for a section during the first phase.
Since we don't do .gots or .plts, we just need to consider the
virtual table relocs for gc. */
static bfd_boolean
elf32_dlx_check_relocs (abfd, info, sec, relocs)
bfd *abfd;
struct bfd_link_info *info;
asection *sec;
const Elf_Internal_Rela *relocs;
elf32_dlx_check_relocs (bfd *abfd,
struct bfd_link_info *info,
asection *sec,
const Elf_Internal_Rela *relocs)
{
Elf_Internal_Shdr *symtab_hdr;
struct elf_link_hash_entry **sym_hashes, **sym_hashes_end;
@ -508,9 +480,8 @@ elf32_dlx_check_relocs (abfd, info, sec, relocs)
/* Given a BFD reloc type, return a howto structure. */
static reloc_howto_type *
elf32_dlx_reloc_type_lookup (abfd, code)
bfd *abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
elf32_dlx_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
@ -535,8 +506,7 @@ elf32_dlx_reloc_type_lookup (abfd, code)
}
static reloc_howto_type *
dlx_rtype_to_howto (r_type)
unsigned int r_type;
dlx_rtype_to_howto (unsigned int r_type)
{
switch (r_type)
{
@ -561,19 +531,17 @@ dlx_rtype_to_howto (r_type)
}
static void
elf32_dlx_info_to_howto (abfd, cache_ptr, dst)
bfd * abfd ATTRIBUTE_UNUSED;
arelent * cache_ptr ATTRIBUTE_UNUSED;
Elf_Internal_Rela * dst ATTRIBUTE_UNUSED;
elf32_dlx_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
arelent * cache_ptr ATTRIBUTE_UNUSED,
Elf_Internal_Rela * dst ATTRIBUTE_UNUSED)
{
abort ();
}
static void
elf32_dlx_info_to_howto_rel (abfd, cache_ptr, dst)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *cache_ptr;
Elf_Internal_Rela *dst;
elf32_dlx_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
arelent *cache_ptr,
Elf_Internal_Rela *dst)
{
unsigned int r_type;

381
bfd/elf32-i370.c
View File

@ -1,31 +1,31 @@
/* i370-specific support for 32-bit ELF
Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004
Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, 2005
Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support.
Hacked by Linas Vepstas for i370 linas@linas.org
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* This file is based on a preliminary PowerPC ELF ABI.
But its been hacked on for the IBM 360/370 architectures.
Basically, the 31bit relocation works, and just about everything
else is a wild card. In particular, don't expect shared libs or
dynamic loading to work ... its never been tested ...
*/
dynamic loading to work ... its never been tested. */
#include "bfd.h"
#include "sysdep.h"
@ -98,7 +98,7 @@ static reloc_howto_type i370_elf_howto_raw[] =
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* 31-bit PC relative */
/* 31-bit PC relative. */
HOWTO (R_I370_REL31, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@ -113,7 +113,7 @@ static reloc_howto_type i370_elf_howto_raw[] =
0x7fffffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* 32-bit PC relative */
/* 32-bit PC relative. */
HOWTO (R_I370_REL32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@ -143,7 +143,7 @@ static reloc_howto_type i370_elf_howto_raw[] =
0xfff, /* dst_mask */
FALSE), /* pcrel_offset */
/* 12-bit PC relative */
/* 12-bit PC relative. */
HOWTO (R_I370_REL12, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
@ -173,7 +173,7 @@ static reloc_howto_type i370_elf_howto_raw[] =
0xff, /* dst_mask */
FALSE), /* pcrel_offset */
/* 8-bit PC relative */
/* 8-bit PC relative. */
HOWTO (R_I370_REL8, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
@ -226,19 +226,10 @@ static reloc_howto_type i370_elf_howto_raw[] =
};
static void i370_elf_howto_init
PARAMS ((void));
static reloc_howto_type *i370_elf_reloc_type_lookup
PARAMS ((bfd *, bfd_reloc_code_real_type));
static void i370_elf_info_to_howto
PARAMS ((bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst));
static bfd_boolean i370_elf_set_private_flags
PARAMS ((bfd *, flagword));
/* Initialize the i370_elf_howto_table, so that linear accesses can be done. */
static void
i370_elf_howto_init ()
i370_elf_howto_init (void)
{
unsigned int i, type;
@ -249,21 +240,21 @@ i370_elf_howto_init ()
i370_elf_howto_table[type] = &i370_elf_howto_raw[i];
}
}
static reloc_howto_type *
i370_elf_reloc_type_lookup (abfd, code)
bfd *abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
i370_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
enum i370_reloc_type i370_reloc = R_I370_NONE;
if (!i370_elf_howto_table[ R_I370_ADDR31 ]) /* Initialize howto table if needed */
if (!i370_elf_howto_table[ R_I370_ADDR31 ])
/* Initialize howto table if needed. */
i370_elf_howto_init ();
switch ((int)code)
switch ((int) code)
{
default:
return (reloc_howto_type *)NULL;
return NULL;
case BFD_RELOC_NONE: i370_reloc = R_I370_NONE; break;
case BFD_RELOC_32: i370_reloc = R_I370_ADDR31; break;
@ -276,30 +267,6 @@ i370_elf_reloc_type_lookup (abfd, code)
return i370_elf_howto_table[ (int)i370_reloc ];
};
static bfd_boolean i370_elf_merge_private_bfd_data
PARAMS ((bfd *, bfd *));
static bfd_boolean i370_elf_relocate_section
PARAMS ((bfd *, struct bfd_link_info *info, bfd *, asection *, bfd_byte *,
Elf_Internal_Rela *relocs, Elf_Internal_Sym *local_syms,
asection **));
static void i370_elf_post_process_headers
PARAMS ((bfd *, struct bfd_link_info *));
static bfd_boolean i370_elf_create_dynamic_sections
PARAMS ((bfd *, struct bfd_link_info *));
static bfd_boolean i370_elf_fake_sections
PARAMS ((bfd *, Elf_Internal_Shdr *, asection *));
static bfd_boolean i370_elf_check_relocs
PARAMS ((bfd *, struct bfd_link_info *, asection *,
const Elf_Internal_Rela *));
static bfd_boolean i370_elf_adjust_dynamic_symbol
PARAMS ((struct bfd_link_info *, struct elf_link_hash_entry *));
static bfd_boolean i370_elf_adjust_dynindx
PARAMS ((struct elf_link_hash_entry *, PTR));
static bfd_boolean i370_elf_size_dynamic_sections
PARAMS ((bfd *, struct bfd_link_info *));
static bfd_boolean i370_elf_finish_dynamic_sections
PARAMS ((bfd *, struct bfd_link_info *));
/* The name of the dynamic interpreter. This is put in the .interp
section. */
@ -308,26 +275,24 @@ static bfd_boolean i370_elf_finish_dynamic_sections
/* Set the howto pointer for an i370 ELF reloc. */
static void
i370_elf_info_to_howto (abfd, cache_ptr, dst)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *cache_ptr;
Elf_Internal_Rela *dst;
i370_elf_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
arelent *cache_ptr,
Elf_Internal_Rela *dst)
{
if (!i370_elf_howto_table[ R_I370_ADDR31 ]) /* Initialize howto table */
if (!i370_elf_howto_table[ R_I370_ADDR31 ])
/* Initialize howto table. */
i370_elf_howto_init ();
BFD_ASSERT (ELF32_R_TYPE (dst->r_info) < (unsigned int) R_I370_max);
cache_ptr->howto = i370_elf_howto_table[ELF32_R_TYPE (dst->r_info)];
}
/* hack alert -- the following several routines look generic to me ...
* why are we bothering with them ???
*/
/* Hack alert -- the following several routines look generic to me ...
why are we bothering with them ? */
/* Function to set whether a module needs the -mrelocatable bit set. */
static bfd_boolean
i370_elf_set_private_flags (abfd, flags)
bfd *abfd;
flagword flags;
i370_elf_set_private_flags (bfd *abfd, flagword flags)
{
BFD_ASSERT (!elf_flags_init (abfd)
|| elf_elfheader (abfd)->e_flags == flags);
@ -338,11 +303,10 @@ i370_elf_set_private_flags (abfd, flags)
}
/* Merge backend specific data from an object file to the output
object file when linking */
object file when linking. */
static bfd_boolean
i370_elf_merge_private_bfd_data (ibfd, obfd)
bfd *ibfd;
bfd *obfd;
i370_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd)
{
flagword old_flags;
flagword new_flags;
@ -353,16 +317,16 @@ i370_elf_merge_private_bfd_data (ibfd, obfd)
new_flags = elf_elfheader (ibfd)->e_flags;
old_flags = elf_elfheader (obfd)->e_flags;
if (!elf_flags_init (obfd)) /* First call, no flags set */
if (!elf_flags_init (obfd)) /* First call, no flags set. */
{
elf_flags_init (obfd) = TRUE;
elf_elfheader (obfd)->e_flags = new_flags;
}
else if (new_flags == old_flags) /* Compatible flags are ok */
else if (new_flags == old_flags) /* Compatible flags are ok. */
;
else /* Incompatible flags */
else /* Incompatible flags. */
{
(*_bfd_error_handler)
("%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)",
@ -378,9 +342,8 @@ i370_elf_merge_private_bfd_data (ibfd, obfd)
/* Handle an i370 specific section when reading an object file. This
is called when elfcode.h finds a section with an unknown type. */
/* XXX hack alert bogus This routine is mostly all junk and almost
* certainly does the wrong thing. Its here simply because it does
* just enough to allow glibc-2.1 ld.so to compile & link.
*/
certainly does the wrong thing. Its here simply because it does
just enough to allow glibc-2.1 ld.so to compile & link. */
static bfd_boolean
i370_elf_section_from_shdr (bfd *abfd,
@ -408,15 +371,13 @@ i370_elf_section_from_shdr (bfd *abfd,
/* Set up any other section flags and such that may be necessary. */
/* XXX hack alert bogus This routine is mostly all junk and almost
* certainly does the wrong thing. Its here simply because it does
* just enough to allow glibc-2.1 ld.so to compile & link.
*/
certainly does the wrong thing. Its here simply because it does
just enough to allow glibc-2.1 ld.so to compile & link. */
static bfd_boolean
i370_elf_fake_sections (abfd, shdr, asect)
bfd *abfd ATTRIBUTE_UNUSED;
Elf_Internal_Shdr *shdr;
asection *asect;
i370_elf_fake_sections (bfd *abfd ATTRIBUTE_UNUSED,
Elf_Internal_Shdr *shdr,
asection *asect)
{
if ((asect->flags & SEC_EXCLUDE) != 0)
shdr->sh_flags |= SHF_EXCLUDE;
@ -431,16 +392,13 @@ i370_elf_fake_sections (abfd, shdr, asect)
to output sections (just like _bfd_elf_create_dynamic_sections has
to create .dynbss and .rela.bss). */
/* XXX hack alert bogus This routine is mostly all junk and almost
* certainly does the wrong thing. Its here simply because it does
* just enough to allow glibc-2.1 ld.so to compile & link.
*/
certainly does the wrong thing. Its here simply because it does
just enough to allow glibc-2.1 ld.so to compile & link. */
static bfd_boolean
i370_elf_create_dynamic_sections (abfd, info)
bfd *abfd;
struct bfd_link_info *info;
i370_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
{
register asection *s;
asection *s;
flagword flags;
if (!_bfd_elf_create_dynamic_sections(abfd, info))
@ -463,7 +421,7 @@ i370_elf_create_dynamic_sections (abfd, info)
return FALSE;
}
/* xxx beats me, seem to need a rela.text ... */
/* XXX beats me, seem to need a rela.text ... */
s = bfd_make_section_with_flags (abfd, ".rela.text",
flags | SEC_READONLY);
if (s == NULL
@ -478,14 +436,12 @@ i370_elf_create_dynamic_sections (abfd, info)
change the definition to something the rest of the link can
understand. */
/* XXX hack alert bogus This routine is mostly all junk and almost
* certainly does the wrong thing. Its here simply because it does
* just enough to allow glibc-2.1 ld.so to compile & link.
*/
certainly does the wrong thing. Its here simply because it does
just enough to allow glibc-2.1 ld.so to compile & link. */
static bfd_boolean
i370_elf_adjust_dynamic_symbol (info, h)
struct bfd_link_info *info;
struct elf_link_hash_entry *h;
i370_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
struct elf_link_hash_entry *h)
{
bfd *dynobj = elf_hash_table (info)->dynobj;
asection *s;
@ -594,14 +550,11 @@ i370_elf_adjust_dynamic_symbol (info, h)
/* Increment the index of a dynamic symbol by a given amount. Called
via elf_link_hash_traverse. */
/* XXX hack alert bogus This routine is mostly all junk and almost
* certainly does the wrong thing. Its here simply because it does
* just enough to allow glibc-2.1 ld.so to compile & link.
*/
certainly does the wrong thing. Its here simply because it does
just enough to allow glibc-2.1 ld.so to compile & link. */
static bfd_boolean
i370_elf_adjust_dynindx (h, cparg)
struct elf_link_hash_entry *h;
PTR cparg;
i370_elf_adjust_dynindx (struct elf_link_hash_entry *h, void * cparg)
{
int *cp = (int *) cparg;
@ -622,14 +575,12 @@ i370_elf_adjust_dynindx (h, cparg)
/* Set the sizes of the dynamic sections. */
/* XXX hack alert bogus This routine is mostly all junk and almost
* certainly does the wrong thing. Its here simply because it does
* just enough to allow glibc-2.1 ld.so to compile & link.
*/
certainly does the wrong thing. Its here simply because it does
just enough to allow glibc-2.1 ld.so to compile & link. */
static bfd_boolean
i370_elf_size_dynamic_sections (output_bfd, info)
bfd *output_bfd;
struct bfd_link_info *info;
i370_elf_size_dynamic_sections (bfd *output_bfd,
struct bfd_link_info *info)
{
bfd *dynobj;
asection *s;
@ -664,10 +615,10 @@ i370_elf_size_dynamic_sections (output_bfd, info)
stripped from the output file below. */
static char *rela_sections[] = { ".rela.got", ".rela.sdata",
".rela.sdata2", ".rela.sbss",
(char *)0 };
NULL };
char **p;
for (p = rela_sections; *p != (char *)0; p++)
for (p = rela_sections; *p != NULL; p++)
{
s = bfd_get_section_by_name (dynobj, *p);
if (s != NULL)
@ -697,32 +648,26 @@ i370_elf_size_dynamic_sections (output_bfd, info)
if (strcmp (name, ".plt") == 0)
{
if (s->size == 0)
{
/* Strip this section if we don't need it; see the
comment below. */
strip = TRUE;
}
/* Strip this section if we don't need it; see the
comment below. */
strip = TRUE;
else
{
/* Remember whether there is a PLT. */
plt = TRUE;
}
/* Remember whether there is a PLT. */
plt = TRUE;
}
else if (strncmp (name, ".rela", 5) == 0)
{
if (s->size == 0)
{
/* If we don't need this section, strip it from the
output file. This is mostly to handle .rela.bss and
.rela.plt. We must create both sections in
create_dynamic_sections, because they must be created
before the linker maps input sections to output
sections. The linker does that before
adjust_dynamic_symbol is called, and it is that
function which decides whether anything needs to go
into these sections. */
strip = TRUE;
}
/* If we don't need this section, strip it from the
output file. This is mostly to handle .rela.bss and
.rela.plt. We must create both sections in
create_dynamic_sections, because they must be created
before the linker maps input sections to output
sections. The linker does that before
adjust_dynamic_symbol is called, and it is that
function which decides whether anything needs to go
into these sections. */
strip = TRUE;
else
{
asection *target;
@ -749,10 +694,8 @@ i370_elf_size_dynamic_sections (output_bfd, info)
else if (strcmp (name, ".got") != 0
&& strcmp (name, ".sdata") != 0
&& strcmp (name, ".sdata2") != 0)
{
/* It's not one of our sections, so don't allocate space. */
continue;
}
/* It's not one of our sections, so don't allocate space. */
continue;
if (strip)
{
@ -766,7 +709,7 @@ i370_elf_size_dynamic_sections (output_bfd, info)
continue;
}
/* Allocate memory for the section contents. */
s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size);
s->contents = bfd_zalloc (dynobj, s->size);
if (s->contents == NULL && s->size != 0)
return FALSE;
}
@ -845,8 +788,7 @@ i370_elf_size_dynamic_sections (output_bfd, info)
}
elf_link_hash_traverse (elf_hash_table (info),
i370_elf_adjust_dynindx,
(PTR) &c);
i370_elf_adjust_dynindx, & c);
elf_hash_table (info)->dynsymcount += c;
}
@ -857,16 +799,14 @@ i370_elf_size_dynamic_sections (output_bfd, info)
allocate space in the global offset table or procedure linkage
table. */
/* XXX hack alert bogus This routine is mostly all junk and almost
* certainly does the wrong thing. Its here simply because it does
* just enough to allow glibc-2.1 ld.so to compile & link.
*/
certainly does the wrong thing. Its here simply because it does
just enough to allow glibc-2.1 ld.so to compile & link. */
static bfd_boolean
i370_elf_check_relocs (abfd, info, sec, relocs)
bfd *abfd;
struct bfd_link_info *info;
asection *sec;
const Elf_Internal_Rela *relocs;
i370_elf_check_relocs (bfd *abfd,
struct bfd_link_info *info,
asection *sec,
const Elf_Internal_Rela *relocs)
{
bfd *dynobj;
Elf_Internal_Shdr *symtab_hdr;
@ -963,14 +903,12 @@ i370_elf_check_relocs (abfd, info, sec, relocs)
/* Finish up the dynamic sections. */
/* XXX hack alert bogus This routine is mostly all junk and almost
* certainly does the wrong thing. Its here simply because it does
* just enough to allow glibc-2.1 ld.so to compile & link.
*/
certainly does the wrong thing. Its here simply because it does
just enough to allow glibc-2.1 ld.so to compile & link. */
static bfd_boolean
i370_elf_finish_dynamic_sections (output_bfd, info)
bfd *output_bfd;
struct bfd_link_info *info;
i370_elf_finish_dynamic_sections (bfd *output_bfd,
struct bfd_link_info *info)
{
asection *sdyn;
bfd *dynobj = elf_hash_table (info)->dynobj;
@ -1078,7 +1016,7 @@ i370_elf_finish_dynamic_sections (output_bfd, info)
sym.st_shndx = indx;
esym = (Elf32_External_Sym *) sdynsym->contents + dindx;
bfd_elf32_swap_symbol_out (output_bfd, &sym, (PTR) esym, (PTR) 0);
bfd_elf32_swap_symbol_out (output_bfd, &sym, esym, NULL);
}
}
@ -1121,16 +1059,14 @@ i370_elf_finish_dynamic_sections (output_bfd, info)
accordingly. */
static bfd_boolean
i370_elf_relocate_section (output_bfd, info, input_bfd, input_section,
contents, relocs, local_syms, local_sections)
bfd *output_bfd;
struct bfd_link_info *info;
bfd *input_bfd;
asection *input_section;
bfd_byte *contents;
Elf_Internal_Rela *relocs;
Elf_Internal_Sym *local_syms;
asection **local_sections;
i370_elf_relocate_section (bfd *output_bfd,
struct bfd_link_info *info,
bfd *input_bfd,
asection *input_section,
bfd_byte *contents,
Elf_Internal_Rela *relocs,
Elf_Internal_Sym *local_syms,
asection **local_sections)
{
Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd);
@ -1151,27 +1087,28 @@ i370_elf_relocate_section (output_bfd, info, input_bfd, input_section,
(info->relocatable) ? " (relocatable)" : "");
#endif
if (!i370_elf_howto_table[ R_I370_ADDR31 ]) /* Initialize howto table if needed */
if (!i370_elf_howto_table[ R_I370_ADDR31 ])
/* Initialize howto table if needed. */
i370_elf_howto_init ();
local_got_offsets = elf_local_got_offsets (input_bfd);
for (; rel < relend; rel++)
{
enum i370_reloc_type r_type = (enum i370_reloc_type)ELF32_R_TYPE (rel->r_info);
bfd_vma offset = rel->r_offset;
bfd_vma addend = rel->r_addend;
bfd_reloc_status_type r = bfd_reloc_other;
Elf_Internal_Sym *sym = (Elf_Internal_Sym *)0;
asection *sec = (asection *)0;
struct elf_link_hash_entry *h = (struct elf_link_hash_entry *)0;
const char *sym_name = (const char *)0;
enum i370_reloc_type r_type = (enum i370_reloc_type) ELF32_R_TYPE (rel->r_info);
bfd_vma offset = rel->r_offset;
bfd_vma addend = rel->r_addend;
bfd_reloc_status_type r = bfd_reloc_other;
Elf_Internal_Sym *sym = NULL;
asection *sec = NULL;
struct elf_link_hash_entry * h = NULL;
const char *sym_name = NULL;
reloc_howto_type *howto;
unsigned long r_symndx;
bfd_vma relocation;
/* Unknown relocation handling */
if ((unsigned)r_type >= (unsigned)R_I370_max
/* Unknown relocation handling. */
if ((unsigned) r_type >= (unsigned) R_I370_max
|| !i370_elf_howto_table[(int)r_type])
{
(*_bfd_error_handler) ("%B: unknown relocation type %d",
@ -1183,7 +1120,7 @@ i370_elf_relocate_section (output_bfd, info, input_bfd, input_section,
continue;
}
howto = i370_elf_howto_table[(int)r_type];
howto = i370_elf_howto_table[(int) r_type];
r_symndx = ELF32_R_SYM (rel->r_info);
if (r_symndx < symtab_hdr->sh_info)
@ -1192,7 +1129,7 @@ i370_elf_relocate_section (output_bfd, info, input_bfd, input_section,
sec = local_sections[r_symndx];
sym_name = "<local symbol>";
relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
relocation = _bfd_elf_rela_local_sym (output_bfd, sym, & sec, rel);
addend = rel->r_addend;
}
else
@ -1214,12 +1151,10 @@ i370_elf_relocate_section (output_bfd, info, input_bfd, input_section,
|| r_type == R_I370_COPY
|| r_type == R_I370_ADDR16
|| r_type == R_I370_RELATIVE))
{
/* In these cases, we don't need the relocation
value. We check specially because in some
obscure cases sec->output_section will be NULL. */
relocation = 0;
}
/* In these cases, we don't need the relocation
value. We check specially because in some
obscure cases sec->output_section will be NULL. */
relocation = 0;
else
relocation = (h->root.u.def.value
+ sec->output_section->vma
@ -1256,23 +1191,23 @@ i370_elf_relocate_section (output_bfd, info, input_bfd, input_section,
ret = FALSE;
continue;
case (int)R_I370_NONE:
case (int) R_I370_NONE:
continue;
/* Relocations that may need to be propagated if this is a shared
object. */
case (int)R_I370_REL31:
case (int) R_I370_REL31:
/* If these relocations are not to a named symbol, they can be
handled right here, no need to bother the dynamic linker. */
if (h == NULL
|| strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0)
break;
/* fall through */
/* Fall through. */
/* Relocations that always need to be propagated if this is a shared
object. */
case (int)R_I370_ADDR31:
case (int)R_I370_ADDR16:
case (int) R_I370_ADDR31:
case (int) R_I370_ADDR16:
if (info->shared
&& r_symndx != 0)
{
@ -1387,8 +1322,8 @@ i370_elf_relocate_section (output_bfd, info, input_bfd, input_section,
}
break;
case (int)R_I370_COPY:
case (int)R_I370_RELATIVE:
case (int) R_I370_COPY:
case (int) R_I370_RELATIVE:
(*_bfd_error_handler)
("%B: Relocation %s is not yet supported for symbol %s.",
input_bfd,
@ -1406,17 +1341,12 @@ i370_elf_relocate_section (output_bfd, info, input_bfd, input_section,
(int)r_type,
sym_name,
r_symndx,
(long)offset,
(long)addend);
(long) offset,
(long) addend);
#endif
r = _bfd_final_link_relocate (howto,
input_bfd,
input_section,
contents,
offset,
relocation,
addend);
r = _bfd_final_link_relocate (howto, input_bfd, input_section, contents,
offset, relocation, addend);
if (r != bfd_reloc_ok)
{
@ -1454,7 +1384,6 @@ i370_elf_relocate_section (output_bfd, info, input_bfd, input_section,
offset);
}
break;
}
}
}
@ -1467,11 +1396,10 @@ i370_elf_relocate_section (output_bfd, info, input_bfd, input_section,
}
static void
i370_elf_post_process_headers (abfd, link_info)
bfd * abfd;
struct bfd_link_info * link_info ATTRIBUTE_UNUSED;
i370_elf_post_process_headers (bfd * abfd,
struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
{
Elf_Internal_Ehdr * i_ehdrp; /* Elf file header, internal form */
Elf_Internal_Ehdr * i_ehdrp; /* Elf file header, internal form. */
i_ehdrp = elf_elfheader (abfd);
i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_LINUX;
@ -1488,16 +1416,15 @@ i370_elf_post_process_headers (abfd, link_info)
#define elf_info_to_howto i370_elf_info_to_howto
#define elf_backend_plt_not_loaded 1
#define elf_backend_rela_normal 1
#define elf_backend_rela_normal 1
#define bfd_elf32_bfd_reloc_type_lookup i370_elf_reloc_type_lookup
#define bfd_elf32_bfd_set_private_flags i370_elf_set_private_flags
#define bfd_elf32_bfd_merge_private_bfd_data i370_elf_merge_private_bfd_data
#define elf_backend_relocate_section i370_elf_relocate_section
/* dynamic loader support is mostly broken; just enough here to be able to
* link glibc's ld.so without errors.
*/
/* Dynamic loader support is mostly broken; just enough here to be able to
link glibc's ld.so without errors. */
#define elf_backend_create_dynamic_sections i370_elf_create_dynamic_sections
#define elf_backend_size_dynamic_sections i370_elf_size_dynamic_sections
#define elf_backend_finish_dynamic_sections i370_elf_finish_dynamic_sections
@ -1505,37 +1432,27 @@ i370_elf_post_process_headers (abfd, link_info)
#define elf_backend_section_from_shdr i370_elf_section_from_shdr
#define elf_backend_adjust_dynamic_symbol i370_elf_adjust_dynamic_symbol
#define elf_backend_check_relocs i370_elf_check_relocs
/*
#define elf_backend_add_symbol_hook i370_elf_add_symbol_hook
#define elf_backend_finish_dynamic_symbol i370_elf_finish_dynamic_symbol
#define elf_backend_additional_program_headers i370_elf_additional_program_headers
#define elf_backend_modify_segment_map i370_elf_modify_segment_map
*/
#define elf_backend_post_process_headers i370_elf_post_process_headers
static int i370_noop
PARAMS ((void));
static int i370_noop ()
static int
i370_noop (void)
{
return 1;
}
/* we need to define these at least as no-ops to link glibc ld.so */
/* We need to define these at least as no-ops to link glibc ld.so. */
#define elf_backend_add_symbol_hook \
(bfd_boolean (*) \
PARAMS ((bfd *, struct bfd_link_info *, Elf_Internal_Sym *, \
const char **, flagword *, asection **, bfd_vma *))) i370_noop
(bfd *, struct bfd_link_info *, Elf_Internal_Sym *, \
const char **, flagword *, asection **, bfd_vma *)) i370_noop
#define elf_backend_finish_dynamic_symbol \
(bfd_boolean (*) \
PARAMS ((bfd *, struct bfd_link_info *, struct elf_link_hash_entry *, \
Elf_Internal_Sym *))) i370_noop
(bfd *, struct bfd_link_info *, struct elf_link_hash_entry *, \
Elf_Internal_Sym *)) i370_noop
#define elf_backend_additional_program_headers \
(int (*) PARAMS ((bfd *))) i370_noop
(int (*) (bfd *)) i370_noop
#define elf_backend_modify_segment_map \
(bfd_boolean (*) PARAMS ((bfd *, struct bfd_link_info *))) i370_noop
(bfd_boolean (*) (bfd *, struct bfd_link_info *)) i370_noop
#include "elf32-target.h"

171
bfd/elf32-i960.c
View File

@ -1,21 +1,22 @@
/* Intel 960 specific support for 32-bit ELF
Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Copyright 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -23,33 +24,73 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#include "elf-bfd.h"
#include "elf/i960.h"
static bfd_reloc_status_type elf32_i960_relocate
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
static reloc_howto_type *elf32_i960_reloc_type_lookup
PARAMS ((bfd *, bfd_reloc_code_real_type));
static void elf32_i960_info_to_howto
PARAMS ((bfd *, arelent *cache_ptr, Elf_Internal_Rela *));
static void elf32_i960_info_to_howto_rel
PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
#define USE_REL 1
#define bfd_elf32_bfd_reloc_type_lookup elf32_i960_reloc_type_lookup
#define elf_info_to_howto elf32_i960_info_to_howto
#define elf_info_to_howto_rel elf32_i960_info_to_howto_rel
/* ELF relocs are against symbols. If we are producing relocatable
output, and the reloc is against an external symbol, and nothing
has given us any additional addend, the resulting reloc will also
be against the same symbol. In such a case, we don't want to
change anything about the way the reloc is handled, since it will
all be done at final link time. Rather than put special case code
into bfd_perform_relocation, all the reloc types use this howto
function. It just short circuits the reloc if producing
relocatable output against an external symbol. */
static bfd_reloc_status_type
elf32_i960_relocate (bfd *abfd ATTRIBUTE_UNUSED,
arelent *reloc_entry,
asymbol *symbol,
PTR data ATTRIBUTE_UNUSED,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
/* HACK: I think this first condition is necessary when producing
relocatable output. After the end of HACK, the code is identical
to bfd_elf_generic_reloc(). I would _guess_ the first change
belongs there rather than here. martindo 1998-10-23. */
if (output_bfd != (bfd *) NULL
&& reloc_entry->howto->pc_relative
&& !reloc_entry->howto->pcrel_offset)
reloc_entry->addend -= symbol->value;
/* This is more dubious. */
else if (output_bfd != (bfd *) NULL
&& (symbol->flags & BSF_SECTION_SYM) != 0)
reloc_entry->addend -= symbol->section->output_section->vma;
else
{
/* ...end of HACK. */
if (output_bfd != (bfd *) NULL
&& (symbol->flags & BSF_SECTION_SYM) == 0
&& (! reloc_entry->howto->partial_inplace
|| reloc_entry->addend == 0))
{
reloc_entry->address += input_section->output_offset;
return bfd_reloc_ok;
}
}
return bfd_reloc_continue;
}
static reloc_howto_type elf_howto_table[]=
{
HOWTO(R_960_NONE, 0, 0, 0, FALSE, 0, complain_overflow_bitfield,
elf32_i960_relocate, "R_960_NONE", TRUE,
0x00000000, 0x00000000, FALSE),
HOWTO (R_960_NONE, 0, 0, 0, FALSE, 0, complain_overflow_bitfield,
elf32_i960_relocate, "R_960_NONE", TRUE,
0x00000000, 0x00000000, FALSE),
EMPTY_HOWTO (1),
HOWTO (R_960_32, 0, 2, 32, FALSE, 0, complain_overflow_bitfield,
elf32_i960_relocate, "R_960_32", TRUE,
0xffffffff, 0xffffffff, FALSE),
elf32_i960_relocate, "R_960_32", TRUE,
0xffffffff, 0xffffffff, FALSE),
HOWTO (R_960_IP24, 0, 2, 24, TRUE, 0, complain_overflow_signed,
elf32_i960_relocate, "R_960_IP24 ", TRUE,
0x00ffffff, 0x00ffffff, FALSE),
elf32_i960_relocate, "R_960_IP24 ", TRUE,
0x00ffffff, 0x00ffffff, FALSE),
EMPTY_HOWTO (4),
EMPTY_HOWTO (5),
EMPTY_HOWTO (6),
@ -74,19 +115,17 @@ elf32_i960_bfd_to_reloc_type (bfd_reloc_code_real_type code)
}
static void
elf32_i960_info_to_howto (abfd, cache_ptr, dst)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *cache_ptr ATTRIBUTE_UNUSED;
Elf_Internal_Rela *dst ATTRIBUTE_UNUSED;
elf32_i960_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
arelent * cache_ptr ATTRIBUTE_UNUSED,
Elf_Internal_Rela * dst ATTRIBUTE_UNUSED)
{
abort ();
}
static void
elf32_i960_info_to_howto_rel (abfd, cache_ptr, dst)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *cache_ptr;
Elf_Internal_Rela *dst;
elf32_i960_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
arelent *cache_ptr,
Elf_Internal_Rela *dst)
{
enum elf_i960_reloc_type type;
@ -96,63 +135,9 @@ elf32_i960_info_to_howto_rel (abfd, cache_ptr, dst)
cache_ptr->howto = &elf_howto_table[(int) type];
}
/* ELF relocs are against symbols. If we are producing relocatable
output, and the reloc is against an external symbol, and nothing
has given us any additional addend, the resulting reloc will also
be against the same symbol. In such a case, we don't want to
change anything about the way the reloc is handled, since it will
all be done at final link time. Rather than put special case code
into bfd_perform_relocation, all the reloc types use this howto
function. It just short circuits the reloc if producing
relocatable output against an external symbol. */
bfd_reloc_status_type
elf32_i960_relocate (abfd, reloc_entry, symbol, data, input_section,
output_bfd, error_message)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *reloc_entry;
asymbol *symbol;
PTR data ATTRIBUTE_UNUSED;
asection *input_section;
bfd *output_bfd;
char **error_message ATTRIBUTE_UNUSED;
{
/* HACK: I think this first condition is necessary when producing
relocatable output. After the end of HACK, the code is identical
to bfd_elf_generic_reloc(). I would _guess_ the first change
belongs there rather than here. martindo 1998-10-23. */
if (output_bfd != (bfd *) NULL
&& reloc_entry->howto->pc_relative
&& !reloc_entry->howto->pcrel_offset)
{
reloc_entry->addend -= symbol->value;
}
/* This is more dubious. */
else if (output_bfd != (bfd *) NULL
&& (symbol->flags & BSF_SECTION_SYM) != 0)
{
reloc_entry->addend -= symbol->section->output_section->vma;
}
else
{
/* end of HACK */
if (output_bfd != (bfd *) NULL
&& (symbol->flags & BSF_SECTION_SYM) == 0
&& (! reloc_entry->howto->partial_inplace
|| reloc_entry->addend == 0))
{
reloc_entry->address += input_section->output_offset;
return bfd_reloc_ok;
}
}
return bfd_reloc_continue;
}
static reloc_howto_type *
elf32_i960_reloc_type_lookup (abfd, code)
bfd *abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
elf32_i960_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
return elf_howto_table + elf32_i960_bfd_to_reloc_type (code);
}

1448
bfd/elf32-ip2k.c
View File

File diff suppressed because it is too large Load Diff

1287
bfd/elf32-m32r.c
View File

File diff suppressed because it is too large Load Diff

312
bfd/elf32-mcore.c
View File

@ -1,22 +1,23 @@
/* Motorola MCore specific support for 32-bit ELF
Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004
Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005
Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
USA. */
/* This file is based on a preliminary RCE ELF ABI. The
information may not match the final RCE ELF ABI. */
@ -31,30 +32,76 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
/* RELA relocs are used here... */
static void mcore_elf_howto_init
PARAMS ((void));
static reloc_howto_type * mcore_elf_reloc_type_lookup
PARAMS ((bfd *, bfd_reloc_code_real_type));
static void mcore_elf_info_to_howto
PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
static bfd_boolean mcore_elf_set_private_flags
PARAMS ((bfd *, flagword));
static bfd_boolean mcore_elf_merge_private_bfd_data
PARAMS ((bfd *, bfd *));
static bfd_reloc_status_type mcore_elf_unsupported_reloc
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
static bfd_boolean mcore_elf_relocate_section
PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
Elf_Internal_Rela *, Elf_Internal_Sym *, asection **));
static asection * mcore_elf_gc_mark_hook
PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *,
struct elf_link_hash_entry *, Elf_Internal_Sym *));
static bfd_boolean mcore_elf_gc_sweep_hook
PARAMS ((bfd *, struct bfd_link_info *, asection *,
const Elf_Internal_Rela *));
static bfd_boolean mcore_elf_check_relocs
PARAMS ((bfd *, struct bfd_link_info *, asection *,
const Elf_Internal_Rela *));
/* Function to set whether a module needs the -mrelocatable bit set. */
static bfd_boolean
mcore_elf_set_private_flags (bfd * abfd, flagword flags)
{
BFD_ASSERT (! elf_flags_init (abfd)
|| elf_elfheader (abfd)->e_flags == flags);
elf_elfheader (abfd)->e_flags = flags;
elf_flags_init (abfd) = TRUE;
return TRUE;
}
/* Merge backend specific data from an object file to the output
object file when linking. */
static bfd_boolean
mcore_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
{
flagword old_flags;
flagword new_flags;
/* Check if we have the same endianess. */
if (! _bfd_generic_verify_endian_match (ibfd, obfd))
return FALSE;
if ( bfd_get_flavour (ibfd) != bfd_target_elf_flavour
|| bfd_get_flavour (obfd) != bfd_target_elf_flavour)
return TRUE;
new_flags = elf_elfheader (ibfd)->e_flags;
old_flags = elf_elfheader (obfd)->e_flags;
if (! elf_flags_init (obfd))
{
/* First call, no flags set. */
elf_flags_init (obfd) = TRUE;
elf_elfheader (obfd)->e_flags = new_flags;
}
else if (new_flags == old_flags)
/* Compatible flags are OK. */
;
else
{
/* FIXME */
}
return TRUE;
}
/* Don't pretend we can deal with unsupported relocs. */
static bfd_reloc_status_type
mcore_elf_unsupported_reloc (bfd * abfd,
arelent * reloc_entry,
asymbol * symbol ATTRIBUTE_UNUSED,
PTR data ATTRIBUTE_UNUSED,
asection * input_section ATTRIBUTE_UNUSED,
bfd * output_bfd ATTRIBUTE_UNUSED,
char ** error_message ATTRIBUTE_UNUSED)
{
BFD_ASSERT (reloc_entry->howto != (reloc_howto_type *)0);
_bfd_error_handler (_("%B: Relocation %s (%d) is not currently supported.\n"),
abfd,
reloc_entry->howto->name,
reloc_entry->howto->type);
return bfd_reloc_notsupported;
}
static reloc_howto_type * mcore_elf_howto_table [(int) R_MCORE_max];
@ -174,7 +221,7 @@ static reloc_howto_type mcore_elf_howto_raw[] =
0x7ff, /* dst_mask */
TRUE), /* pcrel_offset */
/* GNU extension to record C++ vtable hierarchy */
/* GNU extension to record C++ vtable hierarchy. */
HOWTO (R_MCORE_GNU_VTINHERIT, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@ -189,7 +236,7 @@ static reloc_howto_type mcore_elf_howto_raw[] =
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* GNU extension to record C++ vtable member usage */
/* GNU extension to record C++ vtable member usage. */
HOWTO (R_MCORE_GNU_VTENTRY, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@ -225,7 +272,7 @@ static reloc_howto_type mcore_elf_howto_raw[] =
/* Initialize the mcore_elf_howto_table, so that linear accesses can be done. */
static void
mcore_elf_howto_init ()
mcore_elf_howto_init (void)
{
unsigned int i;
@ -242,9 +289,8 @@ mcore_elf_howto_init ()
}
static reloc_howto_type *
mcore_elf_reloc_type_lookup (abfd, code)
bfd * abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
mcore_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
enum elf_mcore_reloc_type mcore_reloc = R_MCORE_NONE;
@ -261,102 +307,31 @@ mcore_elf_reloc_type_lookup (abfd, code)
case BFD_RELOC_VTABLE_ENTRY: mcore_reloc = R_MCORE_GNU_VTENTRY; break;
case BFD_RELOC_RVA: mcore_reloc = R_MCORE_RELATIVE; break;
default:
return (reloc_howto_type *)NULL;
return NULL;
}
if (! mcore_elf_howto_table [R_MCORE_PCRELIMM8BY4]) /* Initialize howto table if needed */
if (! mcore_elf_howto_table [R_MCORE_PCRELIMM8BY4])
/* Initialize howto table if needed. */
mcore_elf_howto_init ();
return mcore_elf_howto_table [(int) mcore_reloc];
};
/* Set the howto pointer for a RCE ELF reloc. */
static void
mcore_elf_info_to_howto (abfd, cache_ptr, dst)
bfd * abfd ATTRIBUTE_UNUSED;
arelent * cache_ptr;
Elf_Internal_Rela * dst;
mcore_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
arelent * cache_ptr,
Elf_Internal_Rela * dst)
{
if (! mcore_elf_howto_table [R_MCORE_PCRELIMM8BY4]) /* Initialize howto table if needed */
if (! mcore_elf_howto_table [R_MCORE_PCRELIMM8BY4])
/* Initialize howto table if needed. */
mcore_elf_howto_init ();
BFD_ASSERT (ELF32_R_TYPE (dst->r_info) < (unsigned int) R_MCORE_max);
cache_ptr->howto = mcore_elf_howto_table [ELF32_R_TYPE (dst->r_info)];
}
/* Function to set whether a module needs the -mrelocatable bit set. */
static bfd_boolean
mcore_elf_set_private_flags (abfd, flags)
bfd * abfd;
flagword flags;
{
BFD_ASSERT (! elf_flags_init (abfd)
|| elf_elfheader (abfd)->e_flags == flags);
elf_elfheader (abfd)->e_flags = flags;
elf_flags_init (abfd) = TRUE;
return TRUE;
}
/* Merge backend specific data from an object file to the output
object file when linking. */
static bfd_boolean
mcore_elf_merge_private_bfd_data (ibfd, obfd)
bfd * ibfd;
bfd * obfd;
{
flagword old_flags;
flagword new_flags;
/* Check if we have the same endianess */
if (! _bfd_generic_verify_endian_match (ibfd, obfd))
return FALSE;
if ( bfd_get_flavour (ibfd) != bfd_target_elf_flavour
|| bfd_get_flavour (obfd) != bfd_target_elf_flavour)
return TRUE;
new_flags = elf_elfheader (ibfd)->e_flags;
old_flags = elf_elfheader (obfd)->e_flags;
if (! elf_flags_init (obfd)) /* First call, no flags set */
{
elf_flags_init (obfd) = TRUE;
elf_elfheader (obfd)->e_flags = new_flags;
}
else if (new_flags == old_flags) /* Compatible flags are ok */
;
else
{
/* FIXME */
}
return TRUE;
}
/* Don't pretend we can deal with unsupported relocs. */
static bfd_reloc_status_type
mcore_elf_unsupported_reloc (abfd, reloc_entry, symbol, data, input_section,
output_bfd, error_message)
bfd * abfd;
arelent * reloc_entry;
asymbol * symbol ATTRIBUTE_UNUSED;
PTR data ATTRIBUTE_UNUSED;
asection * input_section ATTRIBUTE_UNUSED;
bfd * output_bfd ATTRIBUTE_UNUSED;
char ** error_message ATTRIBUTE_UNUSED;
{
BFD_ASSERT (reloc_entry->howto != (reloc_howto_type *)0);
_bfd_error_handler (_("%B: Relocation %s (%d) is not currently supported.\n"),
abfd,
reloc_entry->howto->name,
reloc_entry->howto->type);
return bfd_reloc_notsupported;
}
/* The RELOCATE_SECTION function is called by the ELF backend linker
to handle the relocations for a section.
@ -388,16 +363,14 @@ mcore_elf_unsupported_reloc (abfd, reloc_entry, symbol, data, input_section,
accordingly. */
static bfd_boolean
mcore_elf_relocate_section (output_bfd, info, input_bfd, input_section,
contents, relocs, local_syms, local_sections)
bfd * output_bfd;
struct bfd_link_info * info;
bfd * input_bfd;
asection * input_section;
bfd_byte * contents;
Elf_Internal_Rela * relocs;
Elf_Internal_Sym * local_syms;
asection ** local_sections;
mcore_elf_relocate_section (bfd * output_bfd,
struct bfd_link_info * info,
bfd * input_bfd,
asection * input_section,
bfd_byte * contents,
Elf_Internal_Rela * relocs,
Elf_Internal_Sym * local_syms,
asection ** local_sections)
{
Elf_Internal_Shdr * symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
struct elf_link_hash_entry ** sym_hashes = elf_sym_hashes (input_bfd);
@ -426,15 +399,15 @@ mcore_elf_relocate_section (output_bfd, info, input_bfd, input_section,
bfd_vma offset = rel->r_offset;
bfd_vma addend = rel->r_addend;
bfd_reloc_status_type r = bfd_reloc_other;
asection * sec = (asection *) 0;
asection * sec = NULL;
reloc_howto_type * howto;
bfd_vma relocation;
Elf_Internal_Sym * sym = (Elf_Internal_Sym *) 0;
Elf_Internal_Sym * sym = NULL;
unsigned long r_symndx;
struct elf_link_hash_entry * h = (struct elf_link_hash_entry *) 0;
struct elf_link_hash_entry * h = NULL;
unsigned short oldinst = 0;
/* Unknown relocation handling */
/* Unknown relocation handling. */
if ((unsigned) r_type >= (unsigned) R_MCORE_max
|| ! mcore_elf_howto_table [(int)r_type])
{
@ -553,38 +526,35 @@ mcore_elf_relocate_section (output_bfd, info, input_bfd, input_section,
relocation. */
static asection *
mcore_elf_gc_mark_hook (sec, info, rel, h, sym)
asection * sec;
struct bfd_link_info * info ATTRIBUTE_UNUSED;
Elf_Internal_Rela * rel;
struct elf_link_hash_entry * h;
Elf_Internal_Sym * sym;
mcore_elf_gc_mark_hook (asection * sec,
struct bfd_link_info * info ATTRIBUTE_UNUSED,
Elf_Internal_Rela * rel,
struct elf_link_hash_entry * h,
Elf_Internal_Sym * sym)
{
if (h != NULL)
if (h == NULL)
return bfd_section_from_elf_index (sec->owner, sym->st_shndx);
switch (ELF32_R_TYPE (rel->r_info))
{
switch (ELF32_R_TYPE (rel->r_info))
case R_MCORE_GNU_VTINHERIT:
case R_MCORE_GNU_VTENTRY:
break;
default:
switch (h->root.type)
{
case R_MCORE_GNU_VTINHERIT:
case R_MCORE_GNU_VTENTRY:
break;
case bfd_link_hash_defined:
case bfd_link_hash_defweak:
return h->root.u.def.section;
case bfd_link_hash_common:
return h->root.u.c.p->section;
default:
switch (h->root.type)
{
case bfd_link_hash_defined:
case bfd_link_hash_defweak:
return h->root.u.def.section;
case bfd_link_hash_common:
return h->root.u.c.p->section;
default:
break;
}
break;
}
}
else
return bfd_section_from_elf_index (sec->owner, sym->st_shndx);
return NULL;
}
@ -592,11 +562,10 @@ mcore_elf_gc_mark_hook (sec, info, rel, h, sym)
/* Update the got entry reference counts for the section being removed. */
static bfd_boolean
mcore_elf_gc_sweep_hook (abfd, info, sec, relocs)
bfd * abfd ATTRIBUTE_UNUSED;
struct bfd_link_info * info ATTRIBUTE_UNUSED;
asection * sec ATTRIBUTE_UNUSED;
const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED;
mcore_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED,
struct bfd_link_info * info ATTRIBUTE_UNUSED,
asection * sec ATTRIBUTE_UNUSED,
const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED)
{
return TRUE;
}
@ -606,11 +575,10 @@ mcore_elf_gc_sweep_hook (abfd, info, sec, relocs)
virtual table relocs for gc. */
static bfd_boolean
mcore_elf_check_relocs (abfd, info, sec, relocs)
bfd * abfd;
struct bfd_link_info * info;
asection * sec;
const Elf_Internal_Rela * relocs;
mcore_elf_check_relocs (bfd * abfd,
struct bfd_link_info * info,
asection * sec,
const Elf_Internal_Rela * relocs)
{
Elf_Internal_Shdr * symtab_hdr;
struct elf_link_hash_entry ** sym_hashes;

216
bfd/elf32-openrisc.c
View File

@ -1,22 +1,23 @@
/* OpenRISC-specific support for 32-bit ELF.
Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
Copyright 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
Contributed by Johan Rydberg, jrydberg@opencores.org
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
USA. */
#include "bfd.h"
#include "sysdep.h"
@ -25,35 +26,8 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#include "elf/openrisc.h"
#include "libiberty.h"
/* Forward declarations. */
static reloc_howto_type *openrisc_reloc_type_lookup
PARAMS ((bfd * , bfd_reloc_code_real_type));
static void openrisc_info_to_howto_rela
PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
static bfd_boolean openrisc_elf_relocate_section
PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
Elf_Internal_Rela *, Elf_Internal_Sym *, asection **));
static bfd_reloc_status_type openrisc_final_link_relocate
PARAMS ((reloc_howto_type *, bfd *, asection *, bfd_byte *,
Elf_Internal_Rela *, bfd_vma));
static bfd_boolean openrisc_elf_gc_sweep_hook
PARAMS ((bfd *, struct bfd_link_info *, asection *,
const Elf_Internal_Rela *));
static asection * openrisc_elf_gc_mark_hook
PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *,
struct elf_link_hash_entry *, Elf_Internal_Sym *));
static bfd_boolean openrisc_elf_check_relocs
PARAMS ((bfd *, struct bfd_link_info *, asection *,
const Elf_Internal_Rela *));
static bfd_boolean openrisc_elf_object_p
PARAMS ((bfd *));
static void openrisc_elf_final_write_processing
PARAMS ((bfd *, bfd_boolean));
static reloc_howto_type openrisc_elf_howto_table[] =
{
{
/* This reloc does nothing. */
HOWTO (R_OPENRISC_NONE, /* type */
0, /* rightshift */
@ -172,7 +146,7 @@ static reloc_howto_type openrisc_elf_howto_table[] =
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* GNU extension to record C++ vtable hierarchy */
/* GNU extension to record C++ vtable hierarchy. */
HOWTO (R_OPENRISC_GNU_VTINHERIT, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@ -187,7 +161,7 @@ static reloc_howto_type openrisc_elf_howto_table[] =
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* GNU extension to record C++ vtable member usage */
/* GNU extension to record C++ vtable member usage. */
HOWTO (R_OPENRISC_GNU_VTENTRY, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@ -206,29 +180,28 @@ static reloc_howto_type openrisc_elf_howto_table[] =
/* Map BFD reloc types to OpenRISC ELF reloc types. */
struct openrisc_reloc_map
{
bfd_reloc_code_real_type bfd_reloc_val;
unsigned int openrisc_reloc_val;
};
{
bfd_reloc_code_real_type bfd_reloc_val;
unsigned int openrisc_reloc_val;
};
static const struct openrisc_reloc_map openrisc_reloc_map[] =
{
{ BFD_RELOC_NONE, R_OPENRISC_NONE },
{ BFD_RELOC_32, R_OPENRISC_32 },
{ BFD_RELOC_16, R_OPENRISC_16 },
{ BFD_RELOC_8, R_OPENRISC_8 },
{ BFD_RELOC_OPENRISC_REL_26,R_OPENRISC_INSN_REL_26 },
{ BFD_RELOC_OPENRISC_ABS_26,R_OPENRISC_INSN_ABS_26 },
{
{ BFD_RELOC_NONE, R_OPENRISC_NONE },
{ BFD_RELOC_32, R_OPENRISC_32 },
{ BFD_RELOC_16, R_OPENRISC_16 },
{ BFD_RELOC_8, R_OPENRISC_8 },
{ BFD_RELOC_OPENRISC_REL_26,R_OPENRISC_INSN_REL_26 },
{ BFD_RELOC_OPENRISC_ABS_26,R_OPENRISC_INSN_ABS_26 },
{ BFD_RELOC_HI16, R_OPENRISC_HI_16_IN_INSN },
{ BFD_RELOC_LO16, R_OPENRISC_LO_16_IN_INSN },
{ BFD_RELOC_VTABLE_INHERIT, R_OPENRISC_GNU_VTINHERIT },
{ BFD_RELOC_VTABLE_ENTRY, R_OPENRISC_GNU_VTENTRY }
};
{ BFD_RELOC_LO16, R_OPENRISC_LO_16_IN_INSN },
{ BFD_RELOC_VTABLE_INHERIT, R_OPENRISC_GNU_VTINHERIT },
{ BFD_RELOC_VTABLE_ENTRY, R_OPENRISC_GNU_VTENTRY }
};
static reloc_howto_type *
openrisc_reloc_type_lookup (abfd, code)
bfd * abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
openrisc_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
@ -243,10 +216,9 @@ openrisc_reloc_type_lookup (abfd, code)
/* Set the howto pointer for an OpenRISC ELF reloc. */
static void
openrisc_info_to_howto_rela (abfd, cache_ptr, dst)
bfd * abfd ATTRIBUTE_UNUSED;
arelent * cache_ptr;
Elf_Internal_Rela * dst;
openrisc_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
arelent * cache_ptr,
Elf_Internal_Rela * dst)
{
unsigned int r_type;
@ -259,14 +231,12 @@ openrisc_info_to_howto_rela (abfd, cache_ptr, dst)
routines, but a few relocs, we have to do them ourselves. */
static bfd_reloc_status_type
openrisc_final_link_relocate (howto, input_bfd, input_section, contents, rel,
relocation)
reloc_howto_type *howto;
bfd *input_bfd;
asection *input_section;
bfd_byte *contents;
Elf_Internal_Rela *rel;
bfd_vma relocation;
openrisc_final_link_relocate (reloc_howto_type *howto,
bfd *input_bfd,
asection *input_section,
bfd_byte *contents,
Elf_Internal_Rela *rel,
bfd_vma relocation)
{
bfd_reloc_status_type r = bfd_reloc_ok;
@ -319,16 +289,14 @@ openrisc_final_link_relocate (howto, input_bfd, input_section, contents, rel,
accordingly. */
static bfd_boolean
openrisc_elf_relocate_section (output_bfd, info, input_bfd, input_section,
contents, relocs, local_syms, local_sections)
bfd *output_bfd;
struct bfd_link_info *info;
bfd *input_bfd;
asection *input_section;
bfd_byte *contents;
Elf_Internal_Rela *relocs;
Elf_Internal_Sym *local_syms;
asection **local_sections;
openrisc_elf_relocate_section (bfd *output_bfd,
struct bfd_link_info *info,
bfd *input_bfd,
asection *input_section,
bfd_byte *contents,
Elf_Internal_Rela *relocs,
Elf_Internal_Sym *local_syms,
asection **local_sections)
{
Elf_Internal_Shdr *symtab_hdr;
struct elf_link_hash_entry **sym_hashes;
@ -396,7 +364,7 @@ openrisc_elf_relocate_section (output_bfd, info, input_bfd, input_section,
if (r != bfd_reloc_ok)
{
const char *msg = (const char *) NULL;
const char *msg = NULL;
switch (r)
{
@ -444,38 +412,35 @@ openrisc_elf_relocate_section (output_bfd, info, input_bfd, input_section,
relocation. */
static asection *
openrisc_elf_gc_mark_hook (sec, info, rel, h, sym)
asection *sec;
struct bfd_link_info *info ATTRIBUTE_UNUSED;
Elf_Internal_Rela *rel;
struct elf_link_hash_entry *h;
Elf_Internal_Sym *sym;
openrisc_elf_gc_mark_hook (asection *sec,
struct bfd_link_info *info ATTRIBUTE_UNUSED,
Elf_Internal_Rela *rel,
struct elf_link_hash_entry *h,
Elf_Internal_Sym *sym)
{
if (h != NULL)
if (h == NULL)
return bfd_section_from_elf_index (sec->owner, sym->st_shndx);
switch (ELF32_R_TYPE (rel->r_info))
{
switch (ELF32_R_TYPE (rel->r_info))
case R_OPENRISC_GNU_VTINHERIT:
case R_OPENRISC_GNU_VTENTRY:
break;
default:
switch (h->root.type)
{
case R_OPENRISC_GNU_VTINHERIT:
case R_OPENRISC_GNU_VTENTRY:
break;
case bfd_link_hash_defined:
case bfd_link_hash_defweak:
return h->root.u.def.section;
case bfd_link_hash_common:
return h->root.u.c.p->section;
default:
switch (h->root.type)
{
case bfd_link_hash_defined:
case bfd_link_hash_defweak:
return h->root.u.def.section;
case bfd_link_hash_common:
return h->root.u.c.p->section;
default:
break;
}
break;
}
}
else
return bfd_section_from_elf_index (sec->owner, sym->st_shndx);
return NULL;
}
@ -483,11 +448,10 @@ openrisc_elf_gc_mark_hook (sec, info, rel, h, sym)
/* Update the got entry reference counts for the section being removed. */
static bfd_boolean
openrisc_elf_gc_sweep_hook (abfd, info, sec, relocs)
bfd *abfd ATTRIBUTE_UNUSED;
struct bfd_link_info *info ATTRIBUTE_UNUSED;
asection *sec ATTRIBUTE_UNUSED;
const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED;
openrisc_elf_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED,
struct bfd_link_info *info ATTRIBUTE_UNUSED,
asection *sec ATTRIBUTE_UNUSED,
const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED)
{
return TRUE;
}
@ -497,11 +461,10 @@ openrisc_elf_gc_sweep_hook (abfd, info, sec, relocs)
virtual table relocs for gc. */
static bfd_boolean
openrisc_elf_check_relocs (abfd, info, sec, relocs)
bfd *abfd;
struct bfd_link_info *info;
asection *sec;
const Elf_Internal_Rela *relocs;
openrisc_elf_check_relocs (bfd *abfd,
struct bfd_link_info *info,
asection *sec,
const Elf_Internal_Rela *relocs)
{
Elf_Internal_Shdr *symtab_hdr;
struct elf_link_hash_entry **sym_hashes, **sym_hashes_end;
@ -559,24 +522,17 @@ openrisc_elf_check_relocs (abfd, info, sec, relocs)
/* Set the right machine number. */
static bfd_boolean
openrisc_elf_object_p (abfd)
bfd *abfd;
openrisc_elf_object_p (bfd *abfd)
{
switch (elf_elfheader (abfd)->e_flags & 0xf)
{
default:
(void) bfd_default_set_arch_mach (abfd, bfd_arch_openrisc, 0);
break;
}
bfd_default_set_arch_mach (abfd, bfd_arch_openrisc, 0);
return TRUE;
}
/* Store the machine number in the flags field. */
static void
openrisc_elf_final_write_processing (abfd, linker)
bfd *abfd;
bfd_boolean linker ATTRIBUTE_UNUSED;
openrisc_elf_final_write_processing (bfd *abfd,
bfd_boolean linker ATTRIBUTE_UNUSED)
{
unsigned long val;

601
bfd/elf32-or32.c
View File

@ -1,5 +1,5 @@
/* OR32-specific support for 32-bit ELF
Copyright 2002, 2004 Free Software Foundation, Inc.
Copyright 2002, 2004, 2005 Free Software Foundation, Inc.
Contributed by Ivan Guzvinec <ivang@opencores.org>
This file is part of BFD, the Binary File Descriptor library.
@ -25,31 +25,275 @@
#include "elf/or32.h"
#include "libiberty.h"
static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
PARAMS ((bfd *, bfd_reloc_code_real_type));
static void or32_info_to_howto_rel
PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
static bfd_boolean or32_elf_object_p
PARAMS ((bfd *));
static void or32_elf_final_write_processing
PARAMS ((bfd *, bfd_boolean));
static bfd_reloc_status_type or32_elf_32_reloc
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
static bfd_reloc_status_type or32_elf_16_reloc
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
static bfd_reloc_status_type or32_elf_8_reloc
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
static bfd_reloc_status_type or32_elf_const_reloc
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
static bfd_reloc_status_type or32_elf_consth_reloc
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
static bfd_reloc_status_type or32_elf_jumptarg_reloc
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
/* Try to minimize the amount of space occupied by relocation tables
on the ROM (not that the ROM won't be swamped by other ELF overhead). */
#define USE_REL 1
/* Set the right machine number for an OR32 ELF file. */
static bfd_boolean
or32_elf_object_p (bfd *abfd)
{
(void) bfd_default_set_arch_mach (abfd, bfd_arch_or32, 0);
return TRUE;
}
/* The final processing done just before writing out an OR32 ELF object file.
This gets the OR32 architecture right based on the machine number. */
static void
or32_elf_final_write_processing (bfd *abfd,
bfd_boolean linker ATTRIBUTE_UNUSED)
{
elf_elfheader (abfd)->e_flags &=~ EF_OR32_MACH;
}
static bfd_reloc_status_type
or32_elf_32_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
if (output_bfd != NULL)
{
unsigned long insn;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_32 (abfd, (bfd_byte *) data + addr);
insn += symbol->section->output_section->vma;
insn += symbol->section->output_offset;
insn += symbol->value;
bfd_put_32 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
return bfd_reloc_continue;
}
static bfd_reloc_status_type
or32_elf_16_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
if (output_bfd != NULL)
{
unsigned short insn;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_16 (abfd, (bfd_byte *) data + addr);
insn += symbol->section->output_section->vma;
insn += symbol->section->output_offset;
insn += symbol->value;
bfd_put_16 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
return bfd_reloc_continue;
}
static bfd_reloc_status_type
or32_elf_8_reloc (bfd *abfd ATTRIBUTE_UNUSED,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
if (output_bfd != NULL)
{
unsigned char insn;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_8 (abfd, (bfd_byte *) data + addr);
insn += symbol->section->output_section->vma;
insn += symbol->section->output_offset;
insn += symbol->value;
bfd_put_8 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
return bfd_reloc_continue;
}
/* Do a R_OR32_CONSTH relocation. This has to be done in combination
with a R_OR32_CONST reloc, because there is a carry from the LO16 to
the HI16. Here we just save the information we need; we do the
actual relocation when we see the LO16. OR32 ELF requires that the
LO16 immediately follow the HI16. As a GNU extension, we permit an
arbitrary number of HI16 relocs to be associated with a single LO16
reloc. This extension permits gcc to output the HI and LO relocs
itself. This code is copied from the elf32-mips.c. */
struct or32_consth
{
struct or32_consth *next;
bfd_byte *addr;
bfd_vma addend;
};
/* FIXME: This should not be a static variable. */
static struct or32_consth *or32_consth_list;
static bfd_reloc_status_type
or32_elf_consth_reloc (bfd *abfd ATTRIBUTE_UNUSED,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
bfd_reloc_status_type ret;
bfd_vma relocation;
struct or32_consth *n;
ret = bfd_reloc_ok;
if (bfd_is_und_section (symbol->section)
&& output_bfd == NULL)
ret = bfd_reloc_undefined;
if (bfd_is_com_section (symbol->section))
relocation = 0;
else
relocation = symbol->value;
relocation += symbol->section->output_section->vma;
relocation += symbol->section->output_offset;
relocation += reloc_entry->addend;
if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
return bfd_reloc_outofrange;
/* Save the information, and let LO16 do the actual relocation. */
n = bfd_malloc (sizeof *n);
if (n == NULL)
return bfd_reloc_outofrange;
n->addr = (bfd_byte *) data + reloc_entry->address;
n->addend = relocation;
n->next = or32_consth_list;
or32_consth_list = n;
if (output_bfd != NULL)
reloc_entry->address += input_section->output_offset;
return ret;
}
/* Do a R_OR32_CONST relocation. This is a straightforward 16 bit
inplace relocation; this function exists in order to do the
R_OR32_CONSTH relocation described above. */
static bfd_reloc_status_type
or32_elf_const_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message)
{
if (or32_consth_list != NULL)
{
struct or32_consth *l;
l = or32_consth_list;
while (l != NULL)
{
unsigned long insn;
unsigned long val;
unsigned long vallo;
struct or32_consth *next;
/* Do the HI16 relocation. Note that we actually don't need
to know anything about the LO16 itself, except where to
find the low 16 bits of the addend needed by the LO16. */
insn = bfd_get_32 (abfd, l->addr);
vallo = (bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address)
& 0xffff);
val = ((insn & 0xffff) << 16) + vallo;
val += l->addend;
insn = (insn &~ 0xffff) | ((val >> 16) & 0xffff);
bfd_put_32 (abfd, insn, l->addr);
next = l->next;
free (l);
l = next;
}
or32_consth_list = NULL;
}
if (output_bfd != NULL)
{
unsigned long insn, tmp;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_32 (abfd, (bfd_byte *) data + addr);
tmp = insn & 0x0000ffff;
tmp += symbol->section->output_section->vma;
tmp += symbol->section->output_offset;
tmp += symbol->value;
insn = (insn & 0xffff0000) | (tmp & 0x0000ffff);
bfd_put_32 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
/* Now do the LO16 reloc in the usual way. */
return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data,
input_section, output_bfd, error_message);
}
static bfd_reloc_status_type
or32_elf_jumptarg_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol ATTRIBUTE_UNUSED,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
if (output_bfd != NULL)
{
unsigned long insn, tmp;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_32 (abfd, (bfd_byte *) data + addr);
tmp = insn | 0xfc000000;
tmp -= (input_section->output_offset >> 2);
insn = (insn & 0xfc000000) | (tmp & 0x03ffffff);
bfd_put_32 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
return bfd_reloc_continue;
}
static reloc_howto_type elf_or32_howto_table[] =
{
/* This reloc does nothing. */
@ -210,17 +454,14 @@ static const struct or32_reloc_map or32_reloc_map[] =
};
static reloc_howto_type *
bfd_elf32_bfd_reloc_type_lookup (abfd, code)
bfd *abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
for (i = ARRAY_SIZE (or32_reloc_map); i--;)
{
if (or32_reloc_map[i].bfd_reloc_val == code)
return &elf_or32_howto_table[or32_reloc_map[i].elf_reloc_val];
}
if (or32_reloc_map[i].bfd_reloc_val == code)
return &elf_or32_howto_table[or32_reloc_map[i].elf_reloc_val];
return NULL;
}
@ -228,10 +469,9 @@ bfd_elf32_bfd_reloc_type_lookup (abfd, code)
/* Set the howto pointer for an OR32 ELF reloc. */
static void
or32_info_to_howto_rel (abfd, cache_ptr, dst)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *cache_ptr;
Elf_Internal_Rela *dst;
or32_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
arelent *cache_ptr,
Elf_Internal_Rela *dst)
{
unsigned int r_type;
@ -240,301 +480,6 @@ or32_info_to_howto_rel (abfd, cache_ptr, dst)
cache_ptr->howto = &elf_or32_howto_table[r_type];
}
/* Set the right machine number for an OR32 ELF file. */
static bfd_boolean
or32_elf_object_p (abfd)
bfd *abfd;
{
(void) bfd_default_set_arch_mach (abfd, bfd_arch_or32, 0);
return TRUE;
}
/* The final processing done just before writing out an OR32 ELF object file.
This gets the OR32 architecture right based on the machine number. */
static void
or32_elf_final_write_processing (abfd, linker)
bfd *abfd;
bfd_boolean linker ATTRIBUTE_UNUSED;
{
int mach;
unsigned long val;
switch (mach = bfd_get_mach (abfd))
{
/*
case bfd_mach_arc_base:
val = E_OR32_MACH_BASE;
break;
*/
default:
val = 0;
return;
}
elf_elfheader (abfd)->e_flags &=~ EF_OR32_MACH;
elf_elfheader (abfd)->e_flags |= val;
}
bfd_reloc_status_type
or32_elf_32_reloc (abfd, reloc_entry, symbol, data, input_section,
output_bfd, error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message ATTRIBUTE_UNUSED;
{
if (output_bfd != (bfd *) NULL)
{
unsigned long insn;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_32 (abfd, (bfd_byte *) data + addr);
insn += symbol->section->output_section->vma;
insn += symbol->section->output_offset;
insn += symbol->value;
bfd_put_32 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
return bfd_reloc_continue;
}
bfd_reloc_status_type
or32_elf_16_reloc (abfd, reloc_entry, symbol, data, input_section,
output_bfd, error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message ATTRIBUTE_UNUSED;
{
if (output_bfd != (bfd *) NULL)
{
unsigned short insn;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_16 (abfd, (bfd_byte *) data + addr);
insn += symbol->section->output_section->vma;
insn += symbol->section->output_offset;
insn += symbol->value;
bfd_put_16 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
return bfd_reloc_continue;
}
bfd_reloc_status_type
or32_elf_8_reloc (abfd, reloc_entry, symbol, data, input_section,
output_bfd, error_message)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *reloc_entry;
asymbol *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message ATTRIBUTE_UNUSED;
{
if (output_bfd != (bfd *) NULL)
{
unsigned char insn;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_8 (abfd, (bfd_byte *) data + addr);
insn += symbol->section->output_section->vma;
insn += symbol->section->output_offset;
insn += symbol->value;
bfd_put_8 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
return bfd_reloc_continue;
}
/* Do a R_OR32_CONSTH relocation. This has to be done in combination
with a R_OR32_CONST reloc, because there is a carry from the LO16 to
the HI16. Here we just save the information we need; we do the
actual relocation when we see the LO16. OR32 ELF requires that the
LO16 immediately follow the HI16. As a GNU extension, we permit an
arbitrary number of HI16 relocs to be associated with a single LO16
reloc. This extension permits gcc to output the HI and LO relocs
itself. This code is copied from the elf32-mips.c. */
struct or32_consth
{
struct or32_consth *next;
bfd_byte *addr;
bfd_vma addend;
};
/* FIXME: This should not be a static variable. */
static struct or32_consth *or32_consth_list;
bfd_reloc_status_type
or32_elf_consth_reloc (abfd, reloc_entry, symbol, data, input_section,
output_bfd, error_message)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *reloc_entry;
asymbol *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message ATTRIBUTE_UNUSED;
{
bfd_reloc_status_type ret;
bfd_vma relocation;
struct or32_consth *n;
ret = bfd_reloc_ok;
if (bfd_is_und_section (symbol->section)
&& output_bfd == (bfd *) NULL)
ret = bfd_reloc_undefined;
if (bfd_is_com_section (symbol->section))
relocation = 0;
else
relocation = symbol->value;
relocation += symbol->section->output_section->vma;
relocation += symbol->section->output_offset;
relocation += reloc_entry->addend;
if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
return bfd_reloc_outofrange;
/* Save the information, and let LO16 do the actual relocation. */
n = (struct or32_consth *) bfd_malloc (sizeof *n);
if (n == NULL)
return bfd_reloc_outofrange;
n->addr = (bfd_byte *) data + reloc_entry->address;
n->addend = relocation;
n->next = or32_consth_list;
or32_consth_list = n;
if (output_bfd != (bfd *) NULL)
reloc_entry->address += input_section->output_offset;
return ret;
}
/* Do a R_OR32_CONST relocation. This is a straightforward 16 bit
inplace relocation; this function exists in order to do the
R_OR32_CONSTH relocation described above. */
bfd_reloc_status_type
or32_elf_const_reloc (abfd, reloc_entry, symbol, data, input_section,
output_bfd, error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message;
{
if (or32_consth_list != NULL)
{
struct or32_consth *l;
l = or32_consth_list;
while (l != NULL)
{
unsigned long insn;
unsigned long val;
unsigned long vallo;
struct or32_consth *next;
/* Do the HI16 relocation. Note that we actually don't need
to know anything about the LO16 itself, except where to
find the low 16 bits of the addend needed by the LO16. */
insn = bfd_get_32 (abfd, l->addr);
vallo = (bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address)
& 0xffff);
val = ((insn & 0xffff) << 16) + vallo;
val += l->addend;
insn = (insn &~ 0xffff) | ((val >> 16) & 0xffff);
bfd_put_32 (abfd, insn, l->addr);
next = l->next;
free (l);
l = next;
}
or32_consth_list = NULL;
}
if (output_bfd != (bfd *) NULL)
{
unsigned long insn, tmp;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_32 (abfd, (bfd_byte *) data + addr);
tmp = insn & 0x0000ffff;
tmp += symbol->section->output_section->vma;
tmp += symbol->section->output_offset;
tmp += symbol->value;
insn = (insn & 0xffff0000) | (tmp & 0x0000ffff);
bfd_put_32 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
/* Now do the LO16 reloc in the usual way. */
return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data,
input_section, output_bfd, error_message);
}
bfd_reloc_status_type
or32_elf_jumptarg_reloc (abfd, reloc_entry, symbol, data, input_section,
output_bfd, error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol ATTRIBUTE_UNUSED;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message ATTRIBUTE_UNUSED;
{
if (output_bfd != (bfd *) NULL)
{
unsigned long insn, tmp;
bfd_size_type addr = reloc_entry->address;
reloc_entry->address += input_section->output_offset;
insn = bfd_get_32 (abfd, (bfd_byte *) data + addr);
tmp = insn | 0xfc000000;
tmp -= (input_section->output_offset >> 2);
insn = (insn & 0xfc000000) | (tmp & 0x03ffffff);
bfd_put_32 (abfd, insn, (bfd_byte *) data + addr);
return bfd_reloc_ok;
}
return bfd_reloc_continue;
}
#define TARGET_LITTLE_SYM bfd_elf32_or32_little_vec
#define TARGET_LITTLE_NAME "elf32-littleor32"
#define TARGET_BIG_SYM bfd_elf32_or32_big_vec

366
bfd/elf32-pj.c
View File

@ -1,22 +1,22 @@
/* picoJava specific support for 32-bit ELF
Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1999, 2000, 2001, 2002, 2005 Free Software Foundation, Inc.
Contributed by Steve Chamberlan of Transmeta (sac@pobox.com).
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
@ -25,172 +25,17 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#include "elf-bfd.h"
#include "elf/pj.h"
static bfd_reloc_status_type pj_elf_reloc
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
static reloc_howto_type *pj_elf_reloc_type_lookup
PARAMS ((bfd *, bfd_reloc_code_real_type));
static void pj_elf_info_to_howto
PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
static void pj_elf_final_write_processing
PARAMS ((bfd *, bfd_boolean));
static reloc_howto_type pj_elf_howto_table[] =
{
/* No relocation. */
HOWTO (R_PJ_NONE, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
pj_elf_reloc, /* special_function */
"R_PJ_NONE", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* 32 bit absolute relocation. Setting partial_inplace to TRUE and
src_mask to a non-zero value is similar to the COFF toolchain. */
HOWTO (R_PJ_DATA_DIR32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
pj_elf_reloc, /* special_function */
"R_PJ_DIR32", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* 32 bit PC relative relocation. */
HOWTO (R_PJ_CODE_REL32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
pj_elf_reloc, /* special_function */
"R_PJ_REL32", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* 16 bit PC relative relocation. */
HOWTO (R_PJ_CODE_REL16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overf6w */
pj_elf_reloc, /* special_function */
"R_PJ_REL16", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
EMPTY_HOWTO (4),
EMPTY_HOWTO (5),
HOWTO (R_PJ_CODE_DIR32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
pj_elf_reloc, /* special_function */
"R_PJ_CODE_DIR32", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
EMPTY_HOWTO (7),
EMPTY_HOWTO (8),
EMPTY_HOWTO (9),
EMPTY_HOWTO (10),
EMPTY_HOWTO (11),
EMPTY_HOWTO (12),
HOWTO (R_PJ_CODE_LO16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_unsigned, /* complain_on_overflow */
pj_elf_reloc, /* special_function */
"R_PJ_LO16", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_PJ_CODE_HI16, /* type */
16, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_unsigned, /* complain_on_overflow */
pj_elf_reloc, /* special_function */
"R_PJ_HI16", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* GNU extension to record C++ vtable hierarchy */
HOWTO (R_PJ_GNU_VTINHERIT, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
NULL, /* special_function */
"R_PJ_GNU_VTINHERIT", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* GNU extension to record C++ vtable member usage */
HOWTO (R_PJ_GNU_VTENTRY, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
_bfd_elf_rel_vtable_reloc_fn, /* special_function */
"R_PJ_GNU_VTENTRY", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
};
/* This function is used for normal relocs. This is like the COFF
function, and is almost certainly incorrect for other ELF targets. */
static bfd_reloc_status_type
pj_elf_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol_in;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message ATTRIBUTE_UNUSED;
pj_elf_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol_in,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
unsigned long insn;
bfd_vma sym_value;
@ -262,6 +107,150 @@ pj_elf_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
return bfd_reloc_ok;
}
static reloc_howto_type pj_elf_howto_table[] =
{
/* No relocation. */
HOWTO (R_PJ_NONE, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
pj_elf_reloc, /* special_function */
"R_PJ_NONE", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* 32 bit absolute relocation. Setting partial_inplace to TRUE and
src_mask to a non-zero value is similar to the COFF toolchain. */
HOWTO (R_PJ_DATA_DIR32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
pj_elf_reloc, /* special_function */
"R_PJ_DIR32", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* 32 bit PC relative relocation. */
HOWTO (R_PJ_CODE_REL32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
pj_elf_reloc, /* special_function */
"R_PJ_REL32", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* 16 bit PC relative relocation. */
HOWTO (R_PJ_CODE_REL16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overf6w */
pj_elf_reloc, /* special_function */
"R_PJ_REL16", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
EMPTY_HOWTO (4),
EMPTY_HOWTO (5),
HOWTO (R_PJ_CODE_DIR32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
pj_elf_reloc, /* special_function */
"R_PJ_CODE_DIR32", /* name */
TRUE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
EMPTY_HOWTO (7),
EMPTY_HOWTO (8),
EMPTY_HOWTO (9),
EMPTY_HOWTO (10),
EMPTY_HOWTO (11),
EMPTY_HOWTO (12),
HOWTO (R_PJ_CODE_LO16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_unsigned, /* complain_on_overflow */
pj_elf_reloc, /* special_function */
"R_PJ_LO16", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_PJ_CODE_HI16, /* type */
16, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_unsigned, /* complain_on_overflow */
pj_elf_reloc, /* special_function */
"R_PJ_HI16", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* GNU extension to record C++ vtable hierarchy. */
HOWTO (R_PJ_GNU_VTINHERIT, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
NULL, /* special_function */
"R_PJ_GNU_VTINHERIT", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* GNU extension to record C++ vtable member usage. */
HOWTO (R_PJ_GNU_VTENTRY, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
_bfd_elf_rel_vtable_reloc_fn, /* special_function */
"R_PJ_GNU_VTENTRY", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
};
/* This structure is used to map BFD reloc codes to PJ ELF relocs. */
struct elf_reloc_map
@ -290,17 +279,14 @@ static const struct elf_reloc_map pj_reloc_map[] =
corresponding PJ ELf reloc. */
static reloc_howto_type *
pj_elf_reloc_type_lookup (abfd, code)
bfd *abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
pj_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
for (i = 0; i < sizeof (pj_reloc_map) / sizeof (struct elf_reloc_map); i++)
{
if (pj_reloc_map[i].bfd_reloc_val == code)
return &pj_elf_howto_table[(int) pj_reloc_map[i].elf_reloc_val];
}
if (pj_reloc_map[i].bfd_reloc_val == code)
return & pj_elf_howto_table[(int) pj_reloc_map[i].elf_reloc_val];
return NULL;
}
@ -308,10 +294,9 @@ pj_elf_reloc_type_lookup (abfd, code)
/* Given an ELF reloc, fill in the howto field of a relent. */
static void
pj_elf_info_to_howto (abfd, cache_ptr, dst)
bfd *abfd ATTRIBUTE_UNUSED;
arelent *cache_ptr;
Elf_Internal_Rela *dst;
pj_elf_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
arelent *cache_ptr,
Elf_Internal_Rela *dst)
{
unsigned int r;
@ -326,12 +311,11 @@ pj_elf_info_to_howto (abfd, cache_ptr, dst)
e_flags field. */
static void
pj_elf_final_write_processing (abfd, linker)
bfd *abfd;
bfd_boolean linker ATTRIBUTE_UNUSED;
pj_elf_final_write_processing (bfd *abfd,
bfd_boolean linker ATTRIBUTE_UNUSED)
{
elf_elfheader (abfd)->e_flags |= EF_PICOJAVA_ARCH;
elf_elfheader (abfd)->e_flags |= EF_PICOJAVA_GNUCALLS;
elf_elfheader (abfd)->e_flags |= EF_PICOJAVA_ARCH;
elf_elfheader (abfd)->e_flags |= EF_PICOJAVA_GNUCALLS;
}
#define TARGET_BIG_SYM bfd_elf32_pj_vec

1445
bfd/elf32-v850.c
View File

File diff suppressed because it is too large Load Diff

244
bfd/elf32-xstormy16.c
View File

@ -1,21 +1,22 @@
/* XSTORMY16-specific support for 32-bit ELF.
Copyright 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
/* Xstormy16-specific support for 32-bit ELF.
Copyright 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
USA. */
#include "bfd.h"
#include "sysdep.h"
@ -24,38 +25,48 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#include "elf/xstormy16.h"
#include "libiberty.h"
/* Forward declarations. */
static reloc_howto_type * xstormy16_reloc_type_lookup
PARAMS ((bfd *abfd, bfd_reloc_code_real_type code));
static void xstormy16_info_to_howto_rela
PARAMS ((bfd *, arelent *, Elf_Internal_Rela *));
static bfd_reloc_status_type xstormy16_elf_24_reloc
PARAMS ((bfd *abfd, arelent *reloc_entry, asymbol *symbol,
PTR data, asection *input_section, bfd *output_bfd,
char **error_message));
static bfd_boolean xstormy16_elf_check_relocs
PARAMS ((bfd *, struct bfd_link_info *, asection *,
const Elf_Internal_Rela *));
static bfd_boolean xstormy16_relax_plt_check
PARAMS ((struct elf_link_hash_entry *, PTR));
static bfd_boolean xstormy16_relax_plt_realloc
PARAMS ((struct elf_link_hash_entry *, PTR));
static bfd_boolean xstormy16_elf_relax_section
PARAMS ((bfd *abfd, asection *sec, struct bfd_link_info *link_info,
bfd_boolean *again));
static bfd_boolean xstormy16_elf_always_size_sections
PARAMS ((bfd *, struct bfd_link_info *));
static bfd_boolean xstormy16_elf_relocate_section
PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
Elf_Internal_Rela *, Elf_Internal_Sym *, asection **));
static bfd_boolean xstormy16_elf_finish_dynamic_sections
PARAMS((bfd *, struct bfd_link_info *));
static bfd_boolean xstormy16_elf_gc_sweep_hook
PARAMS ((bfd *, struct bfd_link_info *, asection *,
const Elf_Internal_Rela *));
static asection * xstormy16_elf_gc_mark_hook
PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *,
struct elf_link_hash_entry *, Elf_Internal_Sym *));
/* Handle the R_XSTORMY16_24 reloc, which has an odd bit arrangement. */
static bfd_reloc_status_type
xstormy16_elf_24_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void * data,
asection *input_section,
bfd *output_bfd,
char **error_message ATTRIBUTE_UNUSED)
{
bfd_vma relocation, x;
if (output_bfd != NULL)
{
reloc_entry->address += input_section->output_offset;
return bfd_reloc_ok;
}
if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
return bfd_reloc_outofrange;
if (bfd_is_com_section (symbol->section))
relocation = 0;
else
relocation = symbol->value;
relocation += symbol->section->output_section->vma;
relocation += symbol->section->output_offset;
relocation += reloc_entry->addend;
x = bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address);
x &= 0x0000ff00;
x |= relocation & 0xff;
x |= (relocation << 8) & 0xffff0000;
bfd_put_32 (abfd, x, (bfd_byte *) data + reloc_entry->address);
if (relocation & ~ (bfd_vma) 0xffffff)
return bfd_reloc_overflow;
return bfd_reloc_ok;
}
static reloc_howto_type xstormy16_elf_howto_table [] =
{
@ -238,7 +249,7 @@ static reloc_howto_type xstormy16_elf_howto_table [] =
0, /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* A 12 bit absolute relocation. */
HOWTO (R_XSTORMY16_12, /* type */
0, /* rightshift */
@ -318,9 +329,8 @@ static const reloc_map xstormy16_reloc_map [] =
};
static reloc_howto_type *
xstormy16_reloc_type_lookup (abfd, code)
bfd * abfd ATTRIBUTE_UNUSED;
bfd_reloc_code_real_type code;
xstormy16_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
@ -341,10 +351,9 @@ xstormy16_reloc_type_lookup (abfd, code)
/* Set the howto pointer for an XSTORMY16 ELF reloc. */
static void
xstormy16_info_to_howto_rela (abfd, cache_ptr, dst)
bfd * abfd ATTRIBUTE_UNUSED;
arelent * cache_ptr;
Elf_Internal_Rela * dst;
xstormy16_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
arelent * cache_ptr,
Elf_Internal_Rela * dst)
{
unsigned int r_type = ELF32_R_TYPE (dst->r_info);
@ -357,51 +366,6 @@ xstormy16_info_to_howto_rela (abfd, cache_ptr, dst)
else
abort ();
}
/* Handle the R_XSTORMY16_24 reloc, which has an odd bit arrangement. */
static bfd_reloc_status_type
xstormy16_elf_24_reloc (abfd, reloc_entry, symbol, data, input_section,
output_bfd, error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message ATTRIBUTE_UNUSED;
{
bfd_vma relocation, x;
if (output_bfd != NULL)
{
reloc_entry->address += input_section->output_offset;
return bfd_reloc_ok;
}
if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
return bfd_reloc_outofrange;
if (bfd_is_com_section (symbol->section))
relocation = 0;
else
relocation = symbol->value;
relocation += symbol->section->output_section->vma;
relocation += symbol->section->output_offset;
relocation += reloc_entry->addend;
x = bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address);
x &= 0x0000ff00;
x |= relocation & 0xff;
x |= (relocation << 8) & 0xffff0000;
bfd_put_32 (abfd, x, (bfd_byte *) data + reloc_entry->address);
if (relocation & ~ (bfd_vma) 0xffffff)
return bfd_reloc_overflow;
return bfd_reloc_ok;
}
/* We support 16-bit pointers to code above 64k by generating a thunk
below 64k containing a JMPF instruction to the final address. We
@ -410,11 +374,10 @@ xstormy16_elf_24_reloc (abfd, reloc_entry, symbol, data, input_section,
sections will fall in the address space. */
static bfd_boolean
xstormy16_elf_check_relocs (abfd, info, sec, relocs)
bfd *abfd;
struct bfd_link_info *info;
asection *sec;
const Elf_Internal_Rela *relocs;
xstormy16_elf_check_relocs (bfd *abfd,
struct bfd_link_info *info,
asection *sec,
const Elf_Internal_Rela *relocs)
{
const Elf_Internal_Rela *rel, *relend;
struct elf_link_hash_entry **sym_hashes;
@ -495,7 +458,7 @@ xstormy16_elf_check_relocs (abfd, info, sec, relocs)
unsigned int i;
size = symtab_hdr->sh_info * sizeof (bfd_vma);
local_plt_offsets = (bfd_vma *) bfd_alloc (abfd, size);
local_plt_offsets = bfd_alloc (abfd, size);
if (local_plt_offsets == NULL)
return FALSE;
elf_local_got_offsets (abfd) = local_plt_offsets;
@ -542,9 +505,7 @@ struct relax_plt_data
};
static bfd_boolean
xstormy16_relax_plt_check (h, xdata)
struct elf_link_hash_entry *h;
PTR xdata;
xstormy16_relax_plt_check (struct elf_link_hash_entry *h, void * xdata)
{
struct relax_plt_data *data = (struct relax_plt_data *) xdata;
@ -578,9 +539,7 @@ xstormy16_relax_plt_check (h, xdata)
previously had a plt entry, give it a new entry offset. */
static bfd_boolean
xstormy16_relax_plt_realloc (h, xdata)
struct elf_link_hash_entry *h;
PTR xdata;
xstormy16_relax_plt_realloc (struct elf_link_hash_entry *h, void * xdata)
{
bfd_vma *entry = (bfd_vma *) xdata;
@ -597,11 +556,10 @@ xstormy16_relax_plt_realloc (h, xdata)
}
static bfd_boolean
xstormy16_elf_relax_section (dynobj, splt, info, again)
bfd *dynobj;
asection *splt;
struct bfd_link_info *info;
bfd_boolean *again;
xstormy16_elf_relax_section (bfd *dynobj,
asection *splt,
struct bfd_link_info *info,
bfd_boolean *again)
{
struct relax_plt_data relax_plt_data;
bfd *ibfd;
@ -726,9 +684,8 @@ xstormy16_elf_relax_section (dynobj, splt, info, again)
}
static bfd_boolean
xstormy16_elf_always_size_sections (output_bfd, info)
bfd *output_bfd ATTRIBUTE_UNUSED;
struct bfd_link_info *info;
xstormy16_elf_always_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
struct bfd_link_info *info)
{
bfd *dynobj;
asection *splt;
@ -743,7 +700,7 @@ xstormy16_elf_always_size_sections (output_bfd, info)
splt = bfd_get_section_by_name (dynobj, ".plt");
BFD_ASSERT (splt != NULL);
splt->contents = (bfd_byte *) bfd_zalloc (dynobj, splt->size);
splt->contents = bfd_zalloc (dynobj, splt->size);
if (splt->contents == NULL)
return FALSE;
@ -781,16 +738,14 @@ xstormy16_elf_always_size_sections (output_bfd, info)
accordingly. */
static bfd_boolean
xstormy16_elf_relocate_section (output_bfd, info, input_bfd, input_section,
contents, relocs, local_syms, local_sections)
bfd * output_bfd ATTRIBUTE_UNUSED;
struct bfd_link_info * info;
bfd * input_bfd;
asection * input_section;
bfd_byte * contents;
Elf_Internal_Rela * relocs;
Elf_Internal_Sym * local_syms;
asection ** local_sections;
xstormy16_elf_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED,
struct bfd_link_info * info,
bfd * input_bfd,
asection * input_section,
bfd_byte * contents,
Elf_Internal_Rela * relocs,
Elf_Internal_Sym * local_syms,
asection ** local_sections)
{
Elf_Internal_Shdr * symtab_hdr;
struct elf_link_hash_entry ** sym_hashes;
@ -934,7 +889,7 @@ xstormy16_elf_relocate_section (output_bfd, info, input_bfd, input_section,
if (r != bfd_reloc_ok)
{
const char * msg = (const char *) NULL;
const char * msg = NULL;
switch (r)
{
@ -982,9 +937,8 @@ xstormy16_elf_relocate_section (output_bfd, info, input_bfd, input_section,
/* This must exist if dynobj is ever set. */
static bfd_boolean
xstormy16_elf_finish_dynamic_sections (abfd, info)
bfd *abfd ATTRIBUTE_UNUSED;
struct bfd_link_info *info;
xstormy16_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED,
struct bfd_link_info *info)
{
bfd *dynobj;
asection *splt;
@ -997,9 +951,11 @@ xstormy16_elf_finish_dynamic_sections (abfd, info)
{
bfd_byte *contents = splt->contents;
unsigned int i, size = splt->size;
for (i = 0; i < size; i += 4)
{
unsigned int x = bfd_get_32 (dynobj, contents + i);
BFD_ASSERT (x != 0);
}
}
@ -1011,12 +967,11 @@ xstormy16_elf_finish_dynamic_sections (abfd, info)
relocation. */
static asection *
xstormy16_elf_gc_mark_hook (sec, info, rel, h, sym)
asection * sec;
struct bfd_link_info * info ATTRIBUTE_UNUSED;
Elf_Internal_Rela * rel;
struct elf_link_hash_entry * h;
Elf_Internal_Sym * sym;
xstormy16_elf_gc_mark_hook (asection * sec,
struct bfd_link_info * info ATTRIBUTE_UNUSED,
Elf_Internal_Rela * rel,
struct elf_link_hash_entry * h,
Elf_Internal_Sym * sym)
{
if (h != NULL)
{
@ -1050,11 +1005,10 @@ xstormy16_elf_gc_mark_hook (sec, info, rel, h, sym)
/* Update the got entry reference counts for the section being removed. */
static bfd_boolean
xstormy16_elf_gc_sweep_hook (abfd, info, sec, relocs)
bfd * abfd ATTRIBUTE_UNUSED;
struct bfd_link_info * info ATTRIBUTE_UNUSED;
asection * sec ATTRIBUTE_UNUSED;
const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED;
xstormy16_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED,
struct bfd_link_info * info ATTRIBUTE_UNUSED,
asection * sec ATTRIBUTE_UNUSED,
const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED)
{
return TRUE;
}

7
cpu/ChangeLog
View File

@ -1,3 +1,10 @@
2005-07-01 Nick Clifton <nickc@redhat.com>
* frv.opc: Update to ISO C90 function declaration style.
* iq2000.opc: Likewise.
* m32r.opc: Likewise.
* sh.opc: Likewise.
2005-06-15 Dave Brolley <brolley@redhat.com>
Contributed by Red Hat.

582
cpu/frv.opc
View File

File diff suppressed because it is too large Load Diff

138
cpu/iq2000.opc
View File

@ -1,6 +1,6 @@
/* IQ2000 opcode support. -*- C -*-
Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 2000, 2001, 2002, 2005 Free Software Foundation, Inc.
Contributed by Red Hat Inc; developed under contract from Fujitsu.
@ -18,9 +18,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* This file is an addendum to iq2000.cpu. Heavy use of C code isn't
appropriate in .cpu files, so it resides here. This especially applies
@ -35,8 +34,7 @@
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
<arch>-ibd.h additions use: "-- ibd.h"
*/
<arch>-ibd.h additions use: "-- ibd.h". */
/* -- opc.h */
@ -52,30 +50,30 @@
instructions have same mnemonics but different functionality. */
#define CGEN_VALIDATE_INSN_SUPPORTED
extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn);
extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
/* -- asm.c */
static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_imm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
#include "safe-ctype.h"
static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
/* Special check to ensure that instruction exists for given machine. */
int
iq2000_cgen_insn_supported (cd, insn)
CGEN_CPU_DESC cd;
const CGEN_INSN *insn;
iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
{
int machs = cd->machs;
return ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0);
return (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0;
}
static int iq2000_cgen_isa_register (strp)
const char **strp;
static int
iq2000_cgen_isa_register (const char **strp)
{
int len;
int ch1, ch2;
if (**strp == 'r' || **strp == 'R')
{
len = strlen (*strp);
@ -95,7 +93,9 @@ static int iq2000_cgen_isa_register (strp)
return 1;
}
}
if (**strp == '%' && tolower((*strp)[1]) != 'l' && tolower((*strp)[1]) != 'h')
if (**strp == '%'
&& TOLOWER ((*strp)[1]) != 'l'
&& TOLOWER ((*strp)[1]) != 'h')
return 1;
return 0;
}
@ -103,16 +103,14 @@ static int iq2000_cgen_isa_register (strp)
/* Handle negated literal. */
static const char *
parse_mimm (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
parse_mimm (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
long value;
/* Verify this isn't a register */
/* Verify this isn't a register. */
if (iq2000_cgen_isa_register (strp))
errmsg = _("immediate value cannot be register");
else
@ -123,7 +121,8 @@ parse_mimm (cd, strp, opindex, valuep)
if (errmsg == NULL)
{
long x = (-value) & 0xFFFF0000;
if (x != 0 && x != 0xFFFF0000)
if (x != 0 && x != (long) 0xFFFF0000)
errmsg = _("immediate value out of range");
else
*valuep = (-value & 0xFFFF);
@ -135,14 +134,12 @@ parse_mimm (cd, strp, opindex, valuep)
/* Handle signed/unsigned literal. */
static const char *
parse_imm (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_imm (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
long value;
if (iq2000_cgen_isa_register (strp))
errmsg = _("immediate value cannot be register");
@ -154,7 +151,8 @@ parse_imm (cd, strp, opindex, valuep)
if (errmsg == NULL)
{
long x = value & 0xFFFF0000;
if (x != 0 && x != 0xFFFF0000)
if (x != 0 && x != (long) 0xFFFF0000)
errmsg = _("immediate value out of range");
else
*valuep = (value & 0xFFFF);
@ -166,23 +164,23 @@ parse_imm (cd, strp, opindex, valuep)
/* Handle iq10 21-bit jmp offset. */
static const char *
parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
int reloc;
enum cgen_parse_operand_result *type_addr;
bfd_vma *valuep;
parse_jtargq10 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
int reloc ATTRIBUTE_UNUSED,
enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED,
bfd_vma *valuep)
{
const char *errmsg;
bfd_vma value;
enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21,
&result_type, &value);
& result_type, & value);
if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
/* Check value is within 23-bits (remembering that 2-bit shift right will occur). */
/* Check value is within 23-bits
(remembering that 2-bit shift right will occur). */
if (value > 0x7fffff)
return _("21-bit offset out of range");
}
@ -193,11 +191,10 @@ parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep)
/* Handle high(). */
static const char *
parse_hi16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_hi16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
if (strncasecmp (*strp, "%hi(", 4) == 0)
{
@ -207,17 +204,17 @@ parse_hi16 (cd, strp, opindex, valuep)
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
/* if value has top-bit of %lo on, then it will
/* If value has top-bit of %lo on, then it will
sign-propagate and so we compensate by adding
1 to the resultant %hi value */
1 to the resultant %hi value. */
if (value & 0x8000)
value += 0x10000;
value >>= 16;
@ -227,8 +224,8 @@ parse_hi16 (cd, strp, opindex, valuep)
return errmsg;
}
/* we add %uhi in case a user just wants the high 16-bits or is using
an insn like ori for %lo which does not sign-propagate */
/* We add %uhi in case a user just wants the high 16-bits or is using
an insn like ori for %lo which does not sign-propagate. */
if (strncasecmp (*strp, "%uhi(", 5) == 0)
{
enum cgen_parse_operand_result result_type;
@ -237,16 +234,15 @@ parse_hi16 (cd, strp, opindex, valuep)
*strp += 5;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
value >>= 16;
}
value >>= 16;
*valuep = value;
return errmsg;
@ -260,11 +256,10 @@ parse_hi16 (cd, strp, opindex, valuep)
handles the case where %lo() isn't present. */
static const char *
parse_lo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
parse_lo16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
if (strncasecmp (*strp, "%lo(", 4) == 0)
{
@ -274,9 +269,9 @@ parse_lo16 (cd, strp, opindex, valuep)
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@ -293,11 +288,10 @@ parse_lo16 (cd, strp, opindex, valuep)
handles the case where %lo() isn't present. */
static const char *
parse_mlo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
parse_mlo16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
if (strncasecmp (*strp, "%lo(", 4) == 0)
{
@ -307,9 +301,9 @@ parse_mlo16 (cd, strp, opindex, valuep)
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)

122
cpu/m32r.opc
View File

@ -24,7 +24,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* This file is an addendum to m32r.cpu. Heavy use of C code isn't
appropriate in .cpu files, so it resides here. This especially applies
@ -55,56 +56,46 @@
: X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
: ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
#else
#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value)
extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT);
#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash (buffer, value)
extern unsigned int m32r_cgen_dis_hash (const char *, CGEN_INSN_INT);
#endif
/* -- */
/* -- opc.c */
unsigned int
m32r_cgen_dis_hash (buf, value)
const char * buf ATTRIBUTE_UNUSED;
CGEN_INSN_INT value;
m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value)
{
unsigned int x;
if (value & 0xffff0000) /* 32bit instructions */
if (value & 0xffff0000) /* 32bit instructions. */
value = (value >> 16) & 0xffff;
x = (value>>8) & 0xf0;
x = (value >> 8) & 0xf0;
if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
return x;
if (x == 0x70 || x == 0xf0)
return x | ((value>>8) & 0x0f);
return x | ((value >> 8) & 0x0f);
if (x == 0x30)
return x | ((value & 0x70) >> 4);
else
return x | ((value & 0xf0) >> 4);
}
/* -- */
/* -- asm.c */
static const char * parse_hash
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_hi16
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_slo16
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_ulo16
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
/* Handle '#' prefixes (i.e. skip over them). */
static const char *
parse_hash (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
const char **strp;
int opindex ATTRIBUTE_UNUSED;
long *valuep ATTRIBUTE_UNUSED;
parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
const char **strp,
int opindex ATTRIBUTE_UNUSED,
long *valuep ATTRIBUTE_UNUSED)
{
if (**strp == '#')
++*strp;
@ -114,11 +105,10 @@ parse_hash (cd, strp, opindex, valuep)
/* Handle shigh(), high(). */
static const char *
parse_hi16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_hi16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -131,9 +121,9 @@ parse_hi16 (cd, strp, opindex, valuep)
{
*strp += 5;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@ -145,9 +135,9 @@ parse_hi16 (cd, strp, opindex, valuep)
{
*strp += 6;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@ -167,11 +157,10 @@ parse_hi16 (cd, strp, opindex, valuep)
handles the case where low() isn't present. */
static const char *
parse_slo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
parse_slo16 (CGEN_CPU_DESC cd,
const char ** strp,
int opindex,
long * valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -184,9 +173,9 @@ parse_slo16 (cd, strp, opindex, valuep)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@ -203,9 +192,9 @@ parse_slo16 (cd, strp, opindex, valuep)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16,
NULL, &value);
NULL, & value);
if (**strp != ')')
return "missing `)'";
return MISSING_CLOSING_PARENTHESIS;
++*strp;
*valuep = value;
return errmsg;
@ -219,11 +208,10 @@ parse_slo16 (cd, strp, opindex, valuep)
handles the case where low() isn't present. */
static const char *
parse_ulo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_ulo16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -236,9 +224,9 @@ parse_ulo16 (cd, strp, opindex, valuep)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@ -253,9 +241,6 @@ parse_ulo16 (cd, strp, opindex, valuep)
/* -- */
/* -- dis.c */
static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
/* Immediate values are prefixed with '#'. */
#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \
@ -269,15 +254,15 @@ static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
/* Handle '#' prefixes as operands. */
static void
print_hash (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value ATTRIBUTE_UNUSED;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "#");
}
@ -285,17 +270,16 @@ print_hash (cd, dis_info, value, attrs, pc, length)
#define CGEN_PRINT_INSN my_print_insn
static int
my_print_insn (cd, pc, info)
CGEN_CPU_DESC cd;
bfd_vma pc;
disassemble_info *info;
my_print_insn (CGEN_CPU_DESC cd,
bfd_vma pc,
disassemble_info *info)
{
char buffer[CGEN_MAX_INSN_SIZE];
char *buf = buffer;
bfd_byte buffer[CGEN_MAX_INSN_SIZE];
bfd_byte *buf = buffer;
int status;
int buflen = (pc & 3) == 0 ? 4 : 2;
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
char *x;
bfd_byte *x;
/* Read the base part of the insn. */

34
cpu/sh.opc
View File

@ -1,6 +1,6 @@
/* SHmedia opcode support. -*- C -*-
Copyright 2000 Free Software Foundation, Inc.
Copyright 2000, 2005 Free Software Foundation, Inc.
Contributed by Red Hat Inc; developed under contract from Hitachi
Semiconductor (America) Inc.
@ -19,9 +19,9 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
*/
/* This file is an addendum to sh-media.cpu. Heavy use of C code isn't
appropriate in .cpu files, so it resides here. This especially applies
to assembly/disassembly where parsing/printing can be quite involved.
@ -35,8 +35,7 @@
<arch>-opc.c additions use: "-- opc.c"
<arch>-asm.c additions use: "-- asm.c"
<arch>-dis.c additions use: "-- dis.c"
<arch>-ibd.h additions use: "-- ibd.h"
*/
<arch>-ibd.h additions use: "-- ibd.h" */
/* -- opc.h */
@ -51,27 +50,26 @@
/* -- asm.c */
static const char *
parse_fsd (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
parse_fsd (CGEN_CPU_DESC cd,
const char ** strp,
int opindex,
long * valuep)
{
abort();
abort ();
}
/* -- dis.c */
static void
print_likely (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd;
PTR dis_info;
long value;
unsigned int attrs;
bfd_vma pc;
int length;
print_likely (CGEN_CPU_DESC cd,
void * dis_info,
long value,
unsigned int attrs,
bfd_vma pc,
int length)
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, (value) ? "/l" : "/u");
}

4
include/opcode/ChangeLog
View File

@ -1,3 +1,7 @@
2005-07-01 Nick Clifton <nickc@redhat.com>
* sparc.h: Add typedefs to structure declarations.
2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
PR 1013

160
include/opcode/sparc.h
View File

@ -1,24 +1,24 @@
/* Definitions for opcode table for the sparc.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
2003 Free Software Foundation, Inc.
2003, 2005 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
the GNU Binutils.
This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
the GNU Binutils.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
#include "ansidecl.h"
@ -37,17 +37,18 @@ Boston, MA 02110-1301, USA. */
The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
Don't change this without updating sparc-opc.c. */
enum sparc_opcode_arch_val {
enum sparc_opcode_arch_val
{
SPARC_OPCODE_ARCH_V6 = 0,
SPARC_OPCODE_ARCH_V7,
SPARC_OPCODE_ARCH_V8,
SPARC_OPCODE_ARCH_SPARCLET,
SPARC_OPCODE_ARCH_SPARCLITE,
/* v9 variants must appear last */
/* V9 variants must appear last. */
SPARC_OPCODE_ARCH_V9,
SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
};
/* The highest architecture in the table. */
@ -62,14 +63,15 @@ enum sparc_opcode_arch_val {
/* Table of cpu variants. */
struct sparc_opcode_arch {
typedef struct sparc_opcode_arch
{
const char *name;
/* Mask of sparc_opcode_arch_val's supported.
EG: For v7 this would be
(SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
These are short's because sparc_opcode.architecture is. */
short supported;
};
} sparc_opcode_arch;
extern const struct sparc_opcode_arch sparc_opcode_archs[];
@ -82,44 +84,43 @@ extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);
/* Non-zero if ARCH1 conflicts with ARCH2.
IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
!= SPARC_OPCODE_SUPPORTED (ARCH1)) \
&& ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
!= SPARC_OPCODE_SUPPORTED (ARCH1)) \
&& ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
!= SPARC_OPCODE_SUPPORTED (ARCH2)))
/* Structure of an opcode table entry. */
struct sparc_opcode {
typedef struct sparc_opcode
{
const char *name;
unsigned long match; /* Bits that must be set. */
unsigned long lose; /* Bits that must not be set. */
unsigned long match; /* Bits that must be set. */
unsigned long lose; /* Bits that must not be set. */
const char *args;
/* This was called "delayed" in versions before the flags. */
/* This was called "delayed" in versions before the flags. */
char flags;
short architecture; /* Bitmask of sparc_opcode_arch_val's. */
};
} sparc_opcode;
#define F_DELAYED 1 /* Delayed branch */
#define F_ALIAS 2 /* Alias for a "real" instruction */
#define F_UNBR 4 /* Unconditional branch */
#define F_CONDBR 8 /* Conditional branch */
#define F_JSR 16 /* Subroutine call */
#define F_FLOAT 32 /* Floating point instruction (not a branch) */
#define F_FBR 64 /* Floating point branch */
#define F_DELAYED 1 /* Delayed branch. */
#define F_ALIAS 2 /* Alias for a "real" instruction. */
#define F_UNBR 4 /* Unconditional branch. */
#define F_CONDBR 8 /* Conditional branch. */
#define F_JSR 16 /* Subroutine call. */
#define F_FLOAT 32 /* Floating point instruction (not a branch). */
#define F_FBR 64 /* Floating point branch. */
/* FIXME: Add F_ANACHRONISTIC flag for v9. */
/*
/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
macro), which is 64 bits. It is handled as a special case.
All sparc opcodes are 32 bits, except for the `set' instruction (really a
macro), which is 64 bits. It is handled as a special case.
The match component is a mask saying which bits must match a particular
opcode in order for an instruction to be an instance of that opcode.
The match component is a mask saying which bits must match a particular
opcode in order for an instruction to be an instance of that opcode.
The args component is a string containing one character for each operand of the
instruction.
The args component is a string containing one character for each operand of the
instruction.
Kinds of operands:
Kinds of operands:
# Number used by optimizer. It is ignored.
1 rs1 register.
2 rs2 register.
@ -187,37 +188,35 @@ Kinds of operands:
_ Ancillary state register in rd (v9a)
/ Ancillary state register in rs1 (v9a)
The following chars are unused: (note: ,[] are used as punctuation)
[45]
The following chars are unused: (note: ,[] are used as punctuation)
[45]. */
*/
#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
#define F1(x) (OP (x))
#define DISP30(x) ((x) & 0x3fffffff)
#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
#define ASI_RS2(x) (SIMM13 (x))
#define MEMBAR(x) ((x) & 0x7f)
#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */
#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */
#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */
#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */
#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */
#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */
#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */
#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
#define F1(x) (OP(x))
#define DISP30(x) ((x)&0x3fffffff)
#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */
#define RS2(x) ((x)&0x1f) /* rs2 field */
#define SIMM13(x) ((x)&0x1fff) /* simm13 field */
#define RD(x) (((x)&0x1f) << 25) /* destination register field */
#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */
#define ASI_RS2(x) (SIMM13(x))
#define MEMBAR(x) ((x)&0x7f)
#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */
#define ANNUL (1<<29)
#define BPRED (1<<19) /* v9 */
#define IMMED F3I(1)
#define RD_G0 RD(~0)
#define RS1_G0 RS1(~0)
#define RS2_G0 RS2(~0)
#define ANNUL (1 << 29)
#define BPRED (1 << 19) /* V9. */
#define IMMED F3I (1)
#define RD_G0 RD (~0)
#define RS1_G0 RS1 (~0)
#define RS2_G0 RS2 (~0)
extern const struct sparc_opcode sparc_opcodes[];
extern const int sparc_num_opcodes;
@ -231,11 +230,8 @@ extern const char *sparc_decode_prefetch (int);
extern int sparc_encode_sparclet_cpreg (const char *);
extern const char *sparc_decode_sparclet_cpreg (int);
/*
* Local Variables:
* fill-column: 131
* comment-column: 0
* End:
*/
/* Local Variables:
fill-column: 131
comment-column: 0
End: */
/* end of sparc.h */

59
opcodes/ChangeLog
View File

@ -1,3 +1,62 @@
2005-07-01 Nick Clifton <nickc@redhat.com>
* a29k-dis.c: Update to ISO C90 style function declarations and
fix formatting.
* alpha-opc.c: Likewise.
* arc-dis.c: Likewise.
* arc-opc.c: Likewise.
* avr-dis.c: Likewise.
* cgen-asm.in: Likewise.
* cgen-dis.in: Likewise.
* cgen-ibld.in: Likewise.
* cgen-opc.c: Likewise.
* cris-dis.c: Likewise.
* d10v-dis.c: Likewise.
* d30v-dis.c: Likewise.
* d30v-opc.c: Likewise.
* dis-buf.c: Likewise.
* dlx-dis.c: Likewise.
* h8300-dis.c: Likewise.
* h8500-dis.c: Likewise.
* hppa-dis.c: Likewise.
* i370-dis.c: Likewise.
* i370-opc.c: Likewise.
* m10200-dis.c: Likewise.
* m10300-dis.c: Likewise.
* m68k-dis.c: Likewise.
* m88k-dis.c: Likewise.
* mips-dis.c: Likewise.
* mmix-dis.c: Likewise.
* msp430-dis.c: Likewise.
* ns32k-dis.c: Likewise.
* or32-dis.c: Likewise.
* or32-opc.c: Likewise.
* pdp11-dis.c: Likewise.
* pj-dis.c: Likewise.
* s390-dis.c: Likewise.
* sh-dis.c: Likewise.
* sh64-dis.c: Likewise.
* sparc-dis.c: Likewise.
* sparc-opc.c: Likewise.
* sysdep.h: Likewise.
* tic30-dis.c: Likewise.
* tic4x-dis.c: Likewise.
* tic80-dis.c: Likewise.
* v850-dis.c: Likewise.
* v850-opc.c: Likewise.
* vax-dis.c: Likewise.
* w65-dis.c: Likewise.
* z8kgen.c: Likewise.
* fr30-*: Regenerate.
* frv-*: Regenerate.
* ip2k-*: Regenerate.
* iq2000-*: Regenerate.
* m32r-*: Regenerate.
* ms1-*: Regenerate.
* openrisc-*: Regenerate.
* xstormy16-*: Regenerate.
2005-06-23 Ben Elliston <bje@gnu.org>
* m68k-dis.c: Use ISC C90.

147
opcodes/a29k-dis.c
View File

@ -3,46 +3,34 @@
Free Software Foundation, Inc.
Contributed by Cygnus Support. Written by Jim Kingdon.
This file is part of GDB.
This file is part of GDB and GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "dis-asm.h"
#include "opcode/a29k.h"
static void print_general PARAMS ((int, struct disassemble_info *));
static void print_special PARAMS ((unsigned int, struct disassemble_info *));
static int is_delayed_branch PARAMS ((int));
static void find_bytes_little
PARAMS ((char *, unsigned char *, unsigned char *, unsigned char *,
unsigned char *));
static void find_bytes_big
PARAMS ((char *, unsigned char *, unsigned char *, unsigned char *,
unsigned char *));
static int print_insn PARAMS ((bfd_vma, struct disassemble_info *));
/* Print a symbolic representation of a general-purpose
register number NUM on STREAM.
NUM is a number as found in the instruction, not as found in
debugging symbols; it must be in the range 0-255. */
static void
print_general (num, info)
int num;
struct disassemble_info *info;
print_general (int num, struct disassemble_info *info)
{
if (num < 128)
(*info->fprintf_func) (info->stream, "gr%d", num);
@ -55,29 +43,31 @@ print_general (num, info)
The mnemonics used by the AMD assembler are not quite the same
as the ones in the User's Manual. We use the ones that the
assembler uses. */
static void
print_special (num, info)
unsigned int num;
struct disassemble_info *info;
print_special (unsigned int num, struct disassemble_info *info)
{
/* Register names of registers 0-SPEC0_NUM-1. */
static char *spec0_names[] = {
"vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr",
"pc0", "pc1", "pc2", "mmu", "lru", "rsn", "rma0", "rmc0", "rma1", "rmc1",
"spc0", "spc1", "spc2", "iba0", "ibc0", "iba1", "ibc1", "dba", "dbc",
"cir", "cdr"
static char *spec0_names[] =
{
"vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr",
"pc0", "pc1", "pc2", "mmu", "lru", "rsn", "rma0", "rmc0", "rma1", "rmc1",
"spc0", "spc1", "spc2", "iba0", "ibc0", "iba1", "ibc1", "dba", "dbc",
"cir", "cdr"
};
#define SPEC0_NUM ((sizeof spec0_names) / (sizeof spec0_names[0]))
/* Register names of registers 128-128+SPEC128_NUM-1. */
static char *spec128_names[] = {
"ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr"
static char *spec128_names[] =
{
"ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr"
};
#define SPEC128_NUM ((sizeof spec128_names) / (sizeof spec128_names[0]))
/* Register names of registers 160-160+SPEC160_NUM-1. */
static char *spec160_names[] = {
"fpe", "inte", "fps", "sr163", "exop"
static char *spec160_names[] =
{
"fpe", "inte", "fps", "sr163", "exop"
};
#define SPEC160_NUM ((sizeof spec160_names) / (sizeof spec160_names[0]))
@ -92,9 +82,9 @@ print_special (num, info)
}
/* Is an instruction with OPCODE a delayed branch? */
static int
is_delayed_branch (opcode)
int opcode;
is_delayed_branch (int opcode)
{
return (opcode == 0xa8 || opcode == 0xa9 || opcode == 0xa0 || opcode == 0xa1
|| opcode == 0xa4 || opcode == 0xa5
@ -105,13 +95,13 @@ is_delayed_branch (opcode)
}
/* Now find the four bytes of INSN and put them in *INSN{0,8,16,24}. */
static void
find_bytes_big (insn, insn0, insn8, insn16, insn24)
char *insn;
unsigned char *insn0;
unsigned char *insn8;
unsigned char *insn16;
unsigned char *insn24;
find_bytes_big (char *insn,
unsigned char *insn0,
unsigned char *insn8,
unsigned char *insn16,
unsigned char *insn24)
{
*insn24 = insn[0];
*insn16 = insn[1];
@ -120,12 +110,11 @@ find_bytes_big (insn, insn0, insn8, insn16, insn24)
}
static void
find_bytes_little (insn, insn0, insn8, insn16, insn24)
char *insn;
unsigned char *insn0;
unsigned char *insn8;
unsigned char *insn16;
unsigned char *insn24;
find_bytes_little (char *insn,
unsigned char *insn0,
unsigned char *insn8,
unsigned char *insn16,
unsigned char *insn24)
{
*insn24 = insn[3];
*insn16 = insn[2];
@ -134,16 +123,14 @@ find_bytes_little (insn, insn0, insn8, insn16, insn24)
}
typedef void (*find_byte_func_type)
PARAMS ((char *, unsigned char *, unsigned char *,
unsigned char *, unsigned char *));
(char *, unsigned char *, unsigned char *,
unsigned char *, unsigned char *);
/* Print one instruction from MEMADDR on INFO->STREAM.
Return the size of the instruction (always 4 on a29k). */
static int
print_insn (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
print_insn (bfd_vma memaddr, struct disassemble_info *info)
{
/* The raw instruction. */
char insn[4];
@ -169,11 +156,15 @@ print_insn (memaddr, info)
printf ("%02x%02x%02x%02x ", insn24, insn16, insn8, insn0);
/* Handle the nop (aseq 0x40,gr1,gr1) specially */
if ((insn24==0x70) && (insn16==0x40) && (insn8==0x01) && (insn0==0x01)) {
(*info->fprintf_func) (info->stream,"nop");
return 4;
}
/* Handle the nop (aseq 0x40,gr1,gr1) specially. */
if ( (insn24 == 0x70)
&& (insn16 == 0x40)
&& (insn8 == 0x01)
&& (insn0 == 0x01))
{
(*info->fprintf_func) (info->stream,"nop");
return 4;
}
/* The opcode is always in insn24. */
for (opcode = &a29k_opcodes[0];
@ -206,18 +197,19 @@ print_insn (memaddr, info)
break;
case 'x':
(*info->fprintf_func) (info->stream, "0x%x", (insn16 << 8) + insn0);
(*info->fprintf_func) (info->stream, "0x%x",
(insn16 << 8) + insn0);
break;
case 'h':
/* This used to be %x for binutils. */
(*info->fprintf_func) (info->stream, "0x%x",
(insn16 << 24) + (insn0 << 16));
(insn16 << 24) + (insn0 << 16));
break;
case 'X':
(*info->fprintf_func) (info->stream, "%d",
((insn16 << 8) + insn0) | 0xffff0000);
((insn16 << 8) + insn0) | 0xffff0000);
break;
case 'P':
@ -274,7 +266,8 @@ print_insn (memaddr, info)
break;
case 'F':
(*info->fprintf_func) (info->stream, "%d", (insn16 >> 2) & 15);
(*info->fprintf_func) (info->stream, "%d",
(insn16 >> 2) & 15);
break;
case 'C':
@ -308,14 +301,14 @@ print_insn (memaddr, info)
call _printf
consth _foo
*/
(*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8,
&prev_insn16, &prev_insn24);
(*find_byte_func) (prev_insn, & prev_insn0, & prev_insn8,
& prev_insn16, & prev_insn24);
if (is_delayed_branch (prev_insn24))
{
errcode = (*info->read_memory_func)
(memaddr - 8, (bfd_byte *) &prev_insn[0], 4, info);
(*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8,
&prev_insn16, &prev_insn24);
(memaddr - 8, (bfd_byte *) & prev_insn[0], 4, info);
(*find_byte_func) (prev_insn, & prev_insn0, & prev_insn8,
& prev_insn16, & prev_insn24);
}
}
@ -347,20 +340,18 @@ print_insn (memaddr, info)
}
/* Disassemble an big-endian a29k instruction. */
int
print_insn_big_a29k (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
print_insn_big_a29k (bfd_vma memaddr, struct disassemble_info *info)
{
info->private_data = (PTR) find_bytes_big;
return print_insn (memaddr, info);
}
/* Disassemble a little-endian a29k instruction. */
int
print_insn_little_a29k (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
print_insn_little_a29k (bfd_vma memaddr, struct disassemble_info *info)
{
info->private_data = (PTR) find_bytes_little;
return print_insn (memaddr, info);

412
opcodes/alpha-opc.c
View File

@ -1,5 +1,5 @@
/* alpha-opc.c -- Alpha AXP opcode list
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
Free Software Foundation, Inc.
Contributed by Richard Henderson <rth@cygnus.com>,
patterned after the PPC opcode handling written by Ian Lance Taylor.
@ -54,180 +54,21 @@
_Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */
/* Local insertion and extraction functions */
static unsigned insert_rba PARAMS((unsigned, int, const char **));
static unsigned insert_rca PARAMS((unsigned, int, const char **));
static unsigned insert_za PARAMS((unsigned, int, const char **));
static unsigned insert_zb PARAMS((unsigned, int, const char **));
static unsigned insert_zc PARAMS((unsigned, int, const char **));
static unsigned insert_bdisp PARAMS((unsigned, int, const char **));
static unsigned insert_jhint PARAMS((unsigned, int, const char **));
static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **));
static int extract_rba PARAMS((unsigned, int *));
static int extract_rca PARAMS((unsigned, int *));
static int extract_za PARAMS((unsigned, int *));
static int extract_zb PARAMS((unsigned, int *));
static int extract_zc PARAMS((unsigned, int *));
static int extract_bdisp PARAMS((unsigned, int *));
static int extract_jhint PARAMS((unsigned, int *));
static int extract_ev6hwjhint PARAMS((unsigned, int *));
/* The operands table */
const struct alpha_operand alpha_operands[] =
{
/* The fields are bits, shift, insert, extract, flags */
/* The zero index is used to indicate end-of-list */
#define UNUSED 0
{ 0, 0, 0, 0, 0, 0 },
/* The plain integer register fields */
#define RA (UNUSED + 1)
{ 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
#define RB (RA + 1)
{ 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
#define RC (RB + 1)
{ 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
/* The plain fp register fields */
#define FA (RC + 1)
{ 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
#define FB (FA + 1)
{ 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
#define FC (FB + 1)
{ 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
/* The integer registers when they are ZERO */
#define ZA (FC + 1)
{ 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
#define ZB (ZA + 1)
{ 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
#define ZC (ZB + 1)
{ 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
/* The RB field when it needs parentheses */
#define PRB (ZC + 1)
{ 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
/* The RB field when it needs parentheses _and_ a preceding comma */
#define CPRB (PRB + 1)
{ 5, 16, 0,
AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
/* The RB field when it must be the same as the RA field */
#define RBA (CPRB + 1)
{ 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
/* The RC field when it must be the same as the RB field */
#define RCA (RBA + 1)
{ 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
/* The RC field when it can *default* to RA */
#define DRC1 (RCA + 1)
{ 5, 0, 0,
AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
/* The RC field when it can *default* to RB */
#define DRC2 (DRC1 + 1)
{ 5, 0, 0,
AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
/* The FC field when it can *default* to RA */
#define DFC1 (DRC2 + 1)
{ 5, 0, 0,
AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
/* The FC field when it can *default* to RB */
#define DFC2 (DFC1 + 1)
{ 5, 0, 0,
AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
/* The unsigned 8-bit literal of Operate format insns */
#define LIT (DFC2 + 1)
{ 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
/* The signed 16-bit displacement of Memory format insns. From here
we can't tell what relocation should be used, so don't use a default. */
#define MDISP (LIT + 1)
{ 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
/* The signed "23-bit" aligned displacement of Branch format insns */
#define BDISP (MDISP + 1)
{ 21, 0, BFD_RELOC_23_PCREL_S2,
AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
/* The 26-bit PALcode function */
#define PALFN (BDISP + 1)
{ 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
/* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
#define JMPHINT (PALFN + 1)
{ 14, 0, BFD_RELOC_ALPHA_HINT,
AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
insert_jhint, extract_jhint },
/* The optional hint to RET/JSR_COROUTINE */
#define RETHINT (JMPHINT + 1)
{ 14, 0, -RETHINT,
AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
/* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
#define EV4HWDISP (RETHINT + 1)
#define EV6HWDISP (EV4HWDISP)
{ 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
/* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
#define EV4HWINDEX (EV4HWDISP + 1)
{ 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
/* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
that occur in DEC PALcode. */
#define EV4EXTHWINDEX (EV4HWINDEX + 1)
{ 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
/* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
#define EV5HWDISP (EV4EXTHWINDEX + 1)
{ 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
/* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
#define EV5HWINDEX (EV5HWDISP + 1)
{ 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
/* The 16-bit combined index/scoreboard mask for the ev6
hw_m[ft]pr (pal19/pal1d) insns */
#define EV6HWINDEX (EV5HWINDEX + 1)
{ 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
/* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
#define EV6HWJMPHINT (EV6HWINDEX+ 1)
{ 8, 0, -EV6HWJMPHINT,
AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
insert_ev6hwjhint, extract_ev6hwjhint }
};
const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
/* The RB field when it is the same as the RA field in the same insn.
This operand is marked fake. The insertion function just copies
the RA field into the RB field, and the extraction function just
checks that the fields are the same. */
static unsigned
insert_rba(insn, value, errmsg)
unsigned insn;
int value ATTRIBUTE_UNUSED;
const char **errmsg ATTRIBUTE_UNUSED;
insert_rba (unsigned insn,
int value ATTRIBUTE_UNUSED,
const char **errmsg ATTRIBUTE_UNUSED)
{
return insn | (((insn >> 21) & 0x1f) << 16);
}
static int
extract_rba(insn, invalid)
unsigned insn;
int *invalid;
extract_rba (unsigned insn, int *invalid)
{
if (invalid != (int *) NULL
&& ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
@ -235,22 +76,18 @@ extract_rba(insn, invalid)
return 0;
}
/* The same for the RC field */
/* The same for the RC field. */
static unsigned
insert_rca(insn, value, errmsg)
unsigned insn;
int value ATTRIBUTE_UNUSED;
const char **errmsg ATTRIBUTE_UNUSED;
insert_rca (unsigned insn,
int value ATTRIBUTE_UNUSED,
const char **errmsg ATTRIBUTE_UNUSED)
{
return insn | ((insn >> 21) & 0x1f);
}
static int
extract_rca(insn, invalid)
unsigned insn;
int *invalid;
extract_rca (unsigned insn, int *invalid)
{
if (invalid != (int *) NULL
&& ((insn >> 21) & 0x1f) != (insn & 0x1f))
@ -258,22 +95,18 @@ extract_rca(insn, invalid)
return 0;
}
/* Fake arguments in which the registers must be set to ZERO */
/* Fake arguments in which the registers must be set to ZERO. */
static unsigned
insert_za(insn, value, errmsg)
unsigned insn;
int value ATTRIBUTE_UNUSED;
const char **errmsg ATTRIBUTE_UNUSED;
insert_za (unsigned insn,
int value ATTRIBUTE_UNUSED,
const char **errmsg ATTRIBUTE_UNUSED)
{
return insn | (31 << 21);
}
static int
extract_za(insn, invalid)
unsigned insn;
int *invalid;
extract_za (unsigned insn, int *invalid)
{
if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
*invalid = 1;
@ -281,18 +114,15 @@ extract_za(insn, invalid)
}
static unsigned
insert_zb(insn, value, errmsg)
unsigned insn;
int value ATTRIBUTE_UNUSED;
const char **errmsg ATTRIBUTE_UNUSED;
insert_zb (unsigned insn,
int value ATTRIBUTE_UNUSED,
const char **errmsg ATTRIBUTE_UNUSED)
{
return insn | (31 << 16);
}
static int
extract_zb(insn, invalid)
unsigned insn;
int *invalid;
extract_zb (unsigned insn, int *invalid)
{
if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
*invalid = 1;
@ -300,18 +130,15 @@ extract_zb(insn, invalid)
}
static unsigned
insert_zc(insn, value, errmsg)
unsigned insn;
int value ATTRIBUTE_UNUSED;
const char **errmsg ATTRIBUTE_UNUSED;
insert_zc (unsigned insn,
int value ATTRIBUTE_UNUSED,
const char **errmsg ATTRIBUTE_UNUSED)
{
return insn | 31;
}
static int
extract_zc(insn, invalid)
unsigned insn;
int *invalid;
extract_zc (unsigned insn, int *invalid)
{
if (invalid != (int *) NULL && (insn & 0x1f) != 31)
*invalid = 1;
@ -322,10 +149,7 @@ extract_zc(insn, invalid)
/* The displacement field of a Branch format insn. */
static unsigned
insert_bdisp(insn, value, errmsg)
unsigned insn;
int value;
const char **errmsg;
insert_bdisp (unsigned insn, int value, const char **errmsg)
{
if (errmsg != (const char **)NULL && (value & 3))
*errmsg = _("branch operand unaligned");
@ -333,21 +157,15 @@ insert_bdisp(insn, value, errmsg)
}
static int
extract_bdisp(insn, invalid)
unsigned insn;
int *invalid ATTRIBUTE_UNUSED;
extract_bdisp (unsigned insn, int *invalid ATTRIBUTE_UNUSED)
{
return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
}
/* The hint field of a JMP/JSR insn. */
static unsigned
insert_jhint(insn, value, errmsg)
unsigned insn;
int value;
const char **errmsg;
insert_jhint (unsigned insn, int value, const char **errmsg)
{
if (errmsg != (const char **)NULL && (value & 3))
*errmsg = _("jump hint unaligned");
@ -355,9 +173,7 @@ insert_jhint(insn, value, errmsg)
}
static int
extract_jhint(insn, invalid)
unsigned insn;
int *invalid ATTRIBUTE_UNUSED;
extract_jhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED)
{
return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
}
@ -365,10 +181,7 @@ extract_jhint(insn, invalid)
/* The hint field of an EV6 HW_JMP/JSR insn. */
static unsigned
insert_ev6hwjhint(insn, value, errmsg)
unsigned insn;
int value;
const char **errmsg;
insert_ev6hwjhint (unsigned insn, int value, const char **errmsg)
{
if (errmsg != (const char **)NULL && (value & 3))
*errmsg = _("jump hint unaligned");
@ -376,64 +189,197 @@ insert_ev6hwjhint(insn, value, errmsg)
}
static int
extract_ev6hwjhint(insn, invalid)
unsigned insn;
int *invalid ATTRIBUTE_UNUSED;
extract_ev6hwjhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED)
{
return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
}
/* The operands table. */
const struct alpha_operand alpha_operands[] =
{
/* The fields are bits, shift, insert, extract, flags */
/* The zero index is used to indicate end-of-list */
#define UNUSED 0
{ 0, 0, 0, 0, 0, 0 },
/* The plain integer register fields. */
#define RA (UNUSED + 1)
{ 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
#define RB (RA + 1)
{ 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
#define RC (RB + 1)
{ 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
/* The plain fp register fields. */
#define FA (RC + 1)
{ 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
#define FB (FA + 1)
{ 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
#define FC (FB + 1)
{ 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
/* The integer registers when they are ZERO. */
#define ZA (FC + 1)
{ 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
#define ZB (ZA + 1)
{ 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
#define ZC (ZB + 1)
{ 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
/* The RB field when it needs parentheses. */
#define PRB (ZC + 1)
{ 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
/* The RB field when it needs parentheses _and_ a preceding comma. */
#define CPRB (PRB + 1)
{ 5, 16, 0,
AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
/* The RB field when it must be the same as the RA field. */
#define RBA (CPRB + 1)
{ 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
/* The RC field when it must be the same as the RB field. */
#define RCA (RBA + 1)
{ 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
/* The RC field when it can *default* to RA. */
#define DRC1 (RCA + 1)
{ 5, 0, 0,
AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
/* The RC field when it can *default* to RB. */
#define DRC2 (DRC1 + 1)
{ 5, 0, 0,
AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
/* The FC field when it can *default* to RA. */
#define DFC1 (DRC2 + 1)
{ 5, 0, 0,
AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
/* The FC field when it can *default* to RB. */
#define DFC2 (DFC1 + 1)
{ 5, 0, 0,
AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
/* The unsigned 8-bit literal of Operate format insns. */
#define LIT (DFC2 + 1)
{ 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
/* The signed 16-bit displacement of Memory format insns. From here
we can't tell what relocation should be used, so don't use a default. */
#define MDISP (LIT + 1)
{ 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
/* The signed "23-bit" aligned displacement of Branch format insns. */
#define BDISP (MDISP + 1)
{ 21, 0, BFD_RELOC_23_PCREL_S2,
AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
/* The 26-bit PALcode function */
#define PALFN (BDISP + 1)
{ 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
/* The optional signed "16-bit" aligned displacement of the JMP/JSR hint. */
#define JMPHINT (PALFN + 1)
{ 14, 0, BFD_RELOC_ALPHA_HINT,
AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
insert_jhint, extract_jhint },
/* The optional hint to RET/JSR_COROUTINE. */
#define RETHINT (JMPHINT + 1)
{ 14, 0, -RETHINT,
AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
/* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns. */
#define EV4HWDISP (RETHINT + 1)
#define EV6HWDISP (EV4HWDISP)
{ 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
/* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns. */
#define EV4HWINDEX (EV4HWDISP + 1)
{ 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
/* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
that occur in DEC PALcode. */
#define EV4EXTHWINDEX (EV4HWINDEX + 1)
{ 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
/* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns. */
#define EV5HWDISP (EV4EXTHWINDEX + 1)
{ 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
/* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns. */
#define EV5HWINDEX (EV5HWDISP + 1)
{ 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
/* The 16-bit combined index/scoreboard mask for the ev6
hw_m[ft]pr (pal19/pal1d) insns. */
#define EV6HWINDEX (EV5HWINDEX + 1)
{ 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
/* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn. */
#define EV6HWJMPHINT (EV6HWINDEX+ 1)
{ 8, 0, -EV6HWJMPHINT,
AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
insert_ev6hwjhint, extract_ev6hwjhint }
};
const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
/* Macros used to form opcodes */
/* Macros used to form opcodes. */
/* The main opcode */
/* The main opcode. */
#define OP(x) (((x) & 0x3F) << 26)
#define OP_MASK 0xFC000000
/* Branch format instructions */
/* Branch format instructions. */
#define BRA_(oo) OP(oo)
#define BRA_MASK OP_MASK
#define BRA(oo) BRA_(oo), BRA_MASK
/* Floating point format instructions */
/* Floating point format instructions. */
#define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5))
#define FP_MASK (OP_MASK | 0xFFE0)
#define FP(oo,fff) FP_(oo,fff), FP_MASK
/* Memory format instructions */
/* Memory format instructions. */
#define MEM_(oo) OP(oo)
#define MEM_MASK OP_MASK
#define MEM(oo) MEM_(oo), MEM_MASK
/* Memory/Func Code format instructions */
/* Memory/Func Code format instructions. */
#define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF))
#define MFC_MASK (OP_MASK | 0xFFFF)
#define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK
/* Memory/Branch format instructions */
/* Memory/Branch format instructions. */
#define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14))
#define MBR_MASK (OP_MASK | 0xC000)
#define MBR(oo,h) MBR_(oo,h), MBR_MASK
/* Operate format instructions. The OPRL variant specifies a
literal second argument. */
literal second argument. */
#define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5))
#define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000)
#define OPR_MASK (OP_MASK | 0x1FE0)
#define OPR(oo,ff) OPR_(oo,ff), OPR_MASK
#define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK
/* Generic PALcode format instructions */
/* Generic PALcode format instructions. */
#define PCD_(oo) OP(oo)
#define PCD_MASK OP_MASK
#define PCD(oo) PCD_(oo), PCD_MASK
/* Specific PALcode instructions */
/* Specific PALcode instructions. */
#define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF))
#define SPCD_MASK 0xFFFFFFFF
#define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK
/* Hardware memory (hw_{ld,st}) instructions */
/* Hardware memory (hw_{ld,st}) instructions. */
#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
#define EV4HWMEM_MASK (OP_MASK | 0xF000)
#define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK
@ -459,7 +405,7 @@ extract_ev6hwjhint(insn, invalid)
#define CIX AXP_OPCODE_CIX
#define MAX AXP_OPCODE_MAX
/* Common combinations of arguments */
/* Common combinations of arguments. */
#define ARG_NONE { 0 }
#define ARG_BRA { RA, BDISP }
#define ARG_FBRA { FA, BDISP }
@ -519,10 +465,10 @@ extract_ev6hwjhint(insn, invalid)
EV56 UNA opcodes that were introduced as of the ev56 with
presumably undefined results on previous implementations
that were not assigned to a particular extension.
*/
that were not assigned to a particular extension. */
const struct alpha_opcode alpha_opcodes[] = {
const struct alpha_opcode alpha_opcodes[] =
{
{ "halt", SPCD(0x00,0x0000), BASE, ARG_NONE },
{ "draina", SPCD(0x00,0x0002), BASE, ARG_NONE },
{ "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE },

266
opcodes/arc-dis.c
View File

@ -1,5 +1,5 @@
/* Instruction printing code for the ARC.
Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002
Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
@ -15,7 +15,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "ansidecl.h"
#include "libiberty.h"
@ -34,11 +35,11 @@
#define dbg (0)
#endif
/* Classification of the opcodes for the decoder to print
the instructions. */
typedef enum {
typedef enum
{
CLASS_A4_ARITH,
CLASS_A4_OP3_GENERAL,
CLASS_A4_FLAG,
@ -56,7 +57,6 @@ typedef enum {
CLASS_A4_LR
} a4_decoding_class;
#define BIT(word,n) ((word) & (1 << n))
#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
#define OPCODE(word) (BITS ((word), 27, 31))
@ -64,7 +64,6 @@ typedef enum {
#define FIELDB(word) (BITS ((word), 15, 20))
#define FIELDC(word) (BITS ((word), 9, 14))
/* FIELD D is signed in all of its uses, so we make sure argument is
treated as signed for bit shifting purposes: */
#define FIELDD(word) (BITS (((signed int)word), 0, 8))
@ -146,15 +145,15 @@ typedef enum {
} \
while (0)
#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
#define IS_REG(x) (field##x##isReg)
#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","")
#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[")
#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]")
#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]")
#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","")
#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",")
#define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","")
#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
#define IS_REG(x) (field##x##isReg)
#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT (x, "[","]","","")
#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT (x, "",",[","",",[")
#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT (x, ",","]",",","]")
#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT (x, "","]","","]")
#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT (x, ",","",",","")
#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT (x, "",",","",",")
#define WRITE_FORMAT_x(x) WRITE_FORMAT (x, "","","","")
#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
(IS_REG (x) ? cb1"%r"ca1 : \
usesAuxReg ? cb"%a"ca : \
@ -169,25 +168,8 @@ typedef enum {
static char comment_prefix[] = "\t; ";
static const char *core_reg_name PARAMS ((struct arcDisState *, int));
static const char *aux_reg_name PARAMS ((struct arcDisState *, int));
static const char *cond_code_name PARAMS ((struct arcDisState *, int));
static const char *instruction_name
PARAMS ((struct arcDisState *, int, int, int *));
static void mwerror PARAMS ((struct arcDisState *, const char *));
static const char *post_address PARAMS ((struct arcDisState *, int));
static void write_comments_
PARAMS ((struct arcDisState *, int, int, long int));
static void write_instr_name_
PARAMS ((struct arcDisState *, const char *, int, int, int, int, int, int));
static int dsmOneArcInst PARAMS ((bfd_vma, struct arcDisState *));
static const char *_coreRegName PARAMS ((void *, int));
static int decodeInstr PARAMS ((bfd_vma, disassemble_info *));
static const char *
core_reg_name (state, val)
struct arcDisState * state;
int val;
core_reg_name (struct arcDisState * state, int val)
{
if (state->coreRegName)
return (*state->coreRegName)(state->_this, val);
@ -195,9 +177,7 @@ core_reg_name (state, val)
}
static const char *
aux_reg_name (state, val)
struct arcDisState * state;
int val;
aux_reg_name (struct arcDisState * state, int val)
{
if (state->auxRegName)
return (*state->auxRegName)(state->_this, val);
@ -205,9 +185,7 @@ aux_reg_name (state, val)
}
static const char *
cond_code_name (state, val)
struct arcDisState * state;
int val;
cond_code_name (struct arcDisState * state, int val)
{
if (state->condCodeName)
return (*state->condCodeName)(state->_this, val);
@ -215,11 +193,10 @@ cond_code_name (state, val)
}
static const char *
instruction_name (state, op1, op2, flags)
struct arcDisState * state;
int op1;
int op2;
int * flags;
instruction_name (struct arcDisState * state,
int op1,
int op2,
int * flags)
{
if (state->instName)
return (*state->instName)(state->_this, op1, op2, flags);
@ -227,18 +204,14 @@ instruction_name (state, op1, op2, flags)
}
static void
mwerror (state, msg)
struct arcDisState * state;
const char * msg;
mwerror (struct arcDisState * state, const char * msg)
{
if (state->err != 0)
(*state->err)(state->_this, (msg));
}
static const char *
post_address (state, addr)
struct arcDisState * state;
int addr;
post_address (struct arcDisState * state, int addr)
{
static char id[3 * ARRAY_SIZE (state->addresses)];
int j, i = state->acnt;
@ -257,22 +230,16 @@ post_address (state, addr)
return "";
}
static void my_sprintf PARAMS ((struct arcDisState *, char *, const char *,
...));
static void
my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format,
...))
arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
{
char *bp;
const char *p;
int size, leading_zero, regMap[2];
long auxNum;
va_list ap;
VA_OPEN (ap, format);
VA_FIXEDARG (ap, struct arcDisState *, state);
VA_FIXEDARG (ap, char *, buf);
VA_FIXEDARG (ap, const char *, format);
va_start (ap, format);
bp = buf;
*bp = 0;
@ -413,7 +380,7 @@ my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format,
if (ext)
sprintf (bp, "%s", ext);
else
my_sprintf (state, bp, "%h", val);
arc_sprintf (state, bp, "%h", val);
}
break;
}
@ -435,15 +402,14 @@ my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format,
}
DOCOMM: *bp = 0;
VA_CLOSE (ap);
va_end (ap);
}
static void
write_comments_(state, shimm, is_limm, limm_value)
struct arcDisState * state;
int shimm;
int is_limm;
long limm_value;
write_comments_(struct arcDisState * state,
int shimm,
int is_limm,
long limm_value)
{
if (state->commentBuffer != 0)
{
@ -468,25 +434,25 @@ write_comments_(state, shimm, is_limm, limm_value)
}
}
#define write_comments2(x) write_comments_(state, x, is_limm, limm_value)
#define write_comments() write_comments2(0)
#define write_comments2(x) write_comments_ (state, x, is_limm, limm_value)
#define write_comments() write_comments2 (0)
static const char *condName[] = {
static const char *condName[] =
{
/* 0..15. */
"" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
"nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
};
static void
write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem)
struct arcDisState * state;
const char * instrName;
int cond;
int condCodeIsPartOfName;
int flag;
int signExtend;
int addrWriteBack;
int directMem;
write_instr_name_(struct arcDisState * state,
const char * instrName,
int cond,
int condCodeIsPartOfName,
int flag,
int signExtend,
int addrWriteBack,
int directMem)
{
strcpy (state->instrBuffer, instrName);
@ -540,7 +506,8 @@ write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend
} \
while (0)
enum {
enum
{
op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3,
op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7,
op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
@ -550,9 +517,7 @@ enum {
extern disassemble_info tm_print_insn_info;
static int
dsmOneArcInst (addr, state)
bfd_vma addr;
struct arcDisState * state;
dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
{
int condCodeIsPartOfName = 0;
a4_decoding_class decodingClass;
@ -641,7 +606,7 @@ dsmOneArcInst (addr, state)
}
else
{
switch (BITS (state->words[0],10,11))
switch (BITS (state->words[0], 10, 11))
{
case 0:
instrName = "ld";
@ -665,14 +630,14 @@ dsmOneArcInst (addr, state)
break;
case op_ST:
if (BIT (state->words[0],25))
if (BIT (state->words[0], 25))
{
instrName = "sr";
decodingClass = CLASS_A4_SR;
}
else
{
switch (BITS (state->words[0],22,23))
switch (BITS (state->words[0], 22, 23))
{
case 0:
instrName = "st";
@ -727,7 +692,7 @@ dsmOneArcInst (addr, state)
case 0x3f:
{
decodingClass = CLASS_A4_OP3_SUBOPC3F;
switch( FIELDD (state->words[0]) )
switch (FIELDD (state->words[0]))
{
case 0:
instrName = "brk";
@ -822,7 +787,7 @@ dsmOneArcInst (addr, state)
case op_XOR:
if (state->words[0] == 0x7fffffff)
{
/* nop encoded as xor -1, -1, -1 */
/* NOP encoded as xor -1, -1, -1. */
instrName = "nop";
decodingClass = CLASS_A4_OP3_SUBOPC3F;
}
@ -866,7 +831,7 @@ dsmOneArcInst (addr, state)
if (!repeatsOp)
WRITE_FORMAT_COMMA_x (C);
WRITE_NOP_COMMENT ();
my_sprintf (state, state->operandBuffer, formatString,
arc_sprintf (state, state->operandBuffer, formatString,
fieldA, fieldB, fieldC);
}
else
@ -874,7 +839,7 @@ dsmOneArcInst (addr, state)
WRITE_FORMAT_x (B);
if (!repeatsOp)
WRITE_FORMAT_COMMA_x (C);
my_sprintf (state, state->operandBuffer, formatString,
arc_sprintf (state, state->operandBuffer, formatString,
fieldB, fieldC);
}
write_comments ();
@ -891,13 +856,13 @@ dsmOneArcInst (addr, state)
WRITE_FORMAT_x (A);
WRITE_FORMAT_COMMA_x (B);
WRITE_NOP_COMMENT ();
my_sprintf (state, state->operandBuffer, formatString,
arc_sprintf (state, state->operandBuffer, formatString,
fieldA, fieldB);
}
else
{
WRITE_FORMAT_x (B);
my_sprintf (state, state->operandBuffer, formatString, fieldB);
arc_sprintf (state, state->operandBuffer, formatString, fieldB);
}
write_comments ();
break;
@ -905,17 +870,17 @@ dsmOneArcInst (addr, state)
case CLASS_A4_FLAG:
CHECK_FIELD_B ();
CHECK_FLAG_COND_NULLIFY ();
flag = 0; /* this is the FLAG instruction -- it's redundant */
flag = 0; /* This is the FLAG instruction -- it's redundant. */
write_instr_name ();
WRITE_FORMAT_x (B);
my_sprintf (state, state->operandBuffer, formatString, fieldB);
arc_sprintf (state, state->operandBuffer, formatString, fieldB);
write_comments ();
break;
case CLASS_A4_BRANCH:
fieldA = BITS (state->words[0],7,26) << 2;
fieldA = (fieldA << 10) >> 10; /* make it signed */
fieldA = (fieldA << 10) >> 10; /* Make it signed. */
fieldA += addr + 4;
CHECK_FLAG_COND_NULLIFY ();
flag = 0;
@ -932,8 +897,8 @@ dsmOneArcInst (addr, state)
lr dest<- func addr; j [dest]" */
}
strcat (formatString, "%s"); /* address/label name */
my_sprintf (state, state->operandBuffer, formatString,
strcat (formatString, "%s"); /* Address/label name. */
arc_sprintf (state, state->operandBuffer, formatString,
post_address (state, fieldA));
write_comments ();
break;
@ -949,12 +914,12 @@ dsmOneArcInst (addr, state)
if (!fieldBisReg)
{
fieldAisReg = 0;
fieldA = (fieldB >> 25) & 0x7F; /* flags */
fieldA = (fieldB >> 25) & 0x7F; /* Flags. */
fieldB = (fieldB & 0xFFFFFF) << 2;
state->flow = is_linked ? direct_call : direct_jump;
add_target (fieldB);
/* screwy JLcc requires .jd mode to execute correctly
* but we pretend it is .nd (no delay slot). */
/* Screwy JLcc requires .jd mode to execute correctly
but we pretend it is .nd (no delay slot). */
if (is_linked && state->nullifyMode == BR_exec_when_jump)
state->nullifyMode = BR_exec_when_no_jump;
}
@ -962,24 +927,24 @@ dsmOneArcInst (addr, state)
{
state->flow = is_linked ? indirect_call : indirect_jump;
/* We should also treat this as indirect call if NOT linked
* but the preceding instruction was a "lr blink,[status]"
* and we have a delay slot with "add blink,blink,2".
* For now we can't detect such. */
but the preceding instruction was a "lr blink,[status]"
and we have a delay slot with "add blink,blink,2".
For now we can't detect such. */
state->register_for_indirect_jump = fieldB;
}
write_instr_name ();
strcat (formatString,
IS_REG (B) ? "[%r]" : "%s"); /* address/label name */
IS_REG (B) ? "[%r]" : "%s"); /* Address/label name. */
if (fieldA != 0)
{
fieldAisReg = 0;
WRITE_FORMAT_COMMA_x (A);
}
if (IS_REG (B))
my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
else
my_sprintf (state, state->operandBuffer, formatString,
arc_sprintf (state, state->operandBuffer, formatString,
post_address (state, fieldB), fieldA);
write_comments ();
break;
@ -1005,9 +970,9 @@ dsmOneArcInst (addr, state)
state->_offset += fieldC;
state->_mem_load = 1;
directMem = BIT (state->words[0],5);
addrWriteBack = BIT (state->words[0],3);
signExtend = BIT (state->words[0],0);
directMem = BIT (state->words[0], 5);
addrWriteBack = BIT (state->words[0], 3);
signExtend = BIT (state->words[0], 0);
write_instr_name ();
WRITE_FORMAT_x_COMMA_LB(A);
@ -1017,7 +982,7 @@ dsmOneArcInst (addr, state)
fieldB = fieldC;
WRITE_FORMAT_x_RB (C);
my_sprintf (state, state->operandBuffer, formatString,
arc_sprintf (state, state->operandBuffer, formatString,
fieldA, fieldB, fieldC);
write_comments ();
break;
@ -1036,7 +1001,7 @@ dsmOneArcInst (addr, state)
state->_mem_load = 1;
if (fieldBisReg)
state->ea_reg1 = fieldB;
/* field B is either a shimm (same as fieldC) or limm (different!)
/* Field B is either a shimm (same as fieldC) or limm (different!)
Say ea is not present, so only one of us will do the name lookup. */
else
state->_offset += fieldB, state->_ea_present = 0;
@ -1063,7 +1028,7 @@ dsmOneArcInst (addr, state)
else
WRITE_FORMAT_RB ();
}
my_sprintf (state, state->operandBuffer, formatString,
arc_sprintf (state, state->operandBuffer, formatString,
fieldA, fieldB, fieldC);
write_comments ();
break;
@ -1081,26 +1046,26 @@ dsmOneArcInst (addr, state)
state->_offset = fieldA;
if (fieldBisReg)
state->ea_reg1 = fieldB;
/* field B is either a shimm (same as fieldA) or limm (different!)
/* Field B is either a shimm (same as fieldA) or limm (different!)
Say ea is not present, so only one of us will do the name lookup.
(for is_limm we do the name translation here). */
else
state->_offset += fieldB, state->_ea_present = 0;
directMem = BIT(state->words[0],26);
addrWriteBack = BIT(state->words[0],24);
directMem = BIT (state->words[0], 26);
addrWriteBack = BIT (state->words[0], 24);
write_instr_name();
write_instr_name ();
WRITE_FORMAT_x_COMMA_LB(C);
if (!fieldBisReg)
{
fieldB = state->_offset;
WRITE_FORMAT_x_RB(B);
WRITE_FORMAT_x_RB (B);
}
else
{
WRITE_FORMAT_x(B);
WRITE_FORMAT_x (B);
if (fieldBisReg && fieldA != 0)
{
fieldAisReg = 0;
@ -1109,9 +1074,9 @@ dsmOneArcInst (addr, state)
else
WRITE_FORMAT_RB();
}
my_sprintf (state, state->operandBuffer, formatString,
arc_sprintf (state, state->operandBuffer, formatString,
fieldC, fieldB, fieldA);
write_comments2(fieldA);
write_comments2 (fieldA);
break;
case CLASS_A4_SR:
@ -1119,37 +1084,36 @@ dsmOneArcInst (addr, state)
CHECK_FIELD_B();
CHECK_FIELD_C();
write_instr_name();
write_instr_name ();
WRITE_FORMAT_x_COMMA_LB(C);
/* Try to print B as an aux reg if it is not a core reg. */
usesAuxReg = 1;
WRITE_FORMAT_x(B);
WRITE_FORMAT_RB();
my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
write_comments();
WRITE_FORMAT_x (B);
WRITE_FORMAT_RB ();
arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
write_comments ();
break;
case CLASS_A4_OP3_SUBOPC3F:
write_instr_name();
write_instr_name ();
state->operandBuffer[0] = '\0';
break;
case CLASS_A4_LR:
/* LR instruction */
CHECK_FIELD_A();
CHECK_FIELD_B();
CHECK_FIELD_A ();
CHECK_FIELD_B ();
write_instr_name();
WRITE_FORMAT_x_COMMA_LB(A);
write_instr_name ();
WRITE_FORMAT_x_COMMA_LB (A);
/* Try to print B as an aux reg if it is not a core reg. */
usesAuxReg = 1;
WRITE_FORMAT_x(B);
WRITE_FORMAT_RB();
my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
write_comments();
WRITE_FORMAT_x (B);
WRITE_FORMAT_RB ();
arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
write_comments ();
break;
default:
mwerror (state, "Bad decoding class in ARC disassembler");
break;
@ -1161,23 +1125,23 @@ dsmOneArcInst (addr, state)
/* Returns the name the user specified core extension register. */
static const char *
_coreRegName(arg, regval)
void * arg ATTRIBUTE_UNUSED;
int regval;
_coreRegName(void * arg ATTRIBUTE_UNUSED, int regval)
{
return arcExtMap_coreRegName (regval);
}
/* Returns the name the user specified AUX extension register. */
static const char *
_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
{
return arcExtMap_auxRegName(regval);
}
/* Returns the name the user specified condition code name. */
static const char *
_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
{
@ -1185,6 +1149,7 @@ _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
}
/* Returns the name the user specified extension instruction. */
static const char *
_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
{
@ -1193,15 +1158,15 @@ _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
/* Decode an instruction returning the size of the instruction
in bytes or zero if unrecognized. */
static int
decodeInstr (address, info)
bfd_vma address; /* Address of this instruction. */
disassemble_info * info;
decodeInstr (bfd_vma address, /* Address of this instruction. */
disassemble_info * info)
{
int status;
bfd_byte buffer[4];
struct arcDisState s; /* ARC Disassembler state */
void *stream = info->stream; /* output stream */
struct arcDisState s; /* ARC Disassembler state. */
void *stream = info->stream; /* Output stream. */
fprintf_ftype func = info->fprintf_func;
int bytes;
@ -1218,9 +1183,9 @@ decodeInstr (address, info)
s.words[0] = bfd_getl32(buffer);
else
s.words[0] = bfd_getb32(buffer);
/* always read second word in case of limm */
/* Always read second word in case of limm. */
/* we ignore the result since last insn may not have a limm */
/* We ignore the result since last insn may not have a limm. */
status = (*info->read_memory_func) (address + 4, buffer, 4, info);
if (info->endian == BFD_ENDIAN_LITTLE)
s.words[1] = bfd_getl32(buffer);
@ -1233,23 +1198,24 @@ decodeInstr (address, info)
s.condCodeName = _condCodeName;
s.instName = _instName;
/* disassemble */
bytes = dsmOneArcInst(address, (void *)&s);
/* Disassemble. */
bytes = dsmOneArcInst (address, (void *)& s);
/* display the disassembly instruction */
/* Display the disassembly instruction. */
(*func) (stream, "%08x ", s.words[0]);
(*func) (stream, " ");
(*func) (stream, "%-10s ", s.instrBuffer);
if (__TRANSLATION_REQUIRED(s))
if (__TRANSLATION_REQUIRED (s))
{
bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
(*info->print_address_func) ((bfd_vma) addr, info);
(*func) (stream, "\n");
}
else
(*func) (stream, "%s",s.operandBuffer);
return s.instructionLen;
}

2332
opcodes/arc-opc.c
View File

File diff suppressed because it is too large Load Diff

68
opcodes/avr-dis.c
View File

@ -1,21 +1,21 @@
/* Disassemble AVR instructions.
Copyright 1999, 2000, 2002, 2004 Free Software Foundation, Inc.
Copyright 1999, 2000, 2002, 2004, 2005 Free Software Foundation, Inc.
Contributed by Denis Chertykov <denisc@overta.ru>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#include <assert.h>
#include "sysdep.h"
@ -28,7 +28,7 @@ struct avr_opcodes_s
char *name;
char *constraints;
char *opcode;
int insn_size; /* in words */
int insn_size; /* In words. */
int isa;
unsigned int bin_opcode;
};
@ -42,9 +42,6 @@ const struct avr_opcodes_s avr_opcodes[] =
{NULL, NULL, NULL, 0, 0, 0}
};
static int avr_operand (unsigned int, unsigned int, unsigned int, int,
char *, char *, int, int *, bfd_vma *);
static int
avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constraint,
char *buf, char *comment, int regs, int *sym, bfd_vma *sym_addr)
@ -57,9 +54,9 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
/* Any register operand. */
case 'r':
if (regs)
insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */
insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* Source register. */
else
insn = (insn & 0x01f0) >> 4; /* destination register */
insn = (insn & 0x01f0) >> 4; /* Destination register. */
sprintf (buf, "r%d", insn);
break;
@ -201,6 +198,7 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
case 'P':
{
unsigned int x;
x = (insn & 0xf);
x |= (insn >> 5) & 0x30;
sprintf (buf, "0x%02x", x);
@ -231,29 +229,24 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
return ok;
}
static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *));
static unsigned short
avrdis_opcode (addr, info)
bfd_vma addr;
disassemble_info *info;
avrdis_opcode (bfd_vma addr, disassemble_info *info)
{
bfd_byte buffer[2];
int status;
status = info->read_memory_func(addr, buffer, 2, info);
if (status != 0)
{
info->memory_error_func(status, addr, info);
return -1;
}
return bfd_getl16 (buffer);
status = info->read_memory_func (addr, buffer, 2, info);
if (status == 0)
return bfd_getl16 (buffer);
info->memory_error_func (status, addr, info);
return -1;
}
int
print_insn_avr(addr, info)
bfd_vma addr;
disassemble_info *info;
print_insn_avr (bfd_vma addr, disassemble_info *info)
{
unsigned int insn, insn2;
const struct avr_opcodes_s *opcode;
@ -274,8 +267,7 @@ print_insn_avr(addr, info)
nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s);
avr_bin_masks = (unsigned int *)
xmalloc (nopcodes * sizeof (unsigned int));
avr_bin_masks = xmalloc (nopcodes * sizeof (unsigned int));
for (opcode = avr_opcodes, maskptr = avr_bin_masks;
opcode->name;
@ -305,10 +297,8 @@ print_insn_avr(addr, info)
for (opcode = avr_opcodes, maskptr = avr_bin_masks;
opcode->name;
opcode++, maskptr++)
{
if ((insn & *maskptr) == opcode->bin_opcode)
break;
}
if ((insn & *maskptr) == opcode->bin_opcode)
break;
/* Special case: disassemble `ldd r,b+0' as `ld r,b', and
`std b+0,r' as `st b,r' (next entry in the table). */

58
opcodes/cgen-asm.in
View File

@ -1,26 +1,27 @@
/* Assembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -421,30 +422,3 @@ const CGEN_INSN *
return NULL;
}
}
#if 0 /* This calls back to GAS which we can't do without care. */
/* Record each member of OPVALS in the assembler's symbol table.
This lets GAS parse registers for us.
??? Interesting idea but not currently used. */
/* Record each member of OPVALS in the assembler's symbol table.
FIXME: Not currently used. */
void
@arch@_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
{
CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
const CGEN_KEYWORD_ENTRY * ke;
while ((ke = cgen_keyword_search_next (& search)) != NULL)
{
#if 0 /* Unnecessary, should be done in the search routine. */
if (! @arch@_cgen_opval_supported (ke))
continue;
#endif
cgen_asm_record_register (cd, ke->name, ke->value);
}
}
#endif /* 0 */

46
opcodes/cgen-dis.in
View File

@ -1,27 +1,27 @@
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -56,7 +56,7 @@ static int read_insn
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
unsigned long *);
/* -- disassembler routines inserted here */
/* -- disassembler routines inserted here. */
/* Default print handler. */
@ -101,7 +101,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
; /* Nothing to do. */
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
(*info->print_address_func) (value, info);
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@ -183,6 +183,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
unsigned long *insn_value)
{
int status = (*info->read_memory_func) (pc, buf, buflen, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
@ -287,13 +288,13 @@ print_insn (CGEN_CPU_DESC cd,
length = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
/* length < 0 -> error */
/* Length < 0 -> error. */
if (length < 0)
return length;
if (length > 0)
{
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
/* length is in bits, result is in bytes */
/* Length is in bits, result is in bytes. */
return length / 8;
}
}
@ -343,7 +344,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list {
typedef struct cpu_desc_list
{
struct cpu_desc_list *next;
int isa;
int mach;
@ -428,7 +430,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
if (!cd)
abort ();
/* save this away for future reference */
/* Save this away for future reference. */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;

56
opcodes/cgen-ibld.in
View File

@ -1,25 +1,26 @@
/* Instruction building/extraction support for @arch@. -*- C -*-
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h"
#include "safe-ctype.h"
#undef min
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
#undef max
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
/* Used by the ifield rtx function. */
@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
if (length == 0)
return NULL;
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
static void
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int shift = insn_length - length;
/* Written this way to avoid undefined behaviour. */
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
{
unsigned long x;
int shift;
#if 0
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
#endif
x = cgen_get_insn_value (cd, bufp, word_length);
if (CGEN_INSN_LSB0_P)
@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
return 1;
}
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -539,4 +527,4 @@ extract_insn_normal (CGEN_CPU_DESC cd,
return CGEN_INSN_BITSIZE (insn);
}
/* machine generated code added here */
/* Machine generated code added here. */

2
opcodes/cgen-opc.c
View File

@ -157,7 +157,7 @@ cgen_keyword_search_init (CGEN_KEYWORD *kt, const char *spec)
{
CGEN_KEYWORD_SEARCH search;
/* FIXME: Need to specify format of PARAMS. */
/* FIXME: Need to specify format of params. */
if (spec != NULL)
abort ();

391
opcodes/cris-dis.c
View File

@ -3,21 +3,22 @@
Contributed by Axis Communications AB, Lund, Sweden.
Written by Hans-Peter Nilsson.
This file is part of the GNU binutils and GDB, the GNU debugger.
This file is part of the GNU binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 2, or (at your option) any later
version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "dis-asm.h"
#include "sysdep.h"
@ -92,56 +93,15 @@ static long no_of_case_offsets = 0;
/* Candidate for next case_offset. */
static long last_immediate = 0;
static int number_of_bits
PARAMS ((unsigned int));
static char *format_hex
PARAMS ((unsigned long, char *, struct cris_disasm_data *));
static char *format_dec
PARAMS ((long, char *, int));
static char *format_reg
PARAMS ((struct cris_disasm_data *, int, char *, bfd_boolean));
static char *format_sup_reg
PARAMS ((unsigned int, char *, bfd_boolean));
static int cris_constraint
PARAMS ((const char *, unsigned int, unsigned int,
struct cris_disasm_data *));
static unsigned bytes_to_skip
PARAMS ((unsigned int, const struct cris_opcode *,
enum cris_disass_family));
static char *print_flags
PARAMS ((struct cris_disasm_data *, unsigned int, char *));
static void print_with_operands
PARAMS ((const struct cris_opcode *, unsigned int, unsigned char *,
bfd_vma, disassemble_info *, const struct cris_opcode *,
unsigned int, unsigned char *, bfd_boolean));
static const struct cris_spec_reg *spec_reg_info
PARAMS ((unsigned int, enum cris_disass_family));
static int print_insn_cris_generic
PARAMS ((bfd_vma, disassemble_info *, bfd_boolean));
static int print_insn_cris_with_register_prefix
PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_cris_without_register_prefix
PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_crisv32_with_register_prefix
PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_crisv32_without_register_prefix
PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_crisv10_v32_with_register_prefix
PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_crisv10_v32_without_register_prefix
PARAMS ((bfd_vma, disassemble_info *));
static bfd_boolean cris_parse_disassembler_options
PARAMS ((disassemble_info *, enum cris_disass_family));
static const struct cris_opcode *get_opcode_entry
PARAMS ((unsigned int, unsigned int, struct cris_disasm_data *));
(const char *, unsigned, unsigned, struct cris_disasm_data *);
/* Parse disassembler options and store state in info. FIXME: For the
time being, we abuse static variables. */
static bfd_boolean
cris_parse_disassembler_options (info, distype)
disassemble_info *info;
enum cris_disass_family distype;
cris_parse_disassembler_options (disassemble_info *info,
enum cris_disass_family distype)
{
struct cris_disasm_data *disdata;
@ -159,13 +119,11 @@ cris_parse_disassembler_options (info, distype)
return TRUE;
}
static const struct cris_spec_reg *
spec_reg_info (sreg, distype)
unsigned int sreg;
enum cris_disass_family distype;
spec_reg_info (unsigned int sreg, enum cris_disass_family distype)
{
int i;
for (i = 0; cris_spec_regs[i].name != NULL; i++)
{
if (cris_spec_regs[i].number == sreg)
@ -196,8 +154,7 @@ spec_reg_info (sreg, distype)
/* Return the number of bits in the argument. */
static int
number_of_bits (val)
unsigned int val;
number_of_bits (unsigned int val)
{
int bits;
@ -210,10 +167,9 @@ number_of_bits (val)
/* Get an entry in the opcode-table. */
static const struct cris_opcode *
get_opcode_entry (insn, prefix_insn, disdata)
unsigned int insn;
unsigned int prefix_insn;
struct cris_disasm_data *disdata;
get_opcode_entry (unsigned int insn,
unsigned int prefix_insn,
struct cris_disasm_data *disdata)
{
/* For non-prefixed insns, we keep a table of pointers, indexed by the
insn code. Each entry is initialized when found to be NULL. */
@ -440,121 +396,21 @@ get_opcode_entry (insn, prefix_insn, disdata)
return max_matchedp;
}
/* Format number as hex with a leading "0x" into outbuffer. */
static char *
format_hex (number, outbuffer, disdata)
unsigned long number;
char *outbuffer;
struct cris_disasm_data *disdata;
{
/* Truncate negative numbers on >32-bit hosts. */
number &= 0xffffffff;
sprintf (outbuffer, "0x%lx", number);
/* Save this value for the "case" support. */
if (TRACE_CASE)
last_immediate = number;
return outbuffer + strlen (outbuffer);
}
/* Format number as decimal into outbuffer. Parameter signedp says
whether the number should be formatted as signed (!= 0) or
unsigned (== 0). */
static char *
format_dec (number, outbuffer, signedp)
long number;
char *outbuffer;
int signedp;
{
last_immediate = number;
sprintf (outbuffer, signedp ? "%ld" : "%lu", number);
return outbuffer + strlen (outbuffer);
}
/* Format the name of the general register regno into outbuffer. */
static char *
format_reg (disdata, regno, outbuffer_start, with_reg_prefix)
struct cris_disasm_data *disdata;
int regno;
char *outbuffer_start;
bfd_boolean with_reg_prefix;
{
char *outbuffer = outbuffer_start;
if (with_reg_prefix)
*outbuffer++ = REGISTER_PREFIX_CHAR;
switch (regno)
{
case 15:
/* For v32, there is no context in which we output PC. */
if (disdata->distype == cris_dis_v32)
strcpy (outbuffer, "acr");
else
strcpy (outbuffer, "pc");
break;
case 14:
strcpy (outbuffer, "sp");
break;
default:
sprintf (outbuffer, "r%d", regno);
break;
}
return outbuffer_start + strlen (outbuffer_start);
}
/* Format the name of a support register into outbuffer. */
static char *
format_sup_reg (regno, outbuffer_start, with_reg_prefix)
unsigned int regno;
char *outbuffer_start;
bfd_boolean with_reg_prefix;
{
char *outbuffer = outbuffer_start;
int i;
if (with_reg_prefix)
*outbuffer++ = REGISTER_PREFIX_CHAR;
for (i = 0; cris_support_regs[i].name != NULL; i++)
if (cris_support_regs[i].number == regno)
{
sprintf (outbuffer, "%s", cris_support_regs[i].name);
return outbuffer_start + strlen (outbuffer_start);
}
/* There's supposed to be register names covering all numbers, though
some may be generic names. */
sprintf (outbuffer, "format_sup_reg-BUG");
return outbuffer_start + strlen (outbuffer_start);
}
/* Return -1 if the constraints of a bitwise-matched instruction say
that there is no match. Otherwise return a nonnegative number
indicating the confidence in the match (higher is better). */
static int
cris_constraint (cs, insn, prefix_insn, disdata)
const char *cs;
unsigned int insn;
unsigned int prefix_insn;
struct cris_disasm_data *disdata;
cris_constraint (const char *cs,
unsigned int insn,
unsigned int prefix_insn,
struct cris_disasm_data *disdata)
{
int retval = 0;
int tmp;
int prefix_ok = 0;
const char *s;
for (s = cs; *s; s++)
switch (*s)
{
@ -697,13 +553,105 @@ cris_constraint (cs, insn, prefix_insn, disdata)
return retval;
}
/* Format number as hex with a leading "0x" into outbuffer. */
static char *
format_hex (unsigned long number,
char *outbuffer,
struct cris_disasm_data *disdata)
{
/* Truncate negative numbers on >32-bit hosts. */
number &= 0xffffffff;
sprintf (outbuffer, "0x%lx", number);
/* Save this value for the "case" support. */
if (TRACE_CASE)
last_immediate = number;
return outbuffer + strlen (outbuffer);
}
/* Format number as decimal into outbuffer. Parameter signedp says
whether the number should be formatted as signed (!= 0) or
unsigned (== 0). */
static char *
format_dec (long number, char *outbuffer, int signedp)
{
last_immediate = number;
sprintf (outbuffer, signedp ? "%ld" : "%lu", number);
return outbuffer + strlen (outbuffer);
}
/* Format the name of the general register regno into outbuffer. */
static char *
format_reg (struct cris_disasm_data *disdata,
int regno,
char *outbuffer_start,
bfd_boolean with_reg_prefix)
{
char *outbuffer = outbuffer_start;
if (with_reg_prefix)
*outbuffer++ = REGISTER_PREFIX_CHAR;
switch (regno)
{
case 15:
/* For v32, there is no context in which we output PC. */
if (disdata->distype == cris_dis_v32)
strcpy (outbuffer, "acr");
else
strcpy (outbuffer, "pc");
break;
case 14:
strcpy (outbuffer, "sp");
break;
default:
sprintf (outbuffer, "r%d", regno);
break;
}
return outbuffer_start + strlen (outbuffer_start);
}
/* Format the name of a support register into outbuffer. */
static char *
format_sup_reg (unsigned int regno,
char *outbuffer_start,
bfd_boolean with_reg_prefix)
{
char *outbuffer = outbuffer_start;
int i;
if (with_reg_prefix)
*outbuffer++ = REGISTER_PREFIX_CHAR;
for (i = 0; cris_support_regs[i].name != NULL; i++)
if (cris_support_regs[i].number == regno)
{
sprintf (outbuffer, "%s", cris_support_regs[i].name);
return outbuffer_start + strlen (outbuffer_start);
}
/* There's supposed to be register names covering all numbers, though
some may be generic names. */
sprintf (outbuffer, "format_sup_reg-BUG");
return outbuffer_start + strlen (outbuffer_start);
}
/* Return the length of an instruction. */
static unsigned
bytes_to_skip (insn, matchedp, distype)
unsigned int insn;
const struct cris_opcode *matchedp;
enum cris_disass_family distype;
bytes_to_skip (unsigned int insn,
const struct cris_opcode *matchedp,
enum cris_disass_family distype)
{
/* Each insn is a word plus "immediate" operands. */
unsigned to_skip = 2;
@ -750,10 +698,7 @@ bytes_to_skip (insn, matchedp, distype)
/* Print condition code flags. */
static char *
print_flags (disdata, insn, cp)
struct cris_disasm_data *disdata;
unsigned int insn;
char *cp;
print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp)
{
/* Use the v8 (Etrax 100) flag definitions for disassembly.
The differences with v0 (Etrax 1..4) vs. Svinto are:
@ -780,20 +725,18 @@ print_flags (disdata, insn, cp)
supposed to be output as an address mode. */
static void
print_with_operands (opcodep, insn, buffer, addr, info, prefix_opcodep,
prefix_insn, prefix_buffer, with_reg_prefix)
const struct cris_opcode *opcodep;
unsigned int insn;
unsigned char *buffer;
bfd_vma addr;
disassemble_info *info;
/* If a prefix insn was before this insn (and is supposed to be
output as an address), here is a description of it. */
const struct cris_opcode *prefix_opcodep;
unsigned int prefix_insn;
unsigned char *prefix_buffer;
bfd_boolean with_reg_prefix;
print_with_operands (const struct cris_opcode *opcodep,
unsigned int insn,
unsigned char *buffer,
bfd_vma addr,
disassemble_info *info,
/* If a prefix insn was before this insn (and is supposed
to be output as an address), here is a description of
it. */
const struct cris_opcode *prefix_opcodep,
unsigned int prefix_insn,
unsigned char *prefix_buffer,
bfd_boolean with_reg_prefix)
{
/* Get a buffer of somewhat reasonable size where we store
intermediate parts of the insn. */
@ -1420,15 +1363,13 @@ print_with_operands (opcodep, insn, buffer, addr, info, prefix_opcodep,
/* It could also be an "add", if there are negative case-values. */
else if (strncmp (opcodep->name, "add", 3) == 0)
{
/* The first case is the negated operand to the add. */
case_offset = -last_immediate;
}
/* The first case is the negated operand to the add. */
case_offset = -last_immediate;
/* A bound insn will tell us the number of cases. */
else if (strncmp (opcodep->name, "bound", 5) == 0)
{
no_of_case_offsets = last_immediate + 1;
}
no_of_case_offsets = last_immediate + 1;
/* A jump or jsr or branch breaks the chain of insns for a
case-table, so assume default first-case again. */
else if (info->insn_type == dis_jsr
@ -1444,10 +1385,9 @@ print_with_operands (opcodep, insn, buffer, addr, info, prefix_opcodep,
WITH_REG_PREFIX. */
static int
print_insn_cris_generic (memaddr, info, with_reg_prefix)
bfd_vma memaddr;
disassemble_info *info;
bfd_boolean with_reg_prefix;
print_insn_cris_generic (bfd_vma memaddr,
disassemble_info *info,
bfd_boolean with_reg_prefix)
{
int nbytes;
unsigned int insn;
@ -1631,9 +1571,8 @@ print_insn_cris_generic (memaddr, info, with_reg_prefix)
/* Disassemble, prefixing register names with `$'. CRIS v0..v10. */
static int
print_insn_cris_with_register_prefix (vma, info)
bfd_vma vma;
disassemble_info *info;
print_insn_cris_with_register_prefix (bfd_vma vma,
disassemble_info *info)
{
if (info->private_data == NULL
&& !cris_parse_disassembler_options (info, cris_dis_v0_v10))
@ -1644,9 +1583,8 @@ print_insn_cris_with_register_prefix (vma, info)
/* Disassemble, prefixing register names with `$'. CRIS v32. */
static int
print_insn_crisv32_with_register_prefix (vma, info)
bfd_vma vma;
disassemble_info *info;
print_insn_crisv32_with_register_prefix (bfd_vma vma,
disassemble_info *info)
{
if (info->private_data == NULL
&& !cris_parse_disassembler_options (info, cris_dis_v32))
@ -1658,9 +1596,8 @@ print_insn_crisv32_with_register_prefix (vma, info)
Common v10 and v32 subset. */
static int
print_insn_crisv10_v32_with_register_prefix (vma, info)
bfd_vma vma;
disassemble_info *info;
print_insn_crisv10_v32_with_register_prefix (bfd_vma vma,
disassemble_info *info)
{
if (info->private_data == NULL
&& !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
@ -1671,9 +1608,8 @@ print_insn_crisv10_v32_with_register_prefix (vma, info)
/* Disassemble, no prefixes on register names. CRIS v0..v10. */
static int
print_insn_cris_without_register_prefix (vma, info)
bfd_vma vma;
disassemble_info *info;
print_insn_cris_without_register_prefix (bfd_vma vma,
disassemble_info *info)
{
if (info->private_data == NULL
&& !cris_parse_disassembler_options (info, cris_dis_v0_v10))
@ -1684,9 +1620,8 @@ print_insn_cris_without_register_prefix (vma, info)
/* Disassemble, no prefixes on register names. CRIS v32. */
static int
print_insn_crisv32_without_register_prefix (vma, info)
bfd_vma vma;
disassemble_info *info;
print_insn_crisv32_without_register_prefix (bfd_vma vma,
disassemble_info *info)
{
if (info->private_data == NULL
&& !cris_parse_disassembler_options (info, cris_dis_v32))
@ -1698,9 +1633,8 @@ print_insn_crisv32_without_register_prefix (vma, info)
Common v10 and v32 subset. */
static int
print_insn_crisv10_v32_without_register_prefix (vma, info)
bfd_vma vma;
disassemble_info *info;
print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
disassemble_info *info)
{
if (info->private_data == NULL
&& !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
@ -1714,8 +1648,7 @@ print_insn_crisv10_v32_without_register_prefix (vma, info)
functions seen above. */
disassembler_ftype
cris_get_disassembler (abfd)
bfd *abfd;
cris_get_disassembler (bfd *abfd)
{
/* If there's no bfd in sight, we return what is valid as input in all
contexts if fed back to the assembler: disassembly *with* register
@ -1742,9 +1675,7 @@ cris_get_disassembler (abfd)
return print_insn_cris_without_register_prefix;
}
/*
* Local variables:
* eval: (c-set-style "gnu")
* indent-tabs-mode: t
* End:
*/
/* Local variables:
eval: (c-set-style "gnu")
indent-tabs-mode: t
End: */

136
opcodes/d10v-dis.c
View File

@ -1,19 +1,20 @@
/* Disassemble D10V instructions.
Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 2000, 2001, 2005 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include <stdio.h>
@ -25,57 +26,12 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
so use this mask to keep the parts we want. */
#define PC_MASK 0x0303FFFF
static void dis_2_short PARAMS ((unsigned long insn, bfd_vma memaddr,
struct disassemble_info *info, int order));
static void dis_long PARAMS ((unsigned long insn, bfd_vma memaddr,
struct disassemble_info *info));
static void print_operand
PARAMS ((struct d10v_operand *, long unsigned int, struct d10v_opcode *,
bfd_vma, struct disassemble_info *));
int
print_insn_d10v (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
int status;
bfd_byte buffer[4];
unsigned long insn;
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb32 (buffer);
status = insn & FM11;
switch (status)
{
case 0:
dis_2_short (insn, memaddr, info, 2);
break;
case FM01:
dis_2_short (insn, memaddr, info, 0);
break;
case FM10:
dis_2_short (insn, memaddr, info, 1);
break;
case FM11:
dis_long (insn, memaddr, info);
break;
}
return 4;
}
static void
print_operand (oper, insn, op, memaddr, info)
struct d10v_operand *oper;
unsigned long insn;
struct d10v_opcode *op;
bfd_vma memaddr;
struct disassemble_info *info;
print_operand (struct d10v_operand *oper,
unsigned long insn,
struct d10v_opcode *op,
bfd_vma memaddr,
struct disassemble_info *info)
{
int num, shift;
@ -117,6 +73,7 @@ print_operand (oper, insn, op, memaddr, info)
{
int i;
int match = 0;
num += (oper->flags
& (OPERAND_GPR | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL));
if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1))
@ -155,6 +112,7 @@ print_operand (oper, insn, op, memaddr, info)
{
long max;
int neg = 0;
max = (1 << (oper->bits - 1));
if (num & max)
{
@ -189,10 +147,9 @@ print_operand (oper, insn, op, memaddr, info)
}
static void
dis_long (insn, memaddr, info)
unsigned long insn;
bfd_vma memaddr;
struct disassemble_info *info;
dis_long (unsigned long insn,
bfd_vma memaddr,
struct disassemble_info *info)
{
int i;
struct d10v_opcode *op = (struct d10v_opcode *) d10v_opcodes;
@ -202,10 +159,12 @@ dis_long (insn, memaddr, info)
while (op->name)
{
if ((op->format & LONG_OPCODE) && ((op->mask & insn) == (unsigned long) op->opcode))
if ((op->format & LONG_OPCODE)
&& ((op->mask & insn) == (unsigned long) op->opcode))
{
match = 1;
(*info->fprintf_func) (info->stream, "%s\t", op->name);
for (i = 0; op->operands[i]; i++)
{
oper = (struct d10v_operand *) &d10v_operands[op->operands[i]];
@ -230,11 +189,10 @@ dis_long (insn, memaddr, info)
}
static void
dis_2_short (insn, memaddr, info, order)
unsigned long insn;
bfd_vma memaddr;
struct disassemble_info *info;
int order;
dis_2_short (unsigned long insn,
bfd_vma memaddr,
struct disassemble_info *info,
int order)
{
int i, j;
unsigned int ins[2];
@ -302,3 +260,37 @@ dis_2_short (insn, memaddr, info, order)
if (need_paren)
(*info->fprintf_func) (info->stream, ")");
}
int
print_insn_d10v (bfd_vma memaddr, struct disassemble_info *info)
{
int status;
bfd_byte buffer[4];
unsigned long insn;
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb32 (buffer);
status = insn & FM11;
switch (status)
{
case 0:
dis_2_short (insn, memaddr, info, 2);
break;
case FM01:
dis_2_short (insn, memaddr, info, 0);
break;
case FM10:
dis_2_short (insn, memaddr, info, 1);
break;
case FM11:
dis_long (insn, memaddr, info);
break;
}
return 4;
}

246
opcodes/d30v-dis.c
View File

@ -1,19 +1,20 @@
/* Disassemble D30V instructions.
Copyright 1997, 1998, 2000, 2001 Free Software Foundation, Inc.
Copyright 1997, 1998, 2000, 2001, 2005 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include <stdio.h>
#include "sysdep.h"
@ -23,100 +24,12 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#define PC_MASK 0xFFFFFFFF
static int lookup_opcode PARAMS ((struct d30v_insn *insn, long num, int is_long));
static void print_insn PARAMS ((struct disassemble_info *info, bfd_vma memaddr, long long num,
struct d30v_insn *insn, int is_long, int show_ext));
static int extract_value PARAMS ((long long num, struct d30v_operand *oper, int is_long));
int
print_insn_d30v (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
int status, result;
bfd_byte buffer[12];
unsigned long in1, in2;
struct d30v_insn insn;
long long num;
insn.form = (struct d30v_format *) NULL;
info->bytes_per_line = 8;
info->bytes_per_chunk = 4;
info->display_endian = BFD_ENDIAN_BIG;
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
in1 = bfd_getb32 (buffer);
status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
if (status != 0)
{
info->bytes_per_line = 8;
if (!(result = lookup_opcode (&insn, in1, 0)))
(*info->fprintf_func) (info->stream, ".long\t0x%x", in1);
else
print_insn (info, memaddr, (long long) in1, &insn, 0, result);
return 4;
}
in2 = bfd_getb32 (buffer);
if (in1 & in2 & FM01)
{
/* LONG instruction. */
if (!(result = lookup_opcode (&insn, in1, 1)))
{
(*info->fprintf_func) (info->stream, ".long\t0x%x,0x%x", in1, in2);
return 8;
}
num = (long long) in1 << 32 | in2;
print_insn (info, memaddr, num, &insn, 1, result);
}
else
{
num = in1;
if (!(result = lookup_opcode (&insn, in1, 0)))
(*info->fprintf_func) (info->stream, ".long\t0x%x", in1);
else
print_insn (info, memaddr, num, &insn, 0, result);
switch (((in1 >> 31) << 1) | (in2 >> 31))
{
case 0:
(*info->fprintf_func) (info->stream, "\t||\t");
break;
case 1:
(*info->fprintf_func) (info->stream, "\t->\t");
break;
case 2:
(*info->fprintf_func) (info->stream, "\t<-\t");
default:
break;
}
insn.form = (struct d30v_format *) NULL;
num = in2;
if (!(result = lookup_opcode (&insn, in2, 0)))
(*info->fprintf_func) (info->stream, ".long\t0x%x", in2);
else
print_insn (info, memaddr, num, &insn, 0, result);
}
return 8;
}
/* Return 0 if lookup fails,
1 if found and only one form,
2 if found and there are short and long forms. */
static int
lookup_opcode (insn, num, is_long)
struct d30v_insn *insn;
long num;
int is_long;
lookup_opcode (struct d30v_insn *insn, long num, int is_long)
{
int i = 0, index;
struct d30v_format *f;
@ -173,14 +86,39 @@ lookup_opcode (insn, num, is_long)
return 1;
}
static int
extract_value (long long num, struct d30v_operand *oper, int is_long)
{
int val;
int shift = 12 - oper->position;
int mask = (0xFFFFFFFF >> (32 - oper->bits));
if (is_long)
{
if (oper->bits == 32)
/* Piece together 32-bit constant. */
val = ((num & 0x3FFFF)
| ((num & 0xFF00000) >> 2)
| ((num & 0x3F00000000LL) >> 6));
else
val = (num >> (32 + shift)) & mask;
}
else
val = (num >> shift) & mask;
if (oper->flags & OPERAND_SHIFT)
val <<= 3;
return val;
}
static void
print_insn (info, memaddr, num, insn, is_long, show_ext)
struct disassemble_info *info;
bfd_vma memaddr;
long long num;
struct d30v_insn *insn;
int is_long;
int show_ext;
print_insn (struct disassemble_info *info,
bfd_vma memaddr,
long long num,
struct d30v_insn *insn,
int is_long,
int show_ext)
{
int val, opnum, need_comma = 0;
struct d30v_operand *oper;
@ -216,6 +154,7 @@ print_insn (info, memaddr, num, insn, is_long, show_ext)
while ((opnum = insn->form->operands[opind++]) != 0)
{
int bits;
oper = (struct d30v_operand *) &d30v_operand_table[opnum];
bits = oper->bits;
if (oper->flags & OPERAND_SHIFT)
@ -269,6 +208,7 @@ print_insn (info, memaddr, num, insn, is_long, show_ext)
struct d30v_operand *oper3 =
(struct d30v_operand *) &d30v_operand_table[insn->form->operands[2]];
int id = extract_value (num, oper3, is_long);
found_control = 1;
switch (id)
{
@ -357,6 +297,7 @@ print_insn (info, memaddr, num, insn, is_long, show_ext)
if (oper->flags & OPERAND_SIGNED)
{
int max = (1 << (bits - 1));
if (val & max)
{
val = -val;
@ -375,33 +316,80 @@ print_insn (info, memaddr, num, insn, is_long, show_ext)
(*info->fprintf_func) (info->stream, ")");
}
static int
extract_value (num, oper, is_long)
long long num;
struct d30v_operand *oper;
int is_long;
int
print_insn_d30v (bfd_vma memaddr, struct disassemble_info *info)
{
int val;
int shift = 12 - oper->position;
int mask = (0xFFFFFFFF >> (32 - oper->bits));
int status, result;
bfd_byte buffer[12];
unsigned long in1, in2;
struct d30v_insn insn;
long long num;
if (is_long)
insn.form = NULL;
info->bytes_per_line = 8;
info->bytes_per_chunk = 4;
info->display_endian = BFD_ENDIAN_BIG;
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
if (oper->bits == 32)
{
/* Piece together 32-bit constant. */
val = ((num & 0x3FFFF)
| ((num & 0xFF00000) >> 2)
| ((num & 0x3F00000000LL) >> 6));
}
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
in1 = bfd_getb32 (buffer);
status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
if (status != 0)
{
info->bytes_per_line = 8;
if (!(result = lookup_opcode (&insn, in1, 0)))
(*info->fprintf_func) (info->stream, ".long\t0x%x", in1);
else
val = (num >> (32 + shift)) & mask;
print_insn (info, memaddr, (long long) in1, &insn, 0, result);
return 4;
}
in2 = bfd_getb32 (buffer);
if (in1 & in2 & FM01)
{
/* LONG instruction. */
if (!(result = lookup_opcode (&insn, in1, 1)))
{
(*info->fprintf_func) (info->stream, ".long\t0x%x,0x%x", in1, in2);
return 8;
}
num = (long long) in1 << 32 | in2;
print_insn (info, memaddr, num, &insn, 1, result);
}
else
val = (num >> shift) & mask;
{
num = in1;
if (!(result = lookup_opcode (&insn, in1, 0)))
(*info->fprintf_func) (info->stream, ".long\t0x%x", in1);
else
print_insn (info, memaddr, num, &insn, 0, result);
if (oper->flags & OPERAND_SHIFT)
val <<= 3;
switch (((in1 >> 31) << 1) | (in2 >> 31))
{
case 0:
(*info->fprintf_func) (info->stream, "\t||\t");
break;
case 1:
(*info->fprintf_func) (info->stream, "\t->\t");
break;
case 2:
(*info->fprintf_func) (info->stream, "\t<-\t");
default:
break;
}
return val;
insn.form = NULL;
num = in2;
if (!(result = lookup_opcode (&insn, in2, 0)))
(*info->fprintf_func) (info->stream, ".long\t0x%x", in2);
else
print_insn (info, memaddr, num, &insn, 0, result);
}
return 8;
}

295
opcodes/d30v-opc.c
View File

@ -1,125 +1,126 @@
/* d30v-opc.c -- D30V opcode list
Copyright 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1997, 1998, 1999, 2000, 2005 Free Software Foundation, Inc.
Written by Martin Hunt, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include <stdio.h>
#include "sysdep.h"
#include "opcode/d30v.h"
/* This table is sorted. */
/* If you add anything, it MUST be in alphabetical order */
/* The first field is the name the assembler uses when looking */
/* up orcodes. The second field is the name the disassembler will use. */
/* This allows the assembler to assemble references to r63 (for example) */
/* or "sp". The disassembler will always use the preferred form (sp) */
/* This table is sorted.
If you add anything, it MUST be in alphabetical order.
The first field is the name the assembler uses when looking
up orcodes. The second field is the name the disassembler will use.
This allows the assembler to assemble references to r63 (for example)
or "sp". The disassembler will always use the preferred form (sp). */
const struct pd_reg pre_defined_registers[] =
{
{ "a0", NULL, OPERAND_ACC+0 },
{ "a1", NULL, OPERAND_ACC+1 },
{ "bpc", NULL, OPERAND_CONTROL+3 },
{ "bpsw", NULL, OPERAND_CONTROL+1 },
{ "c", "c", OPERAND_FLAG+7 },
{ "a0", NULL, OPERAND_ACC + 0 },
{ "a1", NULL, OPERAND_ACC + 1 },
{ "bpc", NULL, OPERAND_CONTROL + 3 },
{ "bpsw", NULL, OPERAND_CONTROL + 1 },
{ "c", "c", OPERAND_FLAG + 7 },
{ "cr0", "psw", OPERAND_CONTROL },
{ "cr1", "bpsw", OPERAND_CONTROL+1 },
{ "cr10", "mod_s", OPERAND_CONTROL+10 },
{ "cr11", "mod_e", OPERAND_CONTROL+11 },
{ "cr12", NULL, OPERAND_CONTROL+12 },
{ "cr13", NULL, OPERAND_CONTROL+13 },
{ "cr14", "iba", OPERAND_CONTROL+14 },
{ "cr15", "eit_vb", OPERAND_CONTROL+15 },
{ "cr16", "int_s", OPERAND_CONTROL+16 },
{ "cr17", "int_m", OPERAND_CONTROL+17 },
{ "cr18", NULL, OPERAND_CONTROL+18 },
{ "cr19", NULL, OPERAND_CONTROL+19 },
{ "cr2", "pc", OPERAND_CONTROL+2 },
{ "cr20", NULL, OPERAND_CONTROL+20 },
{ "cr21", NULL, OPERAND_CONTROL+21 },
{ "cr22", NULL, OPERAND_CONTROL+22 },
{ "cr23", NULL, OPERAND_CONTROL+23 },
{ "cr24", NULL, OPERAND_CONTROL+24 },
{ "cr25", NULL, OPERAND_CONTROL+25 },
{ "cr26", NULL, OPERAND_CONTROL+26 },
{ "cr27", NULL, OPERAND_CONTROL+27 },
{ "cr28", NULL, OPERAND_CONTROL+28 },
{ "cr29", NULL, OPERAND_CONTROL+29 },
{ "cr3", "bpc", OPERAND_CONTROL+3 },
{ "cr30", NULL, OPERAND_CONTROL+30 },
{ "cr31", NULL, OPERAND_CONTROL+31 },
{ "cr32", NULL, OPERAND_CONTROL+32 },
{ "cr33", NULL, OPERAND_CONTROL+33 },
{ "cr34", NULL, OPERAND_CONTROL+34 },
{ "cr35", NULL, OPERAND_CONTROL+35 },
{ "cr36", NULL, OPERAND_CONTROL+36 },
{ "cr37", NULL, OPERAND_CONTROL+37 },
{ "cr38", NULL, OPERAND_CONTROL+38 },
{ "cr39", NULL, OPERAND_CONTROL+39 },
{ "cr4", "dpsw", OPERAND_CONTROL+4 },
{ "cr40", NULL, OPERAND_CONTROL+40 },
{ "cr41", NULL, OPERAND_CONTROL+41 },
{ "cr42", NULL, OPERAND_CONTROL+42 },
{ "cr43", NULL, OPERAND_CONTROL+43 },
{ "cr44", NULL, OPERAND_CONTROL+44 },
{ "cr45", NULL, OPERAND_CONTROL+45 },
{ "cr46", NULL, OPERAND_CONTROL+46 },
{ "cr47", NULL, OPERAND_CONTROL+47 },
{ "cr48", NULL, OPERAND_CONTROL+48 },
{ "cr49", NULL, OPERAND_CONTROL+49 },
{ "cr5","dpc", OPERAND_CONTROL+5 },
{ "cr50", NULL, OPERAND_CONTROL+50 },
{ "cr51", NULL, OPERAND_CONTROL+51 },
{ "cr52", NULL, OPERAND_CONTROL+52 },
{ "cr53", NULL, OPERAND_CONTROL+53 },
{ "cr54", NULL, OPERAND_CONTROL+54 },
{ "cr55", NULL, OPERAND_CONTROL+55 },
{ "cr56", NULL, OPERAND_CONTROL+56 },
{ "cr57", NULL, OPERAND_CONTROL+57 },
{ "cr58", NULL, OPERAND_CONTROL+58 },
{ "cr59", NULL, OPERAND_CONTROL+59 },
{ "cr6", NULL, OPERAND_CONTROL+6 },
{ "cr60", NULL, OPERAND_CONTROL+60 },
{ "cr61", NULL, OPERAND_CONTROL+61 },
{ "cr62", NULL, OPERAND_CONTROL+62 },
{ "cr63", NULL, OPERAND_CONTROL+63 },
{ "cr7", "rpt_c", OPERAND_CONTROL+7 },
{ "cr8", "rpt_s", OPERAND_CONTROL+8 },
{ "cr9", "rpt_e", OPERAND_CONTROL+9 },
{ "dpc", NULL, OPERAND_CONTROL+5 },
{ "dpsw", NULL, OPERAND_CONTROL+4 },
{ "eit_vb", NULL, OPERAND_CONTROL+15 },
{ "f0", NULL, OPERAND_FLAG+0 },
{ "f1", NULL, OPERAND_FLAG+1 },
{ "f2", NULL, OPERAND_FLAG+2 },
{ "f3", NULL, OPERAND_FLAG+3 },
{ "f4", "s", OPERAND_FLAG+4 },
{ "f5", "v", OPERAND_FLAG+5 },
{ "f6", "va", OPERAND_FLAG+6 },
{ "f7", "c", OPERAND_FLAG+7 },
{ "iba", NULL, OPERAND_CONTROL+14 },
{ "int_m", NULL, OPERAND_CONTROL+17 },
{ "int_s", NULL, OPERAND_CONTROL+16 },
{ "cr1", "bpsw", OPERAND_CONTROL + 1 },
{ "cr10", "mod_s", OPERAND_CONTROL + 10 },
{ "cr11", "mod_e", OPERAND_CONTROL + 11 },
{ "cr12", NULL, OPERAND_CONTROL + 12 },
{ "cr13", NULL, OPERAND_CONTROL + 13 },
{ "cr14", "iba", OPERAND_CONTROL + 14 },
{ "cr15", "eit_vb", OPERAND_CONTROL + 15 },
{ "cr16", "int_s", OPERAND_CONTROL + 16 },
{ "cr17", "int_m", OPERAND_CONTROL + 17 },
{ "cr18", NULL, OPERAND_CONTROL + 18 },
{ "cr19", NULL, OPERAND_CONTROL + 19 },
{ "cr2", "pc", OPERAND_CONTROL + 2 },
{ "cr20", NULL, OPERAND_CONTROL + 20 },
{ "cr21", NULL, OPERAND_CONTROL + 21 },
{ "cr22", NULL, OPERAND_CONTROL + 22 },
{ "cr23", NULL, OPERAND_CONTROL + 23 },
{ "cr24", NULL, OPERAND_CONTROL + 24 },
{ "cr25", NULL, OPERAND_CONTROL + 25 },
{ "cr26", NULL, OPERAND_CONTROL + 26 },
{ "cr27", NULL, OPERAND_CONTROL + 27 },
{ "cr28", NULL, OPERAND_CONTROL + 28 },
{ "cr29", NULL, OPERAND_CONTROL + 29 },
{ "cr3", "bpc", OPERAND_CONTROL + 3 },
{ "cr30", NULL, OPERAND_CONTROL + 30 },
{ "cr31", NULL, OPERAND_CONTROL + 31 },
{ "cr32", NULL, OPERAND_CONTROL + 32 },
{ "cr33", NULL, OPERAND_CONTROL + 33 },
{ "cr34", NULL, OPERAND_CONTROL + 34 },
{ "cr35", NULL, OPERAND_CONTROL + 35 },
{ "cr36", NULL, OPERAND_CONTROL + 36 },
{ "cr37", NULL, OPERAND_CONTROL + 37 },
{ "cr38", NULL, OPERAND_CONTROL + 38 },
{ "cr39", NULL, OPERAND_CONTROL + 39 },
{ "cr4", "dpsw", OPERAND_CONTROL + 4 },
{ "cr40", NULL, OPERAND_CONTROL + 40 },
{ "cr41", NULL, OPERAND_CONTROL + 41 },
{ "cr42", NULL, OPERAND_CONTROL + 42 },
{ "cr43", NULL, OPERAND_CONTROL + 43 },
{ "cr44", NULL, OPERAND_CONTROL + 44 },
{ "cr45", NULL, OPERAND_CONTROL + 45 },
{ "cr46", NULL, OPERAND_CONTROL + 46 },
{ "cr47", NULL, OPERAND_CONTROL + 47 },
{ "cr48", NULL, OPERAND_CONTROL + 48 },
{ "cr49", NULL, OPERAND_CONTROL + 49 },
{ "cr5","dpc", OPERAND_CONTROL + 5 },
{ "cr50", NULL, OPERAND_CONTROL + 50 },
{ "cr51", NULL, OPERAND_CONTROL + 51 },
{ "cr52", NULL, OPERAND_CONTROL + 52 },
{ "cr53", NULL, OPERAND_CONTROL + 53 },
{ "cr54", NULL, OPERAND_CONTROL + 54 },
{ "cr55", NULL, OPERAND_CONTROL + 55 },
{ "cr56", NULL, OPERAND_CONTROL + 56 },
{ "cr57", NULL, OPERAND_CONTROL + 57 },
{ "cr58", NULL, OPERAND_CONTROL + 58 },
{ "cr59", NULL, OPERAND_CONTROL + 59 },
{ "cr6", NULL, OPERAND_CONTROL + 6 },
{ "cr60", NULL, OPERAND_CONTROL + 60 },
{ "cr61", NULL, OPERAND_CONTROL + 61 },
{ "cr62", NULL, OPERAND_CONTROL + 62 },
{ "cr63", NULL, OPERAND_CONTROL + 63 },
{ "cr7", "rpt_c", OPERAND_CONTROL + 7 },
{ "cr8", "rpt_s", OPERAND_CONTROL + 8 },
{ "cr9", "rpt_e", OPERAND_CONTROL + 9 },
{ "dpc", NULL, OPERAND_CONTROL + 5 },
{ "dpsw", NULL, OPERAND_CONTROL + 4 },
{ "eit_vb", NULL, OPERAND_CONTROL + 15 },
{ "f0", NULL, OPERAND_FLAG + 0 },
{ "f1", NULL, OPERAND_FLAG + 1 },
{ "f2", NULL, OPERAND_FLAG + 2 },
{ "f3", NULL, OPERAND_FLAG + 3 },
{ "f4", "s", OPERAND_FLAG + 4 },
{ "f5", "v", OPERAND_FLAG + 5 },
{ "f6", "va", OPERAND_FLAG + 6 },
{ "f7", "c", OPERAND_FLAG + 7 },
{ "iba", NULL, OPERAND_CONTROL + 14 },
{ "int_m", NULL, OPERAND_CONTROL + 17 },
{ "int_s", NULL, OPERAND_CONTROL + 16 },
{ "link", "r62", 62 },
{ "mod_e", NULL, OPERAND_CONTROL+11 },
{ "mod_s", NULL, OPERAND_CONTROL+10 },
{ "pc", NULL, OPERAND_CONTROL+2 },
{ "mod_e", NULL, OPERAND_CONTROL + 11 },
{ "mod_s", NULL, OPERAND_CONTROL + 10 },
{ "pc", NULL, OPERAND_CONTROL + 2 },
{ "psw", NULL, OPERAND_CONTROL },
{ "pswh", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+2 },
{ "pswl", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+1 },
{ "pswh", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 2 },
{ "pswl", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 1 },
{ "r0", NULL, 0 },
{ "r1", NULL, 1 },
{ "r10", NULL, 10 },
@ -184,24 +185,26 @@ const struct pd_reg pre_defined_registers[] =
{ "r7", NULL, 7 },
{ "r8", NULL, 8 },
{ "r9", NULL, 9 },
{ "rpt_c", NULL, OPERAND_CONTROL+7 },
{ "rpt_e", NULL, OPERAND_CONTROL+9 },
{ "rpt_s", NULL, OPERAND_CONTROL+8 },
{ "s", NULL, OPERAND_FLAG+4 },
{ "rpt_c", NULL, OPERAND_CONTROL + 7 },
{ "rpt_e", NULL, OPERAND_CONTROL + 9 },
{ "rpt_s", NULL, OPERAND_CONTROL + 8 },
{ "s", NULL, OPERAND_FLAG + 4 },
{ "sp", NULL, 63 },
{ "v", NULL, OPERAND_FLAG+5 },
{ "va", NULL, OPERAND_FLAG+6 },
{ "v", NULL, OPERAND_FLAG + 5 },
{ "va", NULL, OPERAND_FLAG + 6 },
};
int
reg_name_cnt()
reg_name_cnt (void)
{
return (sizeof(pre_defined_registers) / sizeof(struct pd_reg));
return sizeof (pre_defined_registers) / sizeof (struct pd_reg);
}
/* OPCODE TABLE */
/* The format of this table is defined in opcode/d30v.h */
const struct d30v_opcode d30v_opcode_table[] = {
/* OPCODE TABLE.
The format of this table is defined in opcode/d30v.h. */
const struct d30v_opcode d30v_opcode_table[] =
{
{ "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 },
{ "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
{ "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
@ -335,52 +338,53 @@ const struct d30v_opcode d30v_opcode_table[] = {
};
/* now define the operand types */
/* format is length, bits, position, flags */
/* Now define the operand types.
Format is length, bits, position, flags. */
const struct d30v_operand d30v_operand_table[] =
{
#define UNUSED (0)
{ 0, 0, 0, 0 },
#define Ra (UNUSED + 1)
{ 6, 6, 0, OPERAND_REG|OPERAND_DEST },
{ 6, 6, 0, OPERAND_REG | OPERAND_DEST },
#define Ra2 (Ra + 1)
{ 6, 6, 0, OPERAND_REG|OPERAND_DEST|OPERAND_2REG },
{ 6, 6, 0, OPERAND_REG | OPERAND_DEST | OPERAND_2REG },
#define Ra3 (Ra2 + 1)
{ 6, 6, 0, OPERAND_REG },
#define Rb (Ra3 + 1)
{ 6, 6, 6, OPERAND_REG },
#define Rb2 (Rb + 1)
{ 6, 6, 6, OPERAND_REG|OPERAND_DEST },
{ 6, 6, 6, OPERAND_REG | OPERAND_DEST },
#define Rc (Rb2 + 1)
{ 6, 6, 12, OPERAND_REG },
#define Aa (Rc + 1)
{ 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST },
{ 6, 1, 0, OPERAND_ACC | OPERAND_REG | OPERAND_DEST },
#define Ab (Aa + 1)
{ 6, 1, 6, OPERAND_ACC|OPERAND_REG },
{ 6, 1, 6, OPERAND_ACC | OPERAND_REG },
#define IMM5 (Ab + 1)
{ 6, 5, 12, OPERAND_NUM },
#define IMM5U (IMM5 + 1)
{ 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */
{ 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used. */
#define IMM5S3 (IMM5U + 1)
{ 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */
{ 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used. */
#define IMM6 (IMM5S3 + 1)
{ 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED },
{ 6, 6, 12, OPERAND_NUM | OPERAND_SIGNED },
#define IMM6U (IMM6 + 1)
{ 6, 6, 0, OPERAND_NUM },
#define IMM6U2 (IMM6U + 1)
{ 6, 6, 12, OPERAND_NUM },
#define REL6S3 (IMM6U2 + 1)
{ 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT|OPERAND_PCREL },
{ 6, 6, 0, OPERAND_NUM | OPERAND_SHIFT | OPERAND_PCREL },
#define REL12S3 (REL6S3 + 1)
{ 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL },
{ 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL },
#define IMM12S3 (REL12S3 + 1)
{ 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
{ 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT },
#define REL18S3 (IMM12S3 + 1)
{ 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL },
{ 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL },
#define IMM18S3 (REL18S3 + 1)
{ 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
{ 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT },
#define REL32 (IMM18S3 + 1)
{ 32, 32, 0, OPERAND_NUM|OPERAND_PCREL },
{ 32, 32, 0, OPERAND_NUM | OPERAND_PCREL },
#define IMM32 (REL32 + 1)
{ 32, 32, 0, OPERAND_NUM },
#define Fa (IMM32 + 1)
@ -393,25 +397,26 @@ const struct d30v_operand d30v_operand_table[] =
{ 0, 0, 0, OPERAND_ATSIGN},
#define ATPAR (ATSIGN + 1) /* "@(" */
{ 0, 0, 0, OPERAND_ATPAR},
#define PLUS (ATPAR + 1) /* postincrement */
#define PLUS (ATPAR + 1) /* Postincrement. */
{ 0, 0, 0, OPERAND_PLUS},
#define MINUS (PLUS + 1) /* postdecrement */
#define MINUS (PLUS + 1) /* Postdecrement. */
{ 0, 0, 0, OPERAND_MINUS},
#define ATMINUS (MINUS + 1) /* predecrement */
#define ATMINUS (MINUS + 1) /* Predecrement. */
{ 0, 0, 0, OPERAND_ATMINUS},
#define Ca (ATMINUS + 1) /* control register */
{ 6, 6, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST},
#define Cb (Ca + 1) /* control register */
{ 6, 6, 6, OPERAND_REG|OPERAND_CONTROL},
#define CC (Cb + 1) /* condition code (CMPcc and CMPUcc) */
#define Ca (ATMINUS + 1) /* Control register. */
{ 6, 6, 0, OPERAND_REG | OPERAND_CONTROL | OPERAND_DEST},
#define Cb (Ca + 1) /* Control register. */
{ 6, 6, 6, OPERAND_REG | OPERAND_CONTROL},
#define CC (Cb + 1) /* Condition code (CMPcc and CMPUcc). */
{ 3, 3, -3, OPERAND_NAME},
#define Fa2 (CC + 1) /* flag register (CMPcc and CMPUcc) */
{ 3, 3, 0, OPERAND_REG|OPERAND_FLAG|OPERAND_DEST},
#define Fake (Fa2 + 1) /* place holder for "id" field in mvfsys and mvtsys */
#define Fa2 (CC + 1) /* Flag register (CMPcc and CMPUcc). */
{ 3, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST},
#define Fake (Fa2 + 1) /* Place holder for "id" field in mvfsys and mvtsys. */
{ 6, 2, 12, OPERAND_SPECIAL},
};
/* now we need to define the instruction formats */
/* Now we need to define the instruction formats. */
const struct d30v_format d30v_format_table[] =
{
{ 0, 0, { 0 } },

76
opcodes/dis-buf.c
View File

@ -2,19 +2,20 @@
Copyright 1993, 1994, 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2005
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "dis-asm.h"
@ -24,11 +25,10 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
/* Get LENGTH bytes from info's buffer, at target address memaddr.
Transfer them to myaddr. */
int
buffer_read_memory (memaddr, myaddr, length, info)
bfd_vma memaddr;
bfd_byte *myaddr;
unsigned int length;
struct disassemble_info *info;
buffer_read_memory (bfd_vma memaddr,
bfd_byte *myaddr,
unsigned int length,
struct disassemble_info *info)
{
unsigned int opb = info->octets_per_byte;
unsigned int end_addr_offset = length / opb;
@ -46,11 +46,11 @@ buffer_read_memory (memaddr, myaddr, length, info)
/* Print an error message. We can assume that this is in response to
an error return from buffer_read_memory. */
void
perror_memory (status, memaddr, info)
int status;
bfd_vma memaddr;
struct disassemble_info *info;
perror_memory (int status,
bfd_vma memaddr,
struct disassemble_info *info)
{
if (status != EIO)
/* Can't happen. */
@ -75,9 +75,7 @@ perror_memory (status, memaddr, info)
addresses). */
void
generic_print_address (addr, info)
bfd_vma addr;
struct disassemble_info *info;
generic_print_address (bfd_vma addr, struct disassemble_info *info)
{
char buf[30];
@ -85,39 +83,11 @@ generic_print_address (addr, info)
(*info->fprintf_func) (info->stream, "0x%s", buf);
}
#if 0
/* Just concatenate the address as hex. This is included for
completeness even though both GDB and objdump provide their own (to
print symbolic addresses). */
void generic_strcat_address PARAMS ((bfd_vma, char *, int));
void
generic_strcat_address (addr, buf, len)
bfd_vma addr;
char *buf;
int len;
{
if (buf != (char *)NULL && len > 0)
{
char tmpBuf[30];
sprintf_vma (tmpBuf, addr);
if ((strlen (buf) + strlen (tmpBuf)) <= (unsigned int) len)
strcat (buf, tmpBuf);
else
strncat (buf, tmpBuf, (len - strlen(buf)));
}
return;
}
#endif
/* Just return true. */
int
generic_symbol_at_address (addr, info)
bfd_vma addr ATTRIBUTE_UNUSED;
struct disassemble_info *info ATTRIBUTE_UNUSED;
generic_symbol_at_address (bfd_vma addr ATTRIBUTE_UNUSED,
struct disassemble_info *info ATTRIBUTE_UNUSED)
{
return 1;
}

210
opcodes/dlx-dis.c
View File

@ -1,5 +1,5 @@
/* Instruction printing code for the DLX Microprocessor
Copyright 2002 Free Software Foundation, Inc.
Copyright 2002, 2005 Free Software Foundation, Inc.
Contributed by Kuang Hwa Lin. Written by Kuang Hwa Lin, 03/2002.
This program is free software; you can redistribute it and/or modify
@ -14,7 +14,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "dis-asm.h"
@ -36,79 +37,55 @@
unsigned char opc, rs1, rs2, rd;
unsigned long imm26, imm16, func, current_insn_addr;
static unsigned char dlx_get_opcode PARAMS ((unsigned long));
static unsigned char dlx_get_rs1 PARAMS ((unsigned long));
static unsigned char dlx_get_rs2 PARAMS ((unsigned long));
static unsigned char dlx_get_rdR PARAMS ((unsigned long));
static unsigned long dlx_get_func PARAMS ((unsigned long));
static unsigned long dlx_get_imm16 PARAMS ((unsigned long));
static unsigned long dlx_get_imm26 PARAMS ((unsigned long));
static void operand_deliminator PARAMS ((struct disassemble_info *, char *));
static unsigned char dlx_r_type PARAMS ((struct disassemble_info *));
static unsigned char dlx_load_type PARAMS ((struct disassemble_info *));
static unsigned char dlx_store_type PARAMS ((struct disassemble_info *));
static unsigned char dlx_aluI_type PARAMS ((struct disassemble_info *));
static unsigned char dlx_br_type PARAMS ((struct disassemble_info *));
static unsigned char dlx_jmp_type PARAMS ((struct disassemble_info *));
static unsigned char dlx_jr_type PARAMS ((struct disassemble_info *));
/* Print one instruction from MEMADDR on INFO->STREAM.
Return the size of the instruction (always 4 on dlx). */
static unsigned char
dlx_get_opcode (opcode)
unsigned long opcode;
dlx_get_opcode (unsigned long opcode)
{
return (unsigned char) ((opcode >> 26) & 0x3F);
}
static unsigned char
dlx_get_rs1 (opcode)
unsigned long opcode;
dlx_get_rs1 (unsigned long opcode)
{
return (unsigned char) ((opcode >> 21) & 0x1F);
}
static unsigned char
dlx_get_rs2 (opcode)
unsigned long opcode;
dlx_get_rs2 (unsigned long opcode)
{
return (unsigned char) ((opcode >> 16) & 0x1F);
}
static unsigned char
dlx_get_rdR (opcode)
unsigned long opcode;
dlx_get_rdR (unsigned long opcode)
{
return (unsigned char) ((opcode >> 11) & 0x1F);
}
static unsigned long
dlx_get_func (opcode)
unsigned long opcode;
dlx_get_func (unsigned long opcode)
{
return (unsigned char) (opcode & 0x7FF);
}
static unsigned long
dlx_get_imm16 (opcode)
unsigned long opcode;
dlx_get_imm16 (unsigned long opcode)
{
return (unsigned long) (opcode & 0xFFFF);
}
static unsigned long
dlx_get_imm26 (opcode)
unsigned long opcode;
dlx_get_imm26 (unsigned long opcode)
{
return (unsigned long) (opcode & 0x03FFFFFF);
}
/* Fill the opcode to the max length. */
static void
operand_deliminator (info, ptr)
struct disassemble_info *info;
char *ptr;
operand_deliminator (struct disassemble_info *info, char *ptr)
{
int difft = 8 - (int) strlen (ptr);
@ -120,9 +97,9 @@ operand_deliminator (info, ptr)
}
/* Process the R-type opcode. */
static unsigned char
dlx_r_type (info)
struct disassemble_info *info;
dlx_r_type (struct disassemble_info *info)
{
unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */
int r_opc_num = (sizeof r_opc) / (sizeof (char));
@ -132,7 +109,7 @@ dlx_r_type (info)
char *name;
}
dlx_r_opcode[] =
{
{
{ NOPF, "nop" }, /* NOP */
{ ADDF, "add" }, /* Add */
{ ADDUF, "addu" }, /* Add Unsigned */
@ -174,7 +151,7 @@ dlx_r_type (info)
continue;
else
break;
}
}
if (idx == r_opc_num)
return NIL;
@ -202,8 +179,7 @@ dlx_r_type (info)
/* Process the memory read opcode. */
static unsigned char
dlx_load_type (info)
struct disassemble_info* info;
dlx_load_type (struct disassemble_info* info)
{
struct _load_opcode
{
@ -211,17 +187,17 @@ dlx_load_type (info)
char *name;
}
dlx_load_opcode[] =
{
{ OPC(LHIOP), "lhi" }, /* Load HI to register. */
{ OPC(LBOP), "lb" }, /* load byte sign extended. */
{ OPC(LBUOP), "lbu" }, /* load byte unsigned. */
{ OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */
{ OPC(LHOP), "lh" }, /* load halfword sign extended. */
{ OPC(LHUOP), "lhu" }, /* load halfword unsigned. */
{ OPC(LSHUOP),"ldsthu"}, /* load store halfword unsigned. */
{ OPC(LWOP), "lw" }, /* load word. */
{ OPC(LSWOP), "ldstw" } /* load store word. */
};
{
{ OPC(LHIOP), "lhi" }, /* Load HI to register. */
{ OPC(LBOP), "lb" }, /* load byte sign extended. */
{ OPC(LBUOP), "lbu" }, /* load byte unsigned. */
{ OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */
{ OPC(LHOP), "lh" }, /* load halfword sign extended. */
{ OPC(LHUOP), "lhu" }, /* load halfword unsigned. */
{ OPC(LSHUOP),"ldsthu"}, /* load store halfword unsigned. */
{ OPC(LWOP), "lw" }, /* load word. */
{ OPC(LSWOP), "ldstw" } /* load store word. */
};
int dlx_load_opcode_num =
(sizeof dlx_load_opcode) / (sizeof dlx_load_opcode[0]);
int idx;
@ -253,8 +229,7 @@ dlx_load_type (info)
/* Process the memory store opcode. */
static unsigned char
dlx_store_type (info)
struct disassemble_info* info;
dlx_store_type (struct disassemble_info* info)
{
struct _store_opcode
{
@ -262,11 +237,11 @@ dlx_store_type (info)
char *name;
}
dlx_store_opcode[] =
{
{ OPC(SBOP), "sb" }, /* Store byte. */
{ OPC(SHOP), "sh" }, /* Store halfword. */
{ OPC(SWOP), "sw" }, /* Store word. */
};
{
{ OPC(SBOP), "sb" }, /* Store byte. */
{ OPC(SHOP), "sh" }, /* Store halfword. */
{ OPC(SWOP), "sw" }, /* Store word. */
};
int dlx_store_opcode_num =
(sizeof dlx_store_opcode) / (sizeof dlx_store_opcode[0]);
int idx;
@ -287,8 +262,7 @@ dlx_store_type (info)
/* Process the Arithmetic and Logical I-TYPE opcode. */
static unsigned char
dlx_aluI_type (info)
struct disassemble_info* info;
dlx_aluI_type (struct disassemble_info* info)
{
struct _aluI_opcode
{
@ -296,34 +270,34 @@ dlx_aluI_type (info)
char *name;
}
dlx_aluI_opcode[] =
{
{ OPC(ADDIOP), "addi" }, /* Store byte. */
{ OPC(ADDUIOP), "addui" }, /* Store halfword. */
{ OPC(SUBIOP), "subi" }, /* Store word. */
{ OPC(SUBUIOP), "subui" }, /* Store word. */
{ OPC(ANDIOP), "andi" }, /* Store word. */
{ OPC(ORIOP), "ori" }, /* Store word. */
{ OPC(XORIOP), "xori" }, /* Store word. */
{ OPC(SLLIOP), "slli" }, /* Store word. */
{ OPC(SRAIOP), "srai" }, /* Store word. */
{ OPC(SRLIOP), "srli" }, /* Store word. */
{ OPC(SEQIOP), "seqi" }, /* Store word. */
{ OPC(SNEIOP), "snei" }, /* Store word. */
{ OPC(SLTIOP), "slti" }, /* Store word. */
{ OPC(SGTIOP), "sgti" }, /* Store word. */
{ OPC(SLEIOP), "slei" }, /* Store word. */
{ OPC(SGEIOP), "sgei" }, /* Store word. */
{ OPC(SEQUIOP), "sequi" }, /* Store word. */
{ OPC(SNEUIOP), "sneui" }, /* Store word. */
{ OPC(SLTUIOP), "sltui" }, /* Store word. */
{ OPC(SGTUIOP), "sgtui" }, /* Store word. */
{ OPC(SLEUIOP), "sleui" }, /* Store word. */
{ OPC(SGEUIOP), "sgeui" }, /* Store word. */
{
{ OPC(ADDIOP), "addi" }, /* Store byte. */
{ OPC(ADDUIOP), "addui" }, /* Store halfword. */
{ OPC(SUBIOP), "subi" }, /* Store word. */
{ OPC(SUBUIOP), "subui" }, /* Store word. */
{ OPC(ANDIOP), "andi" }, /* Store word. */
{ OPC(ORIOP), "ori" }, /* Store word. */
{ OPC(XORIOP), "xori" }, /* Store word. */
{ OPC(SLLIOP), "slli" }, /* Store word. */
{ OPC(SRAIOP), "srai" }, /* Store word. */
{ OPC(SRLIOP), "srli" }, /* Store word. */
{ OPC(SEQIOP), "seqi" }, /* Store word. */
{ OPC(SNEIOP), "snei" }, /* Store word. */
{ OPC(SLTIOP), "slti" }, /* Store word. */
{ OPC(SGTIOP), "sgti" }, /* Store word. */
{ OPC(SLEIOP), "slei" }, /* Store word. */
{ OPC(SGEIOP), "sgei" }, /* Store word. */
{ OPC(SEQUIOP), "sequi" }, /* Store word. */
{ OPC(SNEUIOP), "sneui" }, /* Store word. */
{ OPC(SLTUIOP), "sltui" }, /* Store word. */
{ OPC(SGTUIOP), "sgtui" }, /* Store word. */
{ OPC(SLEUIOP), "sleui" }, /* Store word. */
{ OPC(SGEUIOP), "sgeui" }, /* Store word. */
#if 0
{ OPC(MVTSOP), "mvts" }, /* Store word. */
{ OPC(MVFSOP), "mvfs" }, /* Store word. */
{ OPC(MVTSOP), "mvts" }, /* Store word. */
{ OPC(MVFSOP), "mvfs" }, /* Store word. */
#endif
};
};
int dlx_aluI_opcode_num =
(sizeof dlx_aluI_opcode) / (sizeof dlx_aluI_opcode[0]);
int idx;
@ -346,8 +320,7 @@ dlx_aluI_type (info)
/* Process the branch instruction. */
static unsigned char
dlx_br_type (info)
struct disassemble_info* info;
dlx_br_type (struct disassemble_info* info)
{
struct _br_opcode
{
@ -355,10 +328,10 @@ dlx_br_type (info)
char *name;
}
dlx_br_opcode[] =
{
{ OPC(BEQOP), "beqz" }, /* Store byte. */
{ OPC(BNEOP), "bnez" } /* Store halfword. */
};
{
{ OPC(BEQOP), "beqz" }, /* Store byte. */
{ OPC(BNEOP), "bnez" } /* Store halfword. */
};
int dlx_br_opcode_num =
(sizeof dlx_br_opcode) / (sizeof dlx_br_opcode[0]);
int idx;
@ -372,8 +345,8 @@ dlx_br_type (info)
imm16 += (current_insn_addr + 4);
(*info->fprintf_func) (info->stream, "%s", dlx_br_opcode[idx].name);
operand_deliminator (info, dlx_br_opcode[idx].name);
(*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
(*info->fprintf_func) (info->stream, "0x%08x", (int)imm16);
(*info->fprintf_func) (info->stream, "r%d,", (int) rs1);
(*info->fprintf_func) (info->stream, "0x%08x", (int) imm16);
return (unsigned char) IBR_TYPE;
}
@ -384,8 +357,7 @@ dlx_br_type (info)
/* Process the jump instruction. */
static unsigned char
dlx_jmp_type (info)
struct disassemble_info* info;
dlx_jmp_type (struct disassemble_info* info)
{
struct _jmp_opcode
{
@ -393,13 +365,13 @@ dlx_jmp_type (info)
char *name;
}
dlx_jmp_opcode[] =
{
{ OPC(JOP), "j" }, /* Store byte. */
{ OPC(JALOP), "jal" }, /* Store halfword. */
{ OPC(BREAKOP), "break" }, /* Store halfword. */
{ OPC(TRAPOP), "trap" }, /* Store halfword. */
{ OPC(RFEOP), "rfe" } /* Store halfword. */
};
{
{ OPC(JOP), "j" }, /* Store byte. */
{ OPC(JALOP), "jal" }, /* Store halfword. */
{ OPC(BREAKOP), "break" }, /* Store halfword. */
{ OPC(TRAPOP), "trap" }, /* Store halfword. */
{ OPC(RFEOP), "rfe" } /* Store halfword. */
};
int dlx_jmp_opcode_num =
(sizeof dlx_jmp_opcode) / (sizeof dlx_jmp_opcode[0]);
int idx;
@ -425,15 +397,15 @@ dlx_jmp_type (info)
/* Process the jump register instruction. */
static unsigned char
dlx_jr_type (info)
struct disassemble_info* info;
dlx_jr_type (struct disassemble_info* info)
{
struct _jr_opcode
{
unsigned long opcode;
char *name;
}
dlx_jr_opcode[] = {
dlx_jr_opcode[] =
{
{ OPC(JROP), "jr" }, /* Store byte. */
{ OPC(JALROP), "jalr" } /* Store halfword. */
};
@ -453,29 +425,27 @@ dlx_jr_type (info)
return (unsigned char) NIL;
}
typedef unsigned char (* dlx_insn) PARAMS ((struct disassemble_info *));
typedef unsigned char (* dlx_insn) (struct disassemble_info *);
/* This is the main DLX insn handling routine. */
int
print_insn_dlx (memaddr, info)
bfd_vma memaddr;
struct disassemble_info* info;
print_insn_dlx (bfd_vma memaddr, struct disassemble_info* info)
{
bfd_byte buffer[4];
int insn_idx;
unsigned long insn_word;
unsigned char rtn_code;
unsigned long dlx_insn_type[] =
{
(unsigned long) dlx_r_type,
(unsigned long) dlx_load_type,
(unsigned long) dlx_store_type,
(unsigned long) dlx_aluI_type,
(unsigned long) dlx_br_type,
(unsigned long) dlx_jmp_type,
(unsigned long) dlx_jr_type,
(unsigned long) NULL
{
(unsigned long) dlx_r_type,
(unsigned long) dlx_load_type,
(unsigned long) dlx_store_type,
(unsigned long) dlx_aluI_type,
(unsigned long) dlx_br_type,
(unsigned long) dlx_jmp_type,
(unsigned long) dlx_jr_type,
(unsigned long) NULL
};
int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (unsigned long))) - 1;
int status =

164
opcodes/fr30-asm.c
View File

@ -1,26 +1,27 @@
/* Assembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -50,26 +51,13 @@ static const char * parse_insn_normal
/* -- asm.c */
/* Handle register lists for LDMx and STMx. */
static int parse_register_number
PARAMS ((const char **));
static const char * parse_register_list
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *, int, int));
static const char * parse_low_register_list_ld
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_hi_register_list_ld
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_low_register_list_st
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_hi_register_list_st
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static int
parse_register_number (strp)
const char **strp;
parse_register_number (const char **strp)
{
int regno;
if (**strp < '0' || **strp > '9')
return -1; /* error. */
return -1; /* Error. */
regno = **strp - '0';
++*strp;
@ -83,30 +71,29 @@ parse_register_number (strp)
}
static const char *
parse_register_list (cd, strp, opindex, valuep, high_low, load_store)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
const char **strp;
int opindex ATTRIBUTE_UNUSED;
unsigned long *valuep;
int high_low; /* 0 == high, 1 == low */
int load_store; /* 0 == load, 1 == store */
parse_register_list (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
const char **strp,
int opindex ATTRIBUTE_UNUSED,
unsigned long *valuep,
int high_low, /* 0 == high, 1 == low. */
int load_store) /* 0 == load, 1 == store. */
{
int regno;
*valuep = 0;
while (**strp && **strp != ')')
{
int regno;
if (**strp != 'R' && **strp != 'r')
break;
++*strp;
regno = parse_register_number (strp);
if (regno == -1)
return "Register number is not valid";
return _("Register number is not valid");
if (regno > 7 && !high_low)
return "Register must be between r0 and r7";
return _("Register must be between r0 and r7");
if (regno < 8 && high_low)
return "Register must be between r8 and r15";
return _("Register must be between r8 and r15");
if (high_low)
regno -= 8;
@ -125,55 +112,55 @@ parse_register_list (cd, strp, opindex, valuep, high_low, load_store)
}
if (!*strp || **strp != ')')
return "Register list is not valid";
return _("Register list is not valid");
return NULL;
}
static const char *
parse_low_register_list_ld (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_low_register_list_ld (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
return parse_register_list (cd, strp, opindex, valuep, 0/*low*/, 0/*load*/);
return parse_register_list (cd, strp, opindex, valuep,
0 /* Low. */, 0 /* Load. */);
}
static const char *
parse_hi_register_list_ld (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_hi_register_list_ld (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
return parse_register_list (cd, strp, opindex, valuep, 1/*high*/, 0/*load*/);
return parse_register_list (cd, strp, opindex, valuep,
1 /* High. */, 0 /* Load. */);
}
static const char *
parse_low_register_list_st (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_low_register_list_st (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
return parse_register_list (cd, strp, opindex, valuep, 0/*low*/, 1/*store*/);
return parse_register_list (cd, strp, opindex, valuep,
0 /* Low. */, 1 /* Store. */);
}
static const char *
parse_hi_register_list_st (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_hi_register_list_st (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
return parse_register_list (cd, strp, opindex, valuep, 1/*high*/, 1/*store*/);
return parse_register_list (cd, strp, opindex, valuep,
1 /* High. */, 1 /* Store. */);
}
/* -- */
const char * fr30_cgen_parse_operand
PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
/* Main entry point for operand parsing.
@ -189,11 +176,10 @@ const char * fr30_cgen_parse_operand
the handlers. */
const char *
fr30_cgen_parse_operand (cd, opindex, strp, fields)
CGEN_CPU_DESC cd;
int opindex;
const char ** strp;
CGEN_FIELDS * fields;
fr30_cgen_parse_operand (CGEN_CPU_DESC cd,
int opindex,
const char ** strp,
CGEN_FIELDS * fields)
{
const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */
@ -333,8 +319,7 @@ cgen_parse_fn * const fr30_cgen_parse_handlers[] =
};
void
fr30_cgen_init_asm (cd)
CGEN_CPU_DESC cd;
fr30_cgen_init_asm (CGEN_CPU_DESC cd)
{
fr30_cgen_init_opcode_table (cd);
fr30_cgen_init_ibld_table (cd);
@ -717,30 +702,3 @@ fr30_cgen_assemble_insn (CGEN_CPU_DESC cd,
return NULL;
}
}
#if 0 /* This calls back to GAS which we can't do without care. */
/* Record each member of OPVALS in the assembler's symbol table.
This lets GAS parse registers for us.
??? Interesting idea but not currently used. */
/* Record each member of OPVALS in the assembler's symbol table.
FIXME: Not currently used. */
void
fr30_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
{
CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
const CGEN_KEYWORD_ENTRY * ke;
while ((ke = cgen_keyword_search_next (& search)) != NULL)
{
#if 0 /* Unnecessary, should be done in the search routine. */
if (! fr30_cgen_opval_supported (ke))
continue;
#endif
cgen_asm_record_register (cd, ke->name, ke->value);
}
}
#endif /* 0 */

75
opcodes/fr30-desc.c
View File

@ -1429,27 +1429,23 @@ static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
#undef A
/* Initialize anything needed to be done once, before any cpu_open call. */
static void init_tables PARAMS ((void));
static void
init_tables ()
init_tables (void)
{
}
static const CGEN_MACH * lookup_mach_via_bfd_name
PARAMS ((const CGEN_MACH *, const char *));
static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
static void fr30_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
static void build_hw_table (CGEN_CPU_TABLE *);
static void build_ifield_table (CGEN_CPU_TABLE *);
static void build_operand_table (CGEN_CPU_TABLE *);
static void build_insn_table (CGEN_CPU_TABLE *);
static void fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *);
/* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
lookup_mach_via_bfd_name (table, name)
const CGEN_MACH *table;
const char *name;
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
{
while (table->name)
{
@ -1463,8 +1459,7 @@ lookup_mach_via_bfd_name (table, name)
/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
static void
build_hw_table (cd)
CGEN_CPU_TABLE *cd;
build_hw_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -1490,8 +1485,7 @@ build_hw_table (cd)
/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
static void
build_ifield_table (cd)
CGEN_CPU_TABLE *cd;
build_ifield_table (CGEN_CPU_TABLE *cd)
{
cd->ifld_table = & fr30_cgen_ifld_table[0];
}
@ -1499,8 +1493,7 @@ build_ifield_table (cd)
/* Subroutine of fr30_cgen_cpu_open to build the hardware table. */
static void
build_operand_table (cd)
CGEN_CPU_TABLE *cd;
build_operand_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -1508,8 +1501,7 @@ build_operand_table (cd)
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
However each entry is indexed by it's enum so there can be holes in
the table. */
const CGEN_OPERAND **selected =
(const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
cd->operand_table.init_entries = init;
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@ -1532,12 +1524,11 @@ build_operand_table (cd)
operand elements to be in the table [which they mightn't be]. */
static void
build_insn_table (cd)
CGEN_CPU_TABLE *cd;
build_insn_table (CGEN_CPU_TABLE *cd)
{
int i;
const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
for (i = 0; i < MAX_INSNS; ++i)
@ -1550,8 +1541,7 @@ build_insn_table (cd)
/* Subroutine of fr30_cgen_cpu_open to rebuild the tables. */
static void
fr30_cgen_rebuild_tables (cd)
CGEN_CPU_TABLE *cd;
fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
{
int i;
unsigned int isas = cd->isas;
@ -1563,7 +1553,7 @@ fr30_cgen_rebuild_tables (cd)
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
cd->default_insn_bitsize = UNSET;
cd->base_insn_bitsize = UNSET;
cd->min_insn_bitsize = 65535; /* some ridiculously big number */
cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
cd->max_insn_bitsize = 0;
for (i = 0; i < MAX_ISAS; ++i)
if (((1 << i) & isas) != 0)
@ -1575,7 +1565,7 @@ fr30_cgen_rebuild_tables (cd)
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -1584,7 +1574,7 @@ fr30_cgen_rebuild_tables (cd)
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -1696,12 +1686,12 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
}
va_end (ap);
/* mach unspecified means "all" */
/* Mach unspecified means "all". */
if (machs == 0)
machs = (1 << MAX_MACHS) - 1;
/* base mach is always selected */
/* Base mach is always selected. */
machs |= 1;
/* isa unspecified means "all" */
/* ISA unspecified means "all". */
if (isas == 0)
isas = (1 << MAX_ISAS) - 1;
if (endian == CGEN_ENDIAN_UNKNOWN)
@ -1734,9 +1724,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
MACH_NAME is the bfd name of the mach. */
CGEN_CPU_DESC
fr30_cgen_cpu_open_1 (mach_name, endian)
const char *mach_name;
enum cgen_endian endian;
fr30_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
{
return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, endian,
@ -1749,8 +1737,7 @@ fr30_cgen_cpu_open_1 (mach_name, endian)
place as some simulator ports use this but they don't use libopcodes. */
void
fr30_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
fr30_cgen_cpu_close (CGEN_CPU_DESC cd)
{
unsigned int i;
const CGEN_INSN *insns;
@ -1759,23 +1746,17 @@ fr30_cgen_cpu_close (cd)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

167
opcodes/fr30-dis.c
View File

@ -1,27 +1,27 @@
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -56,33 +56,19 @@ static int read_insn
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
unsigned long *);
/* -- disassembler routines inserted here */
/* -- disassembler routines inserted here. */
/* -- dis.c */
static void print_register_list
PARAMS ((PTR, long, long, int));
static void print_hi_register_list_ld
PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
static void print_low_register_list_ld
PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
static void print_hi_register_list_st
PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
static void print_low_register_list_st
PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
static void print_m4
PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
static void
print_register_list (dis_info, value, offset, load_store)
PTR dis_info;
long value;
long offset;
int load_store; /* 0 == load, 1 == store */
print_register_list (void * dis_info,
long value,
long offset,
int load_store) /* 0 == load, 1 == store. */
{
disassemble_info *info = dis_info;
int mask;
int index = 0;
char* comma = "";
char * comma = "";
if (load_store)
mask = 0x80;
@ -111,70 +97,65 @@ print_register_list (dis_info, value, offset, load_store)
}
static void
print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_hi_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
print_register_list (dis_info, value, 8, 0/*load*/);
print_register_list (dis_info, value, 8, 0 /* Load. */);
}
static void
print_low_register_list_ld (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_low_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
print_register_list (dis_info, value, 0, 0/*load*/);
print_register_list (dis_info, value, 0, 0 /* Load. */);
}
static void
print_hi_register_list_st (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_hi_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
print_register_list (dis_info, value, 8, 1/*store*/);
print_register_list (dis_info, value, 8, 1 /* Store. */);
}
static void
print_low_register_list_st (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_low_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
print_register_list (dis_info, value, 0, 1/*store*/);
print_register_list (dis_info, value, 0, 1 /* Store. */);
}
static void
print_m4 (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_m4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "%ld", value);
}
/* -- */
void fr30_cgen_print_operand
PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
void const *, bfd_vma, int));
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@ -192,16 +173,15 @@ void fr30_cgen_print_operand
the handlers. */
void
fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
CGEN_CPU_DESC cd;
int opindex;
PTR xinfo;
CGEN_FIELDS *fields;
void const *attrs ATTRIBUTE_UNUSED;
bfd_vma pc;
int length;
fr30_cgen_print_operand (CGEN_CPU_DESC cd,
int opindex,
void * xinfo,
CGEN_FIELDS *fields,
void const *attrs ATTRIBUTE_UNUSED,
bfd_vma pc,
int length)
{
disassemble_info *info = (disassemble_info *) xinfo;
disassemble_info *info = (disassemble_info *) xinfo;
switch (opindex)
{
@ -329,8 +309,7 @@ cgen_print_fn * const fr30_cgen_print_handlers[] =
void
fr30_cgen_init_dis (cd)
CGEN_CPU_DESC cd;
fr30_cgen_init_dis (CGEN_CPU_DESC cd)
{
fr30_cgen_init_opcode_table (cd);
fr30_cgen_init_ibld_table (cd);
@ -382,7 +361,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
; /* Nothing to do. */
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
(*info->print_address_func) (value, info);
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@ -464,6 +443,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
unsigned long *insn_value)
{
int status = (*info->read_memory_func) (pc, buf, buflen, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
@ -568,13 +548,13 @@ print_insn (CGEN_CPU_DESC cd,
length = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
/* length < 0 -> error */
/* Length < 0 -> error. */
if (length < 0)
return length;
if (length > 0)
{
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
/* length is in bits, result is in bytes */
/* Length is in bits, result is in bytes. */
return length / 8;
}
}
@ -624,7 +604,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list {
typedef struct cpu_desc_list
{
struct cpu_desc_list *next;
int isa;
int mach;
@ -709,7 +690,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
if (!cd)
abort ();
/* save this away for future reference */
/* Save this away for future reference. */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;

132
opcodes/fr30-ibld.c
View File

@ -1,25 +1,26 @@
/* Instruction building/extraction support for fr30. -*- C -*-
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h"
#include "safe-ctype.h"
#undef min
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
#undef max
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
/* Used by the ifield rtx function. */
@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
if (length == 0)
return NULL;
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
static void
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int shift = insn_length - length;
/* Written this way to avoid undefined behaviour. */
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
{
unsigned long x;
int shift;
#if 0
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
#endif
x = cgen_get_insn_value (cd, bufp, word_length);
if (CGEN_INSN_LSB0_P)
@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
return 1;
}
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
return CGEN_INSN_BITSIZE (insn);
}
/* machine generated code added here */
/* Machine generated code added here. */
const char * fr30_cgen_insert_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
/* Main entry point for operand insertion.
@ -559,12 +547,11 @@ const char * fr30_cgen_insert_operand
resolved during parsing. */
const char *
fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_FIELDS * fields;
CGEN_INSN_BYTES_PTR buffer;
bfd_vma pc ATTRIBUTE_UNUSED;
fr30_cgen_insert_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_FIELDS * fields,
CGEN_INSN_BYTES_PTR buffer,
bfd_vma pc ATTRIBUTE_UNUSED)
{
const char * errmsg = NULL;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@ -738,8 +725,7 @@ fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc)
}
int fr30_cgen_extract_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
CGEN_FIELDS *, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
/* Main entry point for operand extraction.
The result is <= 0 for error, >0 for success.
@ -757,13 +743,12 @@ int fr30_cgen_extract_operand
the handlers. */
int
fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_EXTRACT_INFO *ex_info;
CGEN_INSN_INT insn_value;
CGEN_FIELDS * fields;
bfd_vma pc;
fr30_cgen_extract_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_EXTRACT_INFO *ex_info,
CGEN_INSN_INT insn_value,
CGEN_FIELDS * fields,
bfd_vma pc)
{
/* Assume success (for those operands that are nops). */
int length = 1;
@ -954,10 +939,8 @@ cgen_extract_fn * const fr30_cgen_extract_handlers[] =
extract_insn_normal,
};
int fr30_cgen_get_int_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
bfd_vma fr30_cgen_get_vma_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
int fr30_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
bfd_vma fr30_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
@ -965,10 +948,9 @@ bfd_vma fr30_cgen_get_vma_operand
not appropriate. */
int
fr30_cgen_get_int_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
fr30_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
int value;
@ -1094,10 +1076,9 @@ fr30_cgen_get_int_operand (cd, opindex, fields)
}
bfd_vma
fr30_cgen_get_vma_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
fr30_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
bfd_vma value;
@ -1222,10 +1203,8 @@ fr30_cgen_get_vma_operand (cd, opindex, fields)
return value;
}
void fr30_cgen_set_int_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
void fr30_cgen_set_vma_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
void fr30_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
void fr30_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
@ -1233,11 +1212,10 @@ void fr30_cgen_set_vma_operand
not appropriate. */
void
fr30_cgen_set_int_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
int value;
fr30_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
int value)
{
switch (opindex)
{
@ -1355,11 +1333,10 @@ fr30_cgen_set_int_operand (cd, opindex, fields, value)
}
void
fr30_cgen_set_vma_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
bfd_vma value;
fr30_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
bfd_vma value)
{
switch (opindex)
{
@ -1479,8 +1456,7 @@ fr30_cgen_set_vma_operand (cd, opindex, fields, value)
/* Function to call before using the instruction builder tables. */
void
fr30_cgen_init_ibld_table (cd)
CGEN_CPU_DESC cd;
fr30_cgen_init_ibld_table (CGEN_CPU_DESC cd)
{
cd->insert_handlers = & fr30_cgen_insert_handlers[0];
cd->extract_handlers = & fr30_cgen_extract_handlers[0];

20
opcodes/fr30-opc.c
View File

@ -33,10 +33,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
static int asm_hash_insn_p (const CGEN_INSN *);
static unsigned int asm_hash_insn (const char *);
static int dis_hash_insn_p (const CGEN_INSN *);
static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
/* Instruction formats. */
@ -1340,14 +1340,10 @@ dis_hash_insn (buf, value)
return CGEN_DIS_HASH (buf, value);
}
static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
static void
set_fields_bitsize (fields, size)
CGEN_FIELDS *fields;
int size;
set_fields_bitsize (CGEN_FIELDS *fields, int size)
{
CGEN_FIELDS_BITSIZE (fields) = size;
}
@ -1356,15 +1352,15 @@ set_fields_bitsize (fields, size)
This plugs the opcode entries and macro instructions into the cpu table. */
void
fr30_cgen_init_opcode_table (cd)
CGEN_CPU_DESC cd;
fr30_cgen_init_opcode_table (CGEN_CPU_DESC cd)
{
int i;
int num_macros = (sizeof (fr30_cgen_macro_insn_table) /
sizeof (fr30_cgen_macro_insn_table[0]));
const CGEN_IBASE *ib = & fr30_cgen_macro_insn_table[0];
const CGEN_OPCODE *oc = & fr30_cgen_macro_insn_opcode_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
memset (insns, 0, num_macros * sizeof (CGEN_INSN));
for (i = 0; i < num_macros; ++i)
{

4
opcodes/fr30-opc.h
View File

@ -28,9 +28,9 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* -- opc.h */
/* ??? This can be improved upon. */
#undef CGEN_DIS_HASH_SIZE
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 16
#undef CGEN_DIS_HASH
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4)
/* -- */

298
opcodes/frv-asm.c
View File

@ -1,26 +1,27 @@
/* Assembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -48,31 +49,6 @@ static const char * parse_insn_normal
/* -- assembler routines inserted here. */
/* -- asm.c */
static const char * parse_ulo16
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_uslo16
PARAMS ((CGEN_CPU_DESC, const char **, int, signed long *));
static const char * parse_uhi16
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static long parse_register_number
PARAMS ((const char **));
static const char * parse_spr
PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *));
static const char * parse_d12
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_s12
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_u12
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_even_register
PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *));
static const char * parse_A0
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_A1
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_A
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *, unsigned long));
inline static const char *
parse_symbolic_address (CGEN_CPU_DESC cd,
const char **strp,
@ -214,11 +190,10 @@ parse_ld_annotation (CGEN_CPU_DESC cd,
}
static const char *
parse_ulo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_ulo16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -230,7 +205,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
++*strp;
@ -245,7 +220,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
*strp += 9;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GPRELLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -257,7 +232,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
*strp += 7;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -269,7 +244,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
*strp += 15;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_FUNCDESC_GOTLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -281,7 +256,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
*strp += 10;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTOFFLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -293,7 +268,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
*strp += 18;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_FUNCDESC_GOTOFFLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -305,7 +280,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
*strp += 14;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTTLSDESCLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -317,7 +292,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
*strp += 11;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_TLSMOFFLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -329,7 +304,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
*strp += 13;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTTLSOFFLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -341,11 +316,10 @@ parse_ulo16 (cd, strp, opindex, valuep)
}
static const char *
parse_uslo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
signed long *valuep;
parse_uslo16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
signed long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -357,7 +331,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
++*strp;
@ -372,7 +346,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
*strp += 9;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GPRELLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -384,7 +358,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
*strp += 7;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -396,7 +370,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
*strp += 15;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_FUNCDESC_GOTLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -408,7 +382,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
*strp += 10;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTOFFLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -420,7 +394,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
*strp += 18;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_FUNCDESC_GOTOFFLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -432,7 +406,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
*strp += 14;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTTLSDESCLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -444,7 +418,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
*strp += 11;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_TLSMOFFLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -456,7 +430,7 @@ parse_uslo16 (cd, strp, opindex, valuep)
*strp += 13;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTTLSOFFLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -468,11 +442,10 @@ parse_uslo16 (cd, strp, opindex, valuep)
}
static const char *
parse_uhi16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_uhi16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -484,7 +457,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_HI16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
++*strp;
@ -506,7 +479,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
*strp += 9;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GPRELHI,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -518,7 +491,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
*strp += 7;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTHI,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -530,7 +503,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
*strp += 15;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_FUNCDESC_GOTHI,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -542,7 +515,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
*strp += 10;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTOFFHI,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -554,7 +527,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
*strp += 18;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_FUNCDESC_GOTOFFHI,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -578,7 +551,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
*strp += 11;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_TLSMOFFHI,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -590,7 +563,7 @@ parse_uhi16 (cd, strp, opindex, valuep)
*strp += 13;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTTLSOFFHI,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -602,10 +575,10 @@ parse_uhi16 (cd, strp, opindex, valuep)
}
static long
parse_register_number (strp)
const char **strp;
parse_register_number (const char **strp)
{
int regno;
if (**strp < '0' || **strp > '9')
return -1; /* error */
@ -617,11 +590,10 @@ parse_register_number (strp)
}
static const char *
parse_spr (cd, strp, table, valuep)
CGEN_CPU_DESC cd;
const char **strp;
CGEN_KEYWORD * table;
long *valuep;
parse_spr (CGEN_CPU_DESC cd,
const char **strp,
CGEN_KEYWORD * table,
long *valuep)
{
const char *save_strp;
long regno;
@ -632,10 +604,10 @@ parse_spr (cd, strp, table, valuep)
*strp += 4;
regno = parse_register_number (strp);
if (**strp != ']')
return "missing `]'";
return _("missing `]'");
++*strp;
if (! spr_valid (regno))
return "Special purpose register number is out of range";
return _("Special purpose register number is out of range");
*valuep = regno;
return NULL;
}
@ -645,7 +617,7 @@ parse_spr (cd, strp, table, valuep)
if (regno != -1)
{
if (! spr_valid (regno))
return "Special purpose register number is out of range";
return _("Special purpose register number is out of range");
*valuep = regno;
return NULL;
}
@ -655,11 +627,10 @@ parse_spr (cd, strp, table, valuep)
}
static const char *
parse_d12 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
parse_d12 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -673,7 +644,7 @@ parse_d12 (cd, strp, opindex, valuep)
*strp += 9;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GPREL12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
++*strp;
@ -685,7 +656,7 @@ parse_d12 (cd, strp, opindex, valuep)
*strp += 7;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOT12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -697,7 +668,7 @@ parse_d12 (cd, strp, opindex, valuep)
*strp += 15;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_FUNCDESC_GOT12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -709,7 +680,7 @@ parse_d12 (cd, strp, opindex, valuep)
*strp += 10;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTOFF12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -721,7 +692,7 @@ parse_d12 (cd, strp, opindex, valuep)
*strp += 18;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_FUNCDESC_GOTOFF12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -733,7 +704,7 @@ parse_d12 (cd, strp, opindex, valuep)
*strp += 14;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTTLSDESC12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -745,7 +716,7 @@ parse_d12 (cd, strp, opindex, valuep)
*strp += 11;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_TLSMOFF12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -757,7 +728,7 @@ parse_d12 (cd, strp, opindex, valuep)
*strp += 13;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTTLSOFF12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -769,11 +740,10 @@ parse_d12 (cd, strp, opindex, valuep)
}
static const char *
parse_s12 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
parse_s12 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -787,7 +757,7 @@ parse_s12 (cd, strp, opindex, valuep)
*strp += 9;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GPREL12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
++*strp;
@ -799,7 +769,7 @@ parse_s12 (cd, strp, opindex, valuep)
*strp += 7;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOT12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -811,7 +781,7 @@ parse_s12 (cd, strp, opindex, valuep)
*strp += 15;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_FUNCDESC_GOT12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -823,7 +793,7 @@ parse_s12 (cd, strp, opindex, valuep)
*strp += 10;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTOFF12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -835,7 +805,7 @@ parse_s12 (cd, strp, opindex, valuep)
*strp += 18;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_FUNCDESC_GOTOFF12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -847,7 +817,7 @@ parse_s12 (cd, strp, opindex, valuep)
*strp += 14;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTTLSDESC12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -859,7 +829,7 @@ parse_s12 (cd, strp, opindex, valuep)
*strp += 11;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_TLSMOFF12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -871,7 +841,7 @@ parse_s12 (cd, strp, opindex, valuep)
*strp += 13;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GOTTLSOFF12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing ')'";
++*strp;
@ -886,11 +856,10 @@ parse_s12 (cd, strp, opindex, valuep)
}
static const char *
parse_u12 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
parse_u12 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -903,7 +872,7 @@ parse_u12 (cd, strp, opindex, valuep)
*strp += 9;
errmsg = parse_symbolic_address (cd, strp, opindex,
BFD_RELOC_FRV_GPRELU12,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
++*strp;
@ -919,12 +888,11 @@ parse_u12 (cd, strp, opindex, valuep)
}
static const char *
parse_A (cd, strp, opindex, valuep, A)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
unsigned long A;
parse_A (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep,
unsigned long A)
{
const char *errmsg;
@ -936,37 +904,34 @@ parse_A (cd, strp, opindex, valuep, A)
return errmsg;
if (*valuep != A)
return "Value of A operand must be 0 or 1";
return _("Value of A operand must be 0 or 1");
return NULL;
}
static const char *
parse_A0 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_A0 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
return parse_A (cd, strp, opindex, valuep, 0);
}
static const char *
parse_A1 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_A1 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
return parse_A (cd, strp, opindex, valuep, 1);
}
static const char *
parse_even_register (cd, strP, tableP, valueP)
CGEN_CPU_DESC cd;
const char ** strP;
CGEN_KEYWORD * tableP;
long * valueP;
parse_even_register (CGEN_CPU_DESC cd,
const char ** strP,
CGEN_KEYWORD * tableP,
long * valueP)
{
const char * errmsg;
const char * saved_star_strP = * strP;
@ -1003,7 +968,7 @@ parse_call_label (CGEN_CPU_DESC cd,
BFD_RELOC_FRV_GETTLSOFF,
resultp, &value);
if (**strp != ')')
return "missing `)'";
return _("missing `)'");
++*strp;
*valuep = value;
return errmsg;
@ -1016,7 +981,7 @@ parse_call_label (CGEN_CPU_DESC cd,
/* -- */
const char * frv_cgen_parse_operand
PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
/* Main entry point for operand parsing.
@ -1032,11 +997,10 @@ const char * frv_cgen_parse_operand
the handlers. */
const char *
frv_cgen_parse_operand (cd, opindex, strp, fields)
CGEN_CPU_DESC cd;
int opindex;
const char ** strp;
CGEN_FIELDS * fields;
frv_cgen_parse_operand (CGEN_CPU_DESC cd,
int opindex,
const char ** strp,
CGEN_FIELDS * fields)
{
const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */
@ -1308,8 +1272,7 @@ cgen_parse_fn * const frv_cgen_parse_handlers[] =
};
void
frv_cgen_init_asm (cd)
CGEN_CPU_DESC cd;
frv_cgen_init_asm (CGEN_CPU_DESC cd)
{
frv_cgen_init_opcode_table (cd);
frv_cgen_init_ibld_table (cd);
@ -1692,30 +1655,3 @@ frv_cgen_assemble_insn (CGEN_CPU_DESC cd,
return NULL;
}
}
#if 0 /* This calls back to GAS which we can't do without care. */
/* Record each member of OPVALS in the assembler's symbol table.
This lets GAS parse registers for us.
??? Interesting idea but not currently used. */
/* Record each member of OPVALS in the assembler's symbol table.
FIXME: Not currently used. */
void
frv_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
{
CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
const CGEN_KEYWORD_ENTRY * ke;
while ((ke = cgen_keyword_search_next (& search)) != NULL)
{
#if 0 /* Unnecessary, should be done in the search routine. */
if (! frv_cgen_opval_supported (ke))
continue;
#endif
cgen_asm_record_register (cd, ke->name, ke->value);
}
}
#endif /* 0 */

75
opcodes/frv-desc.c
View File

@ -6142,27 +6142,23 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
#undef A
/* Initialize anything needed to be done once, before any cpu_open call. */
static void init_tables PARAMS ((void));
static void
init_tables ()
init_tables (void)
{
}
static const CGEN_MACH * lookup_mach_via_bfd_name
PARAMS ((const CGEN_MACH *, const char *));
static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
static void frv_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
static void build_hw_table (CGEN_CPU_TABLE *);
static void build_ifield_table (CGEN_CPU_TABLE *);
static void build_operand_table (CGEN_CPU_TABLE *);
static void build_insn_table (CGEN_CPU_TABLE *);
static void frv_cgen_rebuild_tables (CGEN_CPU_TABLE *);
/* Subroutine of frv_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
lookup_mach_via_bfd_name (table, name)
const CGEN_MACH *table;
const char *name;
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
{
while (table->name)
{
@ -6176,8 +6172,7 @@ lookup_mach_via_bfd_name (table, name)
/* Subroutine of frv_cgen_cpu_open to build the hardware table. */
static void
build_hw_table (cd)
CGEN_CPU_TABLE *cd;
build_hw_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -6203,8 +6198,7 @@ build_hw_table (cd)
/* Subroutine of frv_cgen_cpu_open to build the hardware table. */
static void
build_ifield_table (cd)
CGEN_CPU_TABLE *cd;
build_ifield_table (CGEN_CPU_TABLE *cd)
{
cd->ifld_table = & frv_cgen_ifld_table[0];
}
@ -6212,8 +6206,7 @@ build_ifield_table (cd)
/* Subroutine of frv_cgen_cpu_open to build the hardware table. */
static void
build_operand_table (cd)
CGEN_CPU_TABLE *cd;
build_operand_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -6221,8 +6214,7 @@ build_operand_table (cd)
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
However each entry is indexed by it's enum so there can be holes in
the table. */
const CGEN_OPERAND **selected =
(const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
cd->operand_table.init_entries = init;
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@ -6245,12 +6237,11 @@ build_operand_table (cd)
operand elements to be in the table [which they mightn't be]. */
static void
build_insn_table (cd)
CGEN_CPU_TABLE *cd;
build_insn_table (CGEN_CPU_TABLE *cd)
{
int i;
const CGEN_IBASE *ib = & frv_cgen_insn_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
for (i = 0; i < MAX_INSNS; ++i)
@ -6263,8 +6254,7 @@ build_insn_table (cd)
/* Subroutine of frv_cgen_cpu_open to rebuild the tables. */
static void
frv_cgen_rebuild_tables (cd)
CGEN_CPU_TABLE *cd;
frv_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
{
int i;
unsigned int isas = cd->isas;
@ -6276,7 +6266,7 @@ frv_cgen_rebuild_tables (cd)
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
cd->default_insn_bitsize = UNSET;
cd->base_insn_bitsize = UNSET;
cd->min_insn_bitsize = 65535; /* some ridiculously big number */
cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
cd->max_insn_bitsize = 0;
for (i = 0; i < MAX_ISAS; ++i)
if (((1 << i) & isas) != 0)
@ -6288,7 +6278,7 @@ frv_cgen_rebuild_tables (cd)
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -6297,7 +6287,7 @@ frv_cgen_rebuild_tables (cd)
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -6409,12 +6399,12 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
}
va_end (ap);
/* mach unspecified means "all" */
/* Mach unspecified means "all". */
if (machs == 0)
machs = (1 << MAX_MACHS) - 1;
/* base mach is always selected */
/* Base mach is always selected. */
machs |= 1;
/* isa unspecified means "all" */
/* ISA unspecified means "all". */
if (isas == 0)
isas = (1 << MAX_ISAS) - 1;
if (endian == CGEN_ENDIAN_UNKNOWN)
@ -6447,9 +6437,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
MACH_NAME is the bfd name of the mach. */
CGEN_CPU_DESC
frv_cgen_cpu_open_1 (mach_name, endian)
const char *mach_name;
enum cgen_endian endian;
frv_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
{
return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, endian,
@ -6462,8 +6450,7 @@ frv_cgen_cpu_open_1 (mach_name, endian)
place as some simulator ports use this but they don't use libopcodes. */
void
frv_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
frv_cgen_cpu_close (CGEN_CPU_DESC cd)
{
unsigned int i;
const CGEN_INSN *insns;
@ -6472,23 +6459,17 @@ frv_cgen_cpu_close (cd)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

125
opcodes/frv-dis.c
View File

@ -1,27 +1,27 @@
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -56,36 +56,28 @@ static int read_insn
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
unsigned long *);
/* -- disassembler routines inserted here */
/* -- disassembler routines inserted here. */
/* -- dis.c */
static void print_spr
PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned));
static void print_hi
PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
static void print_lo
PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
static void
print_at (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
PTR dis_info,
void * dis_info,
long reloc_ann ATTRIBUTE_UNUSED,
long value ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED
)
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "@");
}
static void
print_spr (cd, dis_info, names, regno, attrs)
CGEN_CPU_DESC cd;
PTR dis_info;
CGEN_KEYWORD *names;
long regno;
unsigned int attrs;
print_spr (CGEN_CPU_DESC cd,
void * dis_info,
CGEN_KEYWORD *names,
long regno,
unsigned int attrs)
{
/* Use the register index format for any unnamed registers. */
if (cgen_keyword_lookup_value (names, regno) == NULL)
@ -98,29 +90,25 @@ print_spr (cd, dis_info, names, regno, attrs)
}
static void
print_hi (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_hi (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
if (value)
(*info->fprintf_func) (info->stream, "0x%lx", value);
else
(*info->fprintf_func) (info->stream, "hi(0x%lx)", value);
(*info->fprintf_func) (info->stream, value ? "0x%lx" : "hi(0x%lx)", value);
}
static void
print_lo (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_lo (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
if (value)
@ -132,8 +120,7 @@ print_lo (cd, dis_info, value, attrs, pc, length)
/* -- */
void frv_cgen_print_operand
PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
void const *, bfd_vma, int));
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@ -151,16 +138,15 @@ void frv_cgen_print_operand
the handlers. */
void
frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
CGEN_CPU_DESC cd;
int opindex;
PTR xinfo;
CGEN_FIELDS *fields;
void const *attrs ATTRIBUTE_UNUSED;
bfd_vma pc;
int length;
frv_cgen_print_operand (CGEN_CPU_DESC cd,
int opindex,
void * xinfo,
CGEN_FIELDS *fields,
void const *attrs ATTRIBUTE_UNUSED,
bfd_vma pc,
int length)
{
disassemble_info *info = (disassemble_info *) xinfo;
disassemble_info *info = (disassemble_info *) xinfo;
switch (opindex)
{
@ -420,8 +406,7 @@ cgen_print_fn * const frv_cgen_print_handlers[] =
void
frv_cgen_init_dis (cd)
CGEN_CPU_DESC cd;
frv_cgen_init_dis (CGEN_CPU_DESC cd)
{
frv_cgen_init_opcode_table (cd);
frv_cgen_init_ibld_table (cd);
@ -473,7 +458,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
; /* Nothing to do. */
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
(*info->print_address_func) (value, info);
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@ -555,6 +540,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
unsigned long *insn_value)
{
int status = (*info->read_memory_func) (pc, buf, buflen, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
@ -659,13 +645,13 @@ print_insn (CGEN_CPU_DESC cd,
length = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
/* length < 0 -> error */
/* Length < 0 -> error. */
if (length < 0)
return length;
if (length > 0)
{
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
/* length is in bits, result is in bytes */
/* Length is in bits, result is in bytes. */
return length / 8;
}
}
@ -715,7 +701,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list {
typedef struct cpu_desc_list
{
struct cpu_desc_list *next;
int isa;
int mach;
@ -800,7 +787,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info)
if (!cd)
abort ();
/* save this away for future reference */
/* Save this away for future reference. */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;

132
opcodes/frv-ibld.c
View File

@ -1,25 +1,26 @@
/* Instruction building/extraction support for frv. -*- C -*-
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h"
#include "safe-ctype.h"
#undef min
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
#undef max
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
/* Used by the ifield rtx function. */
@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
if (length == 0)
return NULL;
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
static void
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int shift = insn_length - length;
/* Written this way to avoid undefined behaviour. */
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
{
unsigned long x;
int shift;
#if 0
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
#endif
x = cgen_get_insn_value (cd, bufp, word_length);
if (CGEN_INSN_LSB0_P)
@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
return 1;
}
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
return CGEN_INSN_BITSIZE (insn);
}
/* machine generated code added here */
/* Machine generated code added here. */
const char * frv_cgen_insert_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
/* Main entry point for operand insertion.
@ -559,12 +547,11 @@ const char * frv_cgen_insert_operand
resolved during parsing. */
const char *
frv_cgen_insert_operand (cd, opindex, fields, buffer, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_FIELDS * fields;
CGEN_INSN_BYTES_PTR buffer;
bfd_vma pc ATTRIBUTE_UNUSED;
frv_cgen_insert_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_FIELDS * fields,
CGEN_INSN_BYTES_PTR buffer,
bfd_vma pc ATTRIBUTE_UNUSED)
{
const char * errmsg = NULL;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@ -864,8 +851,7 @@ frv_cgen_insert_operand (cd, opindex, fields, buffer, pc)
}
int frv_cgen_extract_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
CGEN_FIELDS *, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
/* Main entry point for operand extraction.
The result is <= 0 for error, >0 for success.
@ -883,13 +869,12 @@ int frv_cgen_extract_operand
the handlers. */
int
frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_EXTRACT_INFO *ex_info;
CGEN_INSN_INT insn_value;
CGEN_FIELDS * fields;
bfd_vma pc;
frv_cgen_extract_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_EXTRACT_INFO *ex_info,
CGEN_INSN_INT insn_value,
CGEN_FIELDS * fields,
bfd_vma pc)
{
/* Assume success (for those operands that are nops). */
int length = 1;
@ -1192,10 +1177,8 @@ cgen_extract_fn * const frv_cgen_extract_handlers[] =
extract_insn_normal,
};
int frv_cgen_get_int_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
bfd_vma frv_cgen_get_vma_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
int frv_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
bfd_vma frv_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
@ -1203,10 +1186,9 @@ bfd_vma frv_cgen_get_vma_operand
not appropriate. */
int
frv_cgen_get_int_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
frv_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
int value;
@ -1464,10 +1446,9 @@ frv_cgen_get_int_operand (cd, opindex, fields)
}
bfd_vma
frv_cgen_get_vma_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
frv_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
bfd_vma value;
@ -1724,10 +1705,8 @@ frv_cgen_get_vma_operand (cd, opindex, fields)
return value;
}
void frv_cgen_set_int_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
void frv_cgen_set_vma_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
void frv_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
void frv_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
@ -1735,11 +1714,10 @@ void frv_cgen_set_vma_operand
not appropriate. */
void
frv_cgen_set_int_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
int value;
frv_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
int value)
{
switch (opindex)
{
@ -1993,11 +1971,10 @@ frv_cgen_set_int_operand (cd, opindex, fields, value)
}
void
frv_cgen_set_vma_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
bfd_vma value;
frv_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
bfd_vma value)
{
switch (opindex)
{
@ -2253,8 +2230,7 @@ frv_cgen_set_vma_operand (cd, opindex, fields, value)
/* Function to call before using the instruction builder tables. */
void
frv_cgen_init_ibld_table (cd)
CGEN_CPU_DESC cd;
frv_cgen_init_ibld_table (CGEN_CPU_DESC cd)
{
cd->insert_handlers = & frv_cgen_insert_handlers[0];
cd->extract_handlers = & frv_cgen_extract_handlers[0];

277
opcodes/frv-opc.c
View File

@ -34,132 +34,120 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "elf/frv.h"
#include <stdio.h>
static int match_unit
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, CGEN_ATTR_VALUE_TYPE));
static int match_vliw
PARAMS ((VLIW_COMBO *, VLIW_COMBO *, int));
static VLIW_COMBO * add_next_to_vliw
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int find_major_in_vliw
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr400_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr450_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr500_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr550_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, const CGEN_INSN *));
static int check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, const CGEN_INSN *));
/* Returns TRUE if {MAJOR,MACH} is a major branch of the FRV
development tree. */
int
bfd_boolean
frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
{
switch (mach)
{
case bfd_mach_fr400:
if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6)
return 1; /* is a branch */
return TRUE;
break;
case bfd_mach_fr450:
if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6)
return 1; /* is a branch */
return TRUE;
break;
default:
if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6)
return 1; /* is a branch */
return TRUE;
break;
}
return 0; /* not a branch */
return FALSE;
}
int
/* Returns TRUE if {MAJOR,MACH} supports floating point insns. */
bfd_boolean
frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
{
switch (mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
return 0; /* No float insns */
return FALSE;
default:
if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8)
return 1; /* is a float insn */
return TRUE;
break;
}
return 0; /* not a branch */
return FALSE;
}
int
/* Returns TRUE if {MAJOR,MACH} supports media insns. */
bfd_boolean
frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
{
switch (mach)
{
case bfd_mach_fr400:
if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2)
return 1; /* is a media insn */
return TRUE;
break;
case bfd_mach_fr450:
if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6)
return 1; /* is a media insn */
return TRUE;
break;
default:
if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8)
return 1; /* is a media insn */
return TRUE;
break;
}
return 0; /* not a branch */
return FALSE;
}
int
bfd_boolean
frv_is_branch_insn (const CGEN_INSN *insn)
{
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
return TRUE;
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
return 1;
return TRUE;
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
return TRUE;
return 0;
return FALSE;
}
int
bfd_boolean
frv_is_float_insn (const CGEN_INSN *insn)
{
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
return TRUE;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
return 1;
return TRUE;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
return TRUE;
return 0;
return FALSE;
}
int
bfd_boolean
frv_is_media_insn (const CGEN_INSN *insn)
{
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
return TRUE;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
return 1;
return TRUE;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
return TRUE;
return 0;
return FALSE;
}
/* This table represents the allowable packing for vliw insns for the fr400.
@ -397,10 +385,10 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags)
}
}
/* Return 1 if unit1 is a match for unit2.
/* Return TRUE if unit1 is a match for unit2.
Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the
*_allowed_vliw tables above. */
static int
static bfd_boolean
match_unit (FRV_VLIW *vliw,
CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2)
{
@ -408,9 +396,9 @@ match_unit (FRV_VLIW *vliw,
unit1 = vliw->unit_mapping[unit1];
if (unit1 == unit2)
return 1;
return TRUE;
if (unit1 < unit2)
return 0;
return FALSE;
switch (unit1)
{
@ -420,36 +408,34 @@ match_unit (FRV_VLIW *vliw,
/* The 01 versions of these units are within 2 enums of the 0 or 1
versions. */
if (unit1 - unit2 <= 2)
return 1;
return TRUE;
break;
case UNIT_IALL:
case UNIT_FMALL:
/* The ALL versions of these units are within 5 enums of the 0, 1, 2 or 3
versions. */
if (unit1 - unit2 <= 5)
return 1;
return TRUE;
break;
default:
break;
}
return 0;
return FALSE;
}
/* Return 1 if the vliws match, 0 otherwise. */
/* Return TRUE if the vliws match, FALSE otherwise. */
static int
static bfd_boolean
match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size)
{
int i;
for (i = 0; i < vliw_size; ++i)
{
if ((*vliw1)[i] != (*vliw2)[i])
return 0;
}
if ((*vliw1)[i] != (*vliw2)[i])
return FALSE;
return 1;
return TRUE;
}
/* Find the next vliw vliw in the table that can accomodate the new insn.
@ -466,7 +452,7 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
{
fprintf (stderr, "frv-opc.c line %d: bad vliw->next_slot value.\n",
__LINE__);
abort (); /* Should never happen */
abort (); /* Should never happen. */
}
/* The table is sorted by units allowed within slots, so vliws with
@ -483,28 +469,26 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
return NULL;
}
/* Look for the given major insn type in the given vliw. Return 1 if found,
return 0 otherwise. */
/* Look for the given major insn type in the given vliw.
Returns TRUE if found, FALSE otherwise. */
static int
static bfd_boolean
find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
{
int i;
for (i = 0; i < vliw->next_slot; ++i)
if (vliw->major[i] == major)
return 1;
return TRUE;
return 0;
return FALSE;
}
/* Check for constraints between the insns in the vliw due to major insn
types. */
static int
fr400_check_insn_major_constraints (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
)
static bfd_boolean
fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
{
/* In the cpu file, all media insns are represented as being allowed in
both media units. This makes it easier since this is the case for fr500.
@ -516,17 +500,15 @@ fr400_check_insn_major_constraints (
return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1)
&& ! find_major_in_vliw (vliw, FR400_MAJOR_M_2);
case FR400_MAJOR_M_1:
return !find_major_in_vliw (vliw, FR400_MAJOR_M_2);
return ! find_major_in_vliw (vliw, FR400_MAJOR_M_2);
default:
break;
}
return 1;
return TRUE;
}
static int
fr450_check_insn_major_constraints (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
)
static bfd_boolean
fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
{
CGEN_ATTR_VALUE_TYPE other_major;
@ -536,7 +518,7 @@ fr450_check_insn_major_constraints (
/* (M4, M5) and (M4, M6) are allowed. */
if (other_major == FR450_MAJOR_M_4)
if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6)
return 1;
return TRUE;
/* Otherwise, instructions in even-numbered media categories cannot be
executed in parallel with other media instructions. */
@ -556,38 +538,37 @@ fr450_check_insn_major_constraints (
|| other_major == FR450_MAJOR_M_6);
default:
return 1;
return TRUE;
}
}
static int
find_unit_in_vliw (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit
)
static bfd_boolean
find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
{
int i;
for (i = 0; i < vliw->next_slot; ++i)
if (CGEN_INSN_ATTR_VALUE (vliw->insn[i], CGEN_INSN_UNIT) == unit)
return 1;
return TRUE;
return 0; /* not found */
return FALSE; /* Not found. */
}
static int
find_major_in_slot (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, CGEN_ATTR_VALUE_TYPE slot
)
static bfd_boolean
find_major_in_slot (FRV_VLIW *vliw,
CGEN_ATTR_VALUE_TYPE major,
CGEN_ATTR_VALUE_TYPE slot)
{
int i;
for (i = 0; i < vliw->next_slot; ++i)
if (vliw->major[i] == major && (*vliw->current_vliw)[i] == slot)
return 1;
return TRUE;
return 0;
return FALSE;
}
static int
static bfd_boolean
fr550_find_media_in_vliw (FRV_VLIW *vliw)
{
int i;
@ -603,13 +584,13 @@ fr550_find_media_in_vliw (FRV_VLIW *vliw)
|| CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_1)
continue;
return 1; /* found one */
return TRUE; /* Found one. */
}
return 0;
return FALSE;
}
static int
static bfd_boolean
fr550_find_float_in_vliw (FRV_VLIW *vliw)
{
int i;
@ -623,16 +604,16 @@ fr550_find_float_in_vliw (FRV_VLIW *vliw)
if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_FNOP)
continue;
return 1; /* found one */
return TRUE; /* Found one. */
}
return 0;
return FALSE;
}
static int
fr550_check_insn_major_constraints (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, const CGEN_INSN *insn
)
static bfd_boolean
fr550_check_insn_major_constraints (FRV_VLIW *vliw,
CGEN_ATTR_VALUE_TYPE major,
const CGEN_INSN *insn)
{
CGEN_ATTR_VALUE_TYPE unit;
CGEN_ATTR_VALUE_TYPE slot = (*vliw->current_vliw)[vliw->next_slot];
@ -646,8 +627,8 @@ fr550_check_insn_major_constraints (
break;
case UNIT_FM2:
case UNIT_FM3:
/* Floating point insns other than FNOP in slot f2 or f3 cannot coexist with
media insns. */
/* Floating point insns other than FNOP in slot f2 or f3 cannot coexist
with media insns. */
if (major >= FR550_MAJOR_F_1 && major <= FR550_MAJOR_F_4
&& CGEN_INSN_NUM (insn) != FRV_INSN_FNOP)
return ! fr550_find_media_in_vliw (vliw);
@ -657,30 +638,31 @@ fr550_check_insn_major_constraints (
&& CGEN_INSN_NUM (insn) != FRV_INSN_MNOP)
return ! fr550_find_float_in_vliw (vliw);
/* F-2 in slot f2 or f3 cannot coexist with F-2 or F-4 in slot f1 or f2
respectively.
*/
respectively. */
if (major == FR550_MAJOR_F_2)
return ! find_major_in_slot (vliw, FR550_MAJOR_F_2, slot - (UNIT_FM2 - UNIT_FM0))
&& ! find_major_in_slot (vliw, FR550_MAJOR_F_4, slot - (UNIT_FM2 - UNIT_FM0));
return ! find_major_in_slot (vliw, FR550_MAJOR_F_2,
slot - (UNIT_FM2 - UNIT_FM0))
&& ! find_major_in_slot (vliw, FR550_MAJOR_F_4,
slot - (UNIT_FM2 - UNIT_FM0));
/* M-2 or M-5 in slot m2 or m3 cannot coexist with M-2 in slot m1 or m2
respectively. */
if (major == FR550_MAJOR_M_2 || major == FR550_MAJOR_M_5)
return ! find_major_in_slot (vliw, FR550_MAJOR_M_2, slot - (UNIT_FM2 - UNIT_FM0));
return ! find_major_in_slot (vliw, FR550_MAJOR_M_2,
slot - (UNIT_FM2 - UNIT_FM0));
/* M-4 in slot m2 or m3 cannot coexist with M-4 in slot m1 or m2
respectively. */
if (major == FR550_MAJOR_M_4)
return ! find_major_in_slot (vliw, FR550_MAJOR_M_4, slot - (UNIT_FM2 - UNIT_FM0));
return ! find_major_in_slot (vliw, FR550_MAJOR_M_4,
slot - (UNIT_FM2 - UNIT_FM0));
break;
default:
break;
}
return 1; /* all ok */
return TRUE; /* All OK. */
}
static int
fr500_check_insn_major_constraints (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
)
static bfd_boolean
fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
{
/* TODO: A table might be faster for some of the more complex instances
here. */
@ -699,7 +681,7 @@ fr500_check_insn_major_constraints (
case FR500_MAJOR_F_4:
case FR500_MAJOR_F_8:
case FR500_MAJOR_M_8:
return 1; /* OK */
return TRUE; /* OK */
case FR500_MAJOR_I_2:
/* Cannot coexist with I-3 insn. */
return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3);
@ -783,35 +765,33 @@ fr500_check_insn_major_constraints (
abort ();
break;
}
return 1;
return TRUE;
}
static int
check_insn_major_constraints (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, const CGEN_INSN *insn
)
static bfd_boolean
check_insn_major_constraints (FRV_VLIW *vliw,
CGEN_ATTR_VALUE_TYPE major,
const CGEN_INSN *insn)
{
int rc;
switch (vliw->mach)
{
case bfd_mach_fr400:
rc = fr400_check_insn_major_constraints (vliw, major);
break;
return fr400_check_insn_major_constraints (vliw, major);
case bfd_mach_fr450:
rc = fr450_check_insn_major_constraints (vliw, major);
break;
return fr450_check_insn_major_constraints (vliw, major);
case bfd_mach_fr550:
rc = fr550_check_insn_major_constraints (vliw, major, insn);
break;
return fr550_check_insn_major_constraints (vliw, major, insn);
default:
rc = fr500_check_insn_major_constraints (vliw, major);
break;
return fr500_check_insn_major_constraints (vliw, major);
}
return rc;
}
/* Add in insn to the VLIW vliw if possible. Return 0 if successful,
non-zero otherwise. */
/* Add in insn to the VLIW vliw if possible.
Return 0 if successful, non-zero otherwise. */
int
frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
{
@ -832,7 +812,7 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
{
fprintf (stderr, "frv-opc.c line %d: bad insn unit.\n",
__LINE__);
abort (); /* no UNIT specified for this insn in frv.cpu */
abort (); /* No UNIT specified for this insn in frv.cpu. */
}
switch (vliw->mach)
@ -888,22 +868,21 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
return 1;
}
int
spr_valid (regno)
long regno;
bfd_boolean
spr_valid (long regno)
{
if (regno < 0) return 0;
if (regno <= 4095) return 1;
return 0;
if (regno < 0) return FALSE;
if (regno <= 4095) return TRUE;
return FALSE;
}
/* -- */
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
static int asm_hash_insn_p (const CGEN_INSN *);
static unsigned int asm_hash_insn (const char *);
static int dis_hash_insn_p (const CGEN_INSN *);
static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
/* Instruction formats. */
@ -6223,14 +6202,10 @@ dis_hash_insn (buf, value)
return CGEN_DIS_HASH (buf, value);
}
static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
static void
set_fields_bitsize (fields, size)
CGEN_FIELDS *fields;
int size;
set_fields_bitsize (CGEN_FIELDS *fields, int size)
{
CGEN_FIELDS_BITSIZE (fields) = size;
}
@ -6239,15 +6214,15 @@ set_fields_bitsize (fields, size)
This plugs the opcode entries and macro instructions into the cpu table. */
void
frv_cgen_init_opcode_table (cd)
CGEN_CPU_DESC cd;
frv_cgen_init_opcode_table (CGEN_CPU_DESC cd)
{
int i;
int num_macros = (sizeof (frv_cgen_macro_insn_table) /
sizeof (frv_cgen_macro_insn_table[0]));
const CGEN_IBASE *ib = & frv_cgen_macro_insn_table[0];
const CGEN_OPCODE *oc = & frv_cgen_macro_insn_opcode_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
memset (insns, 0, num_macros * sizeof (CGEN_INSN));
for (i = 0; i < num_macros; ++i)
{

35
opcodes/frv-opc.h
View File

@ -38,29 +38,30 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Vliw support. */
#define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8. */
#define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL
typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE];
typedef struct
{
int next_slot;
int constraint_violation;
unsigned long mach;
unsigned long elf_flags;
CGEN_ATTR_VALUE_TYPE *unit_mapping;
VLIW_COMBO *current_vliw;
CGEN_ATTR_VALUE_TYPE major[FRV_VLIW_SIZE];
const CGEN_INSN* insn[FRV_VLIW_SIZE];
int next_slot;
int constraint_violation;
unsigned long mach;
unsigned long elf_flags;
CGEN_ATTR_VALUE_TYPE * unit_mapping;
VLIW_COMBO * current_vliw;
CGEN_ATTR_VALUE_TYPE major[FRV_VLIW_SIZE];
const CGEN_INSN * insn[FRV_VLIW_SIZE];
} FRV_VLIW;
int frv_is_branch_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long));
int frv_is_float_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long));
int frv_is_media_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long));
int frv_is_branch_insn PARAMS ((const CGEN_INSN *));
int frv_is_float_insn PARAMS ((const CGEN_INSN *));
int frv_is_media_insn PARAMS ((const CGEN_INSN *));
void frv_vliw_reset PARAMS ((FRV_VLIW *, unsigned long mach, unsigned long elf_flags));
int frv_vliw_add_insn PARAMS ((FRV_VLIW *, const CGEN_INSN *));
int spr_valid PARAMS ((long));
int frv_is_branch_major (CGEN_ATTR_VALUE_TYPE, unsigned long);
int frv_is_float_major (CGEN_ATTR_VALUE_TYPE, unsigned long);
int frv_is_media_major (CGEN_ATTR_VALUE_TYPE, unsigned long);
int frv_is_branch_insn (const CGEN_INSN *);
int frv_is_float_insn (const CGEN_INSN *);
int frv_is_media_insn (const CGEN_INSN *);
void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long);
int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *);
int spr_valid (long);
/* -- */
/* Enum declaration for frv instruction types. */
typedef enum cgen_insn_type {

304
opcodes/h8300-dis.c
View File

@ -1,5 +1,5 @@
/* Disassemble h8300 instructions.
Copyright 1993, 1994, 1996, 1998, 2000, 2001, 2002, 2003, 2004
Copyright 1993, 1994, 1996, 1998, 2000, 2001, 2002, 2003, 2004, 2005
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
@ -14,7 +14,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#define DEFINE_TABLE
@ -33,23 +34,11 @@ struct h8_instruction
struct h8_instruction *h8_instructions;
static void bfd_h8_disassemble_init PARAMS ((void));
static void print_one_arg PARAMS ((disassemble_info *, bfd_vma, op_type,
int, int, int, int, const char **, int));
static unsigned int bfd_h8_disassemble PARAMS ((bfd_vma,
disassemble_info *,
int));
static void extract_immediate PARAMS ((FILE *,
op_type, int,
unsigned char *,
int *, int *,
const struct h8_opcode *));
/* Run through the opcodes and sort them into order to make them easy
to disassemble. */
static void
bfd_h8_disassemble_init ()
bfd_h8_disassemble_init (void)
{
unsigned int i;
unsigned int nopcodes;
@ -58,8 +47,7 @@ bfd_h8_disassemble_init ()
nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode);
h8_instructions = (struct h8_instruction *)
xmalloc (nopcodes * sizeof (struct h8_instruction));
h8_instructions = xmalloc (nopcodes * sizeof (struct h8_instruction));
for (p = h8_opcodes, pi = h8_instructions; p->name; p++, pi++)
{
@ -97,13 +85,13 @@ bfd_h8_disassemble_init ()
}
static void
extract_immediate (stream, looking_for, thisnib, data, cst, len, q)
FILE *stream;
op_type looking_for;
int thisnib;
unsigned char *data;
int *cst, *len;
const struct h8_opcode *q;
extract_immediate (FILE *stream,
op_type looking_for,
int thisnib,
unsigned char *data,
int *cst,
int *len,
const struct h8_opcode *q)
{
switch (looking_for & SIZE)
{
@ -114,35 +102,37 @@ extract_immediate (stream, looking_for, thisnib, data, cst, len, q)
/* DISP2 special treatment. */
if ((looking_for & MODE) == DISP)
{
if (OP_KIND (q->how) == O_MOVAB ||
OP_KIND (q->how) == O_MOVAW ||
OP_KIND (q->how) == O_MOVAL)
if (OP_KIND (q->how) == O_MOVAB
|| OP_KIND (q->how) == O_MOVAW
|| OP_KIND (q->how) == O_MOVAL)
{
/* Handling for mova insn. */
switch (q->args.nib[0] & MODE) {
case INDEXB:
default:
break;
case INDEXW:
*cst *= 2;
break;
case INDEXL:
*cst *= 4;
break;
}
switch (q->args.nib[0] & MODE)
{
case INDEXB:
default:
break;
case INDEXW:
*cst *= 2;
break;
case INDEXL:
*cst *= 4;
break;
}
}
else
{
/* Handling for non-mova insn. */
switch (OP_SIZE (q->how)) {
default: break;
case SW:
*cst *= 2;
break;
case SL:
*cst *= 4;
break;
}
switch (OP_SIZE (q->how))
{
default: break;
case SW:
*cst *= 2;
break;
case SL:
*cst *= 4;
break;
}
}
}
break;
@ -156,7 +146,7 @@ extract_immediate (stream, looking_for, thisnib, data, cst, len, q)
*cst = (data[0] << 8) + data [1];
#if 0
if ((looking_for & SIZE) == L_16)
*cst = (short) *cst; /* sign extend */
*cst = (short) *cst; /* Sign extend. */
#endif
break;
case L_32:
@ -192,31 +182,25 @@ static const char *cregnames[] =
};
static void
print_one_arg (info, addr, x, cst, cstlen, rdisp_n, rn, pregnames, len)
disassemble_info *info;
bfd_vma addr;
op_type x;
int cst, cstlen, rdisp_n, rn;
const char **pregnames;
int len;
print_one_arg (disassemble_info *info,
bfd_vma addr,
op_type x,
int cst,
int cstlen,
int rdisp_n,
int rn,
const char **pregnames,
int len)
{
void *stream = info->stream;
void * stream = info->stream;
fprintf_ftype outfn = info->fprintf_func;
if ((x & SIZE) == L_3 ||
(x & SIZE) == L_3NZ)
{
outfn (stream, "#0x%x", (unsigned) cst);
}
if ((x & SIZE) == L_3 || (x & SIZE) == L_3NZ)
outfn (stream, "#0x%x", (unsigned) cst);
else if ((x & MODE) == IMM)
{
outfn (stream, "#0x%x", (unsigned) cst);
}
else if ((x & MODE) == DBIT ||
(x & MODE) == KBIT)
{
outfn (stream, "#%d", (unsigned) cst);
}
outfn (stream, "#0x%x", (unsigned) cst);
else if ((x & MODE) == DBIT || (x & MODE) == KBIT)
outfn (stream, "#%d", (unsigned) cst);
else if ((x & MODE) == CONST_2)
outfn (stream, "#2");
else if ((x & MODE) == CONST_4)
@ -262,33 +246,26 @@ print_one_arg (info, addr, x, cst, cstlen, rdisp_n, rn, pregnames, len)
}
}
else if ((x & MODE) == POSTINC)
{
outfn (stream, "@%s+", pregnames[rn]);
}
outfn (stream, "@%s+", pregnames[rn]);
else if ((x & MODE) == POSTDEC)
{
outfn (stream, "@%s-", pregnames[rn]);
}
outfn (stream, "@%s-", pregnames[rn]);
else if ((x & MODE) == PREINC)
{
outfn (stream, "@+%s", pregnames[rn]);
}
outfn (stream, "@+%s", pregnames[rn]);
else if ((x & MODE) == PREDEC)
{
outfn (stream, "@-%s", pregnames[rn]);
}
outfn (stream, "@-%s", pregnames[rn]);
else if ((x & MODE) == IND)
{
outfn (stream, "@%s", pregnames[rn]);
}
outfn (stream, "@%s", pregnames[rn]);
else if ((x & MODE) == ABS || (x & ABSJMP))
{
outfn (stream, "@0x%x:%d", (unsigned) cst, cstlen);
}
outfn (stream, "@0x%x:%d", (unsigned) cst, cstlen);
else if ((x & MODE) == MEMIND)
{
outfn (stream, "@@%d (0x%x)", cst, cst);
}
outfn (stream, "@@%d (0x%x)", cst, cst);
else if ((x & MODE) == VECIND)
{
/* FIXME Multiplier should be 2 or 4, depending on processor mode,
@ -316,53 +293,40 @@ print_one_arg (info, addr, x, cst, cstlen, rdisp_n, rn, pregnames, len)
}
}
else if ((x & MODE) == DISP)
{
outfn (stream, "@(0x%x:%d,%s)", cst, cstlen,
pregnames[rdisp_n]);
}
outfn (stream, "@(0x%x:%d,%s)", cst, cstlen, pregnames[rdisp_n]);
else if ((x & MODE) == INDEXB)
{
/* Always take low half of reg. */
outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen,
regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]);
}
/* Always take low half of reg. */
outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen,
regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]);
else if ((x & MODE) == INDEXW)
{
/* Always take low half of reg. */
outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen,
wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]);
}
/* Always take low half of reg. */
outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen,
wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]);
else if ((x & MODE) == INDEXL)
{
outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen,
lregnames[rdisp_n]);
}
outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen, lregnames[rdisp_n]);
else if (x & CTRL)
{
outfn (stream, cregnames[rn]);
}
outfn (stream, cregnames[rn]);
else if ((x & MODE) == CCR)
{
outfn (stream, "ccr");
}
outfn (stream, "ccr");
else if ((x & MODE) == EXR)
{
outfn (stream, "exr");
}
outfn (stream, "exr");
else if ((x & MODE) == MACREG)
{
outfn (stream, "mac%c", cst ? 'l' : 'h');
}
outfn (stream, "mac%c", cst ? 'l' : 'h');
else
/* xgettext:c-format */
outfn (stream, _("Hmmmm 0x%x"), x);
}
static unsigned int
bfd_h8_disassemble (addr, info, mach)
bfd_vma addr;
disassemble_info *info;
int mach;
bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
{
/* Find the first entry in the table for this opcode. */
int regno[3] = { 0, 0, 0 };
@ -501,12 +465,12 @@ bfd_h8_disassemble (addr, info, mach)
cst[opnr] = (thisnib & 0x8) ? 2 : 1;
}
else if ((looking_for & MODE) == DISP ||
(looking_for & MODE) == ABS ||
(looking_for & MODE) == PCREL ||
(looking_for & MODE) == INDEXB ||
(looking_for & MODE) == INDEXW ||
(looking_for & MODE) == INDEXL)
else if ((looking_for & MODE) == DISP
|| (looking_for & MODE) == ABS
|| (looking_for & MODE) == PCREL
|| (looking_for & MODE) == INDEXB
|| (looking_for & MODE) == INDEXW
|| (looking_for & MODE) == INDEXL)
{
extract_immediate (stream, looking_for, thisnib,
data + len / 2, cst + opnr,
@ -515,36 +479,36 @@ bfd_h8_disassemble (addr, info, mach)
if (q->how == O (O_BRAS, SB))
cst[opnr] -= 1;
}
else if ((looking_for & MODE) == REG ||
(looking_for & MODE) == LOWREG ||
(looking_for & MODE) == IND ||
(looking_for & MODE) == PREINC ||
(looking_for & MODE) == POSTINC ||
(looking_for & MODE) == PREDEC ||
(looking_for & MODE) == POSTDEC)
else if ((looking_for & MODE) == REG
|| (looking_for & MODE) == LOWREG
|| (looking_for & MODE) == IND
|| (looking_for & MODE) == PREINC
|| (looking_for & MODE) == POSTINC
|| (looking_for & MODE) == PREDEC
|| (looking_for & MODE) == POSTDEC)
{
regno[opnr] = thisnib;
}
else if (looking_for & CTRL) /* Control Register */
else if (looking_for & CTRL) /* Control Register. */
{
thisnib &= 7;
if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) ||
((looking_for & MODE) == EXR && (thisnib != C_EXR)) ||
((looking_for & MODE) == MACH && (thisnib != C_MACH)) ||
((looking_for & MODE) == MACL && (thisnib != C_MACL)) ||
((looking_for & MODE) == VBR && (thisnib != C_VBR)) ||
((looking_for & MODE) == SBR && (thisnib != C_SBR)))
if (((looking_for & MODE) == CCR && (thisnib != C_CCR))
|| ((looking_for & MODE) == EXR && (thisnib != C_EXR))
|| ((looking_for & MODE) == MACH && (thisnib != C_MACH))
|| ((looking_for & MODE) == MACL && (thisnib != C_MACL))
|| ((looking_for & MODE) == VBR && (thisnib != C_VBR))
|| ((looking_for & MODE) == SBR && (thisnib != C_SBR)))
goto fail;
if (((looking_for & MODE) == CCR_EXR &&
(thisnib != C_CCR && thisnib != C_EXR)) ||
((looking_for & MODE) == VBR_SBR &&
(thisnib != C_VBR && thisnib != C_SBR)) ||
((looking_for & MODE) == MACREG &&
(thisnib != C_MACH && thisnib != C_MACL)))
if (((looking_for & MODE) == CCR_EXR
&& (thisnib != C_CCR && thisnib != C_EXR))
|| ((looking_for & MODE) == VBR_SBR
&& (thisnib != C_VBR && thisnib != C_SBR))
|| ((looking_for & MODE) == MACREG
&& (thisnib != C_MACH && thisnib != C_MACL)))
goto fail;
if (((looking_for & MODE) == CC_EX_VB_SB &&
(thisnib != C_CCR && thisnib != C_EXR &&
thisnib != C_VBR && thisnib != C_SBR)))
if (((looking_for & MODE) == CC_EX_VB_SB
&& (thisnib != C_CCR && thisnib != C_EXR
&& thisnib != C_VBR && thisnib != C_SBR)))
goto fail;
regno[opnr] = thisnib;
@ -559,8 +523,8 @@ bfd_h8_disassemble (addr, info, mach)
cst[opnr] = thisnib;
cstlen[opnr] = 4;
}
else if ((looking_for & SIZE) == L_16 ||
(looking_for & SIZE) == L_16U)
else if ((looking_for & SIZE) == L_16
|| (looking_for & SIZE) == L_16U)
{
cst[opnr] = (data[len / 2]) * 256 + data[(len + 2) / 2];
cstlen[opnr] = 16;
@ -622,8 +586,8 @@ bfd_h8_disassemble (addr, info, mach)
cstlen[opnr] = 8;
cst[opnr] = data[len / 2];
}
else if ((looking_for & SIZE) == L_3 ||
(looking_for & SIZE) == L_3NZ)
else if ((looking_for & SIZE) == L_3
|| (looking_for & SIZE) == L_3NZ)
{
cst[opnr] = thisnib & 0x7;
if (cst[opnr] == 0 && (looking_for & SIZE) == L_3NZ)
@ -670,10 +634,8 @@ bfd_h8_disassemble (addr, info, mach)
if (regno[0] == 0)
outfn (stream, "er%d", regno[1]);
else
{
outfn (stream, "er%d-er%d", regno[1] - regno[0],
regno[1]);
}
outfn (stream, "er%d-er%d", regno[1] - regno[0],
regno[1]);
return qi->length;
}
if (strncmp (q->name, "mova", 4) == 0)
@ -709,9 +671,9 @@ bfd_h8_disassemble (addr, info, mach)
int nargs;
/* Special case handling for the adds and subs instructions
since in H8 mode thay can only take the r0-r7 registers but
in other (higher) modes they can take the er0-er7 registers
as well. */
since in H8 mode thay can only take the r0-r7 registers
but in other (higher) modes they can take the er0-er7
registers as well. */
if (strcmp (qi->opcode->name, "adds") == 0
|| strcmp (qi->opcode->name, "subs") == 0)
{
@ -720,7 +682,7 @@ bfd_h8_disassemble (addr, info, mach)
}
for (nargs = 0;
nargs < 3 && args[nargs] != (op_type) E;
nargs < 3 && args[nargs] != (op_type) E;
nargs++)
{
int x = args[nargs];
@ -758,25 +720,19 @@ bfd_h8_disassemble (addr, info, mach)
}
int
print_insn_h8300 (addr, info)
bfd_vma addr;
disassemble_info *info;
print_insn_h8300 (bfd_vma addr, disassemble_info *info)
{
return bfd_h8_disassemble (addr, info, 0);
}
int
print_insn_h8300h (addr, info)
bfd_vma addr;
disassemble_info *info;
print_insn_h8300h (bfd_vma addr, disassemble_info *info)
{
return bfd_h8_disassemble (addr, info, 1);
}
int
print_insn_h8300s (addr, info)
bfd_vma addr;
disassemble_info *info;
print_insn_h8300s (bfd_vma addr, disassemble_info *info)
{
return bfd_h8_disassemble (addr, info, 2);
}

38
opcodes/h8500-dis.c
View File

@ -1,5 +1,6 @@
/* Disassemble h8500 instructions.
Copyright 1993, 1998, 2000, 2001, 2002, 2004 Free Software Foundation, Inc.
Copyright 1993, 1998, 2000, 2001, 2002, 2004, 2005
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -13,7 +14,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include <stdio.h>
@ -30,8 +32,6 @@
#include <setjmp.h>
static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *));
struct private
{
/* Points to first byte not fetched. */
@ -49,9 +49,7 @@ struct private
? 1 : fetch_data ((info), (addr)))
static int
fetch_data (info, addr)
struct disassemble_info *info;
bfd_byte *addr;
fetch_data (struct disassemble_info *info, bfd_byte *addr)
{
int status;
struct private *priv = (struct private *) info->private_data;
@ -74,14 +72,11 @@ fetch_data (info, addr)
static char *crname[] = { "sr", "ccr", "*", "br", "ep", "dp", "*", "tp" };
int
print_insn_h8500 (addr, info)
bfd_vma addr;
disassemble_info *info;
print_insn_h8500 (bfd_vma addr, disassemble_info *info)
{
const h8500_opcode_info *opcode;
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
struct private priv;
bfd_byte *buffer = priv.the_buffer;
@ -92,21 +87,6 @@ print_insn_h8500 (addr, info)
/* Error return. */
return -1;
if (0)
{
static int one;
if (!one)
{
one = 1;
for (opcode = h8500_table; opcode->name; opcode++)
{
if ((opcode->bytes[0].contents & 0x8) == 0)
printf ("%s\n", opcode->name);
}
}
}
/* Run down the table to find the one which matches. */
for (opcode = h8500_table; opcode->name; opcode++)
{
@ -127,9 +107,8 @@ print_insn_h8500 (addr, info)
FETCH_DATA (info, buffer + byte + 1);
if ((buffer[byte] & opcode->bytes[byte].mask)
!= (opcode->bytes[byte].contents))
{
goto next;
}
goto next;
else
{
/* Extract any info parts. */
@ -299,6 +278,7 @@ print_insn_h8500 (addr, info)
{
int i;
int nc = 0;
func (stream, "(");
for (i = 0; i < 8; i++)
{

260
opcodes/hppa-dis.c
View File

@ -1,23 +1,24 @@
/* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.
Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2003
Free Software Foundation, Inc.
Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2003,
2005 Free Software Foundation, Inc.
Contributed by the Center for Software Science at the
University of Utah (pa-gdb-bugs@cs.utah.edu).
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "dis-asm.h"
@ -27,32 +28,36 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
/* Integer register names, indexed by the numbers which appear in the
opcodes. */
static const char *const reg_names[] =
{"flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
{
"flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
"r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
"r20", "r21", "r22", "r23", "r24", "r25", "r26", "dp", "ret0", "ret1",
"sp", "r31"};
"sp", "r31"
};
/* Floating point register names, indexed by the numbers which appear in the
opcodes. */
static const char *const fp_reg_names[] =
{"fpsr", "fpe2", "fpe4", "fpe6",
{
"fpsr", "fpe2", "fpe4", "fpe6",
"fr4", "fr5", "fr6", "fr7", "fr8",
"fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
"fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
"fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"};
"fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"
};
typedef unsigned int CORE_ADDR;
/* Get at various relevent fields of an instruction word. */
#define MASK_5 0x1f
#define MASK_5 0x1f
#define MASK_10 0x3ff
#define MASK_11 0x7ff
#define MASK_14 0x3fff
#define MASK_16 0xffff
#define MASK_21 0x1fffff
/* These macros get bit fields using HP's numbering (MSB = 0) */
/* These macros get bit fields using HP's numbering (MSB = 0). */
#define GET_FIELD(X, FROM, TO) \
((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
@ -63,7 +68,8 @@ typedef unsigned int CORE_ADDR;
/* Some of these have been converted to 2-d arrays because they
consume less storage this way. If the maintenance becomes a
problem, convert them back to const 1-d pointer arrays. */
static const char *const control_reg[] = {
static const char *const control_reg[] =
{
"rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
"pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4",
"iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr",
@ -71,55 +77,69 @@ static const char *const control_reg[] = {
"tr4", "tr5", "tr6", "tr7"
};
static const char *const compare_cond_names[] = {
static const char *const compare_cond_names[] =
{
"", ",=", ",<", ",<=", ",<<", ",<<=", ",sv", ",od",
",tr", ",<>", ",>=", ",>", ",>>=", ",>>", ",nsv", ",ev"
};
static const char *const compare_cond_64_names[] = {
static const char *const compare_cond_64_names[] =
{
"", ",*=", ",*<", ",*<=", ",*<<", ",*<<=", ",*sv", ",*od",
",*tr", ",*<>", ",*>=", ",*>", ",*>>=", ",*>>", ",*nsv", ",*ev"
};
static const char *const cmpib_cond_64_names[] = {
static const char *const cmpib_cond_64_names[] =
{
",*<<", ",*=", ",*<", ",*<=", ",*>>=", ",*<>", ",*>=", ",*>"
};
static const char *const add_cond_names[] = {
static const char *const add_cond_names[] =
{
"", ",=", ",<", ",<=", ",nuv", ",znv", ",sv", ",od",
",tr", ",<>", ",>=", ",>", ",uv", ",vnz", ",nsv", ",ev"
};
static const char *const add_cond_64_names[] = {
static const char *const add_cond_64_names[] =
{
"", ",*=", ",*<", ",*<=", ",*nuv", ",*znv", ",*sv", ",*od",
",*tr", ",*<>", ",*>=", ",*>", ",*uv", ",*vnz", ",*nsv", ",*ev"
};
static const char *const wide_add_cond_names[] = {
static const char *const wide_add_cond_names[] =
{
"", ",=", ",<", ",<=", ",nuv", ",*=", ",*<", ",*<=",
",tr", ",<>", ",>=", ",>", ",uv", ",*<>", ",*>=", ",*>"
};
static const char *const logical_cond_names[] = {
static const char *const logical_cond_names[] =
{
"", ",=", ",<", ",<=", 0, 0, 0, ",od",
",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"};
static const char *const logical_cond_64_names[] = {
static const char *const logical_cond_64_names[] =
{
"", ",*=", ",*<", ",*<=", 0, 0, 0, ",*od",
",*tr", ",*<>", ",*>=", ",*>", 0, 0, 0, ",*ev"};
static const char *const unit_cond_names[] = {
static const char *const unit_cond_names[] =
{
"", ",swz", ",sbz", ",shz", ",sdc", ",swc", ",sbc", ",shc",
",tr", ",nwz", ",nbz", ",nhz", ",ndc", ",nwc", ",nbc", ",nhc"
};
static const char *const unit_cond_64_names[] = {
static const char *const unit_cond_64_names[] =
{
"", ",*swz", ",*sbz", ",*shz", ",*sdc", ",*swc", ",*sbc", ",*shc",
",*tr", ",*nwz", ",*nbz", ",*nhz", ",*ndc", ",*nwc", ",*nbc", ",*nhc"
};
static const char *const shift_cond_names[] = {
static const char *const shift_cond_names[] =
{
"", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev"
};
static const char *const shift_cond_64_names[] = {
static const char *const shift_cond_64_names[] =
{
"", ",*=", ",*<", ",*od", ",*tr", ",*<>", ",*>=", ",*ev"
};
static const char *const bb_cond_64_names[] = {
static const char *const bb_cond_64_names[] =
{
",*<", ",*>="
};
static const char *const index_compl_names[] = {"", ",m", ",s", ",sm"};
static const char *const short_ldst_compl_names[] = {"", ",ma", "", ",mb"};
static const char *const short_bytes_compl_names[] = {
static const char *const short_bytes_compl_names[] =
{
"", ",b,m", ",e", ",e,m"
};
static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"};
@ -146,51 +166,25 @@ static const char *const add_compl_names[] = { 0, "", ",l", ",tsv" };
#define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \
(GET_FIELD ((insn), 19, 19) ? 8 : 0))
static void fput_reg PARAMS ((unsigned int, disassemble_info *));
static void fput_fp_reg PARAMS ((unsigned int, disassemble_info *));
static void fput_fp_reg_r PARAMS ((unsigned int, disassemble_info *));
static void fput_creg PARAMS ((unsigned int, disassemble_info *));
static void fput_const PARAMS ((unsigned int, disassemble_info *));
static int extract_3 PARAMS ((unsigned int));
static int extract_5_load PARAMS ((unsigned int));
static int extract_5_store PARAMS ((unsigned int));
static unsigned extract_5r_store PARAMS ((unsigned int));
static unsigned extract_5R_store PARAMS ((unsigned int));
static unsigned extract_10U_store PARAMS ((unsigned int));
static unsigned extract_5Q_store PARAMS ((unsigned int));
static int extract_11 PARAMS ((unsigned int));
static int extract_14 PARAMS ((unsigned int));
static int extract_16 PARAMS ((unsigned int));
static int extract_21 PARAMS ((unsigned int));
static int extract_12 PARAMS ((unsigned int));
static int extract_17 PARAMS ((unsigned int));
static int extract_22 PARAMS ((unsigned int));
/* Utility function to print registers. Put these first, so gcc's function
inlining can do its stuff. */
#define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR)
static void
fput_reg (reg, info)
unsigned reg;
disassemble_info *info;
fput_reg (unsigned reg, disassemble_info *info)
{
(*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0");
}
static void
fput_fp_reg (reg, info)
unsigned reg;
disassemble_info *info;
fput_fp_reg (unsigned reg, disassemble_info *info)
{
(*info->fprintf_func) (info->stream, reg ? fp_reg_names[reg] : "fr0");
}
static void
fput_fp_reg_r (reg, info)
unsigned reg;
disassemble_info *info;
fput_fp_reg_r (unsigned reg, disassemble_info *info)
{
/* Special case floating point exception registers. */
if (reg < 4)
@ -201,9 +195,7 @@ fput_fp_reg_r (reg, info)
}
static void
fput_creg (reg, info)
unsigned reg;
disassemble_info *info;
fput_creg (unsigned reg, disassemble_info *info)
{
(*info->fprintf_func) (info->stream, control_reg[reg]);
}
@ -211,12 +203,10 @@ fput_creg (reg, info)
/* Print constants with sign. */
static void
fput_const (num, info)
unsigned num;
disassemble_info *info;
fput_const (unsigned num, disassemble_info *info)
{
if ((int)num < 0)
(*info->fprintf_func) (info->stream, "-%x", -(int)num);
if ((int) num < 0)
(*info->fprintf_func) (info->stream, "-%x", - (int) num);
else
(*info->fprintf_func) (info->stream, "%x", num);
}
@ -226,81 +216,80 @@ fput_const (num, info)
/* Extract a 3-bit space register number from a be, ble, mtsp or mfsp. */
static int
extract_3 (word)
unsigned word;
extract_3 (unsigned word)
{
return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17);
}
static int
extract_5_load (word)
unsigned word;
extract_5_load (unsigned word)
{
return low_sign_extend (word >> 16 & MASK_5, 5);
}
/* Extract the immediate field from a st{bhw}s instruction. */
static int
extract_5_store (word)
unsigned word;
extract_5_store (unsigned word)
{
return low_sign_extend (word & MASK_5, 5);
}
/* Extract the immediate field from a break instruction. */
static unsigned
extract_5r_store (word)
unsigned word;
extract_5r_store (unsigned word)
{
return (word & MASK_5);
}
/* Extract the immediate field from a {sr}sm instruction. */
static unsigned
extract_5R_store (word)
unsigned word;
extract_5R_store (unsigned word)
{
return (word >> 16 & MASK_5);
}
/* Extract the 10 bit immediate field from a {sr}sm instruction. */
static unsigned
extract_10U_store (word)
unsigned word;
extract_10U_store (unsigned word)
{
return (word >> 16 & MASK_10);
}
/* Extract the immediate field from a bb instruction. */
static unsigned
extract_5Q_store (word)
unsigned word;
extract_5Q_store (unsigned word)
{
return (word >> 21 & MASK_5);
}
/* Extract an 11 bit immediate field. */
static int
extract_11 (word)
unsigned word;
extract_11 (unsigned word)
{
return low_sign_extend (word & MASK_11, 11);
}
/* Extract a 14 bit immediate field. */
static int
extract_14 (word)
unsigned word;
extract_14 (unsigned word)
{
return low_sign_extend (word & MASK_14, 14);
}
/* Extract a 16 bit immediate field (PA2.0 wide only). */
static int
extract_16 (word)
unsigned word;
extract_16 (unsigned word)
{
int m15, m0, m1;
m0 = GET_BIT (word, 16);
m1 = GET_BIT (word, 17);
m15 = GET_BIT (word, 31);
@ -312,8 +301,7 @@ extract_16 (word)
/* Extract a 21 bit constant. */
static int
extract_21 (word)
unsigned word;
extract_21 (unsigned word)
{
int val;
@ -334,43 +322,39 @@ extract_21 (word)
/* Extract a 12 bit constant from branch instructions. */
static int
extract_12 (word)
unsigned word;
extract_12 (unsigned word)
{
return sign_extend (GET_FIELD (word, 19, 28) |
GET_FIELD (word, 29, 29) << 10 |
(word & 0x1) << 11, 12) << 2;
return sign_extend (GET_FIELD (word, 19, 28)
| GET_FIELD (word, 29, 29) << 10
| (word & 0x1) << 11, 12) << 2;
}
/* Extract a 17 bit constant from branch instructions, returning the
19 bit signed value. */
static int
extract_17 (word)
unsigned word;
extract_17 (unsigned word)
{
return sign_extend (GET_FIELD (word, 19, 28) |
GET_FIELD (word, 29, 29) << 10 |
GET_FIELD (word, 11, 15) << 11 |
(word & 0x1) << 16, 17) << 2;
return sign_extend (GET_FIELD (word, 19, 28)
| GET_FIELD (word, 29, 29) << 10
| GET_FIELD (word, 11, 15) << 11
| (word & 0x1) << 16, 17) << 2;
}
static int
extract_22 (word)
unsigned word;
extract_22 (unsigned word)
{
return sign_extend (GET_FIELD (word, 19, 28) |
GET_FIELD (word, 29, 29) << 10 |
GET_FIELD (word, 11, 15) << 11 |
GET_FIELD (word, 6, 10) << 16 |
(word & 0x1) << 21, 22) << 2;
return sign_extend (GET_FIELD (word, 19, 28)
| GET_FIELD (word, 29, 29) << 10
| GET_FIELD (word, 11, 15) << 11
| GET_FIELD (word, 6, 10) << 16
| (word & 0x1) << 21, 22) << 2;
}
/* Print one instruction. */
int
print_insn_hppa (memaddr, info)
bfd_vma memaddr;
disassemble_info *info;
print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
{
bfd_byte buffer[4];
unsigned int insn, i;
@ -390,9 +374,10 @@ print_insn_hppa (memaddr, info)
for (i = 0; i < NUMOPCODES; ++i)
{
const struct pa_opcode *opcode = &pa_opcodes[i];
if ((insn & opcode->mask) == opcode->match)
{
register const char *s;
const char *s;
#ifndef BFD64
if (opcode->arch == pa20w)
continue;
@ -789,10 +774,10 @@ print_insn_hppa (memaddr, info)
float_comp_names[GET_FIELD (insn, 27, 31)]);
break;
/* these four conditions are for the set of instructions
/* These four conditions are for the set of instructions
which distinguish true/false conditions by opcode
rather than by the 'f' bit (sigh): comb, comib,
addb, addib */
addb, addib. */
case 't':
fputs_filtered
(compare_cond_names[GET_FIELD (insn, 16, 18)], info);
@ -1070,8 +1055,8 @@ print_insn_hppa (memaddr, info)
GET_FIELD (insn, 23, 25));
break;
case 'F':
/* if no destination completer and not before a completer
for fcmp, need a space here */
/* If no destination completer and not before a completer
for fcmp, need a space here. */
if (s[1] == 'G' || s[1] == '?')
fputs_filtered
(float_format_names[GET_FIELD (insn, 19, 20)], info);
@ -1094,8 +1079,8 @@ print_insn_hppa (memaddr, info)
float_format_names[1]);
break;
case 'I':
/* if no destination completer and not before a completer
for fcmp, need a space here */
/* If no destination completer and not before a completer
for fcmp, need a space here. */
if (s[1] == '?')
fputs_filtered
(float_format_names[GET_FIELD (insn, 20, 20)], info);
@ -1171,6 +1156,7 @@ print_insn_hppa (memaddr, info)
const char * const * source = float_format_names;
const char * const * dest = float_format_names;
char *t = "";
if (sub == 4)
{
fputs_filtered (",UND ", info);
@ -1212,22 +1198,18 @@ print_insn_hppa (memaddr, info)
{
int cond = GET_FIELD (insn, 27, 31);
if (cond == 0)
fputs_filtered (" ", info);
else if (cond == 1)
fputs_filtered ("acc ", info);
else if (cond == 2)
fputs_filtered ("rej ", info);
else if (cond == 5)
fputs_filtered ("acc8 ", info);
else if (cond == 6)
fputs_filtered ("rej8 ", info);
else if (cond == 9)
fputs_filtered ("acc6 ", info);
else if (cond == 13)
fputs_filtered ("acc4 ", info);
else if (cond == 17)
fputs_filtered ("acc2 ", info);
switch (cond)
{
case 0: fputs_filtered (" ", info); break;
case 1: fputs_filtered ("acc ", info); break;
case 2: fputs_filtered ("rej ", info); break;
case 5: fputs_filtered ("acc8 ", info); break;
case 6: fputs_filtered ("rej8 ", info); break;
case 9: fputs_filtered ("acc6 ", info); break;
case 13: fputs_filtered ("acc4 ", info); break;
case 17: fputs_filtered ("acc2 ", info); break;
default: break;
}
break;
}
@ -1243,9 +1225,9 @@ print_insn_hppa (memaddr, info)
break;
}
}
return sizeof(insn);
return sizeof (insn);
}
}
(*info->fprintf_func) (info->stream, "#%8x", insn);
return sizeof(insn);
return sizeof (insn);
}

50
opcodes/i370-dis.c
View File

@ -1,23 +1,24 @@
/* i370-dis.c -- Disassemble Instruction 370 (ESA/390) instructions
Copyright 1994, 2000, 2003 Free Software Foundation, Inc.
Copyright 1994, 2000, 2003, 2005 Free Software Foundation, Inc.
PowerPC version written by Ian Lance Taylor, Cygnus Support
Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org>
This file is part of GDB, GAS, and the GNU binutils.
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include <stdio.h>
#include "sysdep.h"
@ -25,8 +26,7 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
#include "opcode/i370.h"
/* This file provides several disassembler functions, all of which use
the disassembler interface defined in dis-asm.h.
*/
the disassembler interface defined in dis-asm.h. */
int
print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
@ -44,7 +44,7 @@ print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
return -1;
}
/* Cast the bytes into the insn (in a host-endian indep way) */
/* Cast the bytes into the insn (in a host-endian indep way). */
insn.i[0] = (buffer[0] << 24) & 0xff000000;
insn.i[0] |= (buffer[1] << 16) & 0xff0000;
insn.i[0] |= (buffer[2] << 8) & 0xff00;
@ -70,15 +70,17 @@ print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
masked.i[0] &= 0xffff;
}
masked.i[0] &= opcode->mask.i[0];
if (masked.i[0] != opcode->opcode.i[0]) continue;
if (masked.i[0] != opcode->opcode.i[0])
continue;
if (6 == opcode->len)
{
masked.i[1] &= opcode->mask.i[1];
if (masked.i[1] != opcode->opcode.i[1]) continue;
if (masked.i[1] != opcode->opcode.i[1])
continue;
}
/* Found a match. adjust a tad */
/* Found a match. adjust a tad. */
if (2 == opcode->len)
{
insn.i[0] >>= 16;
@ -95,7 +97,8 @@ print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
if (operand->extract)
(*operand->extract) (insn, &invalid);
}
if (invalid) continue;
if (invalid)
continue;
/* The instruction is valid. */
(*info->fprintf_func) (info->stream, "%s", opcode->name);
@ -113,9 +116,7 @@ print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
if (operand->extract)
value = (*operand->extract) (insn, (int *) NULL);
else
{
value = (insn.i[0] >> operand->shift) & ((1 << operand->bits) - 1);
}
value = (insn.i[0] >> operand->shift) & ((1 << operand->bits) - 1);
/* Print the operand as directed by the flags. */
if ((operand->flags & I370_OPERAND_OPTIONAL) != 0)
@ -148,14 +149,11 @@ print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
(*info->fprintf_func) (info->stream, "%ld", value);
else
(*info->fprintf_func) (info->stream, " %ld, ", value);
}
return opcode->len;
}
/* We could not find a match. */
(*info->fprintf_func) (info->stream, ".short 0x%02x%02x", buffer[0], buffer[1]);

267
opcodes/i370-opc.c
View File

@ -1,24 +1,24 @@
/* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list
Copyright 1994, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Copyright 1994, 1999, 2000, 2001, 2003, 2005 Free Software Foundation, Inc.
PowerPC version written by Ian Lance Taylor, Cygnus Support
Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999
This file is part of GDB, GAS, and the GNU binutils.
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#include <stdio.h>
#include "sysdep.h"
@ -35,14 +35,49 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
inserting operands into instructions and vice-versa is kept in this
file. */
/* Local insertion and extraction functions. */
static i370_insn_t insert_ss_b2 (i370_insn_t, long, const char **);
static i370_insn_t insert_ss_d2 (i370_insn_t, long, const char **);
static i370_insn_t insert_rxf_r3 (i370_insn_t, long, const char **);
static long extract_ss_b2 (i370_insn_t, int *);
static long extract_ss_d2 (i370_insn_t, int *);
static long extract_rxf_r3 (i370_insn_t, int *);
/* The functions used to insert and extract complicated operands. */
static i370_insn_t
insert_ss_b2 (i370_insn_t insn, long value,
const char **errmsg ATTRIBUTE_UNUSED)
{
insn.i[1] |= (value & 0xf) << 28;
return insn;
}
static i370_insn_t
insert_ss_d2 (i370_insn_t insn, long value,
const char **errmsg ATTRIBUTE_UNUSED)
{
insn.i[1] |= (value & 0xfff) << 16;
return insn;
}
static i370_insn_t
insert_rxf_r3 (i370_insn_t insn, long value,
const char **errmsg ATTRIBUTE_UNUSED)
{
insn.i[1] |= (value & 0xf) << 28;
return insn;
}
static long
extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
{
return (insn.i[1] >>28) & 0xf;
}
static long
extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
{
return (insn.i[1] >>16) & 0xfff;
}
static long
extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
{
return (insn.i[1] >>28) & 0xf;
}
/* The operands table.
The fields are bits, shift, insert, extract, flags, name.
@ -53,8 +88,7 @@ static long extract_rxf_r3 (i370_insn_t, int *);
if absent, should take value of zero
I370_OPERAND_INDEX index register; if present, must name a register
if absent, should take value of zero
I370_OPERAND_OPTIONAL other optional operand (usuall reg?)
*/
I370_OPERAND_OPTIONAL other optional operand (usuall reg?). */
const struct i370_operand i370_operands[] =
{
@ -223,180 +257,135 @@ const struct i370_operand i370_operands[] =
#define SS_D2 (SS_B2 + 1)
#define SS_D2_MASK (0xfff)
{ 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" },
};
/* The functions used to insert and extract complicated operands. */
static i370_insn_t
insert_ss_b2 (i370_insn_t insn, long value,
const char **errmsg ATTRIBUTE_UNUSED)
{
insn.i[1] |= (value & 0xf) << 28;
return insn;
}
static i370_insn_t
insert_ss_d2 (i370_insn_t insn, long value,
const char **errmsg ATTRIBUTE_UNUSED)
{
insn.i[1] |= (value & 0xfff) << 16;
return insn;
}
static i370_insn_t
insert_rxf_r3 (i370_insn_t insn, long value,
const char **errmsg ATTRIBUTE_UNUSED)
{
insn.i[1] |= (value & 0xf) << 28;
return insn;
}
static long
extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
{
return (insn.i[1] >>28) & 0xf;
}
static long
extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
{
return (insn.i[1] >>16) & 0xfff;
}
static long
extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
{
return (insn.i[1] >>28) & 0xf;
}
/* Macros used to form opcodes. */
/* The short-instruction opcode. */
#define OPS(x) ((((unsigned short)(x)) & 0xff) << 8)
#define OPS(x) ((((unsigned short) (x)) & 0xff) << 8)
#define OPS_MASK OPS (0xff)
/* the extended instruction opcode */
#define XOPS(x) ((((unsigned short)(x)) & 0xff) << 24)
#define XOPS(x) ((((unsigned short) (x)) & 0xff) << 24)
#define XOPS_MASK XOPS (0xff)
/* the S instruction opcode */
#define SOPS(x) ((((unsigned short)(x)) & 0xffff) << 16)
#define SOPS(x) ((((unsigned short) (x)) & 0xffff) << 16)
#define SOPS_MASK SOPS (0xffff)
/* the E instruction opcode */
#define EOPS(x) (((unsigned short)(x)) & 0xffff)
#define EOPS(x) (((unsigned short) (x)) & 0xffff)
#define EOPS_MASK EOPS (0xffff)
/* the RI instruction opcode */
#define ROPS(x) (((((unsigned short)(x)) & 0xff0) << 20) | \
((((unsigned short)(x)) & 0x00f) << 16))
#define ROPS(x) (((((unsigned short) (x)) & 0xff0) << 20) | \
((((unsigned short) (x)) & 0x00f) << 16))
#define ROPS_MASK ROPS (0xfff)
/* --------------------------------------------------------- */
/* An E form instruction. */
#define E(op) (EOPS (op))
#define E_MASK E (0xffff)
/* An RR form instruction. */
#define RR(op, r1, r2) \
(OPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) | \
((((unsigned short)(r2)) & 0xf) ))
(OPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \
((((unsigned short) (r2)) & 0xf) ))
#define RR_MASK RR (0xff, 0x0, 0x0)
/* An SVC-style instruction. */
#define SVC(op, i) \
(OPS (op) | (((unsigned short)(i)) & 0xff))
(OPS (op) | (((unsigned short) (i)) & 0xff))
#define SVC_MASK SVC (0xff, 0x0)
/* An RRE form instruction. */
#define RRE(op, r1, r2) \
(SOPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) | \
((((unsigned short)(r2)) & 0xf) ))
(SOPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \
((((unsigned short) (r2)) & 0xf) ))
#define RRE_MASK RRE (0xffff, 0x0, 0x0)
/* An RRF form instruction. */
#define RRF(op, r3, r1, r2) \
(SOPS (op) | ((((unsigned short)(r3)) & 0xf) << 12) | \
((((unsigned short)(r1)) & 0xf) << 4) | \
((((unsigned short)(r2)) & 0xf) ))
(SOPS (op) | ((((unsigned short) (r3)) & 0xf) << 12) | \
((((unsigned short) (r1)) & 0xf) << 4) | \
((((unsigned short) (r2)) & 0xf) ))
#define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0)
/* An RX form instruction. */
#define RX(op, r1, x2, b2, d2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(x2)) & 0xf) << 16) | \
((((unsigned short)(b2)) & 0xf) << 12) | \
((((unsigned short)(d2)) & 0xfff)))
(XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
((((unsigned short) (x2)) & 0xf) << 16) | \
((((unsigned short) (b2)) & 0xf) << 12) | \
((((unsigned short) (d2)) & 0xfff)))
#define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0)
/* An RXE form instruction high word. */
#define RXEH(op, r1, x2, b2, d2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(x2)) & 0xf) << 16) | \
((((unsigned short)(b2)) & 0xf) << 12) | \
((((unsigned short)(d2)) & 0xfff)))
(XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
((((unsigned short) (x2)) & 0xf) << 16) | \
((((unsigned short) (b2)) & 0xf) << 12) | \
((((unsigned short) (d2)) & 0xfff)))
#define RXEH_MASK RXEH (0xff, 0, 0, 0, 0)
/* An RXE form instruction low word. */
#define RXEL(op) \
((((unsigned short)(op)) & 0xff) << 16 )
((((unsigned short) (op)) & 0xff) << 16 )
#define RXEL_MASK RXEL (0xff)
/* An RXF form instruction high word. */
#define RXFH(op, r1, x2, b2, d2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(x2)) & 0xf) << 16) | \
((((unsigned short)(b2)) & 0xf) << 12) | \
((((unsigned short)(d2)) & 0xfff)))
(XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
((((unsigned short) (x2)) & 0xf) << 16) | \
((((unsigned short) (b2)) & 0xf) << 12) | \
((((unsigned short) (d2)) & 0xfff)))
#define RXFH_MASK RXFH (0xff, 0, 0, 0, 0)
/* An RXF form instruction low word. */
#define RXFL(op, r3) \
(((((unsigned short)(r3)) & 0xf) << 28 ) | \
((((unsigned short)(op)) & 0xff) << 16 ))
(((((unsigned short) (r3)) & 0xf) << 28 ) | \
((((unsigned short) (op)) & 0xff) << 16 ))
#define RXFL_MASK RXFL (0xff, 0)
/* An RS form instruction. */
#define RS(op, r1, b3, b2, d2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(b3)) & 0xf) << 16) | \
((((unsigned short)(b2)) & 0xf) << 12) | \
((((unsigned short)(d2)) & 0xfff)))
(XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
((((unsigned short) (b3)) & 0xf) << 16) | \
((((unsigned short) (b2)) & 0xf) << 12) | \
((((unsigned short) (d2)) & 0xfff)))
#define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0)
/* An RSI form instruction. */
#define RSI(op, r1, r3, i2) \
(XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(r3)) & 0xf) << 16) | \
((((unsigned short)(i2)) & 0xffff)))
(XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
((((unsigned short) (r3)) & 0xf) << 16) | \
((((unsigned short) (i2)) & 0xffff)))
#define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0)
/* An RI form instruction. */
#define RI(op, r1, i2) \
(ROPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \
((((unsigned short)(i2)) & 0xffff)))
(ROPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
((((unsigned short) (i2)) & 0xffff)))
#define RI_MASK RI (0xfff, 0x0, 0x0)
/* An SI form instruction. */
#define SI(op, i2, b1, d1) \
(XOPS(op) | ((((unsigned short)(i2)) & 0xff) << 16) | \
((((unsigned short)(b1)) & 0xf) << 12) | \
((((unsigned short)(d1)) & 0xfff)))
(XOPS(op) | ((((unsigned short) (i2)) & 0xff) << 16) | \
((((unsigned short) (b1)) & 0xf) << 12) | \
((((unsigned short) (d1)) & 0xfff)))
#define SI_MASK SI (0xff, 0x0, 0x0, 0x0)
@ -409,26 +398,26 @@ extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
/* An SS form instruction high word. */
#define SSH(op, l, b1, d1) \
(XOPS(op) | ((((unsigned short)(l)) & 0xff) << 16) | \
((((unsigned short)(b1)) & 0xf) << 12) | \
((((unsigned short)(d1)) & 0xfff)))
(XOPS(op) | ((((unsigned short) (l)) & 0xff) << 16) | \
((((unsigned short) (b1)) & 0xf) << 12) | \
((((unsigned short) (d1)) & 0xfff)))
/* An SS form instruction low word. */
#define SSL(b2, d2) \
( ((((unsigned short)(b1)) & 0xf) << 28) | \
((((unsigned short)(d1)) & 0xfff) << 16 ))
( ((((unsigned short) (b1)) & 0xf) << 28) | \
((((unsigned short) (d1)) & 0xfff) << 16 ))
#define SS_MASK SSH (0xff, 0x0, 0x0, 0x0)
/* An SSE form instruction high word. */
#define SSEH(op, b1, d1) \
(SOPS(op) | ((((unsigned short)(b1)) & 0xf) << 12) | \
((((unsigned short)(d1)) & 0xfff)))
(SOPS(op) | ((((unsigned short) (b1)) & 0xf) << 12) | \
((((unsigned short) (d1)) & 0xfff)))
/* An SSE form instruction low word. */
#define SSEL(b2, d2) \
( ((((unsigned short)(b1)) & 0xf) << 28) | \
((((unsigned short)(d1)) & 0xfff) << 16 ))
( ((((unsigned short) (b1)) & 0xf) << 28) | \
((((unsigned short) (d1)) & 0xfff) << 16 ))
#define SSE_MASK SSEH (0xffff, 0x0, 0x0)
@ -436,8 +425,7 @@ extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
/* Smaller names for the flags so each entry in the opcodes table will
fit on a single line. These flags are set up so that e.g. IXA means
the insn is supported on the 370/XA or newer architecture.
Note that 370 or older obsolete insn's are not supported ...
*/
Note that 370 or older obsolete insn's are not supported ... */
#define IBF I370_OPCODE_ESA390_BF
#define IBS I370_OPCODE_ESA390_BS
#define ICK I370_OPCODE_ESA390_CK
@ -479,8 +467,8 @@ extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
specific instructions before more general instructions. It is also
sorted by major opcode. */
const struct i370_opcode i370_opcodes[] = {
const struct i370_opcode i370_opcodes[] =
{
/* E form instructions */
{ "pr", 2, {{E(0x0101), 0}}, {{E_MASK, 0}}, IESA, {0} },
@ -546,10 +534,10 @@ const struct i370_opcode i370_opcodes[] = {
{ "sxr", 2, {{RR(0x37,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "xr", 2, {{RR(0x17,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
/* unusual RR formats */
/* Unusual RR formats. */
{ "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} },
/* RRE form instructions */
/* RRE form instructions. */
{ "adbr", 4, {{RRE(0xb31a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "aebr", 4, {{RRE(0xb30a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "axbr", 4, {{RRE(0xb34a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
@ -654,7 +642,7 @@ const struct i370_opcode i370_opcodes[] = {
{ "thdr", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
{ "thder", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
/* RRF form instructions */
/* RRF form instructions. */
{ "cfdbr", 4, {{RRF(0xb399,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "cfdr", 4, {{RRF(0xb3b9,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
{ "cfebr", 4, {{RRF(0xb398,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
@ -673,7 +661,7 @@ const struct i370_opcode i370_opcodes[] = {
{ "tbdr", 4, {{RRF(0xb351,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} },
{ "tbedr", 4, {{RRF(0xb350,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} },
/* RX form instructions */
/* RX form instructions. */
{ "a", 4, {{RX(0x5a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ad", 4, {{RX(0x6a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ae", 4, {{RX(0x7a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
@ -726,7 +714,7 @@ const struct i370_opcode i370_opcodes[] = {
{ "sw", 4, {{RX(0x6f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "x", 4, {{RX(0x57,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
/* RXE form instructions */
/* RXE form instructions. */
{ "adb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "aeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "cdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x19)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
@ -756,13 +744,13 @@ const struct i370_opcode i370_opcodes[] = {
{ "tceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x10)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "tcxb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x12)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
/* RXF form instructions */
/* RXF form instructions. */
{ "madb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
{ "maeb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
{ "msdb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
{ "mseb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
/* RS form instructions */
/* RS form instructions. */
{ "bxh", 4, {{RS(0x86,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "bxle", 4, {{RS(0x87,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "cds", 4, {{RS(0xbb,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
@ -781,7 +769,7 @@ const struct i370_opcode i370_opcodes[] = {
{ "stm", 4, {{RS(0x90,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "trace", 4, {{RS(0x99,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
/* RS form instructions with blank R3 and optional B2 (shift left/right) */
/* RS form instructions with blank R3 and optional B2 (shift left/right). */
{ "sla", 4, {{RS(0x8b,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "slda", 4, {{RS(0x8f,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "sldl", 4, {{RS(0x8d,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
@ -791,11 +779,11 @@ const struct i370_opcode i370_opcodes[] = {
{ "srdl", 4, {{RS(0x8c,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "srl", 4, {{RS(0x88,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
/* RSI form instructions */
/* RSI form instructions. */
{ "brxh", 4, {{RSI(0x84,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
{ "brxle", 4, {{RSI(0x85,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
/* RI form instructions */
/* RI form instructions. */
{ "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
@ -806,7 +794,7 @@ const struct i370_opcode i370_opcodes[] = {
{ "tmh", 4, {{RI(0xa70,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "tml", 4, {{RI(0xa71,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
/* SI form instructions */
/* SI form instructions. */
{ "cli", 4, {{SI(0x95,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "mc", 4, {{SI(0xaf,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "mvi", 4, {{SI(0x92,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
@ -817,7 +805,7 @@ const struct i370_opcode i370_opcodes[] = {
{ "tm", 4, {{SI(0x91,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "xi", 4, {{SI(0x97,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
/* S form instructions */
/* S form instructions. */
{ "cfc", 4, {{S(0xb21a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "csch", 4, {{S(0xb230,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "hsch", 4, {{S(0xb231,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
@ -858,7 +846,7 @@ const struct i370_opcode i370_opcodes[] = {
{ "ts", 4, {{S(0x9300,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "tsch", 4, {{S(0xb235,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
/* SS form instructions */
/* SS form instructions. */
{ "ap", 6, {{SSH(0xfa,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "clc", 6, {{SSH(0xd5,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "cp", 6, {{SSH(0xf9,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
@ -885,7 +873,7 @@ const struct i370_opcode i370_opcodes[] = {
{ "xc", 6, {{SSH(0xd7,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "zap", 6, {{SSH(0xf8,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
/* SSE form instructions */
/* SSE form instructions. */
{ "lasp", 6, {{SSEH(0xe500,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} },
{ "mvcdk", 6, {{SSEH(0xe50f,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
{ "mvcsk", 6, {{SSEH(0xe50e,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
@ -899,7 +887,8 @@ const int i370_num_opcodes =
/* The macro table. This is only used by the assembler. */
const struct i370_macro i370_macros[] = {
const struct i370_macro i370_macros[] =
{
{ "b", 1, I370, "bc 15,%0" },
{ "br", 1, I370, "bcr 15,%0" },

158
opcodes/ip2k-asm.c
View File

@ -1,26 +1,27 @@
/* Assembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -49,24 +50,11 @@ static const char * parse_insn_normal
/* -- asm.c */
#define PARSE_FUNC_DECL(name) \
static const char *name (CGEN_CPU_DESC, const char **, int, long *)
#define PARSE_UFUNC_DECL(name) \
static const char *name (CGEN_CPU_DESC, const char **, int, unsigned long *)
PARSE_UFUNC_DECL (parse_fr);
PARSE_UFUNC_DECL (parse_addr16);
PARSE_UFUNC_DECL (parse_addr16_cjp);
PARSE_FUNC_DECL (parse_lit8);
PARSE_UFUNC_DECL (parse_bit3);
static const char *
parse_fr (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_fr (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
const char *old_strp;
@ -77,7 +65,7 @@ parse_fr (cd, strp, opindex, valuep)
bfd_vma tempvalue;
old_strp = *strp;
afteroffset = NULL;
afteroffset = NULL;
/* Check here to see if you're about to try parsing a w as the first arg
and return an error if you are. */
@ -155,7 +143,7 @@ parse_fr (cd, strp, opindex, valuep)
{
/* Value is ok. Fix up the first 2 bits and return. */
*valuep = 0x0100 | tempvalue;
*strp += 4; /* skip over the (DP) in *strp. */
*strp += 4; /* Skip over the (DP) in *strp. */
return errmsg;
}
else
@ -196,7 +184,7 @@ parse_fr (cd, strp, opindex, valuep)
{
/* Value is ok. Fix up the first 2 bits and return. */
*valuep = 0x0180 | tempvalue;
*strp += 4; /* skip over the (SP) in *strp. */
*strp += 4; /* Skip over the (SP) in *strp. */
return errmsg;
}
else
@ -217,11 +205,11 @@ parse_fr (cd, strp, opindex, valuep)
{
*valuep = value;
/* if a parenthesis is found, warn about invalid form. */
/* If a parenthesis is found, warn about invalid form. */
if (**strp == '(')
errmsg = _("illegal use of parentheses");
/* if a numeric value is specified, ensure that it is between
/* If a numeric value is specified, ensure that it is between
1 and 255. */
else if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
@ -233,11 +221,10 @@ parse_fr (cd, strp, opindex, valuep)
}
static const char *
parse_addr16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_addr16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -250,7 +237,7 @@ parse_addr16 (cd, strp, opindex, valuep)
code = BFD_RELOC_IP2K_LO8DATA;
else
{
/* Something is very wrong. opindex has to be one of the above. */
/* Something is very wrong. opindex has to be one of the above. */
errmsg = _("parse_addr16: invalid opindex.");
return errmsg;
}
@ -259,13 +246,14 @@ parse_addr16 (cd, strp, opindex, valuep)
& result_type, & value);
if (errmsg == NULL)
{
/* We either have a relocation or a number now. */
/* We either have a relocation or a number now. */
if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
/* We got a number back. */
/* We got a number back. */
if (code == BFD_RELOC_IP2K_HI8DATA)
value >>= 8;
else /* code = BFD_RELOC_IP2K_LOW8DATA */
else
/* code = BFD_RELOC_IP2K_LOW8DATA. */
value &= 0x00FF;
}
*valuep = value;
@ -274,13 +262,11 @@ parse_addr16 (cd, strp, opindex, valuep)
return errmsg;
}
static const char *
parse_addr16_cjp (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_addr16_cjp (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -301,7 +287,7 @@ parse_addr16_cjp (cd, strp, opindex, valuep)
if ((value & 0x1) == 0) /* If the address is even .... */
{
if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP)
*valuep = (value >> 1) & 0x1FFF; /* Should mask be 1FFF? */
*valuep = (value >> 1) & 0x1FFF; /* Should mask be 1FFF? */
else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P)
*valuep = (value >> 14) & 0x7;
}
@ -320,20 +306,18 @@ parse_addr16_cjp (cd, strp, opindex, valuep)
return errmsg;
}
static const char *
parse_lit8 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
parse_lit8 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_reloc_code_real_type code = BFD_RELOC_NONE;
bfd_vma value;
/* Parse %OP relocating operators. */
/* Parse %OP relocating operators. */
if (strncmp (*strp, "%bank", 5) == 0)
{
*strp += 5;
@ -364,7 +348,6 @@ parse_lit8 (cd, strp, opindex, valuep)
*strp += 8;
code = BFD_RELOC_IP2K_HI8INSN;
}
/* Parse %op operand. */
if (code != BFD_RELOC_NONE)
@ -382,7 +365,7 @@ parse_lit8 (cd, strp, opindex, valuep)
{
errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
/* Truncate to eight bits to accept both signed and unsigned input. */
/* Truncate to eight bits to accept both signed and unsigned input. */
if (errmsg == NULL)
*valuep &= 0xFF;
}
@ -391,11 +374,10 @@ parse_lit8 (cd, strp, opindex, valuep)
}
static const char *
parse_bit3 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_bit3 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
char mode = 0;
@ -456,11 +438,10 @@ parse_bit3 (cd, strp, opindex, valuep)
return errmsg;
}
/* -- dis.c */
const char * ip2k_cgen_parse_operand
PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
/* Main entry point for operand parsing.
@ -476,11 +457,10 @@ const char * ip2k_cgen_parse_operand
the handlers. */
const char *
ip2k_cgen_parse_operand (cd, opindex, strp, fields)
CGEN_CPU_DESC cd;
int opindex;
const char ** strp;
CGEN_FIELDS * fields;
ip2k_cgen_parse_operand (CGEN_CPU_DESC cd,
int opindex,
const char ** strp,
CGEN_FIELDS * fields)
{
const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */
@ -540,8 +520,7 @@ cgen_parse_fn * const ip2k_cgen_parse_handlers[] =
};
void
ip2k_cgen_init_asm (cd)
CGEN_CPU_DESC cd;
ip2k_cgen_init_asm (CGEN_CPU_DESC cd)
{
ip2k_cgen_init_opcode_table (cd);
ip2k_cgen_init_ibld_table (cd);
@ -924,30 +903,3 @@ ip2k_cgen_assemble_insn (CGEN_CPU_DESC cd,
return NULL;
}
}
#if 0 /* This calls back to GAS which we can't do without care. */
/* Record each member of OPVALS in the assembler's symbol table.
This lets GAS parse registers for us.
??? Interesting idea but not currently used. */
/* Record each member of OPVALS in the assembler's symbol table.
FIXME: Not currently used. */
void
ip2k_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
{
CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
const CGEN_KEYWORD_ENTRY * ke;
while ((ke = cgen_keyword_search_next (& search)) != NULL)
{
#if 0 /* Unnecessary, should be done in the search routine. */
if (! ip2k_cgen_opval_supported (ke))
continue;
#endif
cgen_asm_record_register (cd, ke->name, ke->value);
}
}
#endif /* 0 */

75
opcodes/ip2k-desc.c
View File

@ -858,27 +858,23 @@ static const CGEN_IBASE ip2k_cgen_insn_table[MAX_INSNS] =
#undef A
/* Initialize anything needed to be done once, before any cpu_open call. */
static void init_tables PARAMS ((void));
static void
init_tables ()
init_tables (void)
{
}
static const CGEN_MACH * lookup_mach_via_bfd_name
PARAMS ((const CGEN_MACH *, const char *));
static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
static void ip2k_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
static void build_hw_table (CGEN_CPU_TABLE *);
static void build_ifield_table (CGEN_CPU_TABLE *);
static void build_operand_table (CGEN_CPU_TABLE *);
static void build_insn_table (CGEN_CPU_TABLE *);
static void ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *);
/* Subroutine of ip2k_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
lookup_mach_via_bfd_name (table, name)
const CGEN_MACH *table;
const char *name;
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
{
while (table->name)
{
@ -892,8 +888,7 @@ lookup_mach_via_bfd_name (table, name)
/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */
static void
build_hw_table (cd)
CGEN_CPU_TABLE *cd;
build_hw_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -919,8 +914,7 @@ build_hw_table (cd)
/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */
static void
build_ifield_table (cd)
CGEN_CPU_TABLE *cd;
build_ifield_table (CGEN_CPU_TABLE *cd)
{
cd->ifld_table = & ip2k_cgen_ifld_table[0];
}
@ -928,8 +922,7 @@ build_ifield_table (cd)
/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */
static void
build_operand_table (cd)
CGEN_CPU_TABLE *cd;
build_operand_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -937,8 +930,7 @@ build_operand_table (cd)
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
However each entry is indexed by it's enum so there can be holes in
the table. */
const CGEN_OPERAND **selected =
(const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
cd->operand_table.init_entries = init;
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@ -961,12 +953,11 @@ build_operand_table (cd)
operand elements to be in the table [which they mightn't be]. */
static void
build_insn_table (cd)
CGEN_CPU_TABLE *cd;
build_insn_table (CGEN_CPU_TABLE *cd)
{
int i;
const CGEN_IBASE *ib = & ip2k_cgen_insn_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
for (i = 0; i < MAX_INSNS; ++i)
@ -979,8 +970,7 @@ build_insn_table (cd)
/* Subroutine of ip2k_cgen_cpu_open to rebuild the tables. */
static void
ip2k_cgen_rebuild_tables (cd)
CGEN_CPU_TABLE *cd;
ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
{
int i;
unsigned int isas = cd->isas;
@ -992,7 +982,7 @@ ip2k_cgen_rebuild_tables (cd)
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
cd->default_insn_bitsize = UNSET;
cd->base_insn_bitsize = UNSET;
cd->min_insn_bitsize = 65535; /* some ridiculously big number */
cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
cd->max_insn_bitsize = 0;
for (i = 0; i < MAX_ISAS; ++i)
if (((1 << i) & isas) != 0)
@ -1004,7 +994,7 @@ ip2k_cgen_rebuild_tables (cd)
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -1013,7 +1003,7 @@ ip2k_cgen_rebuild_tables (cd)
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -1125,12 +1115,12 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
}
va_end (ap);
/* mach unspecified means "all" */
/* Mach unspecified means "all". */
if (machs == 0)
machs = (1 << MAX_MACHS) - 1;
/* base mach is always selected */
/* Base mach is always selected. */
machs |= 1;
/* isa unspecified means "all" */
/* ISA unspecified means "all". */
if (isas == 0)
isas = (1 << MAX_ISAS) - 1;
if (endian == CGEN_ENDIAN_UNKNOWN)
@ -1163,9 +1153,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
MACH_NAME is the bfd name of the mach. */
CGEN_CPU_DESC
ip2k_cgen_cpu_open_1 (mach_name, endian)
const char *mach_name;
enum cgen_endian endian;
ip2k_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
{
return ip2k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, endian,
@ -1178,8 +1166,7 @@ ip2k_cgen_cpu_open_1 (mach_name, endian)
place as some simulator ports use this but they don't use libopcodes. */
void
ip2k_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
ip2k_cgen_cpu_close (CGEN_CPU_DESC cd)
{
unsigned int i;
const CGEN_INSN *insns;
@ -1188,23 +1175,17 @@ ip2k_cgen_cpu_close (cd)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

218
opcodes/ip2k-dis.c
View File

@ -1,27 +1,27 @@
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -56,30 +56,17 @@ static int read_insn
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
unsigned long *);
/* -- disassembler routines inserted here */
/* -- disassembler routines inserted here. */
/* -- dis.c */
#define PRINT_FUNC_DECL(name) \
static void name PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int))
PRINT_FUNC_DECL (print_fr);
PRINT_FUNC_DECL (print_dollarhex);
PRINT_FUNC_DECL (print_dollarhex8);
PRINT_FUNC_DECL (print_dollarhex_addr16h);
PRINT_FUNC_DECL (print_dollarhex_addr16l);
PRINT_FUNC_DECL (print_dollarhex_p);
PRINT_FUNC_DECL (print_dollarhex_cj);
PRINT_FUNC_DECL (print_decimal);
static void
print_fr (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_fr (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
const CGEN_KEYWORD_ENTRY *ke;
@ -87,7 +74,7 @@ print_fr (cd, dis_info, value, attrs, pc, length)
long offsettest;
long offsetvalue;
if ( value == 0 ) /* This is (IP) */
if (value == 0) /* This is (IP). */
{
(*info->fprintf_func) (info->stream, "%s", "(IP)");
return;
@ -96,46 +83,43 @@ print_fr (cd, dis_info, value, attrs, pc, length)
offsettest = value >> 7;
offsetvalue = value & 0x7F;
/* Check to see if first two bits are 10 -> (DP) */
if ( offsettest == 2 )
/* Check to see if first two bits are 10 -> (DP). */
if (offsettest == 2)
{
if ( offsetvalue == 0 )
if (offsetvalue == 0)
(*info->fprintf_func) (info->stream, "%s","(DP)");
else
(*info->fprintf_func) (info->stream, "$%x%s",offsetvalue, "(DP)");
return;
}
/* Check to see if first two bits are 11 -> (SP) */
if ( offsettest == 3 )
/* Check to see if first two bits are 11 -> (SP). */
if (offsettest == 3)
{
if ( offsetvalue == 0 )
if (offsetvalue == 0)
(*info->fprintf_func) (info->stream, "%s", "(SP)");
else
(*info->fprintf_func) (info->stream, "$%x%s", offsetvalue,"(SP)");
return;
}
/* Attempt to print as a register keyword. */
/* Attempt to print as a register keyword. */
ke = cgen_keyword_lookup_value (& ip2k_cgen_opval_register_names, value);
if (ke != NULL)
{
(*info->fprintf_func) (info->stream, "%s", ke->name);
return;
}
/* Print as an address literal. */
(*info->fprintf_func) (info->stream, "$%02x", value);
if (ke != NULL)
(*info->fprintf_func) (info->stream, "%s", ke->name);
else
/* Print as an address literal. */
(*info->fprintf_func) (info->stream, "$%02x", value);
}
static void
print_dollarhex (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -143,13 +127,12 @@ print_dollarhex (cd, dis_info, value, attrs, pc, length)
}
static void
print_dollarhex8 (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_dollarhex8 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -157,31 +140,29 @@ print_dollarhex8 (cd, dis_info, value, attrs, pc, length)
}
static void
print_dollarhex_addr16h (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_dollarhex_addr16h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
/* This is a loadh instruction. Shift the value to the left */
/* by 8 bits so that disassembled code will reassemble properly. */
/* This is a loadh instruction. Shift the value to the left
by 8 bits so that disassembled code will reassemble properly. */
value = ((value << 8) & 0xFF00);
(*info->fprintf_func) (info->stream, "$%04x", value);
}
static void
print_dollarhex_addr16l (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_dollarhex_addr16l (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -189,13 +170,12 @@ print_dollarhex_addr16l (cd, dis_info, value, attrs, pc, length)
}
static void
print_dollarhex_p (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_dollarhex_p (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -205,13 +185,12 @@ print_dollarhex_p (cd, dis_info, value, attrs, pc, length)
}
static void
print_dollarhex_cj (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_dollarhex_cj (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -219,15 +198,13 @@ print_dollarhex_cj (cd, dis_info, value, attrs, pc, length)
(*info->fprintf_func) (info->stream, "$%05x", value);
}
static void
print_decimal (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_decimal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
@ -239,8 +216,7 @@ print_decimal (cd, dis_info, value, attrs, pc, length)
/* -- */
void ip2k_cgen_print_operand
PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
void const *, bfd_vma, int));
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@ -258,16 +234,15 @@ void ip2k_cgen_print_operand
the handlers. */
void
ip2k_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
CGEN_CPU_DESC cd;
int opindex;
PTR xinfo;
CGEN_FIELDS *fields;
void const *attrs ATTRIBUTE_UNUSED;
bfd_vma pc;
int length;
ip2k_cgen_print_operand (CGEN_CPU_DESC cd,
int opindex,
void * xinfo,
CGEN_FIELDS *fields,
void const *attrs ATTRIBUTE_UNUSED,
bfd_vma pc,
int length)
{
disassemble_info *info = (disassemble_info *) xinfo;
disassemble_info *info = (disassemble_info *) xinfo;
switch (opindex)
{
@ -323,8 +298,7 @@ cgen_print_fn * const ip2k_cgen_print_handlers[] =
void
ip2k_cgen_init_dis (cd)
CGEN_CPU_DESC cd;
ip2k_cgen_init_dis (CGEN_CPU_DESC cd)
{
ip2k_cgen_init_opcode_table (cd);
ip2k_cgen_init_ibld_table (cd);
@ -376,7 +350,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
; /* Nothing to do. */
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
(*info->print_address_func) (value, info);
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@ -458,6 +432,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
unsigned long *insn_value)
{
int status = (*info->read_memory_func) (pc, buf, buflen, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
@ -562,13 +537,13 @@ print_insn (CGEN_CPU_DESC cd,
length = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
/* length < 0 -> error */
/* Length < 0 -> error. */
if (length < 0)
return length;
if (length > 0)
{
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
/* length is in bits, result is in bytes */
/* Length is in bits, result is in bytes. */
return length / 8;
}
}
@ -618,7 +593,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list {
typedef struct cpu_desc_list
{
struct cpu_desc_list *next;
int isa;
int mach;
@ -703,7 +679,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info)
if (!cd)
abort ();
/* save this away for future reference */
/* Save this away for future reference. */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;

132
opcodes/ip2k-ibld.c
View File

@ -1,25 +1,26 @@
/* Instruction building/extraction support for ip2k. -*- C -*-
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h"
#include "safe-ctype.h"
#undef min
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
#undef max
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
/* Used by the ifield rtx function. */
@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
if (length == 0)
return NULL;
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
static void
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int shift = insn_length - length;
/* Written this way to avoid undefined behaviour. */
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
{
unsigned long x;
int shift;
#if 0
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
#endif
x = cgen_get_insn_value (cd, bufp, word_length);
if (CGEN_INSN_LSB0_P)
@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
return 1;
}
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
return CGEN_INSN_BITSIZE (insn);
}
/* machine generated code added here */
/* Machine generated code added here. */
const char * ip2k_cgen_insert_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
/* Main entry point for operand insertion.
@ -559,12 +547,11 @@ const char * ip2k_cgen_insert_operand
resolved during parsing. */
const char *
ip2k_cgen_insert_operand (cd, opindex, fields, buffer, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_FIELDS * fields;
CGEN_INSN_BYTES_PTR buffer;
bfd_vma pc ATTRIBUTE_UNUSED;
ip2k_cgen_insert_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_FIELDS * fields,
CGEN_INSN_BYTES_PTR buffer,
bfd_vma pc ATTRIBUTE_UNUSED)
{
const char * errmsg = NULL;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@ -615,8 +602,7 @@ ip2k_cgen_insert_operand (cd, opindex, fields, buffer, pc)
}
int ip2k_cgen_extract_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
CGEN_FIELDS *, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
/* Main entry point for operand extraction.
The result is <= 0 for error, >0 for success.
@ -634,13 +620,12 @@ int ip2k_cgen_extract_operand
the handlers. */
int
ip2k_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_EXTRACT_INFO *ex_info;
CGEN_INSN_INT insn_value;
CGEN_FIELDS * fields;
bfd_vma pc;
ip2k_cgen_extract_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_EXTRACT_INFO *ex_info,
CGEN_INSN_INT insn_value,
CGEN_FIELDS * fields,
bfd_vma pc)
{
/* Assume success (for those operands that are nops). */
int length = 1;
@ -701,10 +686,8 @@ cgen_extract_fn * const ip2k_cgen_extract_handlers[] =
extract_insn_normal,
};
int ip2k_cgen_get_int_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
bfd_vma ip2k_cgen_get_vma_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
int ip2k_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
bfd_vma ip2k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
@ -712,10 +695,9 @@ bfd_vma ip2k_cgen_get_vma_operand
not appropriate. */
int
ip2k_cgen_get_int_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
ip2k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
int value;
@ -769,10 +751,9 @@ ip2k_cgen_get_int_operand (cd, opindex, fields)
}
bfd_vma
ip2k_cgen_get_vma_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
ip2k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
bfd_vma value;
@ -825,10 +806,8 @@ ip2k_cgen_get_vma_operand (cd, opindex, fields)
return value;
}
void ip2k_cgen_set_int_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
void ip2k_cgen_set_vma_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
void ip2k_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
void ip2k_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
@ -836,11 +815,10 @@ void ip2k_cgen_set_vma_operand
not appropriate. */
void
ip2k_cgen_set_int_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
int value;
ip2k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
int value)
{
switch (opindex)
{
@ -886,11 +864,10 @@ ip2k_cgen_set_int_operand (cd, opindex, fields, value)
}
void
ip2k_cgen_set_vma_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
bfd_vma value;
ip2k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
bfd_vma value)
{
switch (opindex)
{
@ -938,8 +915,7 @@ ip2k_cgen_set_vma_operand (cd, opindex, fields, value)
/* Function to call before using the instruction builder tables. */
void
ip2k_cgen_init_ibld_table (cd)
CGEN_CPU_DESC cd;
ip2k_cgen_init_ibld_table (CGEN_CPU_DESC cd)
{
cd->insert_handlers = & ip2k_cgen_insert_handlers[0];
cd->extract_handlers = & ip2k_cgen_extract_handlers[0];

38
opcodes/ip2k-opc.c
View File

@ -34,16 +34,15 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "safe-ctype.h"
/* A better hash function for instruction mnemonics. */
/* A better hash function for instruction mnemonics. */
unsigned int
ip2k_asm_hash (insn)
const char* insn;
ip2k_asm_hash (const char* insn)
{
unsigned int hash;
const char* m = insn;
for (hash = 0; *m && !ISSPACE(*m); m++)
hash = (hash * 23) ^ (0x1F & TOLOWER(*m));
for (hash = 0; *m && ! ISSPACE (*m); m++)
hash = (hash * 23) ^ (0x1F & TOLOWER (*m));
/* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */
@ -51,11 +50,10 @@ ip2k_asm_hash (insn)
}
/* Special check to ensure that instruction exists for given machine. */
/* Special check to ensure that instruction exists for given machine. */
int
ip2k_cgen_insn_supported (cd, insn)
CGEN_CPU_DESC cd;
const CGEN_INSN *insn;
ip2k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
{
int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
@ -63,7 +61,7 @@ ip2k_cgen_insn_supported (cd, insn)
if (machs == 0)
return 1;
return ((machs & cd->machs) != 0);
return (machs & cd->machs) != 0;
}
@ -71,10 +69,10 @@ ip2k_cgen_insn_supported (cd, insn)
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
static int asm_hash_insn_p (const CGEN_INSN *);
static unsigned int asm_hash_insn (const char *);
static int dis_hash_insn_p (const CGEN_INSN *);
static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
/* Instruction formats. */
@ -873,14 +871,10 @@ dis_hash_insn (buf, value)
return CGEN_DIS_HASH (buf, value);
}
static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
static void
set_fields_bitsize (fields, size)
CGEN_FIELDS *fields;
int size;
set_fields_bitsize (CGEN_FIELDS *fields, int size)
{
CGEN_FIELDS_BITSIZE (fields) = size;
}
@ -889,15 +883,15 @@ set_fields_bitsize (fields, size)
This plugs the opcode entries and macro instructions into the cpu table. */
void
ip2k_cgen_init_opcode_table (cd)
CGEN_CPU_DESC cd;
ip2k_cgen_init_opcode_table (CGEN_CPU_DESC cd)
{
int i;
int num_macros = (sizeof (ip2k_cgen_macro_insn_table) /
sizeof (ip2k_cgen_macro_insn_table[0]));
const CGEN_IBASE *ib = & ip2k_cgen_macro_insn_table[0];
const CGEN_OPCODE *oc = & ip2k_cgen_macro_insn_opcode_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
memset (insns, 0, num_macros * sizeof (CGEN_INSN));
for (i = 0; i < num_macros; ++i)
{

10
opcodes/ip2k-opc.h
View File

@ -36,14 +36,14 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Override disassembly hashing - there are variable bits in the top
byte of these instructions. */
#define CGEN_DIS_HASH_SIZE 8
#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
#define CGEN_DIS_HASH(buf, value) \
(((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
#define CGEN_ASM_HASH_SIZE 127
#define CGEN_ASM_HASH(insn) ip2k_asm_hash(insn)
#define CGEN_ASM_HASH(insn) ip2k_asm_hash (insn)
extern unsigned int ip2k_asm_hash PARAMS ((const char *insn));
extern int ip2k_cgen_insn_supported
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *));
extern unsigned int ip2k_asm_hash (const char *);
extern int ip2k_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
/* -- opc.c */
/* Enum declaration for ip2k instruction types. */

191
opcodes/iq2000-asm.c
View File

@ -1,26 +1,27 @@
/* Assembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -51,30 +52,24 @@ static const char * parse_insn_normal
#include "safe-ctype.h"
static int iq2000_cgen_isa_register PARAMS ((const char **));
static const char * parse_jtargq10 PARAMS ((CGEN_CPU_DESC, const char **, int, int, enum cgen_parse_operand_result *, bfd_vma *));
static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_imm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_mlo16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
/* Special check to ensure that instruction exists for given machine. */
/* Special check to ensure that instruction exists for given machine */
int
iq2000_cgen_insn_supported (cd, insn)
CGEN_CPU_DESC cd;
const CGEN_INSN *insn;
iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
{
int machs = cd->machs;
return ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0);
return (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0;
}
static int iq2000_cgen_isa_register (strp)
const char **strp;
static int
iq2000_cgen_isa_register (const char **strp)
{
int len;
int ch1, ch2;
if (**strp == 'r' || **strp == 'R')
{
len = strlen (*strp);
@ -94,7 +89,9 @@ static int iq2000_cgen_isa_register (strp)
return 1;
}
}
if (**strp == '%' && TOLOWER((*strp)[1]) != 'l' && TOLOWER((*strp)[1]) != 'h')
if (**strp == '%'
&& TOLOWER ((*strp)[1]) != 'l'
&& TOLOWER ((*strp)[1]) != 'h')
return 1;
return 0;
}
@ -102,11 +99,10 @@ static int iq2000_cgen_isa_register (strp)
/* Handle negated literal. */
static const char *
parse_mimm (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_mimm (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
@ -134,11 +130,10 @@ parse_mimm (cd, strp, opindex, valuep)
/* Handle signed/unsigned literal. */
static const char *
parse_imm (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_imm (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
@ -152,6 +147,7 @@ parse_imm (cd, strp, opindex, valuep)
if (errmsg == NULL)
{
long x = value & 0xFFFF0000;
if (x != 0 && x != (long) 0xFFFF0000)
errmsg = _("immediate value out of range");
else
@ -164,23 +160,23 @@ parse_imm (cd, strp, opindex, valuep)
/* Handle iq10 21-bit jmp offset. */
static const char *
parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
int reloc ATTRIBUTE_UNUSED;
enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED;
bfd_vma *valuep;
parse_jtargq10 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
int reloc ATTRIBUTE_UNUSED,
enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED,
bfd_vma *valuep)
{
const char *errmsg;
bfd_vma value;
enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21,
&result_type, &value);
& result_type, & value);
if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
/* Check value is within 23-bits (remembering that 2-bit shift right will occur). */
/* Check value is within 23-bits
(remembering that 2-bit shift right will occur). */
if (value > 0x7fffff)
return _("21-bit offset out of range");
}
@ -191,11 +187,10 @@ parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep)
/* Handle high(). */
static const char *
parse_hi16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_hi16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
if (strncasecmp (*strp, "%hi(", 4) == 0)
{
@ -205,17 +200,17 @@ parse_hi16 (cd, strp, opindex, valuep)
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
/* if value has top-bit of %lo on, then it will
/* If value has top-bit of %lo on, then it will
sign-propagate and so we compensate by adding
1 to the resultant %hi value */
1 to the resultant %hi value. */
if (value & 0x8000)
value += 0x10000;
value >>= 16;
@ -225,8 +220,8 @@ parse_hi16 (cd, strp, opindex, valuep)
return errmsg;
}
/* we add %uhi in case a user just wants the high 16-bits or is using
an insn like ori for %lo which does not sign-propagate */
/* We add %uhi in case a user just wants the high 16-bits or is using
an insn like ori for %lo which does not sign-propagate. */
if (strncasecmp (*strp, "%uhi(", 5) == 0)
{
enum cgen_parse_operand_result result_type;
@ -235,16 +230,15 @@ parse_hi16 (cd, strp, opindex, valuep)
*strp += 5;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
{
value >>= 16;
}
value >>= 16;
*valuep = value;
return errmsg;
@ -258,11 +252,10 @@ parse_hi16 (cd, strp, opindex, valuep)
handles the case where %lo() isn't present. */
static const char *
parse_lo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_lo16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
if (strncasecmp (*strp, "%lo(", 4) == 0)
{
@ -272,9 +265,9 @@ parse_lo16 (cd, strp, opindex, valuep)
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@ -291,11 +284,10 @@ parse_lo16 (cd, strp, opindex, valuep)
handles the case where %lo() isn't present. */
static const char *
parse_mlo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_mlo16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
long *valuep)
{
if (strncasecmp (*strp, "%lo(", 4) == 0)
{
@ -305,9 +297,9 @@ parse_mlo16 (cd, strp, opindex, valuep)
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@ -322,7 +314,7 @@ parse_mlo16 (cd, strp, opindex, valuep)
/* -- */
const char * iq2000_cgen_parse_operand
PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
/* Main entry point for operand parsing.
@ -338,11 +330,10 @@ const char * iq2000_cgen_parse_operand
the handlers. */
const char *
iq2000_cgen_parse_operand (cd, opindex, strp, fields)
CGEN_CPU_DESC cd;
int opindex;
const char ** strp;
CGEN_FIELDS * fields;
iq2000_cgen_parse_operand (CGEN_CPU_DESC cd,
int opindex,
const char ** strp,
CGEN_FIELDS * fields)
{
const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */
@ -475,8 +466,7 @@ cgen_parse_fn * const iq2000_cgen_parse_handlers[] =
};
void
iq2000_cgen_init_asm (cd)
CGEN_CPU_DESC cd;
iq2000_cgen_init_asm (CGEN_CPU_DESC cd)
{
iq2000_cgen_init_opcode_table (cd);
iq2000_cgen_init_ibld_table (cd);
@ -859,30 +849,3 @@ iq2000_cgen_assemble_insn (CGEN_CPU_DESC cd,
return NULL;
}
}
#if 0 /* This calls back to GAS which we can't do without care. */
/* Record each member of OPVALS in the assembler's symbol table.
This lets GAS parse registers for us.
??? Interesting idea but not currently used. */
/* Record each member of OPVALS in the assembler's symbol table.
FIXME: Not currently used. */
void
iq2000_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
{
CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
const CGEN_KEYWORD_ENTRY * ke;
while ((ke = cgen_keyword_search_next (& search)) != NULL)
{
#if 0 /* Unnecessary, should be done in the search routine. */
if (! iq2000_cgen_opval_supported (ke))
continue;
#endif
cgen_asm_record_register (cd, ke->name, ke->value);
}
}
#endif /* 0 */

75
opcodes/iq2000-desc.c
View File

@ -1863,27 +1863,23 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
#undef A
/* Initialize anything needed to be done once, before any cpu_open call. */
static void init_tables PARAMS ((void));
static void
init_tables ()
init_tables (void)
{
}
static const CGEN_MACH * lookup_mach_via_bfd_name
PARAMS ((const CGEN_MACH *, const char *));
static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
static void iq2000_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
static void build_hw_table (CGEN_CPU_TABLE *);
static void build_ifield_table (CGEN_CPU_TABLE *);
static void build_operand_table (CGEN_CPU_TABLE *);
static void build_insn_table (CGEN_CPU_TABLE *);
static void iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *);
/* Subroutine of iq2000_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
lookup_mach_via_bfd_name (table, name)
const CGEN_MACH *table;
const char *name;
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
{
while (table->name)
{
@ -1897,8 +1893,7 @@ lookup_mach_via_bfd_name (table, name)
/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */
static void
build_hw_table (cd)
CGEN_CPU_TABLE *cd;
build_hw_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -1924,8 +1919,7 @@ build_hw_table (cd)
/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */
static void
build_ifield_table (cd)
CGEN_CPU_TABLE *cd;
build_ifield_table (CGEN_CPU_TABLE *cd)
{
cd->ifld_table = & iq2000_cgen_ifld_table[0];
}
@ -1933,8 +1927,7 @@ build_ifield_table (cd)
/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */
static void
build_operand_table (cd)
CGEN_CPU_TABLE *cd;
build_operand_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -1942,8 +1935,7 @@ build_operand_table (cd)
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
However each entry is indexed by it's enum so there can be holes in
the table. */
const CGEN_OPERAND **selected =
(const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
cd->operand_table.init_entries = init;
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@ -1966,12 +1958,11 @@ build_operand_table (cd)
operand elements to be in the table [which they mightn't be]. */
static void
build_insn_table (cd)
CGEN_CPU_TABLE *cd;
build_insn_table (CGEN_CPU_TABLE *cd)
{
int i;
const CGEN_IBASE *ib = & iq2000_cgen_insn_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
for (i = 0; i < MAX_INSNS; ++i)
@ -1984,8 +1975,7 @@ build_insn_table (cd)
/* Subroutine of iq2000_cgen_cpu_open to rebuild the tables. */
static void
iq2000_cgen_rebuild_tables (cd)
CGEN_CPU_TABLE *cd;
iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
{
int i;
unsigned int isas = cd->isas;
@ -1997,7 +1987,7 @@ iq2000_cgen_rebuild_tables (cd)
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
cd->default_insn_bitsize = UNSET;
cd->base_insn_bitsize = UNSET;
cd->min_insn_bitsize = 65535; /* some ridiculously big number */
cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
cd->max_insn_bitsize = 0;
for (i = 0; i < MAX_ISAS; ++i)
if (((1 << i) & isas) != 0)
@ -2009,7 +1999,7 @@ iq2000_cgen_rebuild_tables (cd)
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -2018,7 +2008,7 @@ iq2000_cgen_rebuild_tables (cd)
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -2130,12 +2120,12 @@ iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
}
va_end (ap);
/* mach unspecified means "all" */
/* Mach unspecified means "all". */
if (machs == 0)
machs = (1 << MAX_MACHS) - 1;
/* base mach is always selected */
/* Base mach is always selected. */
machs |= 1;
/* isa unspecified means "all" */
/* ISA unspecified means "all". */
if (isas == 0)
isas = (1 << MAX_ISAS) - 1;
if (endian == CGEN_ENDIAN_UNKNOWN)
@ -2168,9 +2158,7 @@ iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
MACH_NAME is the bfd name of the mach. */
CGEN_CPU_DESC
iq2000_cgen_cpu_open_1 (mach_name, endian)
const char *mach_name;
enum cgen_endian endian;
iq2000_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
{
return iq2000_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, endian,
@ -2183,8 +2171,7 @@ iq2000_cgen_cpu_open_1 (mach_name, endian)
place as some simulator ports use this but they don't use libopcodes. */
void
iq2000_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
iq2000_cgen_cpu_close (CGEN_CPU_DESC cd)
{
unsigned int i;
const CGEN_INSN *insns;
@ -2193,23 +2180,17 @@ iq2000_cgen_cpu_close (cd)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

69
opcodes/iq2000-dis.c
View File

@ -1,27 +1,27 @@
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -56,12 +56,11 @@ static int read_insn
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
unsigned long *);
/* -- disassembler routines inserted here */
/* -- disassembler routines inserted here. */
void iq2000_cgen_print_operand
PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
void const *, bfd_vma, int));
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@ -79,16 +78,15 @@ void iq2000_cgen_print_operand
the handlers. */
void
iq2000_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
CGEN_CPU_DESC cd;
int opindex;
PTR xinfo;
CGEN_FIELDS *fields;
void const *attrs ATTRIBUTE_UNUSED;
bfd_vma pc;
int length;
iq2000_cgen_print_operand (CGEN_CPU_DESC cd,
int opindex,
void * xinfo,
CGEN_FIELDS *fields,
void const *attrs ATTRIBUTE_UNUSED,
bfd_vma pc,
int length)
{
disassemble_info *info = (disassemble_info *) xinfo;
disassemble_info *info = (disassemble_info *) xinfo;
switch (opindex)
{
@ -201,8 +199,7 @@ cgen_print_fn * const iq2000_cgen_print_handlers[] =
void
iq2000_cgen_init_dis (cd)
CGEN_CPU_DESC cd;
iq2000_cgen_init_dis (CGEN_CPU_DESC cd)
{
iq2000_cgen_init_opcode_table (cd);
iq2000_cgen_init_ibld_table (cd);
@ -254,7 +251,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
; /* Nothing to do. */
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
(*info->print_address_func) (value, info);
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@ -336,6 +333,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
unsigned long *insn_value)
{
int status = (*info->read_memory_func) (pc, buf, buflen, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
@ -440,13 +438,13 @@ print_insn (CGEN_CPU_DESC cd,
length = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
/* length < 0 -> error */
/* Length < 0 -> error. */
if (length < 0)
return length;
if (length > 0)
{
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
/* length is in bits, result is in bytes */
/* Length is in bits, result is in bytes. */
return length / 8;
}
}
@ -496,7 +494,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list {
typedef struct cpu_desc_list
{
struct cpu_desc_list *next;
int isa;
int mach;
@ -581,7 +580,7 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
if (!cd)
abort ();
/* save this away for future reference */
/* Save this away for future reference. */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;

132
opcodes/iq2000-ibld.c
View File

@ -1,25 +1,26 @@
/* Instruction building/extraction support for iq2000. -*- C -*-
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h"
#include "safe-ctype.h"
#undef min
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
#undef max
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
/* Used by the ifield rtx function. */
@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
if (length == 0)
return NULL;
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
static void
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int shift = insn_length - length;
/* Written this way to avoid undefined behaviour. */
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
{
unsigned long x;
int shift;
#if 0
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
#endif
x = cgen_get_insn_value (cd, bufp, word_length);
if (CGEN_INSN_LSB0_P)
@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
return 1;
}
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
return CGEN_INSN_BITSIZE (insn);
}
/* machine generated code added here */
/* Machine generated code added here. */
const char * iq2000_cgen_insert_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
/* Main entry point for operand insertion.
@ -559,12 +547,11 @@ const char * iq2000_cgen_insert_operand
resolved during parsing. */
const char *
iq2000_cgen_insert_operand (cd, opindex, fields, buffer, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_FIELDS * fields;
CGEN_INSN_BYTES_PTR buffer;
bfd_vma pc ATTRIBUTE_UNUSED;
iq2000_cgen_insert_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_FIELDS * fields,
CGEN_INSN_BYTES_PTR buffer,
bfd_vma pc ATTRIBUTE_UNUSED)
{
const char * errmsg = NULL;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@ -721,8 +708,7 @@ iq2000_cgen_insert_operand (cd, opindex, fields, buffer, pc)
}
int iq2000_cgen_extract_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
CGEN_FIELDS *, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
/* Main entry point for operand extraction.
The result is <= 0 for error, >0 for success.
@ -740,13 +726,12 @@ int iq2000_cgen_extract_operand
the handlers. */
int
iq2000_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_EXTRACT_INFO *ex_info;
CGEN_INSN_INT insn_value;
CGEN_FIELDS * fields;
bfd_vma pc;
iq2000_cgen_extract_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_EXTRACT_INFO *ex_info,
CGEN_INSN_INT insn_value,
CGEN_FIELDS * fields,
bfd_vma pc)
{
/* Assume success (for those operands that are nops). */
int length = 1;
@ -907,10 +892,8 @@ cgen_extract_fn * const iq2000_cgen_extract_handlers[] =
extract_insn_normal,
};
int iq2000_cgen_get_int_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
bfd_vma iq2000_cgen_get_vma_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
int iq2000_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
bfd_vma iq2000_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
@ -918,10 +901,9 @@ bfd_vma iq2000_cgen_get_vma_operand
not appropriate. */
int
iq2000_cgen_get_int_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
iq2000_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
int value;
@ -1032,10 +1014,9 @@ iq2000_cgen_get_int_operand (cd, opindex, fields)
}
bfd_vma
iq2000_cgen_get_vma_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
iq2000_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
bfd_vma value;
@ -1145,10 +1126,8 @@ iq2000_cgen_get_vma_operand (cd, opindex, fields)
return value;
}
void iq2000_cgen_set_int_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
void iq2000_cgen_set_vma_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
void iq2000_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
void iq2000_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
@ -1156,11 +1135,10 @@ void iq2000_cgen_set_vma_operand
not appropriate. */
void
iq2000_cgen_set_int_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
int value;
iq2000_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
int value)
{
switch (opindex)
{
@ -1267,11 +1245,10 @@ iq2000_cgen_set_int_operand (cd, opindex, fields, value)
}
void
iq2000_cgen_set_vma_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
bfd_vma value;
iq2000_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
bfd_vma value)
{
switch (opindex)
{
@ -1380,8 +1357,7 @@ iq2000_cgen_set_vma_operand (cd, opindex, fields, value)
/* Function to call before using the instruction builder tables. */
void
iq2000_cgen_init_ibld_table (cd)
CGEN_CPU_DESC cd;
iq2000_cgen_init_ibld_table (CGEN_CPU_DESC cd)
{
cd->insert_handlers = & iq2000_cgen_insert_handlers[0];
cd->extract_handlers = & iq2000_cgen_extract_handlers[0];

20
opcodes/iq2000-opc.c
View File

@ -33,10 +33,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
static int asm_hash_insn_p (const CGEN_INSN *);
static unsigned int asm_hash_insn (const char *);
static int dis_hash_insn_p (const CGEN_INSN *);
static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
/* Instruction formats. */
@ -3425,14 +3425,10 @@ dis_hash_insn (buf, value)
return CGEN_DIS_HASH (buf, value);
}
static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
static void
set_fields_bitsize (fields, size)
CGEN_FIELDS *fields;
int size;
set_fields_bitsize (CGEN_FIELDS *fields, int size)
{
CGEN_FIELDS_BITSIZE (fields) = size;
}
@ -3441,15 +3437,15 @@ set_fields_bitsize (fields, size)
This plugs the opcode entries and macro instructions into the cpu table. */
void
iq2000_cgen_init_opcode_table (cd)
CGEN_CPU_DESC cd;
iq2000_cgen_init_opcode_table (CGEN_CPU_DESC cd)
{
int i;
int num_macros = (sizeof (iq2000_cgen_macro_insn_table) /
sizeof (iq2000_cgen_macro_insn_table[0]));
const CGEN_IBASE *ib = & iq2000_cgen_macro_insn_table[0];
const CGEN_OPCODE *oc = & iq2000_cgen_macro_insn_opcode_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
memset (insns, 0, num_macros * sizeof (CGEN_INSN));
for (i = 0; i < num_macros; ++i)
{

2
opcodes/iq2000-opc.h
View File

@ -39,7 +39,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
instructions have same mnemonics but different functionality. */
#define CGEN_VALIDATE_INSN_SUPPORTED
extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn);
extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
/* -- asm.c */
/* Enum declaration for iq2000 instruction types. */

300
opcodes/m10200-dis.c
View File

@ -1,20 +1,20 @@
/* Disassemble MN10200 instructions.
Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 2000, 2005 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include <stdio.h>
@ -23,14 +23,141 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#include "dis-asm.h"
#include "opintl.h"
static void disassemble PARAMS ((bfd_vma, struct disassemble_info *,
unsigned long insn, unsigned long,
unsigned int));
static void
disassemble (bfd_vma memaddr,
struct disassemble_info *info,
unsigned long insn,
unsigned long extension,
unsigned int size)
{
struct mn10200_opcode *op = (struct mn10200_opcode *)mn10200_opcodes;
const struct mn10200_operand *operand;
int match = 0;
/* Find the opcode. */
while (op->name)
{
int mysize, extra_shift;
if (op->format == FMT_1)
mysize = 1;
else if (op->format == FMT_2
|| op->format == FMT_4)
mysize = 2;
else if (op->format == FMT_3
|| op->format == FMT_5)
mysize = 3;
else if (op->format == FMT_6)
mysize = 4;
else if (op->format == FMT_7)
mysize = 5;
else
abort ();
if (op->format == FMT_2 || op->format == FMT_5)
extra_shift = 8;
else if (op->format == FMT_3
|| op->format == FMT_6
|| op->format == FMT_7)
extra_shift = 16;
else
extra_shift = 0;
if ((op->mask & insn) == op->opcode
&& size == (unsigned int) mysize)
{
const unsigned char *opindex_ptr;
unsigned int nocomma;
int paren = 0;
match = 1;
(*info->fprintf_func) (info->stream, "%s\t", op->name);
/* Now print the operands. */
for (opindex_ptr = op->operands, nocomma = 1;
*opindex_ptr != 0;
opindex_ptr++)
{
unsigned long value;
operand = &mn10200_operands[*opindex_ptr];
if ((operand->flags & MN10200_OPERAND_EXTENDED) != 0)
{
value = (insn & 0xffff) << 8;
value |= extension;
}
else
{
value = ((insn >> (operand->shift))
& ((1L << operand->bits) - 1L));
}
if ((operand->flags & MN10200_OPERAND_SIGNED) != 0)
value = ((long)(value << (32 - operand->bits))
>> (32 - operand->bits));
if (!nocomma
&& (!paren
|| ((operand->flags & MN10200_OPERAND_PAREN) == 0)))
(*info->fprintf_func) (info->stream, ",");
nocomma = 0;
if ((operand->flags & MN10200_OPERAND_DREG) != 0)
{
value = ((insn >> (operand->shift + extra_shift))
& ((1 << operand->bits) - 1));
(*info->fprintf_func) (info->stream, "d%d", value);
}
else if ((operand->flags & MN10200_OPERAND_AREG) != 0)
{
value = ((insn >> (operand->shift + extra_shift))
& ((1 << operand->bits) - 1));
(*info->fprintf_func) (info->stream, "a%d", value);
}
else if ((operand->flags & MN10200_OPERAND_PSW) != 0)
(*info->fprintf_func) (info->stream, "psw");
else if ((operand->flags & MN10200_OPERAND_MDR) != 0)
(*info->fprintf_func) (info->stream, "mdr");
else if ((operand->flags & MN10200_OPERAND_PAREN) != 0)
{
if (paren)
(*info->fprintf_func) (info->stream, ")");
else
{
(*info->fprintf_func) (info->stream, "(");
nocomma = 1;
}
paren = !paren;
}
else if ((operand->flags & MN10200_OPERAND_PCREL) != 0)
(*info->print_address_func)
((value + memaddr + mysize) & 0xffffff, info);
else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0)
(*info->print_address_func) (value, info);
else
(*info->fprintf_func) (info->stream, "%ld", value);
}
/* All done. */
break;
}
op++;
}
if (!match)
(*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn);
}
int
print_insn_mn10200 (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
print_insn_mn10200 (bfd_vma memaddr, struct disassemble_info *info)
{
int status;
bfd_byte buffer[4];
@ -204,138 +331,3 @@ print_insn_mn10200 (memaddr, info)
return consume;
}
static void
disassemble (memaddr, info, insn, extension, size)
bfd_vma memaddr;
struct disassemble_info *info;
unsigned long insn;
unsigned long extension;
unsigned int size;
{
struct mn10200_opcode *op = (struct mn10200_opcode *)mn10200_opcodes;
const struct mn10200_operand *operand;
int match = 0;
/* Find the opcode. */
while (op->name)
{
int mysize, extra_shift;
if (op->format == FMT_1)
mysize = 1;
else if (op->format == FMT_2
|| op->format == FMT_4)
mysize = 2;
else if (op->format == FMT_3
|| op->format == FMT_5)
mysize = 3;
else if (op->format == FMT_6)
mysize = 4;
else if (op->format == FMT_7)
mysize = 5;
else
abort ();
if (op->format == FMT_2 || op->format == FMT_5)
extra_shift = 8;
else if (op->format == FMT_3
|| op->format == FMT_6
|| op->format == FMT_7)
extra_shift = 16;
else
extra_shift = 0;
if ((op->mask & insn) == op->opcode
&& size == (unsigned int) mysize)
{
const unsigned char *opindex_ptr;
unsigned int nocomma;
int paren = 0;
match = 1;
(*info->fprintf_func) (info->stream, "%s\t", op->name);
/* Now print the operands. */
for (opindex_ptr = op->operands, nocomma = 1;
*opindex_ptr != 0;
opindex_ptr++)
{
unsigned long value;
operand = &mn10200_operands[*opindex_ptr];
if ((operand->flags & MN10200_OPERAND_EXTENDED) != 0)
{
value = (insn & 0xffff) << 8;
value |= extension;
}
else
{
value = ((insn >> (operand->shift))
& ((1L << operand->bits) - 1L));
}
if ((operand->flags & MN10200_OPERAND_SIGNED) != 0)
value = ((long)(value << (32 - operand->bits))
>> (32 - operand->bits));
if (!nocomma
&& (!paren
|| ((operand->flags & MN10200_OPERAND_PAREN) == 0)))
(*info->fprintf_func) (info->stream, ",");
nocomma = 0;
if ((operand->flags & MN10200_OPERAND_DREG) != 0)
{
value = ((insn >> (operand->shift + extra_shift))
& ((1 << operand->bits) - 1));
(*info->fprintf_func) (info->stream, "d%d", value);
}
else if ((operand->flags & MN10200_OPERAND_AREG) != 0)
{
value = ((insn >> (operand->shift + extra_shift))
& ((1 << operand->bits) - 1));
(*info->fprintf_func) (info->stream, "a%d", value);
}
else if ((operand->flags & MN10200_OPERAND_PSW) != 0)
(*info->fprintf_func) (info->stream, "psw");
else if ((operand->flags & MN10200_OPERAND_MDR) != 0)
(*info->fprintf_func) (info->stream, "mdr");
else if ((operand->flags & MN10200_OPERAND_PAREN) != 0)
{
if (paren)
(*info->fprintf_func) (info->stream, ")");
else
{
(*info->fprintf_func) (info->stream, "(");
nocomma = 1;
}
paren = !paren;
}
else if ((operand->flags & MN10200_OPERAND_PCREL) != 0)
(*info->print_address_func) ((value + memaddr + mysize) & 0xffffff, info);
else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0)
(*info->print_address_func) (value, info);
else
(*info->fprintf_func) (info->stream, "%ld", value);
}
/* All done. */
break;
}
op++;
}
if (!match)
{
(*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn);
}
}

455
opcodes/m10300-dis.c
View File

@ -1,21 +1,21 @@
/* Disassemble MN10300 instructions.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2005
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include <stdio.h>
@ -24,202 +24,17 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#include "dis-asm.h"
#include "opintl.h"
static void disassemble PARAMS ((bfd_vma, struct disassemble_info *,
unsigned long insn, unsigned int));
#define HAVE_AM33_2 (info->mach == AM33_2)
#define HAVE_AM33 (info->mach == AM33 || HAVE_AM33_2)
#define HAVE_AM30 (info->mach == AM30)
int
print_insn_mn10300 (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
int status;
bfd_byte buffer[4];
unsigned long insn;
unsigned int consume;
/* First figure out how big the opcode is. */
status = (*info->read_memory_func) (memaddr, buffer, 1, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = *(unsigned char *) buffer;
/* These are one byte insns. */
if ((insn & 0xf3) == 0x00
|| (insn & 0xf0) == 0x10
|| (insn & 0xfc) == 0x3c
|| (insn & 0xf3) == 0x41
|| (insn & 0xf3) == 0x40
|| (insn & 0xfc) == 0x50
|| (insn & 0xfc) == 0x54
|| (insn & 0xf0) == 0x60
|| (insn & 0xf0) == 0x70
|| ((insn & 0xf0) == 0x80
&& (insn & 0x0c) >> 2 != (insn & 0x03))
|| ((insn & 0xf0) == 0x90
&& (insn & 0x0c) >> 2 != (insn & 0x03))
|| ((insn & 0xf0) == 0xa0
&& (insn & 0x0c) >> 2 != (insn & 0x03))
|| ((insn & 0xf0) == 0xb0
&& (insn & 0x0c) >> 2 != (insn & 0x03))
|| (insn & 0xff) == 0xcb
|| (insn & 0xfc) == 0xd0
|| (insn & 0xfc) == 0xd4
|| (insn & 0xfc) == 0xd8
|| (insn & 0xf0) == 0xe0
|| (insn & 0xff) == 0xff)
{
consume = 1;
}
/* These are two byte insns. */
else if ((insn & 0xf0) == 0x80
|| (insn & 0xf0) == 0x90
|| (insn & 0xf0) == 0xa0
|| (insn & 0xf0) == 0xb0
|| (insn & 0xfc) == 0x20
|| (insn & 0xfc) == 0x28
|| (insn & 0xf3) == 0x43
|| (insn & 0xf3) == 0x42
|| (insn & 0xfc) == 0x58
|| (insn & 0xfc) == 0x5c
|| ((insn & 0xf0) == 0xc0
&& (insn & 0xff) != 0xcb
&& (insn & 0xff) != 0xcc
&& (insn & 0xff) != 0xcd)
|| (insn & 0xff) == 0xf0
|| (insn & 0xff) == 0xf1
|| (insn & 0xff) == 0xf2
|| (insn & 0xff) == 0xf3
|| (insn & 0xff) == 0xf4
|| (insn & 0xff) == 0xf5
|| (insn & 0xff) == 0xf6)
{
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb16 (buffer);
consume = 2;
}
/* These are three byte insns. */
else if ((insn & 0xff) == 0xf8
|| (insn & 0xff) == 0xcc
|| (insn & 0xff) == 0xf9
|| (insn & 0xf3) == 0x01
|| (insn & 0xf3) == 0x02
|| (insn & 0xf3) == 0x03
|| (insn & 0xfc) == 0x24
|| (insn & 0xfc) == 0x2c
|| (insn & 0xfc) == 0x30
|| (insn & 0xfc) == 0x34
|| (insn & 0xfc) == 0x38
|| (insn & 0xff) == 0xde
|| (insn & 0xff) == 0xdf
|| (insn & 0xff) == 0xf9
|| (insn & 0xff) == 0xcc)
{
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb16 (buffer);
insn <<= 8;
status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn |= *(unsigned char *) buffer;
consume = 3;
}
/* These are four byte insns. */
else if ((insn & 0xff) == 0xfa
|| (insn & 0xff) == 0xf7
|| (insn & 0xff) == 0xfb)
{
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb32 (buffer);
consume = 4;
}
/* These are five byte insns. */
else if ((insn & 0xff) == 0xcd
|| (insn & 0xff) == 0xdc)
{
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb32 (buffer);
consume = 5;
}
/* These are six byte insns. */
else if ((insn & 0xff) == 0xfd
|| (insn & 0xff) == 0xfc)
{
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb32 (buffer);
consume = 6;
}
/* Else its a seven byte insns (in theory). */
else
{
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb32 (buffer);
consume = 7;
/* Handle the 5-byte extended instruction codes. */
if ((insn & 0xfff80000) == 0xfe800000)
consume = 5;
}
disassemble (memaddr, info, insn, consume);
return consume;
}
#define HAVE_AM33 (info->mach == AM33 || HAVE_AM33_2)
#define HAVE_AM30 (info->mach == AM30)
static void
disassemble (memaddr, info, insn, size)
bfd_vma memaddr;
struct disassemble_info *info;
unsigned long insn;
unsigned int size;
disassemble (bfd_vma memaddr,
struct disassemble_info *info,
unsigned long insn,
unsigned int size)
{
struct mn10300_opcode *op = (struct mn10300_opcode *)mn10300_opcodes;
struct mn10300_opcode *op = (struct mn10300_opcode *) mn10300_opcodes;
const struct mn10300_operand *operand;
bfd_byte buffer[4];
unsigned long extension = 0;
@ -282,21 +97,18 @@ disassemble (memaddr, info, insn, size)
extra_shift = 0;
if (size == 1 || size == 2)
{
extension = 0;
}
extension = 0;
else if (size == 3
&& (op->format == FMT_D1
|| op->opcode == 0xdf0000
|| op->opcode == 0xde0000))
{
extension = 0;
}
extension = 0;
else if (size == 3
&& op->format == FMT_D6)
{
extension = 0;
}
extension = 0;
else if (size == 3)
{
insn &= 0xff0000;
@ -314,15 +126,13 @@ disassemble (memaddr, info, insn, size)
&& (op->opcode == 0xfaf80000
|| op->opcode == 0xfaf00000
|| op->opcode == 0xfaf40000))
{
extension = 0;
}
extension = 0;
else if (size == 4
&& (op->format == FMT_D7
|| op->format == FMT_D10))
{
extension = 0;
}
extension = 0;
else if (size == 4)
{
insn &= 0xffff0000;
@ -339,6 +149,7 @@ disassemble (memaddr, info, insn, size)
else if (size == 5 && op->opcode == 0xdc000000)
{
unsigned long temp = 0;
status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info);
if (status != 0)
{
@ -373,6 +184,7 @@ disassemble (memaddr, info, insn, size)
else if (size == 5)
{
unsigned long temp = 0;
status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info);
if (status != 0)
{
@ -414,6 +226,7 @@ disassemble (memaddr, info, insn, size)
else if (size == 6)
{
unsigned long temp = 0;
status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info);
if (status != 0)
{
@ -442,6 +255,7 @@ disassemble (memaddr, info, insn, size)
else if (size == 7 && op->opcode == 0xdd000000)
{
unsigned long temp = 0;
status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info);
if (status != 0)
{
@ -465,6 +279,7 @@ disassemble (memaddr, info, insn, size)
else if (size == 7)
{
unsigned long temp = 0;
status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info);
if (status != 0)
{
@ -506,6 +321,7 @@ disassemble (memaddr, info, insn, size)
if ((operand->flags & MN10300_OPERAND_SPLIT) != 0)
{
unsigned long temp;
value = insn & ((1 << operand->bits) - 1);
value <<= (32 - operand->bits);
temp = extension >> operand->shift;
@ -517,6 +333,7 @@ disassemble (memaddr, info, insn, size)
else if ((operand->flags & MN10300_OPERAND_24BIT) != 0)
{
unsigned long temp;
value = insn & ((1 << operand->bits) - 1);
value <<= (24 - operand->bits);
temp = extension >> operand->shift;
@ -572,15 +389,12 @@ disassemble (memaddr, info, insn, size)
| ((insn >> shl_low) & mask_low));
}
else if ((operand->flags & MN10300_OPERAND_EXTENDED) != 0)
{
value = ((extension >> (operand->shift))
& ((1 << operand->bits) - 1));
}
value = ((extension >> (operand->shift))
& ((1 << operand->bits) - 1));
else
{
value = ((insn >> (operand->shift))
& ((1 << operand->bits) - 1));
}
value = ((insn >> (operand->shift))
& ((1 << operand->bits) - 1));
if ((operand->flags & MN10300_OPERAND_SIGNED) != 0
/* These are properly extended by the code above. */
@ -762,8 +576,185 @@ disassemble (memaddr, info, insn, size)
}
if (!match)
{
/* xgettext:c-format */
(*info->fprintf_func) (info->stream, _("unknown\t0x%04x"), insn);
}
/* xgettext:c-format */
(*info->fprintf_func) (info->stream, _("unknown\t0x%04x"), insn);
}
int
print_insn_mn10300 (bfd_vma memaddr, struct disassemble_info *info)
{
int status;
bfd_byte buffer[4];
unsigned long insn;
unsigned int consume;
/* First figure out how big the opcode is. */
status = (*info->read_memory_func) (memaddr, buffer, 1, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = *(unsigned char *) buffer;
/* These are one byte insns. */
if ((insn & 0xf3) == 0x00
|| (insn & 0xf0) == 0x10
|| (insn & 0xfc) == 0x3c
|| (insn & 0xf3) == 0x41
|| (insn & 0xf3) == 0x40
|| (insn & 0xfc) == 0x50
|| (insn & 0xfc) == 0x54
|| (insn & 0xf0) == 0x60
|| (insn & 0xf0) == 0x70
|| ((insn & 0xf0) == 0x80
&& (insn & 0x0c) >> 2 != (insn & 0x03))
|| ((insn & 0xf0) == 0x90
&& (insn & 0x0c) >> 2 != (insn & 0x03))
|| ((insn & 0xf0) == 0xa0
&& (insn & 0x0c) >> 2 != (insn & 0x03))
|| ((insn & 0xf0) == 0xb0
&& (insn & 0x0c) >> 2 != (insn & 0x03))
|| (insn & 0xff) == 0xcb
|| (insn & 0xfc) == 0xd0
|| (insn & 0xfc) == 0xd4
|| (insn & 0xfc) == 0xd8
|| (insn & 0xf0) == 0xe0
|| (insn & 0xff) == 0xff)
{
consume = 1;
}
/* These are two byte insns. */
else if ((insn & 0xf0) == 0x80
|| (insn & 0xf0) == 0x90
|| (insn & 0xf0) == 0xa0
|| (insn & 0xf0) == 0xb0
|| (insn & 0xfc) == 0x20
|| (insn & 0xfc) == 0x28
|| (insn & 0xf3) == 0x43
|| (insn & 0xf3) == 0x42
|| (insn & 0xfc) == 0x58
|| (insn & 0xfc) == 0x5c
|| ((insn & 0xf0) == 0xc0
&& (insn & 0xff) != 0xcb
&& (insn & 0xff) != 0xcc
&& (insn & 0xff) != 0xcd)
|| (insn & 0xff) == 0xf0
|| (insn & 0xff) == 0xf1
|| (insn & 0xff) == 0xf2
|| (insn & 0xff) == 0xf3
|| (insn & 0xff) == 0xf4
|| (insn & 0xff) == 0xf5
|| (insn & 0xff) == 0xf6)
{
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb16 (buffer);
consume = 2;
}
/* These are three byte insns. */
else if ((insn & 0xff) == 0xf8
|| (insn & 0xff) == 0xcc
|| (insn & 0xff) == 0xf9
|| (insn & 0xf3) == 0x01
|| (insn & 0xf3) == 0x02
|| (insn & 0xf3) == 0x03
|| (insn & 0xfc) == 0x24
|| (insn & 0xfc) == 0x2c
|| (insn & 0xfc) == 0x30
|| (insn & 0xfc) == 0x34
|| (insn & 0xfc) == 0x38
|| (insn & 0xff) == 0xde
|| (insn & 0xff) == 0xdf
|| (insn & 0xff) == 0xf9
|| (insn & 0xff) == 0xcc)
{
status = (*info->read_memory_func) (memaddr, buffer, 2, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb16 (buffer);
insn <<= 8;
status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn |= *(unsigned char *) buffer;
consume = 3;
}
/* These are four byte insns. */
else if ((insn & 0xff) == 0xfa
|| (insn & 0xff) == 0xf7
|| (insn & 0xff) == 0xfb)
{
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb32 (buffer);
consume = 4;
}
/* These are five byte insns. */
else if ((insn & 0xff) == 0xcd
|| (insn & 0xff) == 0xdc)
{
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb32 (buffer);
consume = 5;
}
/* These are six byte insns. */
else if ((insn & 0xff) == 0xfd
|| (insn & 0xff) == 0xfc)
{
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb32 (buffer);
consume = 6;
}
/* Else its a seven byte insns (in theory). */
else
{
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
insn = bfd_getb32 (buffer);
consume = 7;
/* Handle the 5-byte extended instruction codes. */
if ((insn & 0xfff80000) == 0xfe800000)
consume = 5;
}
disassemble (memaddr, info, insn, consume);
return consume;
}

135
opcodes/m32r-asm.c
View File

@ -1,26 +1,27 @@
/* Assembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -48,23 +49,16 @@ static const char * parse_insn_normal
/* -- assembler routines inserted here. */
/* -- asm.c */
static const char * parse_hash
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_hi16
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * parse_slo16
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_ulo16
PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *));
static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
/* Handle '#' prefixes (i.e. skip over them). */
static const char *
parse_hash (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
const char **strp;
int opindex ATTRIBUTE_UNUSED;
long *valuep ATTRIBUTE_UNUSED;
parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
const char **strp,
int opindex ATTRIBUTE_UNUSED,
long *valuep ATTRIBUTE_UNUSED)
{
if (**strp == '#')
++*strp;
@ -74,11 +68,10 @@ parse_hash (cd, strp, opindex, valuep)
/* Handle shigh(), high(). */
static const char *
parse_hi16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_hi16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -91,9 +84,9 @@ parse_hi16 (cd, strp, opindex, valuep)
{
*strp += 5;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@ -105,9 +98,9 @@ parse_hi16 (cd, strp, opindex, valuep)
{
*strp += 6;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@ -127,11 +120,7 @@ parse_hi16 (cd, strp, opindex, valuep)
handles the case where low() isn't present. */
static const char *
parse_slo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
parse_slo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -144,9 +133,9 @@ parse_slo16 (cd, strp, opindex, valuep)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@ -163,9 +152,9 @@ parse_slo16 (cd, strp, opindex, valuep)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16,
NULL, &value);
NULL, & value);
if (**strp != ')')
return "missing `)'";
return MISSING_CLOSING_PARENTHESIS;
++*strp;
*valuep = value;
return errmsg;
@ -179,11 +168,10 @@ parse_slo16 (cd, strp, opindex, valuep)
handles the case where low() isn't present. */
static const char *
parse_ulo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
unsigned long *valuep;
parse_ulo16 (CGEN_CPU_DESC cd,
const char **strp,
int opindex,
unsigned long *valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -196,9 +184,9 @@ parse_ulo16 (cd, strp, opindex, valuep)
{
*strp += 4;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return "missing `)'";
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
@ -213,7 +201,7 @@ parse_ulo16 (cd, strp, opindex, valuep)
/* -- */
const char * m32r_cgen_parse_operand
PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
/* Main entry point for operand parsing.
@ -229,11 +217,10 @@ const char * m32r_cgen_parse_operand
the handlers. */
const char *
m32r_cgen_parse_operand (cd, opindex, strp, fields)
CGEN_CPU_DESC cd;
int opindex;
const char ** strp;
CGEN_FIELDS * fields;
m32r_cgen_parse_operand (CGEN_CPU_DESC cd,
int opindex,
const char ** strp,
CGEN_FIELDS * fields)
{
const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */
@ -348,8 +335,7 @@ cgen_parse_fn * const m32r_cgen_parse_handlers[] =
};
void
m32r_cgen_init_asm (cd)
CGEN_CPU_DESC cd;
m32r_cgen_init_asm (CGEN_CPU_DESC cd)
{
m32r_cgen_init_opcode_table (cd);
m32r_cgen_init_ibld_table (cd);
@ -732,30 +718,3 @@ m32r_cgen_assemble_insn (CGEN_CPU_DESC cd,
return NULL;
}
}
#if 0 /* This calls back to GAS which we can't do without care. */
/* Record each member of OPVALS in the assembler's symbol table.
This lets GAS parse registers for us.
??? Interesting idea but not currently used. */
/* Record each member of OPVALS in the assembler's symbol table.
FIXME: Not currently used. */
void
m32r_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
{
CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
const CGEN_KEYWORD_ENTRY * ke;
while ((ke = cgen_keyword_search_next (& search)) != NULL)
{
#if 0 /* Unnecessary, should be done in the search routine. */
if (! m32r_cgen_opval_supported (ke))
continue;
#endif
cgen_asm_record_register (cd, ke->name, ke->value);
}
}
#endif /* 0 */

75
opcodes/m32r-desc.c
View File

@ -1209,27 +1209,23 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
#undef A
/* Initialize anything needed to be done once, before any cpu_open call. */
static void init_tables PARAMS ((void));
static void
init_tables ()
init_tables (void)
{
}
static const CGEN_MACH * lookup_mach_via_bfd_name
PARAMS ((const CGEN_MACH *, const char *));
static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
static void build_hw_table (CGEN_CPU_TABLE *);
static void build_ifield_table (CGEN_CPU_TABLE *);
static void build_operand_table (CGEN_CPU_TABLE *);
static void build_insn_table (CGEN_CPU_TABLE *);
static void m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *);
/* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
lookup_mach_via_bfd_name (table, name)
const CGEN_MACH *table;
const char *name;
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
{
while (table->name)
{
@ -1243,8 +1239,7 @@ lookup_mach_via_bfd_name (table, name)
/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */
static void
build_hw_table (cd)
CGEN_CPU_TABLE *cd;
build_hw_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -1270,8 +1265,7 @@ build_hw_table (cd)
/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */
static void
build_ifield_table (cd)
CGEN_CPU_TABLE *cd;
build_ifield_table (CGEN_CPU_TABLE *cd)
{
cd->ifld_table = & m32r_cgen_ifld_table[0];
}
@ -1279,8 +1273,7 @@ build_ifield_table (cd)
/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */
static void
build_operand_table (cd)
CGEN_CPU_TABLE *cd;
build_operand_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -1288,8 +1281,7 @@ build_operand_table (cd)
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
However each entry is indexed by it's enum so there can be holes in
the table. */
const CGEN_OPERAND **selected =
(const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
cd->operand_table.init_entries = init;
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@ -1312,12 +1304,11 @@ build_operand_table (cd)
operand elements to be in the table [which they mightn't be]. */
static void
build_insn_table (cd)
CGEN_CPU_TABLE *cd;
build_insn_table (CGEN_CPU_TABLE *cd)
{
int i;
const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
for (i = 0; i < MAX_INSNS; ++i)
@ -1330,8 +1321,7 @@ build_insn_table (cd)
/* Subroutine of m32r_cgen_cpu_open to rebuild the tables. */
static void
m32r_cgen_rebuild_tables (cd)
CGEN_CPU_TABLE *cd;
m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
{
int i;
unsigned int isas = cd->isas;
@ -1343,7 +1333,7 @@ m32r_cgen_rebuild_tables (cd)
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
cd->default_insn_bitsize = UNSET;
cd->base_insn_bitsize = UNSET;
cd->min_insn_bitsize = 65535; /* some ridiculously big number */
cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
cd->max_insn_bitsize = 0;
for (i = 0; i < MAX_ISAS; ++i)
if (((1 << i) & isas) != 0)
@ -1355,7 +1345,7 @@ m32r_cgen_rebuild_tables (cd)
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -1364,7 +1354,7 @@ m32r_cgen_rebuild_tables (cd)
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -1476,12 +1466,12 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
}
va_end (ap);
/* mach unspecified means "all" */
/* Mach unspecified means "all". */
if (machs == 0)
machs = (1 << MAX_MACHS) - 1;
/* base mach is always selected */
/* Base mach is always selected. */
machs |= 1;
/* isa unspecified means "all" */
/* ISA unspecified means "all". */
if (isas == 0)
isas = (1 << MAX_ISAS) - 1;
if (endian == CGEN_ENDIAN_UNKNOWN)
@ -1514,9 +1504,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
MACH_NAME is the bfd name of the mach. */
CGEN_CPU_DESC
m32r_cgen_cpu_open_1 (mach_name, endian)
const char *mach_name;
enum cgen_endian endian;
m32r_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
{
return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, endian,
@ -1529,8 +1517,7 @@ m32r_cgen_cpu_open_1 (mach_name, endian)
place as some simulator ports use this but they don't use libopcodes. */
void
m32r_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
m32r_cgen_cpu_close (CGEN_CPU_DESC cd)
{
unsigned int i;
const CGEN_INSN *insns;
@ -1539,23 +1526,17 @@ m32r_cgen_cpu_close (cd)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

93
opcodes/m32r-dis.c
View File

@ -1,27 +1,27 @@
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -56,12 +56,9 @@ static int read_insn
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
unsigned long *);
/* -- disassembler routines inserted here */
/* -- disassembler routines inserted here. */
/* -- dis.c */
static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
/* Immediate values are prefixed with '#'. */
#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \
@ -75,15 +72,15 @@ static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
/* Handle '#' prefixes as operands. */
static void
print_hash (cd, dis_info, value, attrs, pc, length)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value ATTRIBUTE_UNUSED;
unsigned int attrs ATTRIBUTE_UNUSED;
bfd_vma pc ATTRIBUTE_UNUSED;
int length ATTRIBUTE_UNUSED;
print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
void * dis_info,
long value ATTRIBUTE_UNUSED,
unsigned int attrs ATTRIBUTE_UNUSED,
bfd_vma pc ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED)
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "#");
}
@ -91,10 +88,9 @@ print_hash (cd, dis_info, value, attrs, pc, length)
#define CGEN_PRINT_INSN my_print_insn
static int
my_print_insn (cd, pc, info)
CGEN_CPU_DESC cd;
bfd_vma pc;
disassemble_info *info;
my_print_insn (CGEN_CPU_DESC cd,
bfd_vma pc,
disassemble_info *info)
{
bfd_byte buffer[CGEN_MAX_INSN_SIZE];
bfd_byte *buf = buffer;
@ -149,8 +145,7 @@ my_print_insn (cd, pc, info)
/* -- */
void m32r_cgen_print_operand
PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
void const *, bfd_vma, int));
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@ -168,16 +163,15 @@ void m32r_cgen_print_operand
the handlers. */
void
m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
CGEN_CPU_DESC cd;
int opindex;
PTR xinfo;
CGEN_FIELDS *fields;
void const *attrs ATTRIBUTE_UNUSED;
bfd_vma pc;
int length;
m32r_cgen_print_operand (CGEN_CPU_DESC cd,
int opindex,
void * xinfo,
CGEN_FIELDS *fields,
void const *attrs ATTRIBUTE_UNUSED,
bfd_vma pc,
int length)
{
disassemble_info *info = (disassemble_info *) xinfo;
disassemble_info *info = (disassemble_info *) xinfo;
switch (opindex)
{
@ -272,8 +266,7 @@ cgen_print_fn * const m32r_cgen_print_handlers[] =
void
m32r_cgen_init_dis (cd)
CGEN_CPU_DESC cd;
m32r_cgen_init_dis (CGEN_CPU_DESC cd)
{
m32r_cgen_init_opcode_table (cd);
m32r_cgen_init_ibld_table (cd);
@ -325,7 +318,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
; /* Nothing to do. */
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
(*info->print_address_func) (value, info);
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@ -407,6 +400,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
unsigned long *insn_value)
{
int status = (*info->read_memory_func) (pc, buf, buflen, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
@ -511,13 +505,13 @@ print_insn (CGEN_CPU_DESC cd,
length = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
/* length < 0 -> error */
/* Length < 0 -> error. */
if (length < 0)
return length;
if (length > 0)
{
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
/* length is in bits, result is in bytes */
/* Length is in bits, result is in bytes. */
return length / 8;
}
}
@ -567,7 +561,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list {
typedef struct cpu_desc_list
{
struct cpu_desc_list *next;
int isa;
int mach;
@ -652,7 +647,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info)
if (!cd)
abort ();
/* save this away for future reference */
/* Save this away for future reference. */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;

132
opcodes/m32r-ibld.c
View File

@ -1,25 +1,26 @@
/* Instruction building/extraction support for m32r. -*- C -*-
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h"
#include "safe-ctype.h"
#undef min
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
#undef max
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
/* Used by the ifield rtx function. */
@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
if (length == 0)
return NULL;
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
static void
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int shift = insn_length - length;
/* Written this way to avoid undefined behaviour. */
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
{
unsigned long x;
int shift;
#if 0
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
#endif
x = cgen_get_insn_value (cd, bufp, word_length);
if (CGEN_INSN_LSB0_P)
@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
return 1;
}
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
return CGEN_INSN_BITSIZE (insn);
}
/* machine generated code added here */
/* Machine generated code added here. */
const char * m32r_cgen_insert_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
/* Main entry point for operand insertion.
@ -559,12 +547,11 @@ const char * m32r_cgen_insert_operand
resolved during parsing. */
const char *
m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_FIELDS * fields;
CGEN_INSN_BYTES_PTR buffer;
bfd_vma pc ATTRIBUTE_UNUSED;
m32r_cgen_insert_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_FIELDS * fields,
CGEN_INSN_BYTES_PTR buffer,
bfd_vma pc ATTRIBUTE_UNUSED)
{
const char * errmsg = NULL;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@ -673,8 +660,7 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
}
int m32r_cgen_extract_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
CGEN_FIELDS *, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
/* Main entry point for operand extraction.
The result is <= 0 for error, >0 for success.
@ -692,13 +678,12 @@ int m32r_cgen_extract_operand
the handlers. */
int
m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_EXTRACT_INFO *ex_info;
CGEN_INSN_INT insn_value;
CGEN_FIELDS * fields;
bfd_vma pc;
m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_EXTRACT_INFO *ex_info,
CGEN_INSN_INT insn_value,
CGEN_FIELDS * fields,
bfd_vma pc)
{
/* Assume success (for those operands that are nops). */
int length = 1;
@ -821,10 +806,8 @@ cgen_extract_fn * const m32r_cgen_extract_handlers[] =
extract_insn_normal,
};
int m32r_cgen_get_int_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
bfd_vma m32r_cgen_get_vma_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
int m32r_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
@ -832,10 +815,9 @@ bfd_vma m32r_cgen_get_vma_operand
not appropriate. */
int
m32r_cgen_get_int_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
int value;
@ -928,10 +910,9 @@ m32r_cgen_get_int_operand (cd, opindex, fields)
}
bfd_vma
m32r_cgen_get_vma_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
bfd_vma value;
@ -1023,10 +1004,8 @@ m32r_cgen_get_vma_operand (cd, opindex, fields)
return value;
}
void m32r_cgen_set_int_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
void m32r_cgen_set_vma_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
void m32r_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
void m32r_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
@ -1034,11 +1013,10 @@ void m32r_cgen_set_vma_operand
not appropriate. */
void
m32r_cgen_set_int_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
int value;
m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
int value)
{
switch (opindex)
{
@ -1126,11 +1104,10 @@ m32r_cgen_set_int_operand (cd, opindex, fields, value)
}
void
m32r_cgen_set_vma_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
bfd_vma value;
m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
bfd_vma value)
{
switch (opindex)
{
@ -1220,8 +1197,7 @@ m32r_cgen_set_vma_operand (cd, opindex, fields, value)
/* Function to call before using the instruction builder tables. */
void
m32r_cgen_init_ibld_table (cd)
CGEN_CPU_DESC cd;
m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd)
{
cd->insert_handlers = & m32r_cgen_insert_handlers[0];
cd->extract_handlers = & m32r_cgen_extract_handlers[0];

40
opcodes/m32r-opc.c
View File

@ -32,36 +32,34 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* -- opc.c */
unsigned int
m32r_cgen_dis_hash (buf, value)
const char * buf ATTRIBUTE_UNUSED;
CGEN_INSN_INT value;
m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value)
{
unsigned int x;
if (value & 0xffff0000) /* 32bit instructions */
if (value & 0xffff0000) /* 32bit instructions. */
value = (value >> 16) & 0xffff;
x = (value>>8) & 0xf0;
x = (value >> 8) & 0xf0;
if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
return x;
if (x == 0x70 || x == 0xf0)
return x | ((value>>8) & 0x0f);
return x | ((value >> 8) & 0x0f);
if (x == 0x30)
return x | ((value & 0x70) >> 4);
else
return x | ((value & 0xf0) >> 4);
}
/* -- */
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
static int asm_hash_insn_p (const CGEN_INSN *);
static unsigned int asm_hash_insn (const char *);
static int dis_hash_insn_p (const CGEN_INSN *);
static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
/* Instruction formats. */
@ -1778,14 +1776,10 @@ dis_hash_insn (buf, value)
return CGEN_DIS_HASH (buf, value);
}
static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
static void
set_fields_bitsize (fields, size)
CGEN_FIELDS *fields;
int size;
set_fields_bitsize (CGEN_FIELDS *fields, int size)
{
CGEN_FIELDS_BITSIZE (fields) = size;
}
@ -1794,15 +1788,15 @@ set_fields_bitsize (fields, size)
This plugs the opcode entries and macro instructions into the cpu table. */
void
m32r_cgen_init_opcode_table (cd)
CGEN_CPU_DESC cd;
m32r_cgen_init_opcode_table (CGEN_CPU_DESC cd)
{
int i;
int num_macros = (sizeof (m32r_cgen_macro_insn_table) /
sizeof (m32r_cgen_macro_insn_table[0]));
const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0];
const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
memset (insns, 0, num_macros * sizeof (CGEN_INSN));
for (i = 0; i < num_macros; ++i)
{

4
opcodes/m32r-opc.h
View File

@ -39,8 +39,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
: X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
: ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
#else
#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value)
extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT);
#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash (buffer, value)
extern unsigned int m32r_cgen_dis_hash (const char *, CGEN_INSN_INT);
#endif
/* -- */

2130
opcodes/m68k-dis.c
View File

File diff suppressed because it is too large Load Diff

311
opcodes/m88k-dis.c
View File

@ -1,24 +1,25 @@
/* Print instructions for the Motorola 88000, for GDB and GNU Binutils.
Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993, 1998, 2000, 2001,
2002 Free Software Foundation, Inc.
2002, 2005 Free Software Foundation, Inc.
Contributed by Data General Corporation, November 1989.
Partially derived from an earlier printcmd.c.
This file is part of GDB and the GNU Binutils.
This file is part of GDB and the GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "dis-asm.h"
@ -26,14 +27,16 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#include "opintl.h"
#include "libiberty.h"
typedef struct HASHTAB {
typedef struct HASHTAB
{
const INSTAB *instr;
struct HASHTAB *next;
} HASHTAB;
/* Opcode Mnemonic Op 1 Spec Op 2 Spec Op 3 Spec Simflags Next */
const INSTAB instructions[] = {
const INSTAB instructions[] =
{
{0xf400c800,"jsr ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JSR , 0,0,1,0,0,0,0,1,0,0,0,0} },
{0xf400cc00,"jsr.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JSR , 0,0,1,0,0,0,1,1,0,0,0,0} },
{0xf400c000,"jmp ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JMP , 0,0,1,0,0,0,0,1,0,0,0,0} },
@ -517,134 +520,64 @@ const INSTAB instructions[] = {
};
HASHTAB *hashtable[HASHVAL] = {0};
static int
m88kdis PARAMS ((bfd_vma, unsigned long, struct disassemble_info *));
static void
printop PARAMS ((struct disassemble_info *, const OPSPEC *, unsigned long, bfd_vma, int));
static void
init_disasm PARAMS ((void));
/* Disassemble an M88000 instruction at `memaddr'. */
int
print_insn_m88k (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
bfd_byte buffer[4];
int status;
/* Instruction addresses may have low two bits set. Clear them. */
memaddr &=~ (bfd_vma) 3;
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
return m88kdis (memaddr, bfd_getb32 (buffer), info);
}
/*
* Disassemble the instruction in `instruction'.
* `pc' should be the address of this instruction, it will be used to
* print the target address if this is a relative jump or call the
* disassembled instruction is written to `info'.
*
* The function returns the length of this instruction in bytes.
*/
static int
m88kdis (pc, instruction, info)
bfd_vma pc;
unsigned long instruction;
struct disassemble_info *info;
{
static int ihashtab_initialized = 0;
unsigned int opcode;
const HASHTAB *entry_ptr;
int opmask;
unsigned int class;
if (! ihashtab_initialized)
{
init_disasm ();
ihashtab_initialized = 1;
}
/* Create the appropriate mask to isolate the opcode. */
opmask = DEFMASK;
class = instruction & DEFMASK;
if ((class >= SFU0) && (class <= SFU7))
{
if (instruction < SFU1)
opmask = CTRLMASK;
else
opmask = SFUMASK;
}
else if (class == RRR)
opmask = RRRMASK;
else if (class == RRI10)
opmask = RRI10MASK;
/* Isolate the opcode. */
opcode = instruction & opmask;
/* Search the hash table with the isolated opcode. */
for (entry_ptr = hashtable[opcode % HASHVAL];
(entry_ptr != NULL) && (entry_ptr->instr->opcode != opcode);
entry_ptr = entry_ptr->next)
;
if (entry_ptr == NULL)
(*info->fprintf_func) (info->stream, "word\t%08x", instruction);
else
{
(*info->fprintf_func) (info->stream, "%s", entry_ptr->instr->mnemonic);
printop (info, &(entry_ptr->instr->op1), instruction, pc, 1);
printop (info, &(entry_ptr->instr->op2), instruction, pc, 0);
printop (info, &(entry_ptr->instr->op3), instruction, pc, 0);
}
return 4;
}
/*
* Decode an Operand of an instruction.
*
* This function formats and writes an operand of an instruction to
* info based on the operand specification. When the `first' flag is
* set this is the first operand of an instruction. Undefined operand
* types cause a <dis error> message.
*
* Parameters:
* disassemble_info where the operand may be printed
* OPSPEC *opptr pointer to an operand specification
* UINT inst instruction from which operand is extracted
* UINT pc pc of instruction; used for pc-relative disp.
* int first flag which if nonzero indicates the first
* operand of an instruction
*
* The operand specified is extracted from the instruction and is
* written to buf in the format specified. The operand is preceded by
* a comma if it is not the first operand of an instruction and it is
* not a register indirect form. Registers are preceded by 'r' and
* hex values by '0x'.
*/
/* Initialize the disassembler instruction table.
Initialize the hash table and instruction table for the
disassembler. This should be called once before the first call to
disasm(). */
static void
printop (info, opptr, inst, pc, first)
struct disassemble_info *info;
const OPSPEC *opptr;
unsigned long inst;
bfd_vma pc;
int first;
init_disasm (void)
{
unsigned int hashvalue, hashsize;
struct HASHTAB *hashentries;
unsigned int i;
hashsize = sizeof (instructions) / sizeof (INSTAB);
hashentries = xmalloc (hashsize * sizeof (struct HASHTAB));
for (i = 0; i < HASHVAL; i++)
hashtable[i] = NULL;
for (i = 0; i < hashsize; i++)
{
hashvalue = (instructions[i].opcode) % HASHVAL;
hashentries[i].instr = &instructions[i];
hashentries[i].next = hashtable[hashvalue];
hashtable[hashvalue] = &hashentries[i];
}
}
/* Decode an Operand of an instruction.
This function formats and writes an operand of an instruction to
info based on the operand specification. When the `first' flag is
set this is the first operand of an instruction. Undefined operand
types cause a <dis error> message.
Parameters:
disassemble_info where the operand may be printed
OPSPEC *opptr pointer to an operand specification
UINT inst instruction from which operand is extracted
UINT pc pc of instruction; used for pc-relative disp.
int first flag which if nonzero indicates the first
operand of an instruction
The operand specified is extracted from the instruction and is
written to buf in the format specified. The operand is preceded by
a comma if it is not the first operand of an instruction and it is
not a register indirect form. Registers are preceded by 'r' and
hex values by '0x'. */
static void
printop (struct disassemble_info *info,
const OPSPEC *opptr,
unsigned long inst,
bfd_vma pc,
int first)
{
int extracted_field;
char *cond_mask_sym;
@ -747,34 +680,84 @@ printop (info, opptr, inst, pc, first)
}
}
/*
* Initialize the disassembler instruction table.
*
* Initialize the hash table and instruction table for the
* disassembler. This should be called once before the first call to
* disasm().
*/
/* Disassemble the instruction in `instruction'.
`pc' should be the address of this instruction, it will be used to
print the target address if this is a relative jump or call the
disassembled instruction is written to `info'.
The function returns the length of this instruction in bytes. */
static void
init_disasm ()
static int
m88kdis (bfd_vma pc,
unsigned long instruction,
struct disassemble_info *info)
{
unsigned int hashvalue, hashsize;
struct HASHTAB *hashentries;
unsigned int i;
static int ihashtab_initialized = 0;
unsigned int opcode;
const HASHTAB *entry_ptr;
int opmask;
unsigned int class;
hashsize = sizeof (instructions) / sizeof (INSTAB);
hashentries = (struct HASHTAB *) xmalloc (hashsize * sizeof (struct HASHTAB));
for (i = 0; i < HASHVAL; i++)
hashtable[i] = NULL;
for (i = 0; i < hashsize; i++)
if (! ihashtab_initialized)
{
hashvalue = (instructions[i].opcode) % HASHVAL;
hashentries[i].instr = &instructions[i];
hashentries[i].next = hashtable[hashvalue];
hashtable[hashvalue] = &hashentries[i];
init_disasm ();
ihashtab_initialized = 1;
}
/* Create the appropriate mask to isolate the opcode. */
opmask = DEFMASK;
class = instruction & DEFMASK;
if ((class >= SFU0) && (class <= SFU7))
{
if (instruction < SFU1)
opmask = CTRLMASK;
else
opmask = SFUMASK;
}
else if (class == RRR)
opmask = RRRMASK;
else if (class == RRI10)
opmask = RRI10MASK;
/* Isolate the opcode. */
opcode = instruction & opmask;
/* Search the hash table with the isolated opcode. */
for (entry_ptr = hashtable[opcode % HASHVAL];
(entry_ptr != NULL) && (entry_ptr->instr->opcode != opcode);
entry_ptr = entry_ptr->next)
;
if (entry_ptr == NULL)
(*info->fprintf_func) (info->stream, "word\t%08x", instruction);
else
{
(*info->fprintf_func) (info->stream, "%s", entry_ptr->instr->mnemonic);
printop (info, &(entry_ptr->instr->op1), instruction, pc, 1);
printop (info, &(entry_ptr->instr->op2), instruction, pc, 0);
printop (info, &(entry_ptr->instr->op3), instruction, pc, 0);
}
return 4;
}
/* Disassemble an M88000 instruction at `memaddr'. */
int
print_insn_m88k (bfd_vma memaddr, struct disassemble_info *info)
{
bfd_byte buffer[4];
int status;
/* Instruction addresses may have low two bits set. Clear them. */
memaddr &=~ (bfd_vma) 3;
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
return m88kdis (memaddr, bfd_getb32 (buffer), info);
}

729
opcodes/mips-dis.c
View File

File diff suppressed because it is too large Load Diff

64
opcodes/mmix-dis.c
View File

@ -2,21 +2,22 @@
Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
Written by Hans-Peter Nilsson (hp@bitrange.com)
This file is part of GDB and the GNU binutils.
This file is part of GDB and the GNU binutils.
GDB and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 2,
or (at your option) any later version.
GDB and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 2,
or (at your option) any later version.
GDB and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
GDB and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include <stdio.h>
#include <string.h>
@ -37,14 +38,14 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
} \
while (0)
#define FATAL_DEBUG \
do \
{ \
fprintf (stderr, \
_("Internal: Non-debugged code (test-case missing): %s:%d"), \
__FILE__, __LINE__); \
abort (); \
} \
#define FATAL_DEBUG \
do \
{ \
fprintf (stderr, \
_("Internal: Non-debugged code (test-case missing): %s:%d"),\
__FILE__, __LINE__); \
abort (); \
} \
while (0)
#define ROUND_MODE(n) \
@ -66,17 +67,10 @@ struct mmix_dis_info
char basic_reg_name[256][sizeof ("$255")];
};
static bfd_boolean initialize_mmix_dis_info
PARAMS ((struct disassemble_info *));
static const struct mmix_opcode *get_opcode
PARAMS ((unsigned long));
/* Initialize a target-specific array in INFO. */
static bfd_boolean
initialize_mmix_dis_info (info)
struct disassemble_info *info;
initialize_mmix_dis_info (struct disassemble_info *info)
{
struct mmix_dis_info *minfop = malloc (sizeof (struct mmix_dis_info));
int i;
@ -107,7 +101,8 @@ initialize_mmix_dis_info (info)
long i;
if (syms == NULL)
{ FATAL_DEBUG;
{
FATAL_DEBUG;
free (minfop);
return FALSE;
}
@ -138,7 +133,7 @@ initialize_mmix_dis_info (info)
for (i = 0; mmix_spec_regs[i].name != NULL; i++)
minfop->spec_reg_name[mmix_spec_regs[i].number] = mmix_spec_regs[i].name;
info->private_data = (PTR) minfop;
info->private_data = (void *) minfop;
return TRUE;
}
@ -150,12 +145,12 @@ initialize_mmix_dis_info (info)
"further entry" will just show that there was no other match. */
static const struct mmix_opcode *
get_opcode (insn)
unsigned long insn;
get_opcode (unsigned long insn)
{
static const struct mmix_opcode **opcodes = NULL;
const struct mmix_opcode *opcodep = mmix_opcodes;
unsigned int opcode_part = (insn >> 24) & 255;
if (opcodes == NULL)
opcodes = xcalloc (256, sizeof (struct mmix_opcode *));
@ -213,6 +208,7 @@ get_opcode (insn)
case mmix_operands_roundregs:
{
int midbyte = (insn >> 8) & 255;
if (midbyte <= 4)
return opcodep;
}
@ -248,9 +244,7 @@ get_opcode (insn)
/* The main disassembly function. */
int
print_insn_mmix (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
print_insn_mmix (bfd_vma memaddr, struct disassemble_info *info)
{
unsigned char buffer[4];
unsigned long insn;

72
opcodes/ms1-asm.c
View File

@ -1,26 +1,27 @@
/* Assembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -380,7 +381,7 @@ parse_type (CGEN_CPU_DESC cd,
/* -- dis.c */
const char * ms1_cgen_parse_operand
PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
/* Main entry point for operand parsing.
@ -396,11 +397,10 @@ const char * ms1_cgen_parse_operand
the handlers. */
const char *
ms1_cgen_parse_operand (cd, opindex, strp, fields)
CGEN_CPU_DESC cd;
int opindex;
const char ** strp;
CGEN_FIELDS * fields;
ms1_cgen_parse_operand (CGEN_CPU_DESC cd,
int opindex,
const char ** strp,
CGEN_FIELDS * fields)
{
const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */
@ -565,8 +565,7 @@ cgen_parse_fn * const ms1_cgen_parse_handlers[] =
};
void
ms1_cgen_init_asm (cd)
CGEN_CPU_DESC cd;
ms1_cgen_init_asm (CGEN_CPU_DESC cd)
{
ms1_cgen_init_opcode_table (cd);
ms1_cgen_init_ibld_table (cd);
@ -949,30 +948,3 @@ ms1_cgen_assemble_insn (CGEN_CPU_DESC cd,
return NULL;
}
}
#if 0 /* This calls back to GAS which we can't do without care. */
/* Record each member of OPVALS in the assembler's symbol table.
This lets GAS parse registers for us.
??? Interesting idea but not currently used. */
/* Record each member of OPVALS in the assembler's symbol table.
FIXME: Not currently used. */
void
ms1_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
{
CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
const CGEN_KEYWORD_ENTRY * ke;
while ((ke = cgen_keyword_search_next (& search)) != NULL)
{
#if 0 /* Unnecessary, should be done in the search routine. */
if (! ms1_cgen_opval_supported (ke))
continue;
#endif
cgen_asm_record_register (cd, ke->name, ke->value);
}
}
#endif /* 0 */

75
opcodes/ms1-desc.c
View File

@ -919,27 +919,23 @@ static const CGEN_IBASE ms1_cgen_insn_table[MAX_INSNS] =
#undef A
/* Initialize anything needed to be done once, before any cpu_open call. */
static void init_tables PARAMS ((void));
static void
init_tables ()
init_tables (void)
{
}
static const CGEN_MACH * lookup_mach_via_bfd_name
PARAMS ((const CGEN_MACH *, const char *));
static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
static void ms1_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
static void build_hw_table (CGEN_CPU_TABLE *);
static void build_ifield_table (CGEN_CPU_TABLE *);
static void build_operand_table (CGEN_CPU_TABLE *);
static void build_insn_table (CGEN_CPU_TABLE *);
static void ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *);
/* Subroutine of ms1_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
lookup_mach_via_bfd_name (table, name)
const CGEN_MACH *table;
const char *name;
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
{
while (table->name)
{
@ -953,8 +949,7 @@ lookup_mach_via_bfd_name (table, name)
/* Subroutine of ms1_cgen_cpu_open to build the hardware table. */
static void
build_hw_table (cd)
CGEN_CPU_TABLE *cd;
build_hw_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -980,8 +975,7 @@ build_hw_table (cd)
/* Subroutine of ms1_cgen_cpu_open to build the hardware table. */
static void
build_ifield_table (cd)
CGEN_CPU_TABLE *cd;
build_ifield_table (CGEN_CPU_TABLE *cd)
{
cd->ifld_table = & ms1_cgen_ifld_table[0];
}
@ -989,8 +983,7 @@ build_ifield_table (cd)
/* Subroutine of ms1_cgen_cpu_open to build the hardware table. */
static void
build_operand_table (cd)
CGEN_CPU_TABLE *cd;
build_operand_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -998,8 +991,7 @@ build_operand_table (cd)
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
However each entry is indexed by it's enum so there can be holes in
the table. */
const CGEN_OPERAND **selected =
(const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
cd->operand_table.init_entries = init;
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@ -1022,12 +1014,11 @@ build_operand_table (cd)
operand elements to be in the table [which they mightn't be]. */
static void
build_insn_table (cd)
CGEN_CPU_TABLE *cd;
build_insn_table (CGEN_CPU_TABLE *cd)
{
int i;
const CGEN_IBASE *ib = & ms1_cgen_insn_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
for (i = 0; i < MAX_INSNS; ++i)
@ -1040,8 +1031,7 @@ build_insn_table (cd)
/* Subroutine of ms1_cgen_cpu_open to rebuild the tables. */
static void
ms1_cgen_rebuild_tables (cd)
CGEN_CPU_TABLE *cd;
ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
{
int i;
unsigned int isas = cd->isas;
@ -1053,7 +1043,7 @@ ms1_cgen_rebuild_tables (cd)
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
cd->default_insn_bitsize = UNSET;
cd->base_insn_bitsize = UNSET;
cd->min_insn_bitsize = 65535; /* some ridiculously big number */
cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
cd->max_insn_bitsize = 0;
for (i = 0; i < MAX_ISAS; ++i)
if (((1 << i) & isas) != 0)
@ -1065,7 +1055,7 @@ ms1_cgen_rebuild_tables (cd)
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -1074,7 +1064,7 @@ ms1_cgen_rebuild_tables (cd)
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -1186,12 +1176,12 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
}
va_end (ap);
/* mach unspecified means "all" */
/* Mach unspecified means "all". */
if (machs == 0)
machs = (1 << MAX_MACHS) - 1;
/* base mach is always selected */
/* Base mach is always selected. */
machs |= 1;
/* isa unspecified means "all" */
/* ISA unspecified means "all". */
if (isas == 0)
isas = (1 << MAX_ISAS) - 1;
if (endian == CGEN_ENDIAN_UNKNOWN)
@ -1224,9 +1214,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
MACH_NAME is the bfd name of the mach. */
CGEN_CPU_DESC
ms1_cgen_cpu_open_1 (mach_name, endian)
const char *mach_name;
enum cgen_endian endian;
ms1_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
{
return ms1_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, endian,
@ -1239,8 +1227,7 @@ ms1_cgen_cpu_open_1 (mach_name, endian)
place as some simulator ports use this but they don't use libopcodes. */
void
ms1_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
ms1_cgen_cpu_close (CGEN_CPU_DESC cd)
{
unsigned int i;
const CGEN_INSN *insns;
@ -1249,23 +1236,17 @@ ms1_cgen_cpu_close (cd)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

69
opcodes/ms1-dis.c
View File

@ -1,27 +1,27 @@
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -56,7 +56,7 @@ static int read_insn
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
unsigned long *);
/* -- disassembler routines inserted here */
/* -- disassembler routines inserted here. */
/* -- dis.c */
static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
@ -81,8 +81,7 @@ print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* -- */
void ms1_cgen_print_operand
PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
void const *, bfd_vma, int));
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@ -100,16 +99,15 @@ void ms1_cgen_print_operand
the handlers. */
void
ms1_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
CGEN_CPU_DESC cd;
int opindex;
PTR xinfo;
CGEN_FIELDS *fields;
void const *attrs ATTRIBUTE_UNUSED;
bfd_vma pc;
int length;
ms1_cgen_print_operand (CGEN_CPU_DESC cd,
int opindex,
void * xinfo,
CGEN_FIELDS *fields,
void const *attrs ATTRIBUTE_UNUSED,
bfd_vma pc,
int length)
{
disassemble_info *info = (disassemble_info *) xinfo;
disassemble_info *info = (disassemble_info *) xinfo;
switch (opindex)
{
@ -270,8 +268,7 @@ cgen_print_fn * const ms1_cgen_print_handlers[] =
void
ms1_cgen_init_dis (cd)
CGEN_CPU_DESC cd;
ms1_cgen_init_dis (CGEN_CPU_DESC cd)
{
ms1_cgen_init_opcode_table (cd);
ms1_cgen_init_ibld_table (cd);
@ -323,7 +320,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
; /* Nothing to do. */
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
(*info->print_address_func) (value, info);
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@ -405,6 +402,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
unsigned long *insn_value)
{
int status = (*info->read_memory_func) (pc, buf, buflen, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
@ -509,13 +507,13 @@ print_insn (CGEN_CPU_DESC cd,
length = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
/* length < 0 -> error */
/* Length < 0 -> error. */
if (length < 0)
return length;
if (length > 0)
{
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
/* length is in bits, result is in bytes */
/* Length is in bits, result is in bytes. */
return length / 8;
}
}
@ -565,7 +563,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list {
typedef struct cpu_desc_list
{
struct cpu_desc_list *next;
int isa;
int mach;
@ -650,7 +649,7 @@ print_insn_ms1 (bfd_vma pc, disassemble_info *info)
if (!cd)
abort ();
/* save this away for future reference */
/* Save this away for future reference. */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;

132
opcodes/ms1-ibld.c
View File

@ -1,25 +1,26 @@
/* Instruction building/extraction support for ms1. -*- C -*-
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h"
#include "safe-ctype.h"
#undef min
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
#undef max
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
/* Used by the ifield rtx function. */
@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
if (length == 0)
return NULL;
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
static void
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int shift = insn_length - length;
/* Written this way to avoid undefined behaviour. */
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
{
unsigned long x;
int shift;
#if 0
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
#endif
x = cgen_get_insn_value (cd, bufp, word_length);
if (CGEN_INSN_LSB0_P)
@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
return 1;
}
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
return CGEN_INSN_BITSIZE (insn);
}
/* machine generated code added here */
/* Machine generated code added here. */
const char * ms1_cgen_insert_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
/* Main entry point for operand insertion.
@ -559,12 +547,11 @@ const char * ms1_cgen_insert_operand
resolved during parsing. */
const char *
ms1_cgen_insert_operand (cd, opindex, fields, buffer, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_FIELDS * fields;
CGEN_INSN_BYTES_PTR buffer;
bfd_vma pc ATTRIBUTE_UNUSED;
ms1_cgen_insert_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_FIELDS * fields,
CGEN_INSN_BYTES_PTR buffer,
bfd_vma pc ATTRIBUTE_UNUSED)
{
const char * errmsg = NULL;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@ -732,8 +719,7 @@ ms1_cgen_insert_operand (cd, opindex, fields, buffer, pc)
}
int ms1_cgen_extract_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
CGEN_FIELDS *, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
/* Main entry point for operand extraction.
The result is <= 0 for error, >0 for success.
@ -751,13 +737,12 @@ int ms1_cgen_extract_operand
the handlers. */
int
ms1_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_EXTRACT_INFO *ex_info;
CGEN_INSN_INT insn_value;
CGEN_FIELDS * fields;
bfd_vma pc;
ms1_cgen_extract_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_EXTRACT_INFO *ex_info,
CGEN_INSN_INT insn_value,
CGEN_FIELDS * fields,
bfd_vma pc)
{
/* Assume success (for those operands that are nops). */
int length = 1;
@ -937,10 +922,8 @@ cgen_extract_fn * const ms1_cgen_extract_handlers[] =
extract_insn_normal,
};
int ms1_cgen_get_int_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
bfd_vma ms1_cgen_get_vma_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
int ms1_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
bfd_vma ms1_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
@ -948,10 +931,9 @@ bfd_vma ms1_cgen_get_vma_operand
not appropriate. */
int
ms1_cgen_get_int_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
int value;
@ -1110,10 +1092,9 @@ ms1_cgen_get_int_operand (cd, opindex, fields)
}
bfd_vma
ms1_cgen_get_vma_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
bfd_vma value;
@ -1271,10 +1252,8 @@ ms1_cgen_get_vma_operand (cd, opindex, fields)
return value;
}
void ms1_cgen_set_int_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
void ms1_cgen_set_vma_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
void ms1_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
void ms1_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
@ -1282,11 +1261,10 @@ void ms1_cgen_set_vma_operand
not appropriate. */
void
ms1_cgen_set_int_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
int value;
ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
int value)
{
switch (opindex)
{
@ -1441,11 +1419,10 @@ ms1_cgen_set_int_operand (cd, opindex, fields, value)
}
void
ms1_cgen_set_vma_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
bfd_vma value;
ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
bfd_vma value)
{
switch (opindex)
{
@ -1602,8 +1579,7 @@ ms1_cgen_set_vma_operand (cd, opindex, fields, value)
/* Function to call before using the instruction builder tables. */
void
ms1_cgen_init_ibld_table (cd)
CGEN_CPU_DESC cd;
ms1_cgen_init_ibld_table (CGEN_CPU_DESC cd)
{
cd->insert_handlers = & ms1_cgen_insert_handlers[0];
cd->extract_handlers = & ms1_cgen_extract_handlers[0];

20
opcodes/ms1-opc.c
View File

@ -69,10 +69,10 @@ ms1_asm_hash (const char* insn)
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
static int asm_hash_insn_p (const CGEN_INSN *);
static unsigned int asm_hash_insn (const char *);
static int dis_hash_insn_p (const CGEN_INSN *);
static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
/* Instruction formats. */
@ -839,14 +839,10 @@ dis_hash_insn (buf, value)
return CGEN_DIS_HASH (buf, value);
}
static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
static void
set_fields_bitsize (fields, size)
CGEN_FIELDS *fields;
int size;
set_fields_bitsize (CGEN_FIELDS *fields, int size)
{
CGEN_FIELDS_BITSIZE (fields) = size;
}
@ -855,15 +851,15 @@ set_fields_bitsize (fields, size)
This plugs the opcode entries and macro instructions into the cpu table. */
void
ms1_cgen_init_opcode_table (cd)
CGEN_CPU_DESC cd;
ms1_cgen_init_opcode_table (CGEN_CPU_DESC cd)
{
int i;
int num_macros = (sizeof (ms1_cgen_macro_insn_table) /
sizeof (ms1_cgen_macro_insn_table[0]));
const CGEN_IBASE *ib = & ms1_cgen_macro_insn_table[0];
const CGEN_OPCODE *oc = & ms1_cgen_macro_insn_opcode_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
memset (insns, 0, num_macros * sizeof (CGEN_INSN));
for (i = 0; i < num_macros; ++i)
{

1258
opcodes/msp430-dis.c
View File

File diff suppressed because it is too large Load Diff

999
opcodes/ns32k-dis.c
View File

File diff suppressed because it is too large Load Diff

102
opcodes/openrisc-asm.c
View File

@ -1,26 +1,27 @@
/* Assembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -49,16 +50,12 @@ static const char * parse_insn_normal
/* -- asm.c */
static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
static const char * parse_hi16
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
static const char * parse_lo16
PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
long
openrisc_sign_extend_16bit (value)
long value;
openrisc_sign_extend_16bit (long value)
{
return ((value & 0xffff) ^ 0x8000) - 0x8000;
}
@ -66,11 +63,7 @@ openrisc_sign_extend_16bit (value)
/* Handle hi(). */
static const char *
parse_hi16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
parse_hi16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -85,9 +78,9 @@ parse_hi16 (cd, strp, opindex, valuep)
*strp += 3;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
return MISSING_CLOSING_PARENTHESIS;
++*strp;
if (errmsg == NULL
@ -120,11 +113,7 @@ parse_hi16 (cd, strp, opindex, valuep)
/* Handle lo(). */
static const char *
parse_lo16 (cd, strp, opindex, valuep)
CGEN_CPU_DESC cd;
const char **strp;
int opindex;
long *valuep;
parse_lo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
@ -139,9 +128,9 @@ parse_lo16 (cd, strp, opindex, valuep)
*strp += 3;
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
&result_type, &value);
& result_type, & value);
if (**strp != ')')
return _("missing `)'");
return MISSING_CLOSING_PARENTHESIS;
++*strp;
ret = value;
@ -171,7 +160,7 @@ parse_lo16 (cd, strp, opindex, valuep)
/* -- */
const char * openrisc_cgen_parse_operand
PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *));
(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
/* Main entry point for operand parsing.
@ -187,11 +176,10 @@ const char * openrisc_cgen_parse_operand
the handlers. */
const char *
openrisc_cgen_parse_operand (cd, opindex, strp, fields)
CGEN_CPU_DESC cd;
int opindex;
const char ** strp;
CGEN_FIELDS * fields;
openrisc_cgen_parse_operand (CGEN_CPU_DESC cd,
int opindex,
const char ** strp,
CGEN_FIELDS * fields)
{
const char * errmsg = NULL;
/* Used by scalar operands that still need to be parsed. */
@ -262,8 +250,7 @@ cgen_parse_fn * const openrisc_cgen_parse_handlers[] =
};
void
openrisc_cgen_init_asm (cd)
CGEN_CPU_DESC cd;
openrisc_cgen_init_asm (CGEN_CPU_DESC cd)
{
openrisc_cgen_init_opcode_table (cd);
openrisc_cgen_init_ibld_table (cd);
@ -646,30 +633,3 @@ openrisc_cgen_assemble_insn (CGEN_CPU_DESC cd,
return NULL;
}
}
#if 0 /* This calls back to GAS which we can't do without care. */
/* Record each member of OPVALS in the assembler's symbol table.
This lets GAS parse registers for us.
??? Interesting idea but not currently used. */
/* Record each member of OPVALS in the assembler's symbol table.
FIXME: Not currently used. */
void
openrisc_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals)
{
CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
const CGEN_KEYWORD_ENTRY * ke;
while ((ke = cgen_keyword_search_next (& search)) != NULL)
{
#if 0 /* Unnecessary, should be done in the search routine. */
if (! openrisc_cgen_opval_supported (ke))
continue;
#endif
cgen_asm_record_register (cd, ke->name, ke->value);
}
}
#endif /* 0 */

75
opcodes/openrisc-desc.c
View File

@ -699,27 +699,23 @@ static const CGEN_IBASE openrisc_cgen_insn_table[MAX_INSNS] =
#undef A
/* Initialize anything needed to be done once, before any cpu_open call. */
static void init_tables PARAMS ((void));
static void
init_tables ()
init_tables (void)
{
}
static const CGEN_MACH * lookup_mach_via_bfd_name
PARAMS ((const CGEN_MACH *, const char *));
static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
static void openrisc_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
static void build_hw_table (CGEN_CPU_TABLE *);
static void build_ifield_table (CGEN_CPU_TABLE *);
static void build_operand_table (CGEN_CPU_TABLE *);
static void build_insn_table (CGEN_CPU_TABLE *);
static void openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *);
/* Subroutine of openrisc_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
lookup_mach_via_bfd_name (table, name)
const CGEN_MACH *table;
const char *name;
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
{
while (table->name)
{
@ -733,8 +729,7 @@ lookup_mach_via_bfd_name (table, name)
/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */
static void
build_hw_table (cd)
CGEN_CPU_TABLE *cd;
build_hw_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -760,8 +755,7 @@ build_hw_table (cd)
/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */
static void
build_ifield_table (cd)
CGEN_CPU_TABLE *cd;
build_ifield_table (CGEN_CPU_TABLE *cd)
{
cd->ifld_table = & openrisc_cgen_ifld_table[0];
}
@ -769,8 +763,7 @@ build_ifield_table (cd)
/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */
static void
build_operand_table (cd)
CGEN_CPU_TABLE *cd;
build_operand_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
@ -778,8 +771,7 @@ build_operand_table (cd)
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
However each entry is indexed by it's enum so there can be holes in
the table. */
const CGEN_OPERAND **selected =
(const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
cd->operand_table.init_entries = init;
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
@ -802,12 +794,11 @@ build_operand_table (cd)
operand elements to be in the table [which they mightn't be]. */
static void
build_insn_table (cd)
CGEN_CPU_TABLE *cd;
build_insn_table (CGEN_CPU_TABLE *cd)
{
int i;
const CGEN_IBASE *ib = & openrisc_cgen_insn_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
for (i = 0; i < MAX_INSNS; ++i)
@ -820,8 +811,7 @@ build_insn_table (cd)
/* Subroutine of openrisc_cgen_cpu_open to rebuild the tables. */
static void
openrisc_cgen_rebuild_tables (cd)
CGEN_CPU_TABLE *cd;
openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
{
int i;
unsigned int isas = cd->isas;
@ -833,7 +823,7 @@ openrisc_cgen_rebuild_tables (cd)
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
cd->default_insn_bitsize = UNSET;
cd->base_insn_bitsize = UNSET;
cd->min_insn_bitsize = 65535; /* some ridiculously big number */
cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
cd->max_insn_bitsize = 0;
for (i = 0; i < MAX_ISAS; ++i)
if (((1 << i) & isas) != 0)
@ -845,7 +835,7 @@ openrisc_cgen_rebuild_tables (cd)
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -854,7 +844,7 @@ openrisc_cgen_rebuild_tables (cd)
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
; /* this is ok */
; /* This is ok. */
else
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
@ -966,12 +956,12 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
}
va_end (ap);
/* mach unspecified means "all" */
/* Mach unspecified means "all". */
if (machs == 0)
machs = (1 << MAX_MACHS) - 1;
/* base mach is always selected */
/* Base mach is always selected. */
machs |= 1;
/* isa unspecified means "all" */
/* ISA unspecified means "all". */
if (isas == 0)
isas = (1 << MAX_ISAS) - 1;
if (endian == CGEN_ENDIAN_UNKNOWN)
@ -1004,9 +994,7 @@ openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
MACH_NAME is the bfd name of the mach. */
CGEN_CPU_DESC
openrisc_cgen_cpu_open_1 (mach_name, endian)
const char *mach_name;
enum cgen_endian endian;
openrisc_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
{
return openrisc_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, endian,
@ -1019,8 +1007,7 @@ openrisc_cgen_cpu_open_1 (mach_name, endian)
place as some simulator ports use this but they don't use libopcodes. */
void
openrisc_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
openrisc_cgen_cpu_close (CGEN_CPU_DESC cd)
{
unsigned int i;
const CGEN_INSN *insns;
@ -1029,23 +1016,17 @@ openrisc_cgen_cpu_close (cd)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

69
opcodes/openrisc-dis.c
View File

@ -1,27 +1,27 @@
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -56,12 +56,11 @@ static int read_insn
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
unsigned long *);
/* -- disassembler routines inserted here */
/* -- disassembler routines inserted here. */
void openrisc_cgen_print_operand
PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
void const *, bfd_vma, int));
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
/* Main entry point for printing operands.
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
@ -79,16 +78,15 @@ void openrisc_cgen_print_operand
the handlers. */
void
openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
CGEN_CPU_DESC cd;
int opindex;
PTR xinfo;
CGEN_FIELDS *fields;
void const *attrs ATTRIBUTE_UNUSED;
bfd_vma pc;
int length;
openrisc_cgen_print_operand (CGEN_CPU_DESC cd,
int opindex,
void * xinfo,
CGEN_FIELDS *fields,
void const *attrs ATTRIBUTE_UNUSED,
bfd_vma pc,
int length)
{
disassemble_info *info = (disassemble_info *) xinfo;
disassemble_info *info = (disassemble_info *) xinfo;
switch (opindex)
{
@ -147,8 +145,7 @@ cgen_print_fn * const openrisc_cgen_print_handlers[] =
void
openrisc_cgen_init_dis (cd)
CGEN_CPU_DESC cd;
openrisc_cgen_init_dis (CGEN_CPU_DESC cd)
{
openrisc_cgen_init_opcode_table (cd);
openrisc_cgen_init_ibld_table (cd);
@ -200,7 +197,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
; /* Nothing to do. */
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
(*info->print_address_func) (value, info);
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
@ -282,6 +279,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
unsigned long *insn_value)
{
int status = (*info->read_memory_func) (pc, buf, buflen, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
@ -386,13 +384,13 @@ print_insn (CGEN_CPU_DESC cd,
length = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
/* length < 0 -> error */
/* Length < 0 -> error. */
if (length < 0)
return length;
if (length > 0)
{
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
/* length is in bits, result is in bytes */
/* Length is in bits, result is in bytes. */
return length / 8;
}
}
@ -442,7 +440,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
Print one instruction from PC on INFO->STREAM.
Return the size of the instruction (in bytes). */
typedef struct cpu_desc_list {
typedef struct cpu_desc_list
{
struct cpu_desc_list *next;
int isa;
int mach;
@ -527,7 +526,7 @@ print_insn_openrisc (bfd_vma pc, disassemble_info *info)
if (!cd)
abort ();
/* save this away for future reference */
/* Save this away for future reference. */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
cl->isa = isa;

132
opcodes/openrisc-ibld.c
View File

@ -1,25 +1,26 @@
/* Instruction building/extraction support for openrisc. -*- C -*-
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This file is part of the GNU Binutils and GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
Keep that in mind. */
@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc.,
#include "opintl.h"
#include "safe-ctype.h"
#undef min
#undef min
#define min(a,b) ((a) < (b) ? (a) : (b))
#undef max
#undef max
#define max(a,b) ((a) > (b) ? (a) : (b))
/* Used by the ifield rtx function. */
@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd,
if (length == 0)
return NULL;
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd,
#if CGEN_INT_INSN_P
/* Cover function to store an insn value into an integral insn. Must go here
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
static void
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int shift = insn_length - length;
/* Written this way to avoid undefined behaviour. */
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
}
}
@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd,
{
unsigned long x;
int shift;
#if 0
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
#endif
x = cgen_get_insn_value (cd, bufp, word_length);
if (CGEN_INSN_LSB0_P)
@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd,
return 1;
}
#if 0
if (CGEN_INT_INSN_P
&& word_offset != 0)
abort ();
#endif
if (word_length > 32)
abort ();
@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd,
return CGEN_INSN_BITSIZE (insn);
}
/* machine generated code added here */
/* Machine generated code added here. */
const char * openrisc_cgen_insert_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
/* Main entry point for operand insertion.
@ -559,12 +547,11 @@ const char * openrisc_cgen_insert_operand
resolved during parsing. */
const char *
openrisc_cgen_insert_operand (cd, opindex, fields, buffer, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_FIELDS * fields;
CGEN_INSN_BYTES_PTR buffer;
bfd_vma pc ATTRIBUTE_UNUSED;
openrisc_cgen_insert_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_FIELDS * fields,
CGEN_INSN_BYTES_PTR buffer,
bfd_vma pc ATTRIBUTE_UNUSED)
{
const char * errmsg = NULL;
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
@ -641,8 +628,7 @@ openrisc_cgen_insert_operand (cd, opindex, fields, buffer, pc)
}
int openrisc_cgen_extract_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
CGEN_FIELDS *, bfd_vma));
(CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
/* Main entry point for operand extraction.
The result is <= 0 for error, >0 for success.
@ -660,13 +646,12 @@ int openrisc_cgen_extract_operand
the handlers. */
int
openrisc_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
CGEN_CPU_DESC cd;
int opindex;
CGEN_EXTRACT_INFO *ex_info;
CGEN_INSN_INT insn_value;
CGEN_FIELDS * fields;
bfd_vma pc;
openrisc_cgen_extract_operand (CGEN_CPU_DESC cd,
int opindex,
CGEN_EXTRACT_INFO *ex_info,
CGEN_INSN_INT insn_value,
CGEN_FIELDS * fields,
bfd_vma pc)
{
/* Assume success (for those operands that are nops). */
int length = 1;
@ -752,10 +737,8 @@ cgen_extract_fn * const openrisc_cgen_extract_handlers[] =
extract_insn_normal,
};
int openrisc_cgen_get_int_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
bfd_vma openrisc_cgen_get_vma_operand
PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *));
int openrisc_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
bfd_vma openrisc_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
/* Getting values from cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they return.
@ -763,10 +746,9 @@ bfd_vma openrisc_cgen_get_vma_operand
not appropriate. */
int
openrisc_cgen_get_int_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
openrisc_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
int value;
@ -823,10 +805,9 @@ openrisc_cgen_get_int_operand (cd, opindex, fields)
}
bfd_vma
openrisc_cgen_get_vma_operand (cd, opindex, fields)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
const CGEN_FIELDS * fields;
openrisc_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
const CGEN_FIELDS * fields)
{
bfd_vma value;
@ -882,10 +863,8 @@ openrisc_cgen_get_vma_operand (cd, opindex, fields)
return value;
}
void openrisc_cgen_set_int_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int));
void openrisc_cgen_set_vma_operand
PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma));
void openrisc_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
void openrisc_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
/* Stuffing values in cgen_fields is handled by a collection of functions.
They are distinguished by the type of the VALUE argument they accept.
@ -893,11 +872,10 @@ void openrisc_cgen_set_vma_operand
not appropriate. */
void
openrisc_cgen_set_int_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
int value;
openrisc_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
int value)
{
switch (opindex)
{
@ -950,11 +928,10 @@ openrisc_cgen_set_int_operand (cd, opindex, fields, value)
}
void
openrisc_cgen_set_vma_operand (cd, opindex, fields, value)
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
int opindex;
CGEN_FIELDS * fields;
bfd_vma value;
openrisc_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int opindex,
CGEN_FIELDS * fields,
bfd_vma value)
{
switch (opindex)
{
@ -1009,8 +986,7 @@ openrisc_cgen_set_vma_operand (cd, opindex, fields, value)
/* Function to call before using the instruction builder tables. */
void
openrisc_cgen_init_ibld_table (cd)
CGEN_CPU_DESC cd;
openrisc_cgen_init_ibld_table (CGEN_CPU_DESC cd)
{
cd->insert_handlers = & openrisc_cgen_insert_handlers[0];
cd->extract_handlers = & openrisc_cgen_extract_handlers[0];

20
opcodes/openrisc-opc.c
View File

@ -35,10 +35,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
static int asm_hash_insn_p (const CGEN_INSN *);
static unsigned int asm_hash_insn (const char *);
static int dis_hash_insn_p (const CGEN_INSN *);
static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
/* Instruction formats. */
@ -650,14 +650,10 @@ dis_hash_insn (buf, value)
return CGEN_DIS_HASH (buf, value);
}
static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
static void
set_fields_bitsize (fields, size)
CGEN_FIELDS *fields;
int size;
set_fields_bitsize (CGEN_FIELDS *fields, int size)
{
CGEN_FIELDS_BITSIZE (fields) = size;
}
@ -666,15 +662,15 @@ set_fields_bitsize (fields, size)
This plugs the opcode entries and macro instructions into the cpu table. */
void
openrisc_cgen_init_opcode_table (cd)
CGEN_CPU_DESC cd;
openrisc_cgen_init_opcode_table (CGEN_CPU_DESC cd)
{
int i;
int num_macros = (sizeof (openrisc_cgen_macro_insn_table) /
sizeof (openrisc_cgen_macro_insn_table[0]));
const CGEN_IBASE *ib = & openrisc_cgen_macro_insn_table[0];
const CGEN_OPCODE *oc = & openrisc_cgen_macro_insn_opcode_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
memset (insns, 0, num_macros * sizeof (CGEN_INSN));
for (i = 0; i < num_macros; ++i)
{

2
opcodes/openrisc-opc.h
View File

@ -31,7 +31,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
extern long openrisc_sign_extend_16bit PARAMS ((long));
extern long openrisc_sign_extend_16bit (long);
/* -- */
/* Enum declaration for openrisc instruction types. */
typedef enum cgen_insn_type {

70
opcodes/or32-dis.c
View File

@ -1,5 +1,5 @@
/* Instruction printing code for the OpenRISC 1000
Copyright (C) 2002 Free Software Foundation, Inc.
Copyright (C) 2002, 2005 Free Software Foundation, Inc.
Contributed by Damjan Lampret <lampret@opencores.org>.
Modified from a29k port.
@ -17,7 +17,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#define DEBUG 0
@ -29,20 +30,10 @@
#define EXTEND29(x) ((x) & (unsigned long) 0x10000000 ? ((x) | (unsigned long) 0xf0000000) : ((x)))
static void find_bytes_big PARAMS ((unsigned char *, unsigned long *));
static void find_bytes_little PARAMS ((unsigned char *, unsigned long *));
static unsigned long or32_extract PARAMS ((char, char *, unsigned long));
static int or32_opcode_match PARAMS ((unsigned long, char *));
static void or32_print_register PARAMS ((char, char *, unsigned long, struct disassemble_info *));
static void or32_print_immediate PARAMS ((char, char *, unsigned long, struct disassemble_info *));
static int print_insn PARAMS ((bfd_vma, struct disassemble_info *));
/* Now find the four bytes of INSN_CH and put them in *INSN. */
static void
find_bytes_big (insn_ch, insn)
unsigned char *insn_ch;
unsigned long *insn;
find_bytes_big (unsigned char *insn_ch, unsigned long *insn)
{
*insn =
((unsigned long) insn_ch[0] << 24) +
@ -55,9 +46,7 @@ find_bytes_big (insn_ch, insn)
}
static void
find_bytes_little (insn_ch, insn)
unsigned char *insn_ch;
unsigned long *insn;
find_bytes_little (unsigned char *insn_ch, unsigned long *insn)
{
*insn =
((unsigned long) insn_ch[3] << 24) +
@ -66,14 +55,10 @@ find_bytes_little (insn_ch, insn)
((unsigned long) insn_ch[0]);
}
typedef void (*find_byte_func_type)
PARAMS ((unsigned char *, unsigned long *));
typedef void (*find_byte_func_type) (unsigned char *, unsigned long *);
static unsigned long
or32_extract (param_ch, enc_initial, insn)
char param_ch;
char *enc_initial;
unsigned long insn;
or32_extract (char param_ch, char *enc_initial, unsigned long insn)
{
char *enc;
unsigned long ret = 0;
@ -162,9 +147,7 @@ or32_extract (param_ch, enc_initial, insn)
}
static int
or32_opcode_match (insn, encoding)
unsigned long insn;
char *encoding;
or32_opcode_match (unsigned long insn, char *encoding)
{
unsigned long ones, zeros;
@ -203,11 +186,10 @@ or32_opcode_match (insn, encoding)
/* Print register to INFO->STREAM. Used only by print_insn. */
static void
or32_print_register (param_ch, encoding, insn, info)
char param_ch;
char *encoding;
unsigned long insn;
struct disassemble_info *info;
or32_print_register (char param_ch,
char *encoding,
unsigned long insn,
struct disassemble_info *info)
{
int regnum = or32_extract (param_ch, encoding, insn);
@ -231,11 +213,10 @@ or32_print_register (param_ch, encoding, insn, info)
/* Print immediate to INFO->STREAM. Used only by print_insn. */
static void
or32_print_immediate (param_ch, encoding, insn, info)
char param_ch;
char *encoding;
unsigned long insn;
struct disassemble_info *info;
or32_print_immediate (char param_ch,
char *encoding,
unsigned long insn,
struct disassemble_info *info)
{
int imm = or32_extract(param_ch, encoding, insn);
@ -250,9 +231,7 @@ or32_print_immediate (param_ch, encoding, insn, info)
Return the size of the instruction (always 4 on or32). */
static int
print_insn (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
print_insn (bfd_vma memaddr, struct disassemble_info *info)
{
/* The raw instruction. */
unsigned char insn_ch[4];
@ -260,7 +239,7 @@ print_insn (memaddr, info)
unsigned long addr;
/* The four bytes of the instruction. */
unsigned long insn;
find_byte_func_type find_byte_func = (find_byte_func_type)info->private_data;
find_byte_func_type find_byte_func = (find_byte_func_type) info->private_data;
struct or32_opcode const * opcode;
{
@ -328,21 +307,18 @@ print_insn (memaddr, info)
/* Disassemble a big-endian or32 instruction. */
int
print_insn_big_or32 (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
print_insn_big_or32 (bfd_vma memaddr, struct disassemble_info *info)
{
info->private_data = (PTR) find_bytes_big;
info->private_data = find_bytes_big;
return print_insn (memaddr, info);
}
/* Disassemble a little-endian or32 instruction. */
int
print_insn_little_or32 (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
print_insn_little_or32 (bfd_vma memaddr, struct disassemble_info *info)
{
info->private_data = (PTR) find_bytes_little;
info->private_data = find_bytes_little;
return print_insn (memaddr, info);
}

610
opcodes/or32-opc.c
View File

@ -1,5 +1,5 @@
/* Table of opcodes for the OpenRISC 1000 ISA.
Copyright 2002, 2004 Free Software Foundation, Inc.
Copyright 2002, 2004, 2005 Free Software Foundation, Inc.
Contributed by Damjan Lampret (lampret@opencores.org).
This file is part of gen_or1k_isa, or1k, GDB and GAS.
@ -16,7 +16,8 @@
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* We treat all letters the same in encode/decode routines so
we need to assign some characteristics to them like signess etc. */
@ -30,27 +31,18 @@
#endif
#include "opcode/or32.h"
static unsigned long insn_extract PARAMS ((char, char *));
static unsigned long * cover_insn PARAMS ((unsigned long *, int, unsigned int));
static int num_ones PARAMS ((unsigned long));
static struct insn_op_struct * parse_params PARAMS ((const struct or32_opcode *, struct insn_op_struct *));
static unsigned long or32_extract PARAMS ((char, char *, unsigned long));
static void or32_print_register PARAMS ((char, char *, unsigned long));
static void or32_print_immediate PARAMS ((char, char *, unsigned long));
static unsigned long extend_imm PARAMS ((unsigned long, char));
const struct or32_letter or32_letters[] =
{
{ 'A', NUM_UNSIGNED },
{ 'B', NUM_UNSIGNED },
{ 'D', NUM_UNSIGNED },
{ 'I', NUM_SIGNED },
{ 'K', NUM_UNSIGNED },
{ 'L', NUM_UNSIGNED },
{ 'N', NUM_SIGNED },
{ '0', NUM_UNSIGNED },
{ '\0', 0 } /* Dummy entry. */
};
{
{ 'A', NUM_UNSIGNED },
{ 'B', NUM_UNSIGNED },
{ 'D', NUM_UNSIGNED },
{ 'I', NUM_SIGNED },
{ 'K', NUM_UNSIGNED },
{ 'L', NUM_UNSIGNED },
{ 'N', NUM_SIGNED },
{ '0', NUM_UNSIGNED },
{ '\0', 0 } /* Dummy entry. */
};
/* Opcode encoding:
machine[31:30]: first two bits of opcode
@ -76,263 +68,263 @@ const struct or32_letter or32_letters[] =
#endif /* HAS_EXECUTION */
const struct or32_opcode or32_opcodes[] =
{
{ "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY },
{ "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY },
{ "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG},
{ "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG },
{ "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 },
{ "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/
{ "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/
{
{ "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY },
{ "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY },
{ "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG},
{ "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG },
{ "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 },
{ "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/
{ "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/
{ "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 },
{ "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */
{ "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN, 0 },
{ "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN, 0 },
{ "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN, 0 },
{ "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY },
{ "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 },
{ "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */
{ "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN, 0 },
{ "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN, 0 },
{ "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN, 0 },
{ "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY },
{ "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
{ "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
{ "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
{ "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
{ "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
{ "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
{ "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
{ "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
{ "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
{ "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
{ "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
{ "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 },
{ "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 },
{ "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 },
{ "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 },
{ "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 },
{ "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 },
{ "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 },
{ "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 },
{ "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 },
{ "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 },
{ "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 },
{ "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 },
{ "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 },
{ "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 },
{ "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 },
{ "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 },
{ "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 },
{ "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 },
{ "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 },
{ "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 },
{ "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 },
{ "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 },
{ "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 },
{ "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 },
{ "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 },
{ "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 },
{ "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 },
{ "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 },
{ "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 },
{ "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 },
{ "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 },
{ "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 },
{ "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 },
{ "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 },
{ "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 },
{ "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 },
{ "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 },
{ "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 },
{ "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 },
{ "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 },
{ "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 },
{ "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 },
{ "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 },
{ "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 },
{ "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 },
{ "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 },
{ "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 },
{ "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 },
{ "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 },
{ "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 },
{ "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 },
{ "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 },
{ "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 },
{ "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 },
{ "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 },
{ "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 },
{ "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 },
{ "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 },
{ "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 },
{ "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 },
{ "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 },
{ "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 },
{ "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 },
{ "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 },
{ "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 },
{ "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 },
{ "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 },
{ "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 },
{ "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 },
{ "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 },
{ "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 },
{ "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 },
{ "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 },
{ "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 },
{ "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 },
{ "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0 },
{ "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0 },
{ "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0 },
{ "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0 },
{ "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
{ "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
{ "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
{ "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
{ "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
{ "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
{ "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
{ "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
{ "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
{ "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
{ "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
{ "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 },
{ "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 },
{ "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 },
{ "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 },
{ "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 },
{ "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 },
{ "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 },
{ "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 },
{ "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 },
{ "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 },
{ "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 },
{ "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 },
{ "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 },
{ "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 },
{ "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 },
{ "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 },
{ "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 },
{ "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 },
{ "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 },
{ "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 },
{ "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 },
{ "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 },
{ "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 },
{ "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 },
{ "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 },
{ "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 },
{ "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 },
{ "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 },
{ "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 },
{ "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 },
{ "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 },
{ "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 },
{ "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 },
{ "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 },
{ "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 },
{ "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 },
{ "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 },
{ "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 },
{ "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 },
{ "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 },
{ "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 },
{ "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 },
{ "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 },
{ "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 },
{ "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 },
{ "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 },
{ "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 },
{ "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 },
{ "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 },
{ "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 },
{ "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 },
{ "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 },
{ "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 },
{ "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 },
{ "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 },
{ "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 },
{ "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 },
{ "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 },
{ "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 },
{ "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 },
{ "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 },
{ "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 },
{ "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 },
{ "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 },
{ "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 },
{ "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 },
{ "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 },
{ "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 },
{ "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 },
{ "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 },
{ "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 },
{ "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 },
{ "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 },
{ "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 },
{ "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 },
{ "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0 },
{ "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0 },
{ "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0 },
{ "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0 },
{ "lf.add.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
{ "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
{ "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
{ "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
{ "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
{ "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
{ "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
{ "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
{ "lf.sfne.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
{ "lf.sfgt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
{ "lf.sfge.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
{ "lf.sflt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
{ "lf.sfle.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
{ "lf.cust1.s", "", "00 0xB ----- ----- ---- ---- 0xE ----", EFI, 0 },
{ "lf.add.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
{ "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
{ "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
{ "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
{ "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
{ "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
{ "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
{ "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
{ "lf.sfne.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
{ "lf.sfgt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
{ "lf.sfge.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
{ "lf.sflt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
{ "lf.sfle.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
{ "lf.cust1.s", "", "00 0xB ----- ----- ---- ---- 0xE ----", EFI, 0 },
{ "lf.add.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
{ "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
{ "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
{ "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
{ "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
{ "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
{ "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
{ "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
{ "lf.sfne.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
{ "lf.sfgt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
{ "lf.sfge.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
{ "lf.sflt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
{ "lf.sfle.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
{ "lf.cust1.d", "", "00 0xC ----- ----- ---- ---- 0xE ----", EFI, 0 },
{ "lf.add.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
{ "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
{ "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
{ "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
{ "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
{ "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
{ "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
{ "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
{ "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
{ "lf.sfne.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
{ "lf.sfgt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
{ "lf.sfge.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
{ "lf.sflt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
{ "lf.sfle.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
{ "lf.cust1.d", "", "00 0xC ----- ----- ---- ---- 0xE ----", EFI, 0 },
{ "lvf.ld", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 },
{ "lvf.lw", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 },
{ "lvf.sd", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
{ "lvf.sw", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
{ "lvf.ld", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 },
{ "lvf.lw", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 },
{ "lvf.sd", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
{ "lvf.sw", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
{ "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY },
{ "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY },
{ "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 },
{ "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 },
{ "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 },
{ "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 },
{ "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 },
{ "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY },
{ "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY },
{ "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 },
{ "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 },
{ "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 },
{ "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 },
{ "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 },
{ "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
{ "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 },
{ "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
{ "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 },
{ "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 },
{ "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 },
{ "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 },
{ "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
{ "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 },
{ "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
{ "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 },
{ "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 },
{ "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 },
{ "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 },
{ "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 },
{ "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
{ "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 },
{ "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0 },
{ "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 },
{ "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
{ "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 },
{ "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 },
{ "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 },
{ "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 },
{ "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 },
{ "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 },
{ "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
{ "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 },
{ "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0 },
{ "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 },
{ "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
{ "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 },
{ "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 },
{ "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 },
{ "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 },
{ "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 },
{ "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG },
{ "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG },
{ "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG },
{ "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG },
{ "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG },
{ "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG },
{ "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG },
{ "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG },
{ "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG },
{ "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG },
{ "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG },
{ "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG },
{ "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG },
{ "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG },
{ "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG },
{ "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG },
{ "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG },
{ "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG },
{ "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG },
{ "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG },
{ "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 },
{ "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/
{ "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/
{ "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 },
{ "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/
{ "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/
{ "l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 },
{ "l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 },
{ "l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 },
{ "l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 },
{ "l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 },
{ "l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 },
{ "l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 },
{ "l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 },
{ "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 },
{ "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 },
{ "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 },
{ "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 },
{ "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 },
{ "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 },
{ "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 },
{ "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 },
{ "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 },
{ "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 },
{ "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 },
{ "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 },
{ "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 },
{ "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 },
{ "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 },
{ "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 },
{ "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 },
{ "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 },
{ "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 },
{ "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 },
{ "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 },
{ "l.exths", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 },
{ "l.extbs", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 },
{ "l.exthz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 },
{ "l.extbz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 },
{ "l.extws", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 },
{ "l.extwz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 },
{ "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 },
{ "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 },
{ "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 },
{ "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 },
{ "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 },
{ "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 },
{ "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 },
{ "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 },
{ "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 },
{ "l.exths", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 },
{ "l.extbs", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 },
{ "l.exthz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 },
{ "l.extbz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 },
{ "l.extws", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 },
{ "l.extwz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 },
{ "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 },
{ "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 },
{ "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG },
{ "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG },
{ "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG },
{ "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG },
{ "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG },
{ "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG },
{ "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG },
{ "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG },
{ "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG },
{ "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG },
{ "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG },
{ "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG },
{ "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG },
{ "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG },
{ "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG },
{ "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG },
{ "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG },
{ "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG },
{ "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG },
{ "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG },
{ "l.cust5", "", "11 0xC ----- ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust5", "", "11 0xC ----- ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI, 0 },
/* This section should not be defined in or1ksim, since it contains duplicates,
which would cause machine builder to complain. */
/* This section should not be defined in or1ksim, since it contains duplicates,
which would cause machine builder to complain. */
#ifdef HAS_CUST
{ "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
{ "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
{ "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
{ "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
{ "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
{ "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
{ "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
{ "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
{ "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
{ "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
{ "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
{ "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
{ "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
{ "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
{ "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI, 0 },
{ "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
{ "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
#endif
/* Dummy entry, not included in num_opcodes. This
lets code examine entry i+1 without checking
if we've run off the end of the table. */
{ "", "", "", EFI, 0 }
/* Dummy entry, not included in num_opcodes. This
lets code examine entry i+1 without checking
if we've run off the end of the table. */
{ "", "", "", EFI, 0 }
};
#undef EFI
@ -342,8 +334,6 @@ const struct or32_opcode or32_opcodes[] =
/* Define dummy, if debug is not defined. */
#if !defined HAS_DEBUG
static void debug PARAMS ((int, const char *, ...));
static void
debug (int level ATTRIBUTE_UNUSED, const char *format ATTRIBUTE_UNUSED, ...)
{
@ -355,8 +345,7 @@ const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct o
/* Calculates instruction length in bytes. Always 4 for OR32. */
int
insn_len (insn_index)
int insn_index ATTRIBUTE_UNUSED;
insn_len (int insn_index ATTRIBUTE_UNUSED)
{
return 4;
}
@ -364,8 +353,7 @@ insn_len (insn_index)
/* Is individual insn's operand signed or unsigned? */
int
letter_signed (l)
char l;
letter_signed (char l)
{
const struct or32_letter *pletter;
@ -380,19 +368,18 @@ letter_signed (l)
/* Number of letters in the individual lettered operand. */
int
letter_range (l)
char l;
letter_range (char l)
{
const struct or32_opcode *pinsn;
char *enc;
int range = 0;
for (pinsn = or32_opcodes; strlen(pinsn->name); pinsn++)
for (pinsn = or32_opcodes; strlen (pinsn->name); pinsn ++)
{
if (strchr (pinsn->encoding,l))
{
for (enc = pinsn->encoding; *enc != '\0'; enc++)
if ((*enc == '0') && (*(enc+1) == 'x'))
for (enc = pinsn->encoding; *enc != '\0'; enc ++)
if ((*enc == '0') && (*(enc + 1) == 'x'))
enc += 2;
else if (*enc == l)
range++;
@ -422,8 +409,7 @@ insn_index (char *insn)
}
const char *
insn_name (index)
int index;
insn_name (int index)
{
if (index >= 0 && index < (int) or32_num_opcodes)
return or32_opcodes[index].name;
@ -432,17 +418,16 @@ insn_name (index)
}
void
l_none ()
l_none (void)
{
}
/* Finite automata for instruction decoding building code. */
/* Find simbols in encoding. */
static unsigned long
insn_extract (param_ch, enc_initial)
char param_ch;
char *enc_initial;
insn_extract (char param_ch, char *enc_initial)
{
char *enc;
unsigned long ret = 0;
@ -475,13 +460,13 @@ insn_extract (param_ch, enc_initial)
return ret;
}
#define MAX_AUTOMATA_SIZE (1200)
#define MAX_OP_TABLE_SIZE (1200)
#define LEAF_FLAG (0x80000000)
#define MAX_LEN (8)
#define MAX_AUTOMATA_SIZE 1200
#define MAX_OP_TABLE_SIZE 1200
#define LEAF_FLAG 0x80000000
#define MAX_LEN 8
#ifndef MIN
# define MIN(x,y) ((x) < (y) ? (x) : (y))
#define MIN(x, y) ((x) < (y) ? (x) : (y))
#endif
unsigned long *automata;
@ -501,10 +486,7 @@ struct insn_op_struct *op_data, **op_start;
/* Recursive utility function used to find best match and to build automata. */
static unsigned long *
cover_insn (cur, pass, mask)
unsigned long * cur;
int pass;
unsigned int mask;
cover_insn (unsigned long * cur, int pass, unsigned int mask)
{
int best_first = 0, last_match = -1, ninstr = 0;
unsigned int best_len = 0;
@ -544,13 +526,13 @@ cover_insn (cur, pass, mask)
for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
{
unsigned long m = (1UL << ((unsigned long)len)) - 1;
unsigned long m = (1UL << ((unsigned long) len)) - 1;
debug (9, " (%i(%08X & %08X>>%i = %08X, %08X)",
len,m, cur_mask, i, (cur_mask >> (unsigned)i),
(cur_mask >> (unsigned)i) & m);
(cur_mask >> (unsigned) i) & m);
if ((m & (cur_mask >> (unsigned)i)) == m)
if ((m & (cur_mask >> (unsigned) i)) == m)
{
best_len = len;
best_first = i;
@ -586,7 +568,7 @@ cover_insn (cur, pass, mask)
/* Allocate space for pointers. */
cur += 1 << best_len;
cur_mask = (1 << (unsigned long)best_len) - 1;
cur_mask = (1 << (unsigned long) best_len) - 1;
for (i = 0; i < ((unsigned) 1 << best_len); i++)
{
@ -622,8 +604,7 @@ cover_insn (cur, pass, mask)
/* Returns number of nonzero bits. */
static int
num_ones (value)
unsigned long value;
num_ones (unsigned long value)
{
int c = 0;
@ -636,13 +617,12 @@ num_ones (value)
return c;
}
/* Utility function, which converts parameters from or32_opcode format to more binary form.
Parameters are stored in ti struct. */
/* Utility function, which converts parameters from or32_opcode
format to more binary form. Parameters are stored in ti struct. */
static struct insn_op_struct *
parse_params (opcode, cur)
const struct or32_opcode * opcode;
struct insn_op_struct * cur;
parse_params (const struct or32_opcode * opcode,
struct insn_op_struct * cur)
{
char *args = opcode->args;
int i, type;
@ -705,7 +685,8 @@ parse_params (opcode, cur)
}
else if (*args == '(')
{
/* Next param is displacement. Later we will treat them as one operand. */
/* Next param is displacement.
Later we will treat them as one operand. */
cur--;
cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP;
debug (9, ">%08X %08X\n", cur->type, cur->data);
@ -754,14 +735,14 @@ parse_params (opcode, cur)
/* Constructs new automata based on or32_opcodes array. */
void
build_automata ()
build_automata (void)
{
unsigned int i;
unsigned long *end;
struct insn_op_struct *cur;
automata = (unsigned long *) malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
ti = (struct temp_insn_struct *) malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes);
automata = malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
ti = malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes);
nuncovered = or32_num_opcodes;
printf ("Building automata... ");
@ -794,8 +775,8 @@ build_automata ()
printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes);
printf ("Parsing operands data... ");
op_data = (struct insn_op_struct *) malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct));
op_start = (struct insn_op_struct **) malloc (or32_num_opcodes * sizeof (struct insn_op_struct *));
op_data = malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct));
op_start = malloc (or32_num_opcodes * sizeof (struct insn_op_struct *));
cur = op_data;
for (i = 0; i < or32_num_opcodes; i++)
@ -813,7 +794,7 @@ build_automata ()
}
void
destruct_automata ()
destruct_automata (void)
{
free (ti);
free (automata);
@ -824,8 +805,7 @@ destruct_automata ()
/* Decodes instruction and returns instruction index. */
int
insn_decode (insn)
unsigned int insn;
insn_decode (unsigned int insn)
{
unsigned long *a = automata;
int i;
@ -869,9 +849,7 @@ char *disassembled = &disassembled_str[0];
is proper is figured out from letter description. */
static unsigned long
extend_imm (imm, l)
unsigned long imm;
char l;
extend_imm (unsigned long imm, char l)
{
unsigned long mask;
int letter_bits;
@ -890,10 +868,7 @@ extend_imm (imm, l)
}
static unsigned long
or32_extract (param_ch, enc_initial, insn)
char param_ch;
char *enc_initial;
unsigned long insn;
or32_extract (char param_ch, char *enc_initial, unsigned long insn)
{
char *enc;
unsigned long ret = 0;
@ -972,10 +947,7 @@ or32_extract (param_ch, enc_initial, insn)
/* Print register. Used only by print_insn. */
static void
or32_print_register (param_ch, encoding, insn)
char param_ch;
char *encoding;
unsigned long insn;
or32_print_register (char param_ch, char *encoding, unsigned long insn)
{
int regnum = or32_extract(param_ch, encoding, insn);
@ -985,10 +957,7 @@ or32_print_register (param_ch, encoding, insn)
/* Print immediate. Used only by print_insn. */
static void
or32_print_immediate (param_ch, encoding, insn)
char param_ch;
char *encoding;
unsigned long insn;
or32_print_immediate (char param_ch, char *encoding, unsigned long insn)
{
int imm = or32_extract (param_ch, encoding, insn);
@ -1009,8 +978,7 @@ or32_print_immediate (param_ch, encoding, insn)
Return the size of the instruction. */
int
disassemble_insn (insn)
unsigned long insn;
disassemble_insn (unsigned long insn)
{
int index;
index = insn_decode (insn);

76
opcodes/pdp11-dis.c
View File

@ -1,19 +1,20 @@
/* Print DEC PDP-11 instructions.
Copyright 2001, 2002, 2004 Free Software Foundation, Inc.
Copyright 2001, 2002, 2004, 2005 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "dis-asm.h"
@ -22,31 +23,17 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
#define AFTER_INSTRUCTION "\t"
#define OPERAND_SEPARATOR ", "
#define JUMP 0x1000 /* flag that this operand is used in a jump */
#define JUMP 0x1000 /* Flag that this operand is used in a jump. */
#define FPRINTF (*info->fprintf_func)
#define F info->stream
/* sign-extend a 16-bit number in an int */
/* Sign-extend a 16-bit number in an int. */
#define SIGN_BITS (8 * sizeof (int) - 16)
#define sign_extend(x) (((x) << SIGN_BITS) >> SIGN_BITS)
static int read_word PARAMS ((bfd_vma memaddr, int *word,
disassemble_info *info));
static void print_signed_octal PARAMS ((int n, disassemble_info *info));
static void print_reg PARAMS ((int reg, disassemble_info *info));
static void print_freg PARAMS ((int freg, disassemble_info *info));
static int print_operand PARAMS ((bfd_vma *memaddr, int code,
disassemble_info *info));
static int print_foperand PARAMS ((bfd_vma *memaddr, int code,
disassemble_info *info));
int print_insn_pdp11 PARAMS ((bfd_vma memaddr, disassemble_info *info));
static int
read_word (memaddr, word, info)
bfd_vma memaddr;
int *word;
disassemble_info *info;
read_word (bfd_vma memaddr, int *word, disassemble_info *info)
{
int status;
bfd_byte x[2];
@ -60,9 +47,7 @@ read_word (memaddr, word, info)
}
static void
print_signed_octal (n, info)
int n;
disassemble_info *info;
print_signed_octal (int n, disassemble_info *info)
{
if (n < 0)
FPRINTF (F, "-%o", -n);
@ -71,11 +56,9 @@ print_signed_octal (n, info)
}
static void
print_reg (reg, info)
int reg;
disassemble_info *info;
print_reg (int reg, disassemble_info *info)
{
/* mask off the addressing mode, if any */
/* Mask off the addressing mode, if any. */
reg &= 7;
switch (reg)
@ -89,18 +72,13 @@ print_reg (reg, info)
}
static void
print_freg (freg, info)
int freg;
disassemble_info *info;
print_freg (int freg, disassemble_info *info)
{
FPRINTF (F, "fr%d", freg);
}
static int
print_operand (memaddr, code, info)
bfd_vma *memaddr;
int code;
disassemble_info *info;
print_operand (bfd_vma *memaddr, int code, disassemble_info *info)
{
int mode = (code >> 3) & 7;
int reg = code & 7;
@ -120,6 +98,7 @@ print_operand (memaddr, code, info)
if (reg == 7)
{
int data;
if (read_word (*memaddr, &data, info) < 0)
return -1;
FPRINTF (F, "$");
@ -137,6 +116,7 @@ print_operand (memaddr, code, info)
if (reg == 7)
{
int address;
if (read_word (*memaddr, &address, info) < 0)
return -1;
FPRINTF (F, "*$%o", address);
@ -167,6 +147,7 @@ print_operand (memaddr, code, info)
if (reg == 7)
{
bfd_vma address = *memaddr + sign_extend (disp);
if (mode == 7)
FPRINTF (F, "*");
if (!(code & JUMP))
@ -189,10 +170,7 @@ print_operand (memaddr, code, info)
}
static int
print_foperand (memaddr, code, info)
bfd_vma *memaddr;
int code;
disassemble_info *info;
print_foperand (bfd_vma *memaddr, int code, disassemble_info *info)
{
int mode = (code >> 3) & 7;
int reg = code & 7;
@ -209,9 +187,7 @@ print_foperand (memaddr, code, info)
on INFO->STREAM. Returns length of the instruction, in bytes. */
int
print_insn_pdp11 (memaddr, info)
bfd_vma memaddr;
disassemble_info *info;
print_insn_pdp11 (bfd_vma memaddr, disassemble_info *info)
{
bfd_vma start_memaddr = memaddr;
int opcode;

42
opcodes/pj-dis.c
View File

@ -1,20 +1,21 @@
/* pj-dis.c -- Disassemble picoJava instructions.
Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Copyright 1999, 2000, 2001, 2002, 2005 Free Software Foundation, Inc.
Contributed by Steve Chamberlain, of Transmeta (sac@pobox.com).
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include <stdio.h>
#include "sysdep.h"
@ -23,17 +24,10 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
extern const pj_opc_info_t pj_opc_info[512];
static int get_int PARAMS ((bfd_vma, int *, struct disassemble_info *));
static int
get_int (memaddr, iptr, info)
bfd_vma memaddr;
int *iptr;
struct disassemble_info *info;
get_int (bfd_vma memaddr, int *iptr, struct disassemble_info *info)
{
unsigned char ival[4];
int status = info->read_memory_func (memaddr, ival, 4, info);
*iptr = (ival[0] << 24)
@ -45,9 +39,7 @@ get_int (memaddr, iptr, info)
}
int
print_insn_pj (addr, info)
bfd_vma addr;
struct disassemble_info *info;
print_insn_pj (bfd_vma addr, struct disassemble_info *info)
{
fprintf_ftype fprintf_fn = info->fprintf_func;
void *stream = info->stream;
@ -60,6 +52,7 @@ print_insn_pj (addr, info)
if (opcode == 0xff)
{
unsigned char byte_2;
if ((status = info->read_memory_func (addr + 1, &byte_2, 1, info)))
goto fail;
fprintf_fn (stream, "%s\t", pj_opc_info[opcode + byte_2].u.name);
@ -71,6 +64,7 @@ print_insn_pj (addr, info)
int insn_start = addr;
const pj_opc_info_t *op = &pj_opc_info[opcode];
int a;
addr++;
fprintf_fn (stream, "%s", op->u.name);
@ -115,7 +109,6 @@ print_insn_pj (addr, info)
/* The lookupswitch instruction is followed by the default
address, element count and pairs of values and
addresses. */
if (strcmp (op->u.name, "lookupswitch") == 0)
{
int count;
@ -149,6 +142,7 @@ print_insn_pj (addr, info)
}
return addr - insn_start;
}
for (a = 0; op->arg[a]; a++)
{
unsigned char data[4];

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