[gas/]
* config/tc-mips.c (macro2): Implement rotates by zero using shifts
by zero.
[gas/testsuite]
* gas/mips/rol.s: Add rotate by zero tests.
* gas/mips/rol.d: Update accordingly.
* gas/mips/rol64.d: Expect rotates by zero to use dsrl.
This commit is contained in:
Richard Sandiford
parent
a08bafb59b
commit
483fc7cd61
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@ -1,3 +1,8 @@
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2002-08-20 Richard Sandiford <rsandifo@redhat.com>
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* config/tc-mips.c (macro2): Implement rotates by zero using shifts
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by zero.
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2002-08-19 Elena Zannoni <ezannoni@redhat.com>
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From matthew green <mrg@redhat.com>
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@ -6653,22 +6653,27 @@ macro2 (ip)
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case M_DROL_I:
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{
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unsigned int rot;
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char *l, *r;
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if (imm_expr.X_op != O_constant)
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as_bad (_("rotate count too large"));
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rot = imm_expr.X_add_number & 0x3f;
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if (! rot)
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break;
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l = (rot < 0x20) ? "dsll" : "dsll32";
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r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
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rot &= 0x1f;
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
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"d,w,<", AT, sreg, rot);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
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"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
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"d,v,t", dreg, dreg, AT);
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if (rot == 0)
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
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"d,w,<", dreg, sreg, 0);
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else
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{
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char *l, *r;
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l = (rot < 0x20) ? "dsll" : "dsll32";
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r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
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rot &= 0x1f;
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
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"d,w,<", AT, sreg, rot);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
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"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
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"d,v,t", dreg, dreg, AT);
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}
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}
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break;
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@ -6679,14 +6684,18 @@ macro2 (ip)
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if (imm_expr.X_op != O_constant)
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as_bad (_("rotate count too large"));
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rot = imm_expr.X_add_number & 0x1f;
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if (! rot)
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break;
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
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"d,w,<", AT, sreg, rot);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
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"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
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"d,v,t", dreg, dreg, AT);
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if (rot == 0)
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
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"d,w,<", dreg, sreg, 0);
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else
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{
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
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"d,w,<", AT, sreg, rot);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
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"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
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"d,v,t", dreg, dreg, AT);
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}
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}
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break;
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@ -6715,22 +6724,27 @@ macro2 (ip)
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case M_DROR_I:
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{
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unsigned int rot;
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char *l, *r;
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if (imm_expr.X_op != O_constant)
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as_bad (_("rotate count too large"));
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rot = imm_expr.X_add_number & 0x3f;
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if (! rot)
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break;
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r = (rot < 0x20) ? "dsrl" : "dsrl32";
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l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
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rot &= 0x1f;
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
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"d,w,<", AT, sreg, rot);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
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"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
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"d,v,t", dreg, dreg, AT);
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if (rot == 0)
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
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"d,w,<", dreg, sreg, 0);
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else
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{
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char *l, *r;
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r = (rot < 0x20) ? "dsrl" : "dsrl32";
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l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
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rot &= 0x1f;
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
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"d,w,<", AT, sreg, rot);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
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"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
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"d,v,t", dreg, dreg, AT);
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}
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}
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break;
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@ -6741,14 +6755,18 @@ macro2 (ip)
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if (imm_expr.X_op != O_constant)
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as_bad (_("rotate count too large"));
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rot = imm_expr.X_add_number & 0x1f;
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if (! rot)
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break;
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
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"d,w,<", AT, sreg, rot);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
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"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
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"d,v,t", dreg, dreg, AT);
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if (rot == 0)
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
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"d,w,<", dreg, sreg, 0);
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else
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{
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
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"d,w,<", AT, sreg, rot);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
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"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
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"d,v,t", dreg, dreg, AT);
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}
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}
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break;
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@ -1,3 +1,9 @@
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2002-08-20 Richard Sandiford <rsandifo@redhat.com>
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* gas/mips/rol.s: Add rotate by zero tests.
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* gas/mips/rol.d: Update accordingly.
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* gas/mips/rol64.d: Expect rotates by zero to use dsrl.
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2002-08-19 Elena Zannoni <ezannoni@redhat.com>
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From matthew green <mrg@redhat.com>
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@ -21,17 +21,20 @@ Disassembly of section .text:
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0+002c <[^>]*> sll at,a1,0x1
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0+0030 <[^>]*> srl a0,a1,0x1f
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0+0034 <[^>]*> or a0,a0,at
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0+0038 <[^>]*> negu at,a1
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0+003c <[^>]*> sllv at,a0,at
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0+0040 <[^>]*> srlv a0,a0,a1
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0+0044 <[^>]*> or a0,a0,at
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0+0048 <[^>]*> negu at,a2
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0+004c <[^>]*> sllv at,a1,at
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0+0050 <[^>]*> srlv a0,a1,a2
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0+0054 <[^>]*> or a0,a0,at
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0+0058 <[^>]*> srl at,a0,0x1
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0+005c <[^>]*> sll a0,a0,0x1f
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0+0060 <[^>]*> or a0,a0,at
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0+0064 <[^>]*> srl at,a1,0x1
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0+0068 <[^>]*> sll a0,a1,0x1f
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0+006c <[^>]*> or a0,a0,at
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0+0038 <[^>]*> srl a0,a1,0x0
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0+003c <[^>]*> negu at,a1
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0+0040 <[^>]*> sllv at,a0,at
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0+0044 <[^>]*> srlv a0,a0,a1
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0+0048 <[^>]*> or a0,a0,at
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0+004c <[^>]*> negu at,a2
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0+0050 <[^>]*> sllv at,a1,at
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0+0054 <[^>]*> srlv a0,a1,a2
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0+0058 <[^>]*> or a0,a0,at
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0+005c <[^>]*> srl at,a0,0x1
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0+0060 <[^>]*> sll a0,a0,0x1f
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0+0064 <[^>]*> or a0,a0,at
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0+0068 <[^>]*> srl at,a1,0x1
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0+006c <[^>]*> sll a0,a1,0x1f
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0+0070 <[^>]*> or a0,a0,at
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0+0074 <[^>]*> srl a0,a1,0x0
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...
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@ -5,8 +5,11 @@ foo:
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rol $4,$5,$6
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rol $4,1
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rol $4,$5,1
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rol $4,$5,0
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ror $4,$5
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ror $4,$5,$6
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ror $4,1
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ror $4,$5,1
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ror $4,$5,0
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.space 8
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@ -18,45 +18,49 @@ Disassembly of section .text:
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0+0020 <[^>]*> dsll at,a0,0x1
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0+0024 <[^>]*> dsrl32 a0,a0,0x1f
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0+0028 <[^>]*> or a0,a0,at
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0+002c <[^>]*> dsll at,a1,0x1
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0+0030 <[^>]*> dsrl32 a0,a1,0x1f
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0+0034 <[^>]*> or a0,a0,at
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0+0038 <[^>]*> dsll at,a1,0x1f
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0+003c <[^>]*> dsrl32 a0,a1,0x1
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0+0040 <[^>]*> or a0,a0,at
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0+0044 <[^>]*> dsll32 at,a1,0x0
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0+0048 <[^>]*> dsrl32 a0,a1,0x0
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0+004c <[^>]*> or a0,a0,at
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0+0050 <[^>]*> dsll32 at,a1,0x1
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0+0054 <[^>]*> dsrl a0,a1,0x1f
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0+0058 <[^>]*> or a0,a0,at
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0+005c <[^>]*> dsll32 at,a1,0x1f
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0+0060 <[^>]*> dsrl a0,a1,0x1
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0+0064 <[^>]*> or a0,a0,at
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0+0068 <[^>]*> dnegu at,a1
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0+006c <[^>]*> dsllv at,a0,at
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0+0070 <[^>]*> dsrlv a0,a0,a1
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0+0074 <[^>]*> or a0,a0,at
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0+0078 <[^>]*> dnegu at,a2
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0+007c <[^>]*> dsllv at,a1,at
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0+0080 <[^>]*> dsrlv a0,a1,a2
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0+0084 <[^>]*> or a0,a0,at
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0+0088 <[^>]*> dsrl at,a0,0x1
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0+008c <[^>]*> dsll32 a0,a0,0x1f
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0+0090 <[^>]*> or a0,a0,at
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0+0094 <[^>]*> dsrl at,a1,0x1
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0+0098 <[^>]*> dsll32 a0,a1,0x1f
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0+009c <[^>]*> or a0,a0,at
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0+00a0 <[^>]*> dsrl at,a1,0x1f
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0+00a4 <[^>]*> dsll32 a0,a1,0x1
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0+002c <[^>]*> dsrl a0,a1,0x0
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0+0030 <[^>]*> dsll at,a1,0x1
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0+0034 <[^>]*> dsrl32 a0,a1,0x1f
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0+0038 <[^>]*> or a0,a0,at
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0+003c <[^>]*> dsll at,a1,0x1f
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0+0040 <[^>]*> dsrl32 a0,a1,0x1
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0+0044 <[^>]*> or a0,a0,at
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0+0048 <[^>]*> dsll32 at,a1,0x0
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0+004c <[^>]*> dsrl32 a0,a1,0x0
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0+0050 <[^>]*> or a0,a0,at
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0+0054 <[^>]*> dsll32 at,a1,0x1
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0+0058 <[^>]*> dsrl a0,a1,0x1f
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0+005c <[^>]*> or a0,a0,at
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0+0060 <[^>]*> dsll32 at,a1,0x1f
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0+0064 <[^>]*> dsrl a0,a1,0x1
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0+0068 <[^>]*> or a0,a0,at
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0+006c <[^>]*> dsrl a0,a1,0x0
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0+0070 <[^>]*> dnegu at,a1
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0+0074 <[^>]*> dsllv at,a0,at
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0+0078 <[^>]*> dsrlv a0,a0,a1
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0+007c <[^>]*> or a0,a0,at
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0+0080 <[^>]*> dnegu at,a2
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0+0084 <[^>]*> dsllv at,a1,at
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0+0088 <[^>]*> dsrlv a0,a1,a2
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0+008c <[^>]*> or a0,a0,at
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0+0090 <[^>]*> dsrl at,a0,0x1
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0+0094 <[^>]*> dsll32 a0,a0,0x1f
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0+0098 <[^>]*> or a0,a0,at
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0+009c <[^>]*> dsrl a0,a1,0x0
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0+00a0 <[^>]*> dsrl at,a1,0x1
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0+00a4 <[^>]*> dsll32 a0,a1,0x1f
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0+00a8 <[^>]*> or a0,a0,at
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0+00ac <[^>]*> dsrl32 at,a1,0x0
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0+00b0 <[^>]*> dsll32 a0,a1,0x0
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0+00ac <[^>]*> dsrl at,a1,0x1f
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0+00b0 <[^>]*> dsll32 a0,a1,0x1
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0+00b4 <[^>]*> or a0,a0,at
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0+00b8 <[^>]*> dsrl32 at,a1,0x1
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0+00bc <[^>]*> dsll a0,a1,0x1f
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0+00b8 <[^>]*> dsrl32 at,a1,0x0
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0+00bc <[^>]*> dsll32 a0,a1,0x0
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0+00c0 <[^>]*> or a0,a0,at
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0+00c4 <[^>]*> dsrl32 at,a1,0x1f
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0+00c8 <[^>]*> dsll a0,a1,0x1
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0+00c4 <[^>]*> dsrl32 at,a1,0x1
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0+00c8 <[^>]*> dsll a0,a1,0x1f
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0+00cc <[^>]*> or a0,a0,at
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0+00d0 <[^>]*> dsrl32 at,a1,0x1f
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0+00d4 <[^>]*> dsll a0,a1,0x1
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0+00d8 <[^>]*> or a0,a0,at
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0+00dc <[^>]*> dsrl a0,a1,0x0
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...
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Loading…
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