Enable Intel GFNI instructions.
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .gfni. * doc/c-i386.texi: Document .gfni. * testsuite/gas/i386/i386.exp: Add GFNI tests. * testsuite/gas/i386/avx.s: New GFNI test. * testsuite/gas/i386/x86-64-avx.s: Likewise. * testsuite/gas/i386/avx.d: Adjust. * testsuite/gas/i386/avx-intel.d: Likewise * testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise. * testsuite/gas/i386/avx512f_gfni-intel.d: New test. * testsuite/gas/i386/avx512f_gfni.d: Likewise. * testsuite/gas/i386/avx512f_gfni.s: Likewise. * testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise. * testsuite/gas/i386/avx512vl_gfni.d: Likewise. * testsuite/gas/i386/avx512vl_gfni.s: Likewise. * testsuite/gas/i386/gfni-intel.d: Likewise. * testsuite/gas/i386/gfni.d: Likewise. * testsuite/gas/i386/gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx_gfni.s: Likewise. * testsuite/gas/i386/x86-64-gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-gfni.d: Likewise. * testsuite/gas/i386/x86-64-gfni.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF. (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2. (prefix_table): Updated (see prefixes above). (three_byte_table): Likewise. (vex_w_table): Likewise. * i386-dis-evex.h: Likewise. * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI. (cpu_flags): Add CpuGFNI. * i386-opc.h (enum): Add CpuGFNI. (i386_cpu_flags): Add cpugfni. * i386-opc.tbl: Add Intel GFNI instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
This commit is contained in:
Igor Tsimbalist
parent
53467f5707
commit
48521003d5
|
|
@ -996,6 +996,8 @@ static const arch_entry cpu_arch[] =
|
|||
CPU_PTWRITE_FLAGS, 0 },
|
||||
{ STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
|
||||
CPU_CET_FLAGS, 0 },
|
||||
{ STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
|
||||
CPU_GFNI_FLAGS, 0 },
|
||||
};
|
||||
|
||||
static const noarch_entry cpu_noarch[] =
|
||||
|
|
|
|||
|
|
@ -168,6 +168,7 @@ accept various extension mnemonics. For example,
|
|||
@code{rdpid},
|
||||
@code{ptwrite},
|
||||
@code{cet},
|
||||
@code{gfni},
|
||||
@code{prefetchwt1},
|
||||
@code{clflushopt},
|
||||
@code{se1},
|
||||
|
|
@ -1225,7 +1226,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
|
|||
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
|
||||
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
|
||||
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
|
||||
@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
|
||||
@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.gfni}
|
||||
@end multitable
|
||||
|
||||
Apart from the warning, there are only two other effects on
|
||||
|
|
|
|||
|
|
@ -215,6 +215,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps ymm2,ymm6,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb ymm6,ymm5,ymm4
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b4 f4 c0 1d fe ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4
|
||||
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4
|
||||
|
|
@ -291,6 +298,22 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
|
||||
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb ymm6,ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx\+0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx-0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx-0x1020\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb ymm6,ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx\+0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx-0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx-0x1020\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4
|
||||
|
|
@ -745,6 +768,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps xmm7,xmm6,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb xmm6,xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b4 f4 c0 1d fe ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist xmm6,xmm4,0x7
|
||||
|
|
@ -797,6 +827,22 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb xmm6,xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx\+0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx-0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx-0x810\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb xmm6,xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx\+0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx-0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx-0x810\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps xmm7,xmm2,xmm6,xmm4
|
||||
|
|
@ -1641,6 +1687,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb ymm6,ymm5,ymm4
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b4 f4 c0 1d fe ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4
|
||||
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4
|
||||
|
|
@ -1754,6 +1808,24 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb ymm6,ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx\+0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx-0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx-0x1020\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb ymm6,ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx\+0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx-0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx-0x1020\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4
|
||||
|
|
@ -2435,6 +2507,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb xmm6,xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b4 f4 c0 1d fe ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[ecx\]
|
||||
|
|
@ -2515,6 +2595,24 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb xmm6,xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx\+0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx-0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx-0x810\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb xmm6,xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx\+0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx-0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx-0x810\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
|
||||
|
|
|
|||
|
|
@ -214,6 +214,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps \(%ecx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%ecx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb %ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%ecx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b4 f4 c0 1d fe ff vgf2p8mulb -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb 0xfe0\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb 0x1000\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb -0x1000\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb -0x1020\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
|
||||
|
|
@ -290,6 +297,22 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd \$0x7,\(%ecx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%ecx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb \$0x7b,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%ecx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb \$0x7b,0x1000\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb \$0x7b,-0x1000\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb \$0x7b,-0x1020\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb \$0x7b,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%ecx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb \$0x7b,0x1000\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1000\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1020\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%ecx\),%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
|
|
@ -744,6 +767,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps \(%ecx\),%xmm6,%xmm7
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%ecx\),%xmm6,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb %xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%ecx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b4 f4 c0 1d fe ff vgf2p8mulb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb 0x7f0\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb 0x800\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb -0x800\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb -0x810\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%ecx\),%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%ecx\),%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist \$0x7,%xmm4,%xmm6
|
||||
|
|
@ -796,6 +826,22 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd \$0x7,\(%ecx\),%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%ecx\),%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb \$0x7b,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%ecx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb \$0x7b,0x800\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb \$0x7b,-0x800\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb \$0x7b,-0x810\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb \$0x7b,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%ecx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb \$0x7b,0x800\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x800\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x810\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%ecx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
|
|
@ -1640,6 +1686,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%ecx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%ecx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb %ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%ecx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%ecx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b4 f4 c0 1d fe ff vgf2p8mulb -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb 0xfe0\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb 0x1000\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb -0x1000\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb -0x1020\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%ecx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
|
||||
|
|
@ -1753,6 +1807,24 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%ecx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%ecx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb \$0x7b,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%ecx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%ecx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb \$0x7b,0x1000\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb \$0x7b,-0x1000\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb \$0x7b,-0x1020\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb \$0x7b,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%ecx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%ecx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb \$0x7b,0x1000\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1000\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1020\(%edx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%ecx\),%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%ecx\),%ymm2,%ymm7
|
||||
|
|
@ -2434,6 +2506,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%ecx\),%xmm6,%xmm7
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%ecx\),%xmm6,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb %xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%ecx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%ecx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b4 f4 c0 1d fe ff vgf2p8mulb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb 0x7f0\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb 0x800\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb -0x800\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb -0x810\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%ecx\),%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%ecx\),%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%ecx\),%xmm4,%xmm6
|
||||
|
|
@ -2514,6 +2594,24 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%ecx\),%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%ecx\),%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb \$0x7b,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%ecx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%ecx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb \$0x7b,0x800\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb \$0x7b,-0x800\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb \$0x7b,-0x810\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb \$0x7b,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%ecx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%ecx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb \$0x7b,0x800\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x800\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x810\(%edx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%ecx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%ecx\),%xmm2,%xmm7
|
||||
|
|
|
|||
|
|
@ -221,6 +221,13 @@ _start:
|
|||
vcmpgt_oqps (%ecx),%ymm6,%ymm2
|
||||
vcmptrue_usps %ymm4,%ymm6,%ymm2
|
||||
vcmptrue_usps (%ecx),%ymm6,%ymm2
|
||||
vgf2p8mulb %ymm4, %ymm5, %ymm6
|
||||
vgf2p8mulb (%ecx), %ymm5, %ymm6
|
||||
vgf2p8mulb -123456(%esp,%esi,8), %ymm5, %ymm6
|
||||
vgf2p8mulb 4064(%edx), %ymm5, %ymm6
|
||||
vgf2p8mulb 4096(%edx), %ymm5, %ymm6
|
||||
vgf2p8mulb -4096(%edx), %ymm5, %ymm6
|
||||
vgf2p8mulb -4128(%edx), %ymm5, %ymm6
|
||||
|
||||
# Tests for op ymm/mem256, xmm
|
||||
vcvtpd2dqy %ymm4,%xmm4
|
||||
|
|
@ -309,6 +316,22 @@ _start:
|
|||
vshufpd $7,(%ecx),%ymm6,%ymm2
|
||||
vshufps $7,%ymm4,%ymm6,%ymm2
|
||||
vshufps $7,(%ecx),%ymm6,%ymm2
|
||||
vgf2p8affineqb $0xab, %ymm4, %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, %ymm4, %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, (%ecx), %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, -123456(%esp,%esi,8), %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, 4064(%edx), %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, 4096(%edx), %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, -4096(%edx), %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, -4128(%edx), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $0xab, %ymm4, %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, %ymm4, %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, (%ecx), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, -123456(%esp,%esi,8), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, 4064(%edx), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, 4096(%edx), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, -4096(%edx), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, -4128(%edx), %ymm5, %ymm6
|
||||
|
||||
# Tests for op ymm, ymm/mem256, ymm, ymm
|
||||
vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
|
|
@ -783,6 +806,13 @@ _start:
|
|||
vcmpgt_oqps (%ecx),%xmm6,%xmm7
|
||||
vcmptrue_usps %xmm4,%xmm6,%xmm2
|
||||
vcmptrue_usps (%ecx),%xmm6,%xmm7
|
||||
vgf2p8mulb %xmm4, %xmm5, %xmm6
|
||||
vgf2p8mulb (%ecx), %xmm5, %xmm6
|
||||
vgf2p8mulb -123456(%esp,%esi,8), %xmm5, %xmm6
|
||||
vgf2p8mulb 2032(%edx), %xmm5, %xmm6
|
||||
vgf2p8mulb 2048(%edx), %xmm5, %xmm6
|
||||
vgf2p8mulb -2048(%edx), %xmm5, %xmm6
|
||||
vgf2p8mulb -2064(%edx), %xmm5, %xmm6
|
||||
|
||||
# Tests for op mem128, xmm, xmm
|
||||
vmaskmovps (%ecx),%xmm4,%xmm6
|
||||
|
|
@ -843,6 +873,22 @@ _start:
|
|||
vshufpd $7,(%ecx),%xmm6,%xmm2
|
||||
vshufps $7,%xmm4,%xmm6,%xmm2
|
||||
vshufps $7,(%ecx),%xmm6,%xmm2
|
||||
vgf2p8affineqb $0xab, %xmm4, %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, %xmm4, %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, (%ecx), %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, -123456(%esp,%esi,8), %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, 2032(%edx), %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, 2048(%edx), %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, -2048(%edx), %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, -2064(%edx), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $0xab, %xmm4, %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, %xmm4, %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, (%ecx), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, -123456(%esp,%esi,8), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, 2032(%edx), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, 2048(%edx), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, -2048(%edx), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, -2064(%edx), %xmm5, %xmm6
|
||||
|
||||
# Tests for op xmm, xmm/mem128, xmm, xmm
|
||||
vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
|
|
@ -1777,6 +1823,14 @@ _start:
|
|||
vcmptrue_usps ymm2,ymm6,ymm4
|
||||
vcmptrue_usps ymm2,ymm6,YMMWORD PTR [ecx]
|
||||
vcmptrue_usps ymm2,ymm6,[ecx]
|
||||
vgf2p8mulb ymm6, ymm5, ymm4
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [ecx]
|
||||
vgf2p8mulb ymm6, ymm5, [ecx]
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [esp+esi*8-123456]
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [edx+4064]
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [edx+4096]
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [edx-4096]
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [edx-4128]
|
||||
|
||||
# Tests for op ymm/mem256, xmm
|
||||
vcvtpd2dq xmm4,ymm4
|
||||
|
|
@ -1902,6 +1956,24 @@ _start:
|
|||
vshufps ymm2,ymm6,ymm4,7
|
||||
vshufps ymm2,ymm6,YMMWORD PTR [ecx],7
|
||||
vshufps ymm2,ymm6,[ecx],7
|
||||
vgf2p8affineqb ymm6, ymm5, ymm4, 0xab
|
||||
vgf2p8affineqb ymm6, ymm5, ymm4, 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [ecx], 123
|
||||
vgf2p8affineqb ymm6, ymm5, [ecx], 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [esp+esi*8-123456], 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [edx+4064], 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [edx+4096], 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [edx-4096], 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [edx-4128], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, ymm4, 0xab
|
||||
vgf2p8affineinvqb ymm6, ymm5, ymm4, 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [ecx], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, [ecx], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [esp+esi*8-123456], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [edx+4064], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [edx+4096], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [edx-4096], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [edx-4128], 123
|
||||
|
||||
# Tests for op ymm, ymm/mem256, ymm, ymm
|
||||
vblendvpd ymm7,ymm2,ymm6,ymm4
|
||||
|
|
@ -2603,6 +2675,14 @@ _start:
|
|||
vcmptrue_usps xmm2,xmm6,xmm4
|
||||
vcmptrue_usps xmm7,xmm6,XMMWORD PTR [ecx]
|
||||
vcmptrue_usps xmm7,xmm6,[ecx]
|
||||
vgf2p8mulb xmm6, xmm5, xmm4
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [ecx]
|
||||
vgf2p8mulb xmm6, xmm5, [ecx]
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [esp+esi*8-123456]
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [edx+2032]
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [edx+2048]
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [edx-2048]
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [edx-2064]
|
||||
|
||||
# Tests for op mem128, xmm, xmm
|
||||
vmaskmovps xmm6,xmm4,XMMWORD PTR [ecx]
|
||||
|
|
@ -2691,6 +2771,24 @@ _start:
|
|||
vshufps xmm2,xmm6,xmm4,7
|
||||
vshufps xmm2,xmm6,XMMWORD PTR [ecx],7
|
||||
vshufps xmm2,xmm6,[ecx],7
|
||||
vgf2p8affineqb xmm6, xmm5, xmm4, 0xab
|
||||
vgf2p8affineqb xmm6, xmm5, xmm4, 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [ecx], 123
|
||||
vgf2p8affineqb xmm6, xmm5, [ecx], 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [esp+esi*8-123456], 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [edx+2032], 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [edx+2048], 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [edx-2048], 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [edx-2064], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, xmm4, 0xab
|
||||
vgf2p8affineinvqb xmm6, xmm5, xmm4, 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [ecx], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, [ecx], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [esp+esi*8-123456], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [edx+2032], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [edx+2048], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [edx-2048], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [edx-2064], 123
|
||||
|
||||
# Tests for op xmm, xmm/mem128, xmm, xmm
|
||||
vblendvpd xmm7,xmm2,xmm6,xmm4
|
||||
|
|
|
|||
|
|
@ -0,0 +1,46 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: i386 AVX512F/GFNI insns (Intel disassembly)
|
||||
#source: avx512f_gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce f4 ab[ ]*vgf2p8affineqb zmm6,zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f ce f4 ab[ ]*vgf2p8affineqb zmm6\{k7\},zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf ce f4 ab[ ]*vgf2p8affineqb zmm6\{k7\}\{z\},zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce 72 7f 7b[ ]*vgf2p8affineqb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 ce 72 7f 7b[ ]*vgf2p8affineqb zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf f4 ab[ ]*vgf2p8affineinvqb zmm6,zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f cf f4 ab[ ]*vgf2p8affineinvqb zmm6\{k7\},zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf cf f4 ab[ ]*vgf2p8affineinvqb zmm6\{k7\}\{z\},zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf 72 7f 7b[ ]*vgf2p8affineinvqb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 cf 72 7f 7b[ ]*vgf2p8affineinvqb zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf f4[ ]*vgf2p8mulb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 4f cf f4[ ]*vgf2p8mulb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 cf cf f4[ ]*vgf2p8mulb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf 72 7f[ ]*vgf2p8mulb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce f4 ab[ ]*vgf2p8affineqb zmm6,zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f ce f4 ab[ ]*vgf2p8affineqb zmm6\{k7\},zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf ce f4 ab[ ]*vgf2p8affineqb zmm6\{k7\}\{z\},zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce 72 7f 7b[ ]*vgf2p8affineqb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 ce 72 7f 7b[ ]*vgf2p8affineqb zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf f4 ab[ ]*vgf2p8affineinvqb zmm6,zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f cf f4 ab[ ]*vgf2p8affineinvqb zmm6\{k7\},zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf cf f4 ab[ ]*vgf2p8affineinvqb zmm6\{k7\}\{z\},zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf 72 7f 7b[ ]*vgf2p8affineinvqb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 cf 72 7f 7b[ ]*vgf2p8affineinvqb zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf f4[ ]*vgf2p8mulb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 4f cf f4[ ]*vgf2p8mulb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 cf cf f4[ ]*vgf2p8mulb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf 72 7f[ ]*vgf2p8mulb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
#pass
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: i386 AVX512F/GFNI insns
|
||||
#source: avx512f_gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf f4[ ]*vgf2p8mulb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 4f cf f4[ ]*vgf2p8mulb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 cf cf f4[ ]*vgf2p8mulb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf 72 7f[ ]*vgf2p8mulb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf f4[ ]*vgf2p8mulb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 4f cf f4[ ]*vgf2p8mulb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 cf cf f4[ ]*vgf2p8mulb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf 72 7f[ ]*vgf2p8mulb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
#pass
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
# Check 32bit AVX512F,GFNI instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vgf2p8affineqb $0xab, %zmm4, %zmm5, %zmm6 # AVX512F,GFNI
|
||||
vgf2p8affineqb $0xab, %zmm4, %zmm5, %zmm6{%k7} # AVX512F,GFNI
|
||||
vgf2p8affineqb $0xab, %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512F,GFNI
|
||||
vgf2p8affineqb $123, -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512F,GFNI
|
||||
vgf2p8affineqb $123, 8128(%edx), %zmm5, %zmm6 # AVX512F,GFNI Disp8
|
||||
vgf2p8affineqb $123, 1016(%edx){1to8}, %zmm5, %zmm6 # AVX512F,GFNI Disp8
|
||||
|
||||
vgf2p8affineinvqb $0xab, %zmm4, %zmm5, %zmm6 # AVX512F,GFNI
|
||||
vgf2p8affineinvqb $0xab, %zmm4, %zmm5, %zmm6{%k7} # AVX512F,GFNI
|
||||
vgf2p8affineinvqb $0xab, %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512F,GFNI
|
||||
vgf2p8affineinvqb $123, -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512F,GFNI
|
||||
vgf2p8affineinvqb $123, 8128(%edx), %zmm5, %zmm6 # AVX512F,GFNI Disp8
|
||||
vgf2p8affineinvqb $123, 1016(%edx){1to8}, %zmm5, %zmm6 # AVX512F,GFNI Disp8
|
||||
|
||||
vgf2p8mulb %zmm4, %zmm5, %zmm6 # AVX512F,GFNI
|
||||
vgf2p8mulb %zmm4, %zmm5, %zmm6{%k7} # AVX512F,GFNI
|
||||
vgf2p8mulb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512F,GFNI
|
||||
vgf2p8mulb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512F,GFNI
|
||||
vgf2p8mulb 8128(%edx), %zmm5, %zmm6 # AVX512F,GFNI Disp8
|
||||
|
||||
.intel_syntax noprefix
|
||||
vgf2p8affineqb zmm6, zmm5, zmm4, 0xab # AVX512F,GFNI
|
||||
vgf2p8affineqb zmm6{k7}, zmm5, zmm4, 0xab # AVX512F,GFNI
|
||||
vgf2p8affineqb zmm6{k7}{z}, zmm5, zmm4, 0xab # AVX512F,GFNI
|
||||
vgf2p8affineqb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512F,GFNI
|
||||
vgf2p8affineqb zmm6, zmm5, ZMMWORD PTR [edx+8128], 123 # AVX512F,GFNI Disp8
|
||||
vgf2p8affineqb zmm6, zmm5, [edx+1016]{1to8}, 123 # AVX512F,GFNI Disp8
|
||||
|
||||
vgf2p8affineinvqb zmm6, zmm5, zmm4, 0xab # AVX512F,GFNI
|
||||
vgf2p8affineinvqb zmm6{k7}, zmm5, zmm4, 0xab # AVX512F,GFNI
|
||||
vgf2p8affineinvqb zmm6{k7}{z}, zmm5, zmm4, 0xab # AVX512F,GFNI
|
||||
vgf2p8affineinvqb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512F,GFNI
|
||||
vgf2p8affineinvqb zmm6, zmm5, ZMMWORD PTR [edx+8128], 123 # AVX512F,GFNI Disp8
|
||||
vgf2p8affineinvqb zmm6, zmm5, [edx+1016]{1to8}, 123 # AVX512F,GFNI Disp8
|
||||
|
||||
vgf2p8mulb zmm6, zmm5, zmm4 # AVX512F,GFNI
|
||||
vgf2p8mulb zmm6{k7}, zmm5, zmm4 # AVX512F,GFNI
|
||||
vgf2p8mulb zmm6{k7}{z}, zmm5, zmm4 # AVX512F,GFNI
|
||||
vgf2p8mulb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512F,GFNI
|
||||
vgf2p8mulb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512F,GFNI Disp8
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: i386 AVX512VL/GFNI insns (Intel disassembly)
|
||||
#source: avx512vl_gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce f4 ab[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f ce f4 ab[ ]*vgf2p8affineqb xmm6\{k7\}\{z\},xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce f4 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce 72 7f 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f ce 72 7f 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce f4 ab[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 af ce f4 ab[ ]*vgf2p8affineqb ymm6\{k7\}\{z\},ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce f4 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce 72 7f 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f ce 72 7f 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf f4 ab[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f cf f4 ab[ ]*vgf2p8affineinvqb xmm6\{k7\}\{z\},xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf f4 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf 72 7f 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f cf 72 7f 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf f4 ab[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 af cf f4 ab[ ]*vgf2p8affineinvqb ymm6\{k7\}\{z\},ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf f4 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf 72 7f 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f cf 72 7f 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf f4[ ]*vgf2p8mulb xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f cf f4[ ]*vgf2p8mulb xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf 72 7f[ ]*vgf2p8mulb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf f4[ ]*vgf2p8mulb ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af cf f4[ ]*vgf2p8mulb ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf 72 7f[ ]*vgf2p8mulb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce f4 ab[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f ce f4 ab[ ]*vgf2p8affineqb xmm6\{k7\}\{z\},xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce 72 7f 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f ce 72 7f 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce f4 ab[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 af ce f4 ab[ ]*vgf2p8affineqb ymm6\{k7\}\{z\},ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce 72 7f 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f ce 72 7f 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf f4 ab[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f cf f4 ab[ ]*vgf2p8affineinvqb xmm6\{k7\}\{z\},xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf 72 7f 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f cf 72 7f 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf f4 ab[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 af cf f4 ab[ ]*vgf2p8affineinvqb ymm6\{k7\}\{z\},ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f cf 30 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,QWORD PTR \[eax\]\{1to4\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf 72 7f 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f cf 72 7f 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf f4[ ]*vgf2p8mulb xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f cf f4[ ]*vgf2p8mulb xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf 72 7f[ ]*vgf2p8mulb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf f4[ ]*vgf2p8mulb ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af cf f4[ ]*vgf2p8mulb ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf 72 7f[ ]*vgf2p8mulb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
#pass
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: i386 AVX512VL/GFNI insns
|
||||
#source: avx512vl_gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce f4 7b[ ]*vgf2p8affineqb \$0x7b,%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 af ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce f4 7b[ ]*vgf2p8affineqb \$0x7b,%ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf f4 7b[ ]*vgf2p8affineinvqb \$0x7b,%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 af cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf f4 7b[ ]*vgf2p8affineinvqb \$0x7b,%ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf f4[ ]*vgf2p8mulb %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f cf f4[ ]*vgf2p8mulb %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf 72 7f[ ]*vgf2p8mulb 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf f4[ ]*vgf2p8mulb %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af cf f4[ ]*vgf2p8mulb %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf 72 7f[ ]*vgf2p8mulb 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 af ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 af cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f cf 30 7b[ ]*vgf2p8affineinvqb \$0x7b,\(%eax\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf f4[ ]*vgf2p8mulb %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 8f cf f4[ ]*vgf2p8mulb %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf 72 7f[ ]*vgf2p8mulb 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf f4[ ]*vgf2p8mulb %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 af cf f4[ ]*vgf2p8mulb %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf 72 7f[ ]*vgf2p8mulb 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
#pass
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
# Check 32bit AVX512VL,GFNI instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vgf2p8affineqb $0xab, %xmm4, %xmm5, %xmm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineqb $0xab, %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512VL,GFNI
|
||||
vgf2p8affineqb $123, %xmm4, %xmm5, %xmm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineqb $123, -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineqb $123, 2032(%edx), %xmm5, %xmm6{%k7} # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineqb $123, 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineqb $0xab, %ymm4, %ymm5, %ymm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineqb $0xab, %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512VL,GFNI
|
||||
vgf2p8affineqb $123, %ymm4, %ymm5, %ymm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineqb $123, -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineqb $123, 4064(%edx), %ymm5, %ymm6{%k7} # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineqb $123, 1016(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512VL,GFNI Disp8
|
||||
|
||||
vgf2p8affineinvqb $0xab, %xmm4, %xmm5, %xmm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $0xab, %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $123, %xmm4, %xmm5, %xmm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $123, -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $123, 2032(%edx), %xmm5, %xmm6{%k7} # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineinvqb $123, 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineinvqb $0xab, %ymm4, %ymm5, %ymm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $0xab, %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $123, %ymm4, %ymm5, %ymm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $123, -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $123, 4064(%edx), %ymm5, %ymm6{%k7} # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineinvqb $123, 1016(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512VL,GFNI Disp8
|
||||
|
||||
vgf2p8mulb %xmm4, %xmm5, %xmm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8mulb %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512VL,GFNI
|
||||
vgf2p8mulb -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8mulb 2032(%edx), %xmm5, %xmm6{%k7} # AVX512VL,GFNI Disp8
|
||||
vgf2p8mulb %ymm4, %ymm5, %ymm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8mulb %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512VL,GFNI
|
||||
vgf2p8mulb -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512VL,GFNI
|
||||
vgf2p8mulb 4064(%edx), %ymm5, %ymm6{%k7} # AVX512VL,GFNI Disp8
|
||||
|
||||
.intel_syntax noprefix
|
||||
vgf2p8affineqb xmm6{k7}, xmm5, xmm4, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineqb xmm6{k7}{z}, xmm5, xmm4, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineqb xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,GFNI
|
||||
vgf2p8affineqb xmm6{k7}, xmm5, XMMWORD PTR [edx+2032], 123 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineqb xmm6{k7}, xmm5, [edx+1016]{1to2}, 123 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineqb ymm6{k7}, ymm5, ymm4, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineqb ymm6{k7}{z}, ymm5, ymm4, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineqb ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,GFNI
|
||||
vgf2p8affineqb ymm6{k7}, ymm5, YMMWORD PTR [edx+4064], 123 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineqb ymm6{k7}, ymm5, [edx+1016]{1to4}, 123 # AVX512VL,GFNI Disp8
|
||||
|
||||
vgf2p8affineinvqb xmm6{k7}, xmm5, xmm4, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb xmm6{k7}{z}, xmm5, xmm4, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb xmm6{k7}, xmm5, XMMWORD PTR [edx+2032], 123 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineinvqb xmm6{k7}, xmm5, [edx+1016]{1to2}, 123 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineinvqb ymm6{k7}, ymm5, ymm4, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb ymm6{k7}{z}, ymm5, ymm4, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb ymm6{k7}, ymm5, [eax]{1to4}, 123 # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb ymm6{k7}, ymm5, YMMWORD PTR [edx+4064], 123 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineinvqb ymm6{k7}, ymm5, [edx+1016]{1to4}, 123 # AVX512VL,GFNI Disp8
|
||||
|
||||
vgf2p8mulb xmm6{k7}, xmm5, xmm4 # AVX512VL,GFNI
|
||||
vgf2p8mulb xmm6{k7}{z}, xmm5, xmm4 # AVX512VL,GFNI
|
||||
vgf2p8mulb xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512VL,GFNI
|
||||
vgf2p8mulb xmm6{k7}, xmm5, XMMWORD PTR [edx+2032] # AVX512VL,GFNI Disp8
|
||||
vgf2p8mulb ymm6{k7}, ymm5, ymm4 # AVX512VL,GFNI
|
||||
vgf2p8mulb ymm6{k7}{z}, ymm5, ymm4 # AVX512VL,GFNI
|
||||
vgf2p8mulb ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456] # AVX512VL,GFNI
|
||||
vgf2p8mulb ymm6{k7}, ymm5, YMMWORD PTR [edx+4064] # AVX512VL,GFNI Disp8
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: i386 GFNI insns (Intel disassembly)
|
||||
#source: gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ec[ ]*gf2p8mulb xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ac f4 c0 1d fe ff[ ]*gf2p8mulb xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf aa f0 07 00 00[ ]*gf2p8mulb xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ec ab[ ]*gf2p8affineqb xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ac f4 c0 1d fe ff 7b[ ]*gf2p8affineqb xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce aa f0 07 00 00 7b[ ]*gf2p8affineqb xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ec ab[ ]*gf2p8affineinvqb xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ac f4 c0 1d fe ff 7b[ ]*gf2p8affineinvqb xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf aa f0 07 00 00 7b[ ]*gf2p8affineinvqb xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ec[ ]*gf2p8mulb xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ac f4 c0 1d fe ff[ ]*gf2p8mulb xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf aa f0 07 00 00[ ]*gf2p8mulb xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ec ab[ ]*gf2p8affineqb xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ac f4 c0 1d fe ff 7b[ ]*gf2p8affineqb xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce aa f0 07 00 00 7b[ ]*gf2p8affineqb xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ec ab[ ]*gf2p8affineinvqb xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ac f4 c0 1d fe ff 7b[ ]*gf2p8affineinvqb xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf aa f0 07 00 00 7b[ ]*gf2p8affineinvqb xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
|
||||
#pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: i386 GFNI insns
|
||||
#source: gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ec[ ]*gf2p8mulb %xmm4,%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ac f4 c0 1d fe ff[ ]*gf2p8mulb -0x1e240\(%esp,%esi,8\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf aa f0 07 00 00[ ]*gf2p8mulb 0x7f0\(%edx\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ec ab[ ]*gf2p8affineqb \$0xab,%xmm4,%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ac f4 c0 1d fe ff 7b[ ]*gf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce aa f0 07 00 00 7b[ ]*gf2p8affineqb \$0x7b,0x7f0\(%edx\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ec ab[ ]*gf2p8affineinvqb \$0xab,%xmm4,%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ac f4 c0 1d fe ff 7b[ ]*gf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf aa f0 07 00 00 7b[ ]*gf2p8affineinvqb \$0x7b,0x7f0\(%edx\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ec[ ]*gf2p8mulb %xmm4,%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ac f4 c0 1d fe ff[ ]*gf2p8mulb -0x1e240\(%esp,%esi,8\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf aa f0 07 00 00[ ]*gf2p8mulb 0x7f0\(%edx\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ec ab[ ]*gf2p8affineqb \$0xab,%xmm4,%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ac f4 c0 1d fe ff 7b[ ]*gf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce aa f0 07 00 00 7b[ ]*gf2p8affineqb \$0x7b,0x7f0\(%edx\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ec ab[ ]*gf2p8affineinvqb \$0xab,%xmm4,%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ac f4 c0 1d fe ff 7b[ ]*gf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf aa f0 07 00 00 7b[ ]*gf2p8affineinvqb \$0x7b,0x7f0\(%edx\),%xmm5
|
||||
#pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# Check GFNI instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
gf2p8mulb %xmm4, %xmm5
|
||||
gf2p8mulb -123456(%esp,%esi,8), %xmm5
|
||||
gf2p8mulb 2032(%edx), %xmm5
|
||||
|
||||
gf2p8affineqb $0xab, %xmm4, %xmm5
|
||||
gf2p8affineqb $123, -123456(%esp,%esi,8), %xmm5
|
||||
gf2p8affineqb $123, 2032(%edx), %xmm5
|
||||
|
||||
gf2p8affineinvqb $0xab, %xmm4, %xmm5
|
||||
gf2p8affineinvqb $123, -123456(%esp,%esi,8), %xmm5
|
||||
gf2p8affineinvqb $123, 2032(%edx), %xmm5
|
||||
|
||||
.intel_syntax noprefix
|
||||
|
||||
gf2p8mulb xmm5, xmm4
|
||||
gf2p8mulb xmm5, XMMWORD PTR [esp+esi*8-123456]
|
||||
gf2p8mulb xmm5, XMMWORD PTR [edx+2032]
|
||||
|
||||
gf2p8affineqb xmm5, xmm4, 0xab
|
||||
gf2p8affineqb xmm5, XMMWORD PTR [esp+esi*8-123456], 123
|
||||
gf2p8affineqb xmm5, XMMWORD PTR [edx+2032], 123
|
||||
|
||||
gf2p8affineinvqb xmm5, xmm4, 0xab
|
||||
gf2p8affineinvqb xmm5, XMMWORD PTR [esp+esi*8-123456], 123
|
||||
gf2p8affineinvqb xmm5, XMMWORD PTR [edx+2032], 123
|
||||
|
|
@ -374,6 +374,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||
run_dump_test "avx512vbmi2-intel"
|
||||
run_dump_test "avx512vbmi2_vl"
|
||||
run_dump_test "avx512vbmi2_vl-intel"
|
||||
run_dump_test "avx512f_gfni"
|
||||
run_dump_test "avx512f_gfni-intel"
|
||||
run_dump_test "avx512vl_gfni"
|
||||
run_dump_test "avx512vl_gfni-intel"
|
||||
run_dump_test "clzero"
|
||||
run_dump_test "disassem"
|
||||
run_dump_test "mwaitx-bdver4"
|
||||
|
|
@ -383,6 +387,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||
run_dump_test "rdpid-intel"
|
||||
run_dump_test "ptwrite"
|
||||
run_dump_test "ptwrite-intel"
|
||||
run_dump_test "gfni"
|
||||
run_dump_test "gfni-intel"
|
||||
run_list_test "avx512vl-1" "-al"
|
||||
run_list_test "avx512vl-2" "-al"
|
||||
run_dump_test "fpu-bad"
|
||||
|
|
@ -626,6 +632,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-avx-scalar"
|
||||
run_dump_test "x86-64-avx-scalar-intel"
|
||||
run_dump_test "x86-64-avx256int"
|
||||
run_dump_test "x86-64-avx_gfni"
|
||||
run_dump_test "x86-64-avx_gfni-intel"
|
||||
run_dump_test "x86-64-avx256int-intel"
|
||||
run_dump_test "x86-64-avx2"
|
||||
run_dump_test "x86-64-avx2-intel"
|
||||
|
|
@ -799,6 +807,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-avx512vbmi2-intel"
|
||||
run_dump_test "x86-64-avx512vbmi2_vl"
|
||||
run_dump_test "x86-64-avx512vbmi2_vl-intel"
|
||||
run_dump_test "x86-64-avx512f_gfni"
|
||||
run_dump_test "x86-64-avx512f_gfni-intel"
|
||||
run_dump_test "x86-64-avx512vl_gfni"
|
||||
run_dump_test "x86-64-avx512vl_gfni-intel"
|
||||
run_dump_test "x86-64-clzero"
|
||||
run_dump_test "x86-64-mwaitx-bdver4"
|
||||
run_list_test "x86-64-mwaitx-reg"
|
||||
|
|
@ -807,6 +819,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-rdpid-intel"
|
||||
run_dump_test "x86-64-ptwrite"
|
||||
run_dump_test "x86-64-ptwrite-intel"
|
||||
run_dump_test "x86-64-gfni"
|
||||
run_dump_test "x86-64-gfni-intel"
|
||||
run_dump_test "x86-64-fence-as-lock-add-yes"
|
||||
run_dump_test "x86-64-fence-as-lock-add-no"
|
||||
run_dump_test "x86-64-pr20141"
|
||||
|
|
|
|||
|
|
@ -215,6 +215,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps ymm2,ymm6,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb ymm6,ymm5,ymm4
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4
|
||||
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4
|
||||
|
|
@ -291,6 +298,22 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb ymm6,ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb ymm6,ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4
|
||||
|
|
@ -745,6 +768,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps xmm7,xmm6,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb xmm6,xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 a2 51 cf b4 f0 c0 1d fe ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist xmm6,xmm4,0x7
|
||||
|
|
@ -801,6 +831,22 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb xmm6,xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb xmm6,xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps xmm7,xmm2,xmm6,xmm4
|
||||
|
|
@ -1803,6 +1849,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb ymm6,ymm5,ymm4
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4
|
||||
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4
|
||||
|
|
@ -1916,6 +1970,24 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb ymm6,ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb ymm6,ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
|
||||
|
|
@ -2597,6 +2669,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb xmm6,xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 a2 51 cf b4 f0 c0 1d fe ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[rcx\]
|
||||
|
|
@ -2677,6 +2757,24 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb xmm6,xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb xmm6,xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
|
||||
|
|
|
|||
|
|
@ -215,6 +215,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps \(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb %ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb -0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb 0xfe0\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb 0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb -0x1020\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
|
||||
|
|
@ -291,6 +298,22 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd \$0x7,\(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb \$0x7b,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb \$0x7b,0xfe0\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb \$0x7b,0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb \$0x7b,-0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb \$0x7b,-0x1020\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb \$0x7b,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb \$0x7b,0xfe0\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb \$0x7b,0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1020\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
|
|
@ -745,6 +768,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps \(%rcx\),%xmm6,%xmm7
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%rcx\),%xmm6,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb %xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 a2 51 cf b4 f0 c0 1d fe ff vgf2p8mulb -0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb 0x7f0\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb 0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb -0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb -0x810\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%rcx\),%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist \$0x7,%xmm4,%xmm6
|
||||
|
|
@ -801,6 +831,22 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd \$0x7,\(%rcx\),%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%rcx\),%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb \$0x7b,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb \$0x7b,0x7f0\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb \$0x7b,0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb \$0x7b,-0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb \$0x7b,-0x810\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb \$0x7b,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb \$0x7b,0x7f0\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb \$0x7b,0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x810\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
|
|
@ -1803,6 +1849,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb %ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb -0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb 0xfe0\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb 0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb -0x1020\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
|
||||
|
|
@ -1916,6 +1970,24 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb \$0x7b,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb \$0x7b,0xfe0\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb \$0x7b,0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb \$0x7b,-0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb \$0x7b,-0x1020\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb \$0x7b,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb \$0x7b,0xfe0\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb \$0x7b,0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1020\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7
|
||||
|
|
@ -2597,6 +2669,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%rcx\),%xmm6,%xmm7
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%rcx\),%xmm6,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb %xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 a2 51 cf b4 f0 c0 1d fe ff vgf2p8mulb -0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb 0x7f0\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb 0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb -0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb -0x810\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%rcx\),%xmm4,%xmm6
|
||||
|
|
@ -2677,6 +2757,24 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%rcx\),%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%rcx\),%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb \$0x7b,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb \$0x7b,0x7f0\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb \$0x7b,0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb \$0x7b,-0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb \$0x7b,-0x810\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb \$0x7b,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb \$0x7b,0x7f0\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb \$0x7b,0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x810\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
|
|
|
|||
|
|
@ -215,6 +215,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps ymm2,ymm6,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb ymm6,ymm5,ymm4
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4
|
||||
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4
|
||||
|
|
@ -291,6 +298,22 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb ymm6,ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb ymm6,ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4
|
||||
|
|
@ -745,6 +768,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps xmm7,xmm6,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb xmm6,xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 a2 51 cf b4 f0 c0 1d fe ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist xmm6,xmm4,0x7
|
||||
|
|
@ -801,6 +831,22 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb xmm6,xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb xmm6,xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps xmm7,xmm2,xmm6,xmm4
|
||||
|
|
@ -1803,6 +1849,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb ymm6,ymm5,ymm4
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4
|
||||
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4
|
||||
|
|
@ -1916,6 +1970,24 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb ymm6,ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb ymm6,ymm5,ymm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
|
||||
|
|
@ -2597,6 +2669,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb xmm6,xmm5,xmm4
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 a2 51 cf b4 f0 c0 1d fe ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[rcx\]
|
||||
|
|
@ -2677,6 +2757,24 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb xmm6,xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb xmm6,xmm5,xmm4,0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\],0x7b
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
|
||||
|
|
|
|||
|
|
@ -214,6 +214,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps \(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb %ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb -0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb 0xfe0\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb 0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb -0x1020\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
|
||||
|
|
@ -290,6 +297,22 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd \$0x7,\(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb \$0x7b,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb \$0x7b,0xfe0\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb \$0x7b,0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb \$0x7b,-0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb \$0x7b,-0x1020\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb \$0x7b,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb \$0x7b,0xfe0\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb \$0x7b,0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1020\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7
|
||||
|
|
@ -744,6 +767,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps \(%rcx\),%xmm6,%xmm7
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%rcx\),%xmm6,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb %xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 a2 51 cf b4 f0 c0 1d fe ff vgf2p8mulb -0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb 0x7f0\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb 0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb -0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb -0x810\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%rcx\),%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist \$0x7,%xmm4,%xmm6
|
||||
|
|
@ -800,6 +830,22 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd \$0x7,\(%rcx\),%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%rcx\),%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb \$0x7b,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb \$0x7b,0x7f0\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb \$0x7b,0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb \$0x7b,-0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb \$0x7b,-0x810\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb \$0x7b,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb \$0x7b,0x7f0\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb \$0x7b,0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x810\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps %xmm4,%xmm6,%xmm2,%xmm7
|
||||
|
|
@ -1802,6 +1848,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb %ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb -0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb 0xfe0\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb 0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb -0x1020\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
|
||||
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%rcx\),%xmm4
|
||||
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
|
||||
|
|
@ -1915,6 +1969,24 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%rcx\),%ymm6,%ymm2
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb \$0x7b,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb \$0x7b,0xfe0\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb \$0x7b,0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb \$0x7b,-0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb \$0x7b,-0x1020\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb \$0x7b,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d5 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb \$0x7b,0xfe0\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb \$0x7b,0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1000\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1020\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7
|
||||
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7
|
||||
|
|
@ -2596,6 +2668,14 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%rcx\),%xmm6,%xmm7
|
||||
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%rcx\),%xmm6,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb %xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 a2 51 cf b4 f0 c0 1d fe ff vgf2p8mulb -0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb 0x7f0\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb 0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb -0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb -0x810\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%rcx\),%xmm4,%xmm6
|
||||
|
|
@ -2676,6 +2756,24 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%rcx\),%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%rcx\),%xmm6,%xmm2
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb \$0x7b,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb \$0x7b,0x7f0\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb \$0x7b,0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb \$0x7b,-0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb \$0x7b,-0x810\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb \$0x7b,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 a3 d1 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb \$0x7b,0x7f0\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb \$0x7b,0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x800\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x810\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7
|
||||
|
|
|
|||
|
|
@ -221,6 +221,13 @@ _start:
|
|||
vcmpgt_oqps (%rcx),%ymm6,%ymm2
|
||||
vcmptrue_usps %ymm4,%ymm6,%ymm2
|
||||
vcmptrue_usps (%rcx),%ymm6,%ymm2
|
||||
vgf2p8mulb %ymm4, %ymm5, %ymm6
|
||||
vgf2p8mulb (%rcx), %ymm5, %ymm6
|
||||
vgf2p8mulb -123456(%rax,%r14,8), %ymm5, %ymm6
|
||||
vgf2p8mulb 4064(%rdx), %ymm5, %ymm6
|
||||
vgf2p8mulb 4096(%rdx), %ymm5, %ymm6
|
||||
vgf2p8mulb -4096(%rdx), %ymm5, %ymm6
|
||||
vgf2p8mulb -4128(%rdx), %ymm5, %ymm6
|
||||
|
||||
# Tests for op ymm/mem256, xmm
|
||||
vcvtpd2dqy %ymm4,%xmm4
|
||||
|
|
@ -309,6 +316,22 @@ _start:
|
|||
vshufpd $7,(%rcx),%ymm6,%ymm2
|
||||
vshufps $7,%ymm4,%ymm6,%ymm2
|
||||
vshufps $7,(%rcx),%ymm6,%ymm2
|
||||
vgf2p8affineqb $0xab, %ymm4, %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, %ymm4, %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, (%rcx), %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, -123456(%rax,%r14,8), %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, 4064(%rdx), %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, 4096(%rdx), %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, -4096(%rdx), %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, -4128(%rdx), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $0xab, %ymm4, %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, %ymm4, %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, (%rcx), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, -123456(%rax,%r14,8), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, 4064(%rdx), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, 4096(%rdx), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, -4096(%rdx), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, -4128(%rdx), %ymm5, %ymm6
|
||||
|
||||
# Tests for op ymm, ymm/mem256, ymm, ymm
|
||||
vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
|
||||
|
|
@ -783,6 +806,13 @@ _start:
|
|||
vcmpgt_oqps (%rcx),%xmm6,%xmm7
|
||||
vcmptrue_usps %xmm4,%xmm6,%xmm2
|
||||
vcmptrue_usps (%rcx),%xmm6,%xmm7
|
||||
vgf2p8mulb %xmm4, %xmm5, %xmm6
|
||||
vgf2p8mulb (%rcx), %xmm5, %xmm6
|
||||
vgf2p8mulb -123456(%rax,%r14,8), %xmm5, %xmm6
|
||||
vgf2p8mulb 2032(%rdx), %xmm5, %xmm6
|
||||
vgf2p8mulb 2048(%rdx), %xmm5, %xmm6
|
||||
vgf2p8mulb -2048(%rdx), %xmm5, %xmm6
|
||||
vgf2p8mulb -2064(%rdx), %xmm5, %xmm6
|
||||
|
||||
# Tests for op mem128, xmm, xmm
|
||||
vmaskmovps (%rcx),%xmm4,%xmm6
|
||||
|
|
@ -847,6 +877,22 @@ _start:
|
|||
vshufpd $7,(%rcx),%xmm6,%xmm2
|
||||
vshufps $7,%xmm4,%xmm6,%xmm2
|
||||
vshufps $7,(%rcx),%xmm6,%xmm2
|
||||
vgf2p8affineqb $0xab, %xmm4, %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, %xmm4, %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, (%rcx), %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, -123456(%rax,%r14,8), %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, 2032(%rdx), %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, 2048(%rdx), %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, -2048(%rdx), %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, -2064(%rdx), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $0xab, %xmm4, %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, %xmm4, %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, (%rcx), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, -123456(%rax,%r14,8), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, 2032(%rdx), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, 2048(%rdx), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, -2048(%rdx), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, -2064(%rdx), %xmm5, %xmm6
|
||||
|
||||
# Tests for op xmm, xmm/mem128, xmm, xmm
|
||||
vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
|
||||
|
|
@ -1958,6 +2004,14 @@ _start:
|
|||
vcmptrue_usps ymm2,ymm6,ymm4
|
||||
vcmptrue_usps ymm2,ymm6,YMMWORD PTR [rcx]
|
||||
vcmptrue_usps ymm2,ymm6,[rcx]
|
||||
vgf2p8mulb ymm6, ymm5, ymm4
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [rcx]
|
||||
vgf2p8mulb ymm6, ymm5, [rcx]
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [rax+r14*8-123456]
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [rdx+4064]
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [rdx+4096]
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [rdx-4096]
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [rdx-4128]
|
||||
|
||||
# Tests for op ymm/mem256, xmm
|
||||
vcvtpd2dq xmm4,ymm4
|
||||
|
|
@ -2083,6 +2137,24 @@ _start:
|
|||
vshufps ymm2,ymm6,ymm4,7
|
||||
vshufps ymm2,ymm6,YMMWORD PTR [rcx],7
|
||||
vshufps ymm2,ymm6,[rcx],7
|
||||
vgf2p8affineqb ymm6, ymm5, ymm4, 0xab
|
||||
vgf2p8affineqb ymm6, ymm5, ymm4, 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [rcx], 123
|
||||
vgf2p8affineqb ymm6, ymm5, [rcx], 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [rax+r14*8-123456], 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [rdx+4064], 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [rdx+4096], 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [rdx-4096], 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [rdx-4128], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, ymm4, 0xab
|
||||
vgf2p8affineinvqb ymm6, ymm5, ymm4, 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [rcx], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, [rcx], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [rax+r14*8-123456], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [rdx+4064], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [rdx+4096], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [rdx-4096], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [rdx-4128], 123
|
||||
|
||||
# Tests for op ymm, ymm/mem256, ymm, ymm
|
||||
vblendvpd ymm7,ymm2,ymm6,ymm4
|
||||
|
|
@ -2784,6 +2856,15 @@ _start:
|
|||
vcmptrue_usps xmm2,xmm6,xmm4
|
||||
vcmptrue_usps xmm7,xmm6,XMMWORD PTR [rcx]
|
||||
vcmptrue_usps xmm7,xmm6,[rcx]
|
||||
vgf2p8mulb xmm6, xmm5, xmm4
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [rcx]
|
||||
vgf2p8mulb xmm6, xmm5, [rcx]
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [rax+r14*8-123456]
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [rdx+2032]
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [rdx+2048]
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [rdx-2048]
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [rdx-2064]
|
||||
|
||||
|
||||
# Tests for op mem128, xmm, xmm
|
||||
vmaskmovps xmm6,xmm4,XMMWORD PTR [rcx]
|
||||
|
|
@ -2872,6 +2953,25 @@ _start:
|
|||
vshufps xmm2,xmm6,xmm4,7
|
||||
vshufps xmm2,xmm6,XMMWORD PTR [rcx],7
|
||||
vshufps xmm2,xmm6,[rcx],7
|
||||
vgf2p8affineqb xmm6, xmm5, xmm4, 0xab
|
||||
vgf2p8affineqb xmm6, xmm5, xmm4, 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [rcx], 123
|
||||
vgf2p8affineqb xmm6, xmm5, [rcx], 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [rax+r14*8-123456], 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [rdx+2032], 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [rdx+2048], 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [rdx-2048], 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [rdx-2064], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, xmm4, 0xab
|
||||
vgf2p8affineinvqb xmm6, xmm5, xmm4, 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [rcx], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, [rcx], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [rax+r14*8-123456], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [rdx+2032], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [rdx+2048], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [rdx-2048], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [rdx-2064], 123
|
||||
|
||||
|
||||
# Tests for op xmm, xmm/mem128, xmm, xmm
|
||||
vblendvpd xmm7,xmm2,xmm6,xmm4
|
||||
|
|
|
|||
|
|
@ -0,0 +1,46 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: x86_64 AVX512F/GFNI insns (Intel disassembly)
|
||||
#source: x86-64-avx512f_gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 40 ce f4 ab[ ]*vgf2p8affineqb zmm30,zmm29,zmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 47 ce f4 ab[ ]*vgf2p8affineqb zmm30\{k7\},zmm29,zmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 c7 ce f4 ab[ ]*vgf2p8affineqb zmm30\{k7\}\{z\},zmm29,zmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 40 ce b4 f0 23 01 00 00 7b[ ]*vgf2p8affineqb zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 40 ce 72 7f 7b[ ]*vgf2p8affineqb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 50 ce 72 7f 7b[ ]*vgf2p8affineqb zmm30,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 40 cf f4 ab[ ]*vgf2p8affineinvqb zmm30,zmm29,zmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 47 cf f4 ab[ ]*vgf2p8affineinvqb zmm30\{k7\},zmm29,zmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 c7 cf f4 ab[ ]*vgf2p8affineinvqb zmm30\{k7\}\{z\},zmm29,zmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 40 cf b4 f0 23 01 00 00 7b[ ]*vgf2p8affineinvqb zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 40 cf 72 7f 7b[ ]*vgf2p8affineinvqb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 50 cf 72 7f 7b[ ]*vgf2p8affineinvqb zmm30,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 cf f4[ ]*vgf2p8mulb zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 cf f4[ ]*vgf2p8mulb zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 cf f4[ ]*vgf2p8mulb zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 cf b4 f0 23 01 00 00[ ]*vgf2p8mulb zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 cf 72 7f[ ]*vgf2p8mulb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 40 ce f4 ab[ ]*vgf2p8affineqb zmm30,zmm29,zmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 47 ce f4 ab[ ]*vgf2p8affineqb zmm30\{k7\},zmm29,zmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 c7 ce f4 ab[ ]*vgf2p8affineqb zmm30\{k7\}\{z\},zmm29,zmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 40 ce b4 f0 34 12 00 00 7b[ ]*vgf2p8affineqb zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 40 ce 72 7f 7b[ ]*vgf2p8affineqb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 50 ce 72 7f 7b[ ]*vgf2p8affineqb zmm30,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 40 cf f4 ab[ ]*vgf2p8affineinvqb zmm30,zmm29,zmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 47 cf f4 ab[ ]*vgf2p8affineinvqb zmm30\{k7\},zmm29,zmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 c7 cf f4 ab[ ]*vgf2p8affineinvqb zmm30\{k7\}\{z\},zmm29,zmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 40 cf b4 f0 34 12 00 00 7b[ ]*vgf2p8affineinvqb zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 40 cf 72 7f 7b[ ]*vgf2p8affineinvqb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 50 cf b2 00 04 00 00 7b[ ]*vgf2p8affineinvqb zmm30,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 cf f4[ ]*vgf2p8mulb zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 cf f4[ ]*vgf2p8mulb zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 cf f4[ ]*vgf2p8mulb zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 cf b4 f0 34 12 00 00[ ]*vgf2p8mulb zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 cf 72 7f[ ]*vgf2p8mulb zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
#pass
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86_64 AVX512F/GFNI insns
|
||||
#source: x86-64-avx512f_gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 40 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 47 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 c7 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 40 ce b4 f0 23 01 00 00 7b[ ]*vgf2p8affineqb \$0x7b,0x123\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 40 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 50 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 40 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 47 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 c7 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 40 cf b4 f0 23 01 00 00 7b[ ]*vgf2p8affineinvqb \$0x7b,0x123\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 40 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 50 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 cf f4[ ]*vgf2p8mulb %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 cf f4[ ]*vgf2p8mulb %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 cf f4[ ]*vgf2p8mulb %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 cf b4 f0 23 01 00 00[ ]*vgf2p8mulb 0x123\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 cf 72 7f[ ]*vgf2p8mulb 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 40 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 47 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 c7 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 40 ce b4 f0 34 12 00 00 7b[ ]*vgf2p8affineqb \$0x7b,0x1234\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 40 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 50 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 40 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 47 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 c7 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 40 cf b4 f0 34 12 00 00 7b[ ]*vgf2p8affineinvqb \$0x7b,0x1234\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 40 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 50 cf b2 00 04 00 00 7b[ ]*vgf2p8affineinvqb \$0x7b,0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 40 cf f4[ ]*vgf2p8mulb %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 47 cf f4[ ]*vgf2p8mulb %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 c7 cf f4[ ]*vgf2p8mulb %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 40 cf b4 f0 34 12 00 00[ ]*vgf2p8mulb 0x1234\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 40 cf 72 7f[ ]*vgf2p8mulb 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
#pass
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
# Check 64bit AVX512F,GFNI instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vgf2p8affineqb $0xab, %zmm28, %zmm29, %zmm30 # AVX512F,GFNI
|
||||
vgf2p8affineqb $0xab, %zmm28, %zmm29, %zmm30{%k7} # AVX512F,GFNI
|
||||
vgf2p8affineqb $0xab, %zmm28, %zmm29, %zmm30{%k7}{z} # AVX512F,GFNI
|
||||
vgf2p8affineqb $123, 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512F,GFNI
|
||||
vgf2p8affineqb $123, 8128(%rdx), %zmm29, %zmm30 # AVX512F,GFNI Disp8
|
||||
vgf2p8affineqb $123, 1016(%rdx){1to8}, %zmm29, %zmm30 # AVX512F,GFNI Disp8
|
||||
|
||||
vgf2p8affineinvqb $0xab, %zmm28, %zmm29, %zmm30 # AVX512F,GFNI
|
||||
vgf2p8affineinvqb $0xab, %zmm28, %zmm29, %zmm30{%k7} # AVX512F,GFNI
|
||||
vgf2p8affineinvqb $0xab, %zmm28, %zmm29, %zmm30{%k7}{z} # AVX512F,GFNI
|
||||
vgf2p8affineinvqb $123, 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512F,GFNI
|
||||
vgf2p8affineinvqb $123, 8128(%rdx), %zmm29, %zmm30 # AVX512F,GFNI Disp8
|
||||
vgf2p8affineinvqb $123, 1016(%rdx){1to8}, %zmm29, %zmm30 # AVX512F,GFNI Disp8
|
||||
|
||||
vgf2p8mulb %zmm28, %zmm29, %zmm30 # AVX512F,GFNI
|
||||
vgf2p8mulb %zmm28, %zmm29, %zmm30{%k7} # AVX512F,GFNI
|
||||
vgf2p8mulb %zmm28, %zmm29, %zmm30{%k7}{z} # AVX512F,GFNI
|
||||
vgf2p8mulb 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512F,GFNI
|
||||
vgf2p8mulb 8128(%rdx), %zmm29, %zmm30 # AVX512F,GFNI Disp8
|
||||
|
||||
.intel_syntax noprefix
|
||||
vgf2p8affineqb zmm30, zmm29, zmm28, 0xab # AVX512F,GFNI
|
||||
vgf2p8affineqb zmm30{k7}, zmm29, zmm28, 0xab # AVX512F,GFNI
|
||||
vgf2p8affineqb zmm30{k7}{z}, zmm29, zmm28, 0xab # AVX512F,GFNI
|
||||
vgf2p8affineqb zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512F,GFNI
|
||||
vgf2p8affineqb zmm30, zmm29, ZMMWORD PTR [rdx+8128], 123 # AVX512F,GFNI Disp8
|
||||
vgf2p8affineqb zmm30, zmm29, [rdx+1016]{1to8}, 123 # AVX512F,GFNI Disp8
|
||||
|
||||
vgf2p8affineinvqb zmm30, zmm29, zmm28, 0xab # AVX512F,GFNI
|
||||
vgf2p8affineinvqb zmm30{k7}, zmm29, zmm28, 0xab # AVX512F,GFNI
|
||||
vgf2p8affineinvqb zmm30{k7}{z}, zmm29, zmm28, 0xab # AVX512F,GFNI
|
||||
vgf2p8affineinvqb zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512F,GFNI
|
||||
vgf2p8affineinvqb zmm30, zmm29, ZMMWORD PTR [rdx+8128], 123 # AVX512F,GFNI Disp8
|
||||
vgf2p8affineinvqb zmm30, zmm29, [rdx+1024]{1to8}, 123 # AVX512F,GFNI
|
||||
|
||||
vgf2p8mulb zmm30, zmm29, zmm28 # AVX512F,GFNI
|
||||
vgf2p8mulb zmm30{k7}, zmm29, zmm28 # AVX512F,GFNI
|
||||
vgf2p8mulb zmm30{k7}{z}, zmm29, zmm28 # AVX512F,GFNI
|
||||
vgf2p8mulb zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512F,GFNI
|
||||
vgf2p8mulb zmm30, zmm29, ZMMWORD PTR [rdx+8128] # AVX512F,GFNI Disp8
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: x86_64 AVX512VL/GFNI insns (Intel disassembly)
|
||||
#source: x86-64-avx512vl_gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 00 ce f4 ab[ ]*vgf2p8affineqb xmm30,xmm29,xmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 07 ce f4 ab[ ]*vgf2p8affineqb xmm30\{k7\},xmm29,xmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 87 ce f4 ab[ ]*vgf2p8affineqb xmm30\{k7\}\{z\},xmm29,xmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 00 ce b4 f0 23 01 00 00 7b[ ]*vgf2p8affineqb xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 00 ce 72 7f 7b[ ]*vgf2p8affineqb xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 10 ce 72 7f 7b[ ]*vgf2p8affineqb xmm30,xmm29,QWORD PTR \[rdx\+0x3f8\]\{1to2\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 20 ce f4 ab[ ]*vgf2p8affineqb ymm30,ymm29,ymm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 27 ce f4 ab[ ]*vgf2p8affineqb ymm30\{k7\},ymm29,ymm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 a7 ce f4 ab[ ]*vgf2p8affineqb ymm30\{k7\}\{z\},ymm29,ymm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 20 ce b4 f0 23 01 00 00 7b[ ]*vgf2p8affineqb ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 20 ce 72 7f 7b[ ]*vgf2p8affineqb ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 30 ce 72 7f 7b[ ]*vgf2p8affineqb ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 00 cf f4 ab[ ]*vgf2p8affineinvqb xmm30,xmm29,xmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 07 cf f4 ab[ ]*vgf2p8affineinvqb xmm30\{k7\},xmm29,xmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 87 cf f4 ab[ ]*vgf2p8affineinvqb xmm30\{k7\}\{z\},xmm29,xmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 00 cf b4 f0 23 01 00 00 7b[ ]*vgf2p8affineinvqb xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 00 cf 72 7f 7b[ ]*vgf2p8affineinvqb xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 10 cf 72 7f 7b[ ]*vgf2p8affineinvqb xmm30,xmm29,QWORD PTR \[rdx\+0x3f8\]\{1to2\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 20 cf f4 ab[ ]*vgf2p8affineinvqb ymm30,ymm29,ymm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 27 cf f4 ab[ ]*vgf2p8affineinvqb ymm30\{k7\},ymm29,ymm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 a7 cf f4 ab[ ]*vgf2p8affineinvqb ymm30\{k7\}\{z\},ymm29,ymm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 20 cf b4 f0 23 01 00 00 7b[ ]*vgf2p8affineinvqb ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 20 cf 72 7f 7b[ ]*vgf2p8affineinvqb ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 30 cf 72 7f 7b[ ]*vgf2p8affineinvqb ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 cf f4[ ]*vgf2p8mulb xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 cf f4[ ]*vgf2p8mulb xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 cf f4[ ]*vgf2p8mulb xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 cf b4 f0 23 01 00 00[ ]*vgf2p8mulb xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 cf 72 7f[ ]*vgf2p8mulb xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 cf f4[ ]*vgf2p8mulb ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 cf f4[ ]*vgf2p8mulb ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 cf f4[ ]*vgf2p8mulb ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 cf b4 f0 23 01 00 00[ ]*vgf2p8mulb ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 cf 72 7f[ ]*vgf2p8mulb ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 00 ce f4 ab[ ]*vgf2p8affineqb xmm30,xmm29,xmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 07 ce f4 ab[ ]*vgf2p8affineqb xmm30\{k7\},xmm29,xmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 87 ce f4 ab[ ]*vgf2p8affineqb xmm30\{k7\}\{z\},xmm29,xmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 00 ce b4 f0 34 12 00 00 7b[ ]*vgf2p8affineqb xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 00 ce 72 7f 7b[ ]*vgf2p8affineqb xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 10 ce 72 7f 7b[ ]*vgf2p8affineqb xmm30,xmm29,QWORD PTR \[rdx\+0x3f8\]\{1to2\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 20 ce f4 ab[ ]*vgf2p8affineqb ymm30,ymm29,ymm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 27 ce f4 ab[ ]*vgf2p8affineqb ymm30\{k7\},ymm29,ymm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 a7 ce f4 ab[ ]*vgf2p8affineqb ymm30\{k7\}\{z\},ymm29,ymm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 20 ce b4 f0 34 12 00 00 7b[ ]*vgf2p8affineqb ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 20 ce 72 7f 7b[ ]*vgf2p8affineqb ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 30 ce 72 7f 7b[ ]*vgf2p8affineqb ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 00 cf f4 ab[ ]*vgf2p8affineinvqb xmm30,xmm29,xmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 07 cf f4 ab[ ]*vgf2p8affineinvqb xmm30\{k7\},xmm29,xmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 87 cf f4 ab[ ]*vgf2p8affineinvqb xmm30\{k7\}\{z\},xmm29,xmm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 00 cf b4 f0 34 12 00 00 7b[ ]*vgf2p8affineinvqb xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 00 cf 72 7f 7b[ ]*vgf2p8affineinvqb xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 10 cf 72 7f 7b[ ]*vgf2p8affineinvqb xmm30,xmm29,QWORD PTR \[rdx\+0x3f8\]\{1to2\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 20 cf f4 ab[ ]*vgf2p8affineinvqb ymm30,ymm29,ymm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 27 cf f4 ab[ ]*vgf2p8affineinvqb ymm30\{k7\},ymm29,ymm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 a7 cf f4 ab[ ]*vgf2p8affineinvqb ymm30\{k7\}\{z\},ymm29,ymm28,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 20 cf b4 f0 34 12 00 00 7b[ ]*vgf2p8affineinvqb ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 20 cf 72 7f 7b[ ]*vgf2p8affineinvqb ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 30 cf b2 00 04 00 00 7b[ ]*vgf2p8affineinvqb ymm30,ymm29,QWORD PTR \[rdx\+0x400\]\{1to4\},0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 cf f4[ ]*vgf2p8mulb xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 cf f4[ ]*vgf2p8mulb xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 cf f4[ ]*vgf2p8mulb xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 cf b4 f0 34 12 00 00[ ]*vgf2p8mulb xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 cf 72 7f[ ]*vgf2p8mulb xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 cf f4[ ]*vgf2p8mulb ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 cf f4[ ]*vgf2p8mulb ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 cf f4[ ]*vgf2p8mulb ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 cf b4 f0 34 12 00 00[ ]*vgf2p8mulb ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 cf 72 7f[ ]*vgf2p8mulb ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
#pass
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86_64 AVX512VL/GFNI insns
|
||||
#source: x86-64-avx512vl_gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 00 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 07 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 87 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 00 ce b4 f0 23 01 00 00 7b[ ]*vgf2p8affineqb \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 00 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 10 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 20 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 27 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 a7 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 20 ce b4 f0 23 01 00 00 7b[ ]*vgf2p8affineqb \$0x7b,0x123\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 20 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 30 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 00 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 07 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 87 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 00 cf b4 f0 23 01 00 00 7b[ ]*vgf2p8affineinvqb \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 00 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 10 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 20 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 27 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 a7 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 20 cf b4 f0 23 01 00 00 7b[ ]*vgf2p8affineinvqb \$0x7b,0x123\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 20 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 30 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 cf f4[ ]*vgf2p8mulb %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 cf f4[ ]*vgf2p8mulb %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 cf f4[ ]*vgf2p8mulb %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 cf b4 f0 23 01 00 00[ ]*vgf2p8mulb 0x123\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 cf 72 7f[ ]*vgf2p8mulb 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 cf f4[ ]*vgf2p8mulb %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 cf f4[ ]*vgf2p8mulb %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 cf f4[ ]*vgf2p8mulb %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 cf b4 f0 23 01 00 00[ ]*vgf2p8mulb 0x123\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 cf 72 7f[ ]*vgf2p8mulb 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 00 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 07 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 87 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 00 ce b4 f0 34 12 00 00 7b[ ]*vgf2p8affineqb \$0x7b,0x1234\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 00 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 10 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 20 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 27 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 a7 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 20 ce b4 f0 34 12 00 00 7b[ ]*vgf2p8affineqb \$0x7b,0x1234\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 20 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 30 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 00 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 07 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 87 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 00 cf b4 f0 34 12 00 00 7b[ ]*vgf2p8affineinvqb \$0x7b,0x1234\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 00 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 10 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 20 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 27 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 03 95 a7 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 23 95 20 cf b4 f0 34 12 00 00 7b[ ]*vgf2p8affineinvqb \$0x7b,0x1234\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 20 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 95 30 cf b2 00 04 00 00 7b[ ]*vgf2p8affineinvqb \$0x7b,0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 00 cf f4[ ]*vgf2p8mulb %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 07 cf f4[ ]*vgf2p8mulb %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 87 cf f4[ ]*vgf2p8mulb %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 00 cf b4 f0 34 12 00 00[ ]*vgf2p8mulb 0x1234\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 00 cf 72 7f[ ]*vgf2p8mulb 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 20 cf f4[ ]*vgf2p8mulb %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 27 cf f4[ ]*vgf2p8mulb %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 15 a7 cf f4[ ]*vgf2p8mulb %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 15 20 cf b4 f0 34 12 00 00[ ]*vgf2p8mulb 0x1234\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 15 20 cf 72 7f[ ]*vgf2p8mulb 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
#pass
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
# Check 64bit AVX512VL,GFNI instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vgf2p8affineqb $0xab, %xmm28, %xmm29, %xmm30 # AVX512VL,GFNI
|
||||
vgf2p8affineqb $0xab, %xmm28, %xmm29, %xmm30{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineqb $0xab, %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512VL,GFNI
|
||||
vgf2p8affineqb $123, 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512VL,GFNI
|
||||
vgf2p8affineqb $123, 2032(%rdx), %xmm29, %xmm30 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineqb $123, 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineqb $0xab, %ymm28, %ymm29, %ymm30 # AVX512VL,GFNI
|
||||
vgf2p8affineqb $0xab, %ymm28, %ymm29, %ymm30{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineqb $0xab, %ymm28, %ymm29, %ymm30{%k7}{z} # AVX512VL,GFNI
|
||||
vgf2p8affineqb $123, 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512VL,GFNI
|
||||
vgf2p8affineqb $123, 4064(%rdx), %ymm29, %ymm30 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineqb $123, 1016(%rdx){1to4}, %ymm29, %ymm30 # AVX512VL,GFNI Disp8
|
||||
|
||||
vgf2p8affineinvqb $0xab, %xmm28, %xmm29, %xmm30 # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $0xab, %xmm28, %xmm29, %xmm30{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $0xab, %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $123, 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $123, 2032(%rdx), %xmm29, %xmm30 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineinvqb $123, 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineinvqb $0xab, %ymm28, %ymm29, %ymm30 # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $0xab, %ymm28, %ymm29, %ymm30{%k7} # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $0xab, %ymm28, %ymm29, %ymm30{%k7}{z} # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $123, 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb $123, 4064(%rdx), %ymm29, %ymm30 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineinvqb $123, 1016(%rdx){1to4}, %ymm29, %ymm30 # AVX512VL,GFNI Disp8
|
||||
|
||||
vgf2p8mulb %xmm28, %xmm29, %xmm30 # AVX512VL,GFNI
|
||||
vgf2p8mulb %xmm28, %xmm29, %xmm30{%k7} # AVX512VL,GFNI
|
||||
vgf2p8mulb %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512VL,GFNI
|
||||
vgf2p8mulb 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512VL,GFNI
|
||||
vgf2p8mulb 2032(%rdx), %xmm29, %xmm30 # AVX512VL,GFNI Disp8
|
||||
vgf2p8mulb %ymm28, %ymm29, %ymm30 # AVX512VL,GFNI
|
||||
vgf2p8mulb %ymm28, %ymm29, %ymm30{%k7} # AVX512VL,GFNI
|
||||
vgf2p8mulb %ymm28, %ymm29, %ymm30{%k7}{z} # AVX512VL,GFNI
|
||||
vgf2p8mulb 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512VL,GFNI
|
||||
vgf2p8mulb 4064(%rdx), %ymm29, %ymm30 # AVX512VL,GFNI Disp8
|
||||
|
||||
.intel_syntax noprefix
|
||||
vgf2p8affineqb xmm30, xmm29, xmm28, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineqb xmm30{k7}, xmm29, xmm28, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineqb xmm30{k7}{z}, xmm29, xmm28, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineqb xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,GFNI
|
||||
vgf2p8affineqb xmm30, xmm29, XMMWORD PTR [rdx+2032], 123 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineqb xmm30, xmm29, [rdx+1016]{1to2}, 123 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineqb ymm30, ymm29, ymm28, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineqb ymm30{k7}, ymm29, ymm28, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineqb ymm30{k7}{z}, ymm29, ymm28, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineqb ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,GFNI
|
||||
vgf2p8affineqb ymm30, ymm29, YMMWORD PTR [rdx+4064], 123 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineqb ymm30, ymm29, [rdx+1016]{1to4}, 123 # AVX512VL,GFNI Disp8
|
||||
|
||||
vgf2p8affineinvqb xmm30, xmm29, xmm28, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb xmm30{k7}, xmm29, xmm28, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb xmm30{k7}{z}, xmm29, xmm28, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb xmm30, xmm29, XMMWORD PTR [rdx+2032], 123 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineinvqb xmm30, xmm29, [rdx+1016]{1to2}, 123 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineinvqb ymm30, ymm29, ymm28, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb ymm30{k7}, ymm29, ymm28, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb ymm30{k7}{z}, ymm29, ymm28, 0xab # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,GFNI
|
||||
vgf2p8affineinvqb ymm30, ymm29, YMMWORD PTR [rdx+4064], 123 # AVX512VL,GFNI Disp8
|
||||
vgf2p8affineinvqb ymm30, ymm29, [rdx+1024]{1to4}, 123 # AVX512VL,GFNI
|
||||
|
||||
vgf2p8mulb xmm30, xmm29, xmm28 # AVX512VL,GFNI
|
||||
vgf2p8mulb xmm30{k7}, xmm29, xmm28 # AVX512VL,GFNI
|
||||
vgf2p8mulb xmm30{k7}{z}, xmm29, xmm28 # AVX512VL,GFNI
|
||||
vgf2p8mulb xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512VL,GFNI
|
||||
vgf2p8mulb xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512VL,GFNI Disp8
|
||||
vgf2p8mulb ymm30, ymm29, ymm28 # AVX512VL,GFNI
|
||||
vgf2p8mulb ymm30{k7}, ymm29, ymm28 # AVX512VL,GFNI
|
||||
vgf2p8mulb ymm30{k7}{z}, ymm29, ymm28 # AVX512VL,GFNI
|
||||
vgf2p8mulb ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512VL,GFNI
|
||||
vgf2p8mulb ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512VL,GFNI Disp8
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: x86_64 AVX/GFNI insns (Intel disassembly)
|
||||
#source: x86-64-avx_gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 55 cf f4[ ]*vgf2p8mulb ymm6,ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a2 55 cf b4 f0 c0 1d fe ff[ ]*vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 55 cf 72 7e[ ]*vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0x7e\]
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 ce f4 ab[ ]*vgf2p8affineqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d5 ce b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 ce 72 7e 7b[ ]*vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x7e\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 cf f4 ab[ ]*vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d5 cf b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 cf 72 7e 7b[ ]*vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x7e\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 51 cf f4[ ]*vgf2p8mulb xmm6,xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a2 51 cf b4 f0 c0 1d fe ff[ ]*vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 51 cf 72 7e[ ]*vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7e\]
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 ce f4 ab[ ]*vgf2p8affineqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d1 ce b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 ce 72 7e 7b[ ]*vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7e\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 cf f4 ab[ ]*vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d1 cf b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 cf 72 7e 7b[ ]*vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7e\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 55 cf f4[ ]*vgf2p8mulb ymm6,ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a2 55 cf b4 f0 c0 1d fe ff[ ]*vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 55 cf 72 7e[ ]*vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0x7e\]
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 ce f4 ab[ ]*vgf2p8affineqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d5 ce b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 ce 72 7e 7b[ ]*vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x7e\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 cf f4 ab[ ]*vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d5 cf b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 cf 72 7e 7b[ ]*vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x7e\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 51 cf f4[ ]*vgf2p8mulb xmm6,xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a2 51 cf b4 f0 c0 1d fe ff[ ]*vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 51 cf 72 7e[ ]*vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7e\]
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 ce f4 ab[ ]*vgf2p8affineqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d1 ce b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 ce 72 7e 7b[ ]*vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7e\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 cf f4 ab[ ]*vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d1 cf b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 cf 72 7e 7b[ ]*vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7e\],0x7b
|
||||
#pass
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86_64 AVX/GFNI insns
|
||||
#source: x86-64-avx_gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 55 cf f4[ ]*vgf2p8mulb %ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a2 55 cf b4 f0 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 55 cf 72 7e[ ]*vgf2p8mulb 0x7e\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d5 ce b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 ce 72 7e 7b[ ]*vgf2p8affineqb \$0x7b,0x7e\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d5 cf b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 cf 72 7e 7b[ ]*vgf2p8affineinvqb \$0x7b,0x7e\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 51 cf f4[ ]*vgf2p8mulb %xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a2 51 cf b4 f0 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 51 cf 72 7e[ ]*vgf2p8mulb 0x7e\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d1 ce b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 ce 72 7e 7b[ ]*vgf2p8affineqb \$0x7b,0x7e\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d1 cf b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 cf 72 7e 7b[ ]*vgf2p8affineinvqb \$0x7b,0x7e\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 55 cf f4[ ]*vgf2p8mulb %ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a2 55 cf b4 f0 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 55 cf 72 7e[ ]*vgf2p8mulb 0x7e\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d5 ce b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 ce 72 7e 7b[ ]*vgf2p8affineqb \$0x7b,0x7e\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d5 cf b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d5 cf 72 7e 7b[ ]*vgf2p8affineinvqb \$0x7b,0x7e\(%rdx\),%ymm5,%ymm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 51 cf f4[ ]*vgf2p8mulb %xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a2 51 cf b4 f0 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e2 51 cf 72 7e[ ]*vgf2p8mulb 0x7e\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d1 ce b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 ce 72 7e 7b[ ]*vgf2p8affineqb \$0x7b,0x7e\(%rdx\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 a3 d1 cf b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
|
||||
[ ]*[a-f0-9]+:[ ]*c4 e3 d1 cf 72 7e 7b[ ]*vgf2p8affineinvqb \$0x7b,0x7e\(%rdx\),%xmm5,%xmm6
|
||||
#pass
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
# Check AVX GFNI instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vgf2p8mulb %ymm4, %ymm5, %ymm6
|
||||
vgf2p8mulb -123456(%rax,%r14,8), %ymm5, %ymm6
|
||||
vgf2p8mulb 126(%rdx), %ymm5, %ymm6
|
||||
|
||||
vgf2p8affineqb $0xab, %ymm4, %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, -123456(%rax,%r14,8), %ymm5, %ymm6
|
||||
vgf2p8affineqb $123, 126(%rdx), %ymm5, %ymm6
|
||||
|
||||
vgf2p8affineinvqb $0xab, %ymm4, %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, -123456(%rax,%r14,8), %ymm5, %ymm6
|
||||
vgf2p8affineinvqb $123, 126(%rdx), %ymm5, %ymm6
|
||||
|
||||
vgf2p8mulb %xmm4, %xmm5, %xmm6
|
||||
vgf2p8mulb -123456(%rax,%r14,8), %xmm5, %xmm6
|
||||
vgf2p8mulb 126(%rdx), %xmm5, %xmm6
|
||||
|
||||
vgf2p8affineqb $0xab, %xmm4, %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, -123456(%rax,%r14,8), %xmm5, %xmm6
|
||||
vgf2p8affineqb $123, 126(%rdx), %xmm5, %xmm6
|
||||
|
||||
vgf2p8affineinvqb $0xab, %xmm4, %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, -123456(%rax,%r14,8), %xmm5, %xmm6
|
||||
vgf2p8affineinvqb $123, 126(%rdx), %xmm5, %xmm6
|
||||
|
||||
.intel_syntax noprefix
|
||||
|
||||
vgf2p8mulb ymm6, ymm5, ymm4
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [rax+r14*8-123456]
|
||||
vgf2p8mulb ymm6, ymm5, YMMWORD PTR [rdx+126]
|
||||
|
||||
vgf2p8affineqb ymm6, ymm5, ymm4, 0xab
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [rax+r14*8-123456], 123
|
||||
vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [rdx+126], 123
|
||||
|
||||
vgf2p8affineinvqb ymm6, ymm5, ymm4, 0xab
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [rax+r14*8-123456], 123
|
||||
vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [rdx+126], 123
|
||||
|
||||
vgf2p8mulb xmm6, xmm5, xmm4
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [rax+r14*8-123456]
|
||||
vgf2p8mulb xmm6, xmm5, XMMWORD PTR [rdx+126]
|
||||
|
||||
vgf2p8affineqb xmm6, xmm5, xmm4, 0xab
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [rax+r14*8-123456], 123
|
||||
vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [rdx+126], 123
|
||||
|
||||
vgf2p8affineinvqb xmm6, xmm5, xmm4, 0xab
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [rax+r14*8-123456], 123
|
||||
vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [rdx+126], 123
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: x86_64 GFNI insns (Intel disassembly)
|
||||
#source: x86-64-gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ec[ ]*gf2p8mulb xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*66 42 0f 38 cf ac f0 c0 1d fe ff[ ]*gf2p8mulb xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf aa f0 07 00 00[ ]*gf2p8mulb xmm5,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ec ab[ ]*gf2p8affineqb xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*66 42 0f 3a ce ac f0 c0 1d fe ff 7b[ ]*gf2p8affineqb xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce aa f0 07 00 00 7b[ ]*gf2p8affineqb xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ec ab[ ]*gf2p8affineinvqb xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*66 42 0f 3a cf ac f0 c0 1d fe ff 7b[ ]*gf2p8affineinvqb xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf aa f0 07 00 00 7b[ ]*gf2p8affineinvqb xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ec[ ]*gf2p8mulb xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*66 42 0f 38 cf ac f0 c0 1d fe ff[ ]*gf2p8mulb xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf aa f0 07 00 00[ ]*gf2p8mulb xmm5,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ec ab[ ]*gf2p8affineqb xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*66 42 0f 3a ce ac f0 c0 1d fe ff 7b[ ]*gf2p8affineqb xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce aa f0 07 00 00 7b[ ]*gf2p8affineqb xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ec ab[ ]*gf2p8affineinvqb xmm5,xmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*66 42 0f 3a cf ac f0 c0 1d fe ff 7b[ ]*gf2p8affineinvqb xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf aa f0 07 00 00 7b[ ]*gf2p8affineinvqb xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
|
||||
#pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86_64 GFNI insns
|
||||
#source: x86-64-gfni.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ec[ ]*gf2p8mulb %xmm4,%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 42 0f 38 cf ac f0 c0 1d fe ff[ ]*gf2p8mulb -0x1e240\(%rax,%r14,8\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf aa f0 07 00 00[ ]*gf2p8mulb 0x7f0\(%rdx\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ec ab[ ]*gf2p8affineqb \$0xab,%xmm4,%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 42 0f 3a ce ac f0 c0 1d fe ff 7b[ ]*gf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce aa f0 07 00 00 7b[ ]*gf2p8affineqb \$0x7b,0x7f0\(%rdx\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ec ab[ ]*gf2p8affineinvqb \$0xab,%xmm4,%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 42 0f 3a cf ac f0 c0 1d fe ff 7b[ ]*gf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf aa f0 07 00 00 7b[ ]*gf2p8affineinvqb \$0x7b,0x7f0\(%rdx\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ec[ ]*gf2p8mulb %xmm4,%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 42 0f 38 cf ac f0 c0 1d fe ff[ ]*gf2p8mulb -0x1e240\(%rax,%r14,8\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 38 cf aa f0 07 00 00[ ]*gf2p8mulb 0x7f0\(%rdx\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ec ab[ ]*gf2p8affineqb \$0xab,%xmm4,%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 42 0f 3a ce ac f0 c0 1d fe ff 7b[ ]*gf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a ce aa f0 07 00 00 7b[ ]*gf2p8affineqb \$0x7b,0x7f0\(%rdx\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ec ab[ ]*gf2p8affineinvqb \$0xab,%xmm4,%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 42 0f 3a cf ac f0 c0 1d fe ff 7b[ ]*gf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*66 0f 3a cf aa f0 07 00 00 7b[ ]*gf2p8affineinvqb \$0x7b,0x7f0\(%rdx\),%xmm5
|
||||
#pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# Check 64bit GFNI instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
gf2p8mulb %xmm4, %xmm5
|
||||
gf2p8mulb -123456(%rax,%r14,8), %xmm5
|
||||
gf2p8mulb 2032(%rdx), %xmm5
|
||||
|
||||
gf2p8affineqb $0xab, %xmm4, %xmm5
|
||||
gf2p8affineqb $123, -123456(%rax,%r14,8), %xmm5
|
||||
gf2p8affineqb $123, 2032(%rdx), %xmm5
|
||||
|
||||
gf2p8affineinvqb $0xab, %xmm4, %xmm5
|
||||
gf2p8affineinvqb $123, -123456(%rax,%r14,8), %xmm5
|
||||
gf2p8affineinvqb $123, 2032(%rdx), %xmm5
|
||||
|
||||
.intel_syntax noprefix
|
||||
|
||||
gf2p8mulb xmm5, xmm4
|
||||
gf2p8mulb xmm5, XMMWORD PTR [rax+r14*8-123456]
|
||||
gf2p8mulb xmm5, XMMWORD PTR [rdx+2032]
|
||||
|
||||
gf2p8affineqb xmm5, xmm4, 0xab
|
||||
gf2p8affineqb xmm5, XMMWORD PTR [rax+r14*8-123456], 123
|
||||
gf2p8affineqb xmm5, XMMWORD PTR [rdx+2032], 123
|
||||
|
||||
gf2p8affineinvqb xmm5, xmm4, 0xab
|
||||
gf2p8affineinvqb xmm5, XMMWORD PTR [rax+r14*8-123456], 123
|
||||
gf2p8affineinvqb xmm5, XMMWORD PTR [rdx+2032], 123
|
||||
|
|
@ -527,7 +527,7 @@ static const struct dis386 evex_table[][256] = {
|
|||
{ PREFIX_TABLE (PREFIX_EVEX_0F38CC) },
|
||||
{ PREFIX_TABLE (PREFIX_EVEX_0F38CD) },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_EVEX_0F38CF) },
|
||||
/* D0 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -817,8 +817,8 @@ static const struct dis386 evex_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_EVEX_0F3ACE) },
|
||||
{ PREFIX_TABLE (PREFIX_EVEX_0F3ACF) },
|
||||
/* D0 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -2533,6 +2533,12 @@ static const struct dis386 evex_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ "vrsqrt28s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexS }, 0 },
|
||||
},
|
||||
/* PREFIX_EVEX_0F38CF */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "vgf2p8mulb", { XM, Vex, EXx }, 0 },
|
||||
},
|
||||
/* PREFIX_EVEX_0F3A00 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -2821,6 +2827,18 @@ static const struct dis386 evex_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ VEX_W_TABLE (EVEX_W_0F3A73_P_2) },
|
||||
},
|
||||
/* PREFIX_EVEX_0F3ACE */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ VEX_W_TABLE (EVEX_W_0F3ACE_P_2) },
|
||||
},
|
||||
/* PREFIX_EVEX_0F3ACF */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ VEX_W_TABLE (EVEX_W_0F3ACF_P_2) },
|
||||
},
|
||||
#endif /* NEED_PREFIX_TABLE */
|
||||
|
||||
#ifdef NEED_VEX_W_TABLE
|
||||
|
|
@ -3947,6 +3965,16 @@ static const struct dis386 evex_table[][256] = {
|
|||
{ "vpshrdd", { XM, Vex, EXx, Ib }, 0 },
|
||||
{ "vpshrdq", { XM, Vex, EXx, Ib }, 0 },
|
||||
},
|
||||
/* EVEX_W_0F3ACE_P_2 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
|
||||
},
|
||||
/* EVEX_W_0F3ACF_P_2 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
|
||||
},
|
||||
#endif /* NEED_VEX_W_TABLE */
|
||||
#ifdef NEED_MOD_TABLE
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1059,6 +1059,7 @@ enum
|
|||
PREFIX_0F38CB,
|
||||
PREFIX_0F38CC,
|
||||
PREFIX_0F38CD,
|
||||
PREFIX_0F38CF,
|
||||
PREFIX_0F38DB,
|
||||
PREFIX_0F38DC,
|
||||
PREFIX_0F38DD,
|
||||
|
|
@ -1091,6 +1092,8 @@ enum
|
|||
PREFIX_0F3A62,
|
||||
PREFIX_0F3A63,
|
||||
PREFIX_0F3ACC,
|
||||
PREFIX_0F3ACE,
|
||||
PREFIX_0F3ACF,
|
||||
PREFIX_0F3ADF,
|
||||
PREFIX_VEX_0F10,
|
||||
PREFIX_VEX_0F11,
|
||||
|
|
@ -1312,6 +1315,7 @@ enum
|
|||
PREFIX_VEX_0F38BD,
|
||||
PREFIX_VEX_0F38BE,
|
||||
PREFIX_VEX_0F38BF,
|
||||
PREFIX_VEX_0F38CF,
|
||||
PREFIX_VEX_0F38DB,
|
||||
PREFIX_VEX_0F38DC,
|
||||
PREFIX_VEX_0F38DD,
|
||||
|
|
@ -1388,6 +1392,8 @@ enum
|
|||
PREFIX_VEX_0F3A7D,
|
||||
PREFIX_VEX_0F3A7E,
|
||||
PREFIX_VEX_0F3A7F,
|
||||
PREFIX_VEX_0F3ACE,
|
||||
PREFIX_VEX_0F3ACF,
|
||||
PREFIX_VEX_0F3ADF,
|
||||
PREFIX_VEX_0F3AF0,
|
||||
|
||||
|
|
@ -1653,6 +1659,7 @@ enum
|
|||
PREFIX_EVEX_0F38CB,
|
||||
PREFIX_EVEX_0F38CC,
|
||||
PREFIX_EVEX_0F38CD,
|
||||
PREFIX_EVEX_0F38CF,
|
||||
|
||||
PREFIX_EVEX_0F3A00,
|
||||
PREFIX_EVEX_0F3A01,
|
||||
|
|
@ -1701,7 +1708,9 @@ enum
|
|||
PREFIX_EVEX_0F3A70,
|
||||
PREFIX_EVEX_0F3A71,
|
||||
PREFIX_EVEX_0F3A72,
|
||||
PREFIX_EVEX_0F3A73
|
||||
PREFIX_EVEX_0F3A73,
|
||||
PREFIX_EVEX_0F3ACE,
|
||||
PREFIX_EVEX_0F3ACF
|
||||
};
|
||||
|
||||
enum
|
||||
|
|
@ -2180,6 +2189,7 @@ enum
|
|||
VEX_W_0F385A_P_2_M_0,
|
||||
VEX_W_0F3878_P_2,
|
||||
VEX_W_0F3879_P_2,
|
||||
VEX_W_0F38CF_P_2,
|
||||
VEX_W_0F38DB_P_2,
|
||||
VEX_W_0F38DC_P_2,
|
||||
VEX_W_0F38DD_P_2,
|
||||
|
|
@ -2223,6 +2233,8 @@ enum
|
|||
VEX_W_0F3A4C_P_2,
|
||||
VEX_W_0F3A62_P_2,
|
||||
VEX_W_0F3A63_P_2,
|
||||
VEX_W_0F3ACE_P_2,
|
||||
VEX_W_0F3ACF_P_2,
|
||||
VEX_W_0F3ADF_P_2,
|
||||
|
||||
EVEX_W_0F10_P_0,
|
||||
|
|
@ -2469,7 +2481,9 @@ enum
|
|||
EVEX_W_0F3A70_P_2,
|
||||
EVEX_W_0F3A71_P_2,
|
||||
EVEX_W_0F3A72_P_2,
|
||||
EVEX_W_0F3A73_P_2
|
||||
EVEX_W_0F3A73_P_2,
|
||||
EVEX_W_0F3ACE_P_2,
|
||||
EVEX_W_0F3ACF_P_2
|
||||
};
|
||||
|
||||
typedef void (*op_rtn) (int bytemode, int sizeflag);
|
||||
|
|
@ -4549,6 +4563,13 @@ static const struct dis386 prefix_table[][4] = {
|
|||
{ "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
|
||||
},
|
||||
|
||||
/* PREFIX_0F38CF */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
|
||||
},
|
||||
|
||||
/* PREFIX_0F38DB */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -4774,6 +4795,20 @@ static const struct dis386 prefix_table[][4] = {
|
|||
{ "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
|
||||
},
|
||||
|
||||
/* PREFIX_0F3ACE */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
|
||||
},
|
||||
|
||||
/* PREFIX_0F3ACF */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
|
||||
},
|
||||
|
||||
/* PREFIX_0F3ADF */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -6341,6 +6376,13 @@ static const struct dis386 prefix_table[][4] = {
|
|||
{ "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_0F38CF */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ VEX_W_TABLE (VEX_W_0F38CF_P_2) },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_0F38DB */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -6870,6 +6912,20 @@ static const struct dis386 prefix_table[][4] = {
|
|||
{ VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_0F3ACE */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_0F3ACF */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_0F3ADF */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -7297,7 +7353,7 @@ static const struct dis386 three_byte_table[][256] = {
|
|||
{ PREFIX_TABLE (PREFIX_0F38CC) },
|
||||
{ PREFIX_TABLE (PREFIX_0F38CD) },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_0F38CF) },
|
||||
/* d0 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -7587,8 +7643,8 @@ static const struct dis386 three_byte_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_0F3ACC) },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_0F3ACE) },
|
||||
{ PREFIX_TABLE (PREFIX_0F3ACF) },
|
||||
/* d0 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -9049,7 +9105,7 @@ static const struct dis386 vex_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_0F38CF) },
|
||||
/* d0 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -9339,8 +9395,8 @@ static const struct dis386 vex_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
|
||||
{ PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
|
||||
/* d0 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
|
|
@ -11266,6 +11322,10 @@ static const struct dis386 vex_w_table[][2] = {
|
|||
/* VEX_W_0F3879_P_2 */
|
||||
{ "vpbroadcastw", { XM, EXxmm_mw }, 0 },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F38CF_P_2 */
|
||||
{ "vgf2p8mulb", { XM, Vex, EXx }, 0 },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F38DB_P_2 */
|
||||
{ "vaesimc", { XM, EXx }, 0 },
|
||||
|
|
@ -11446,6 +11506,16 @@ static const struct dis386 vex_w_table[][2] = {
|
|||
/* VEX_W_0F3A63_P_2 */
|
||||
{ "vpcmpistri", { XM, EXx, Ib }, 0 },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F3ACE_P_2 */
|
||||
{ Bad_Opcode },
|
||||
{ "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F3ACF_P_2 */
|
||||
{ Bad_Opcode },
|
||||
{ "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F3ADF_P_2 */
|
||||
{ "vaeskeygenassist", { XM, EXx, Ib }, 0 },
|
||||
|
|
|
|||
|
|
@ -267,6 +267,8 @@ static initializer cpu_flag_init[] =
|
|||
"CpuPTWRITE" },
|
||||
{ "CPU_CET_FLAGS",
|
||||
"CpuCET" },
|
||||
{ "CPU_GFNI_FLAGS",
|
||||
"CpuGFNI" },
|
||||
{ "CPU_ANY_X87_FLAGS",
|
||||
"CPU_ANY_287_FLAGS|Cpu8087" },
|
||||
{ "CPU_ANY_287_FLAGS",
|
||||
|
|
@ -532,6 +534,7 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (CpuRDPID),
|
||||
BITFIELD (CpuPTWRITE),
|
||||
BITFIELD (CpuCET),
|
||||
BITFIELD (CpuGFNI),
|
||||
BITFIELD (CpuRegMMX),
|
||||
BITFIELD (CpuRegXMM),
|
||||
BITFIELD (CpuRegYMM),
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -212,6 +212,8 @@ enum
|
|||
CpuPTWRITE,
|
||||
/* CET instruction support required */
|
||||
CpuCET,
|
||||
/* GFNI instructions required */
|
||||
CpuGFNI,
|
||||
/* MMX register support required */
|
||||
CpuRegMMX,
|
||||
/* XMM register support required */
|
||||
|
|
@ -237,10 +239,8 @@ enum
|
|||
|
||||
/* If you get a compiler error for zero width of the unused field,
|
||||
comment it out. */
|
||||
|
||||
#define CpuUnused (CpuMax + 1)
|
||||
|
||||
|
||||
/* We can check if an instruction is available with array instead
|
||||
of bitfield. */
|
||||
typedef union i386_cpu_flags
|
||||
|
|
@ -337,6 +337,7 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpurdpid:1;
|
||||
unsigned int cpuptwrite:1;
|
||||
unsigned int cpucet:1;
|
||||
unsigned int cpugfni:1;
|
||||
unsigned int cpuregmmx:1;
|
||||
unsigned int cpuregxmm:1;
|
||||
unsigned int cpuregymm:1;
|
||||
|
|
|
|||
|
|
@ -1806,6 +1806,15 @@ pclmullqhqdq, 2, 0x660f3a44, 0x10, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSu
|
|||
pclmulhqhqdq, 2, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
|
||||
// GFNI
|
||||
|
||||
gf2p8affineqb, 3, 0x66ce, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
gf2p8affineqb, 3, 0x660f3ace, None, 3, CpuGFNI, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
gf2p8affineinvqb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
gf2p8affineinvqb, 3, 0x660f3acf, None, 3, CpuGFNI, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
gf2p8mulb, 2, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
gf2p8mulb, 2, 0x660f38cf, None, 3, CpuGFNI, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
|
||||
// AVX instructions.
|
||||
|
||||
vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
|
|
@ -2591,6 +2600,17 @@ vpclmulhqlqdq, 3, 0x6644, 0x1, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVV
|
|||
vpclmullqhqdq, 3, 0x6644, 0x10, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuAVX|CpuPCLMUL, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
// GFNI + AVX
|
||||
|
||||
vgf2p8affineinvqb, 4, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vgf2p8affineinvqb, 4, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
|
||||
vgf2p8affineqb, 4, 0x66ce, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vgf2p8affineqb, 4, 0x66ce, None, 1, CpuAVX|CpuGFNI, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
|
||||
vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
// FSGSBASE, RDRND and F16C
|
||||
|
||||
rdfsbase, 1, 0xf30fae, 0x0, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
|
||||
|
|
@ -6042,6 +6062,22 @@ vpshrdw, 4, 0x6672, None, 1, CpuAVX512_VBMI2|CpuAVX512VL, Modrm|EVex=3|Masking=3
|
|||
|
||||
// AVX512_VBMI2 instructions end
|
||||
|
||||
// AVX512 + GFNI instructions
|
||||
|
||||
vgf2p8affineinvqb, 4, 0x66cf, None, 1, CpuAVX512F|CpuGFNI, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vgf2p8affineinvqb, 4, 0x66cf, None, 1, CpuGFNI|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vgf2p8affineinvqb, 4, 0x66cf, None, 1, CpuGFNI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vgf2p8affineqb, 4, 0x66ce, None, 1, CpuAVX512F|CpuGFNI, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vgf2p8affineqb, 4, 0x66ce, None, 1, CpuGFNI|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vgf2p8affineqb, 4, 0x66ce, None, 1, CpuGFNI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX512F|CpuGFNI, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vgf2p8mulb, 3, 0x66cf, None, 1, CpuGFNI|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vgf2p8mulb, 3, 0x66cf, None, 1, CpuGFNI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
// AVX512 + GFNI instructions end
|
||||
|
||||
// CLZERO instructions
|
||||
|
||||
clzero, 0, 0xf01fc, None, 3, CpuCLZERO, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
|
|
|
|||
11009
opcodes/i386-tbl.h
11009
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue