TIC4X testcase commit
* binutils/testsuite/binutils-all/objcopy.exp: Disable tic4x from test * binutils/testsuite/binutils-all/objdump.exp: Setup proper values for tic4x testcase * gas/testsuite/gas/all/gas.exp: Setup for tic4x testcase * gas/testsuite/gas/macros/macros.exp: Ditto * gas/testsuite/gas/all/gas.exp: Setup for tic4x testcase * gas/testsuite/gas/macros/macros.exp: Ditto * gas/testsuite/gas/tic4x: New tic4x gas testsuite directory * ld/testsuite/ld-scripts/script.exp: Setup for tic4x testcase
This commit is contained in:
parent
23ce3b1cd0
commit
48c5eb8a70
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@ -1,3 +1,9 @@
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2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com>
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* testsuite/binutils-all/objcopy.exp: Disable tic4x from test
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* testsuite/binutils-all/objdump.exp: Setup proper values for tic4x
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testcase
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2002-11-14 Nick Clifton <nickc@redhat.com>
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* readelf.c (process_program_headers): Add comment about return
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@ -80,7 +80,7 @@ if ![string match "" $got] then {
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setup_xfail "m8*-*"
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setup_xfail "or32-*-rtems*" "or32-*-coff"
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setup_xfail "sh-*-coff*" "sh-*-rtems*"
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setup_xfail "tic80-*-*" "w65-*" "z8*-*"
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setup_xfail "tic4x-*-*" "tic80-*-*" "w65-*" "z8*-*"
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clear_xfail "hppa*64*-*-hpux*" "hppa*-*-linux*" "hppa*-*-lites*"
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clear_xfail "hppa*-*-*n*bsd*" "hppa*-*-rtems*" "*-*-*elf*" "m68*-*-sysv4*"
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@ -96,6 +96,11 @@ if ![regexp $want $got all text_name text_size data_name data_size] then {
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verbose "data name is $data_name size is $data_size"
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set ets 8
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set eds 4
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# The [ti]c4x target has the property sizeof(char)=sizeof(long)=1
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if [istarget *c4x*-*-*] then {
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set ets 2
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set eds 1
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}
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# c54x section sizes are in bytes, not octets; adjust accordingly
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if [istarget *c54x*-*-*] then {
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set ets 4
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@ -1,3 +1,28 @@
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2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com>
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* testsuite/gas/all/gas.exp: Setup for tic4x testcase
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* testsuite/gas/macros/macros.exp: Ditto
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* testsuite/gas/tic4x: New tic4x gas testsuite directory
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* testsuite/gas/tic4x/addressing.s: Create
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* testsuite/gas/tic4x/addressing_c3x.d: Create
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* testsuite/gas/tic4x/addressing_c4x.d: Create
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* testsuite/gas/tic4x/allopcodes.S: Create
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* testsuite/gas/tic4x/data.d: Create
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* testsuite/gas/tic4x/data.s: Create
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* testsuite/gas/tic4x/float.d: Create
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* testsuite/gas/tic4x/float.s: Create
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* testsuite/gas/tic4x/opclasses.h: Create
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* testsuite/gas/tic4x/opcodes.s: Create
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* testsuite/gas/tic4x/opcodes_c3x.d: Create
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* testsuite/gas/tic4x/opcodes_c4x.d: Create
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* testsuite/gas/tic4x/rebuild.sh: Create
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* testsuite/gas/tic4x/registers.s: Create
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* testsuite/gas/tic4x/registers_c3x.d: Create
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* testsuite/gas/tic4x/registers_c4x.d: Create
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* testsuite/gas/tic4x/tic4x.exp: Create
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* testsuite/gas/tic4x/zeros.d: Create
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* testsuite/gas/tic4x/zeros.s: Create
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2002-11-16 Svein E. Seldal <Svein.Seldal@solidas.com>
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* config/tc-tic4x.c: Remove c4x_pseudo_ignore function.
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@ -90,8 +90,10 @@ proc do_930509a {} {
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# C54x assembler (for compatibility) does not allow differences between
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# forward references
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# C30 counts a four byte offset as a difference of one.
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if { ![istarget hppa*-*-*]
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&& ![istarget *c30*-*-*] && ![istarget *c54x*-*-*] } then {
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if { ![istarget hppa*-*-*] &&
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![istarget *c30*-*-*] &&
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![istarget *c4x*-*-*] &&
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![istarget *c54x*-*-*] } then {
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# the vax fails because VMS can apparently actually handle this
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# case in relocs, so gas doesn't handle it itself.
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setup_xfail "h8300*-*-elf*" "mn10200*-*-*" "mn10300*-*-*" "vax*-*-vms*"
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# These directives are done in the c54x-specific tests instead
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case $target_triplet in {
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{ hppa*-*-* } { }
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{ *c4x*-*-* } { }
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{ *c54x*-*-* } { }
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default {
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run_dump_test struct
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# We omit the ARM toolchains because they define locals to
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# start with '.', which eliminates .eos, .text etc from the output.
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# Omit c54x, since .tag and .def mean something different on that target
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if { ([istarget *-*-coff*] && ![istarget m88*-*-*] && ![istarget *arm*-*-coff] && ![istarget thumb*-*-coff] && ![istarget xscale-*-coff] && ![istarget *c54x*-*-coff]) \
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if { ([istarget *-*-coff*] && ![istarget m88*-*-*] && ![istarget *arm*-*-coff] && ![istarget thumb*-*-coff] && ![istarget xscale-*-coff] && ![istarget *c4x*-*-coff] && ![istarget *c54x*-*-coff]) \
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||([istarget *-*-pe*] && ![istarget arm*-*-pe*] && ![istarget thumb*-*-pe*]) \
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|| [istarget a29k-*-udi*] \
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|| [istarget a29k-*-ebmon*] \
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@ -158,6 +161,7 @@ proc test_cond {} {
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# again, p2align doesn't work on c54x target
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case $target_triplet in {
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{ hppa*-*-* } { }
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{ *c4x*-*-* } { }
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{ *c54x*-*-* } { }
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default {
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test_cond
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@ -4,13 +4,13 @@ if { ![istarget hppa*-*-*] || [istarget *-*-linux*] } {
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run_dump_test test1
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}
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if ![istarget *c54x*-*-*] {
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if { ![istarget *c54x*-*-*] && ![istarget *c4x*-*-*] } {
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run_dump_test test2
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}
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run_dump_test test3
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if ![istarget *c54x*-*-*] {
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if { ![istarget *c54x*-*-*] && ![istarget *c4x*-*-*] } {
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run_dump_test irp
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run_dump_test rept
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}
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case $target_triplet in {
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{ hppa*-*-* } { if [istarget *-*-linux*] { run_dump_test semi } }
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{ *c4x*-*-* } { }
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{ *c54x*-*-* } { }
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default {
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run_dump_test semi
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}
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}
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if { ![istarget hppa*-*-*] || [istarget *-*-linux*]} {
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if { ![istarget hppa*-*-*] || [istarget *-*-linux*] } {
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# FIXME: Due to macro mishandling of ONLY_STANDARD_ESCAPES.
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setup_xfail "avr-*" "cris-*"
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setup_xfail "rs6000-*-*"
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# FIXME: Due to difference in what "consecutive octets" means.
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setup_xfail "*c54x*-*"
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setup_xfail "*c4x*-*-*" "*c54x*-*"
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run_dump_test strings
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}
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;;
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;; test all addressing modes and register constraints
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;; (types/classes is read from include/opcodes/tic4x.h)
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;;
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.text
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start:
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;;
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;; Type B - infix condition branch
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;;
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Type_BI:bu Type_BI ; Unconditional branch (00000)
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bc Type_BI ; Carry branch (00001)
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blo Type_BI ; Lower than branch (00001)
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bls Type_BI ; Lower than or same branch (00010)
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bhi Type_BI ; Higher than branch (00011)
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bhs Type_BI ; Higher than or same branch (00100)
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bnc Type_BI ; No carry branch (00100)
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beq Type_BI ; Equal to branch (00101)
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bz Type_BI ; Zero branch (00101)
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bne Type_BI ; Not equal to branch (00110)
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bnz Type_BI ; Not zero branch (00110)
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blt Type_BI ; Less than branch (00111)
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bn Type_BI ; Negative branch (00111)
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ble Type_BI ; Less than or equal to branch (01000)
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bgt Type_BI ; Greater than branch (01001)
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bp Type_BI ; Positive branch (01001)
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bge Type_BI ; Greater than or equal branch (01010)
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bnn Type_BI ; Nonnegative branch (01010)
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bnv Type_BI ; No overflow branch (01000)
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bv Type_BI ; Overflow branch (01101)
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bnuf Type_BI ; No underflow branch (01110)
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buf Type_BI ; Underflow branch (01111)
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bnlv Type_BI ; No latched overflow branch (10000)
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blv Type_BI ; Latched overflow branch (10001)
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bnluf Type_BI ; No latched FP underflow branch (10010)
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bluf Type_BI ; Latched FP underflow branch (10011)
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bzuf Type_BI ; Zero or FP underflow branch (10100)
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b Type_BI ; Unconditional branch (00000)
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;;
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;; Type C - infix condition load
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;;
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Type_CI:ldiu R0,R0 ; Unconditional load (00000)
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ldic R0,R0 ; Carry load (00001)
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ldilo R0,R0 ; Lower than load (00001)
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ldils R0,R0 ; Lower than or same load (00010)
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ldihi R0,R0 ; Higher than load (00011)
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ldihs R0,R0 ; Higher than or same load (00100)
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ldinc R0,R0 ; No carry load (00100)
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ldieq R0,R0 ; Equal to load (00101)
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ldiz R0,R0 ; Zero load (00101)
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ldine R0,R0 ; Not equal to load (00110)
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ldinz R0,R0 ; Not zero load (00110)
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ldil R0,R0 ; Less than load (00111)
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ldin R0,R0 ; Negative load (00111)
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ldile R0,R0 ; Less than or equal to load (01000)
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ldigt R0,R0 ; Greater than load (01001)
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ldip R0,R0 ; Positive load (01001)
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ldige R0,R0 ; Greater than or equal load (01010)
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ldinn R0,R0 ; Nonnegative load (01010)
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ldinv R0,R0 ; No overflow load (01000)
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ldiv R0,R0 ; Overflow load (01101)
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ldinuf R0,R0 ; No underflow load (01110)
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ldiuf R0,R0 ; Underflow load (01111)
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ldinlv R0,R0 ; No latched overflow load (10000)
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ldilv R0,R0 ; Latched overflow load (10001)
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ldinluf R0,R0 ; No latched FP underflow load (10010)
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ldiluf R0,R0 ; Latched FP underflow load (10011)
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ldizuf R0,R0 ; Zero or FP underflow load (10100)
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;;
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;; Type * - Indirect (full)
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;;
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Type_ind:
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ldi *AR0,R0 ; Indirect addressing (G=10)
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ldi *+AR0(5),R0 ; with predisplacement add
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ldi *-AR0(5),R0 ; with predisplacement subtract
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ldi *++AR0(5),R0 ; with predisplacement add and modify
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ldi *--AR0(5),R0 ; with predisplacement subtract and modify
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ldi *AR0++(5),R0 ; with postdisplacement add and modify
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ldi *AR0--(5),R0 ; with postdisplacement subtract and modify
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ldi *AR0++(5)%,R0 ; with postdisplacement add and circular modify
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ldi *AR0--(5)%,R0 ; with postdisplacement subtract and circular modify
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ldi *+AR0(IR0),R0 ; with predisplacement add
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ldi *-AR0(IR0),R0 ; with predisplacement subtract
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ldi *++AR0(IR0),R0 ; with predisplacement add and modify
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ldi *--AR0(IR0),R0 ; with predisplacement subtract and modify
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ldi *AR0++(IR0),R0 ; with postdisplacement add and modify
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ldi *AR0--(IR0),R0 ; with postdisplacement subtract and modify
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ldi *AR0++(IR0)%,R0 ; with postdisplacement add and circular modify
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ldi *AR0--(IR0)%,R0 ; with postdisplacement subtract and circular modify
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ldi *AR0++(IR0)B,R0 ; with postincrement add and bit-reversed modify
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ldi *AR0++,R0 ; Same as *AR0++(1)
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;;
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;; Type # - Direct for ldp
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;;
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Type_ldp:
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ldp 12
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ldp @start
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ldp start
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;;
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;; Type @ - Direct
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;;
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Type_dir:
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ldi @start,R0
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ldi start,R0
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ldi @16,R0
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ldi @65535,R0
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;;
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;; Type A - Address register
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;;
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Type_A: dbc AR0,R0
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dbc AR2,R0
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dbc AR7,R0
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;;
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;; Type B - Unsigned integer (PC)
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;;
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Type_B: br start
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br 0x809800
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;;
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;; Type C - Indirect
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;;
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.ifdef TEST_C4X
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Type_C: addc3 *+AR0(5),R0,R0
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.endif
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;;
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;; Type E - Register (all)
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;;
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Type_E: andn3 R0,R0,R0
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andn3 AR0,R0,R0
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addc3 DP,R0,R0
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andn3 R7,R0,R0
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;;
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;; Type e - Register (0-11)
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;;
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Type_ee:subf3 R7,R0,R0
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addf3 R0,R0,R0
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addf3 R7,R0,R0
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cmpf3 R7,R0
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.ifdef TEST_C4X
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addf3 R11,R0,R0
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.endif
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;;
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;; Type F - Short float immediate
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;;
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Type_F: ldf 0,R0
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ldf 3.5,R0
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ldf -3.5,R0
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ldf 0e-3.5e-1,R0
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;;
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;; Type G - Register (all)
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;;
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Type_G: andn3 R0,AR0,R0
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addc3 R0,DP,R0
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addc3 R0,R0,R0
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andn3 R0,R7,R0
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;;
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;; Type g - Register (0-11)
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;;
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Type_gg:subf3 R0,R7,R0
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addf3 R0,R0,R0
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addf3 R0,R7,R0
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cmpf3 R0,R7
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.ifdef TEST_C4X
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addf3 R0,R11,R0
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.endif
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;;
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;; Type H - Register (0-7)
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;;
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Type_H: stf R0,*AR0 &|| stf R0,*AR0
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stf R0,*AR0 &|| stf R2,*AR0
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stf R0,*AR0 &|| stf R7,*AR0
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;;
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;; Type I - Indirect
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;;
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Type_I: addf3 *AR0,R0,R0 ; Indirect addressing (G=10)
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addf3 *+AR0(1),R0,R0 ; with predisplacement add
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addf3 *-AR0(1),R0,R0 ; with predisplacement subtract
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addf3 *++AR0(1),R0,R0 ; with predisplacement add and modify
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addf3 *--AR0(1),R0,R0 ; with predisplacement subtract and modify
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addf3 *AR0++(1),R0,R0 ; with postdisplacement add and modify
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addf3 *AR0--(1),R0,R0 ; with postdisplacement subtract and modify
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addf3 *AR0++(1)%,R0,R0; with postdisplacement add and circular modify
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addf3 *AR0--(1)%,R0,R0; with postdisplacement subtract and circular modify
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addf3 *+AR0(IR0),R0,R0; with predisplacement add
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addf3 *-AR0(IR0),R0,R0; with predisplacement subtract
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addf3 *++AR0(IR0),R0,R0; with predisplacement add and modify
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addf3 *--AR0(IR0),R0,R0; with predisplacement subtract and modify
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addf3 *AR0++(IR0),R0,R0; with postdisplacement add and modify
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addf3 *AR0--(IR0),R0,R0; with postdisplacement subtract and modify
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addf3 *AR0++(IR0)%,R0,R0; with postdisplacement add and circular modify
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addf3 *AR0--(IR0)%,R0,R0; with postdisplacement subtract and circular modify
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addf3 *AR0++(IR0)B,R0,R0; with postincrement add and bit-reversed modify
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addf3 *AR0++,R0,R0 ; Same as *AR0++(1)
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;;
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;; Type J - Indirect
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;;
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Type_J: addf3 R0,*AR0,R0 ; Indirect addressing (G=10)
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addf3 R0,*+AR0(1),R0 ; with predisplacement add
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addf3 R0,*-AR0(1),R0 ; with predisplacement subtract
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addf3 R0,*++AR0(1),R0 ; with predisplacement add and modify
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addf3 R0,*--AR0(1),R0 ; with predisplacement subtract and modify
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addf3 R0,*AR0++(1),R0 ; with postdisplacement add and modify
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addf3 R0,*AR0--(1),R0 ; with postdisplacement subtract and modify
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addf3 R0,*AR0++(1)%,R0; with postdisplacement add and circular modify
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addf3 R0,*AR0--(1)%,R0; with postdisplacement subtract and circular modify
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addf3 R0,*+AR0(IR0),R0; with predisplacement add
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addf3 R0,*-AR0(IR0),R0; with predisplacement subtract
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addf3 R0,*++AR0(IR0),R0; with predisplacement add and modify
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addf3 R0,*--AR0(IR0),R0; with predisplacement subtract and modify
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addf3 R0,*AR0++(IR0),R0; with postdisplacement add and modify
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addf3 R0,*AR0--(IR0),R0; with postdisplacement subtract and modify
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addf3 R0,*AR0++(IR0)%,R0; with postdisplacement add and circular modify
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addf3 R0,*AR0--(IR0)%,R0; with postdisplacement subtract and circular modify
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addf3 R0,*AR0++(IR0)B,R0; with postincrement add and bit-reversed modify
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addf3 R0,*AR0++,R0 ; Same as *AR0++(1)
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;;
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;; Type K - Register (0-7)
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;;
|
||||
Type_K: ldf *AR0,R0 &|| ldf *AR0,R0
|
||||
ldf *AR0,R0 &|| ldf *AR0,R2
|
||||
ldf *AR0,R0 &|| ldf *AR0,R7
|
||||
|
||||
;;
|
||||
;; Type L - Register (0-7)
|
||||
;;
|
||||
Type_L: stf R0,*AR0 &|| stf R0,*AR0
|
||||
stf R2,*AR0 &|| stf R0,*AR0
|
||||
stf R7,*AR0 &|| stf R0,*AR0
|
||||
|
||||
;;
|
||||
;; Type M - Register (2-3)
|
||||
;;
|
||||
Type_M: mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R2
|
||||
mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R3
|
||||
|
||||
;;
|
||||
;; Type N - Register (0-1)
|
||||
;;
|
||||
Type_N: mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R2
|
||||
mpyf3 *AR0,*AR0,R1 &|| addf3 R0,R0,R2
|
||||
|
||||
;;
|
||||
;; Type O - Indirect
|
||||
;;
|
||||
.ifdef TEST_C4X
|
||||
Type_O: addc3 *+AR0(5),*+AR0(5),R0
|
||||
.endif
|
||||
|
||||
;;
|
||||
;; Type P - Displacement (PC rel)
|
||||
;;
|
||||
Type_P: callc start
|
||||
callc 1
|
||||
|
||||
;;
|
||||
;; Type Q - Register (all)
|
||||
;;
|
||||
Type_Q: ldi R0,R0
|
||||
ldi AR0,R0
|
||||
ldi DP,R0
|
||||
ldi SP,R0
|
||||
|
||||
;;
|
||||
;; Type q - Register (0-11)
|
||||
;;
|
||||
Type_qq:fix R0,R0
|
||||
fix R7,R0
|
||||
.ifdef TEST_C4X
|
||||
fix R11,R0
|
||||
absf R11,R0
|
||||
.endif
|
||||
|
||||
;;
|
||||
;; Type R - Register (all)
|
||||
;;
|
||||
Type_R: ldi R0,R0
|
||||
ldi R0,AR0
|
||||
ldi R0,DP
|
||||
ldi R0,SP
|
||||
|
||||
;;
|
||||
;; Type r - Register (0-11)
|
||||
;;
|
||||
Type_rr:ldf R0,R0
|
||||
ldf R0,R7
|
||||
.ifdef TEST_C4X
|
||||
ldf R0,R11
|
||||
.endif
|
||||
|
||||
;;
|
||||
;; Type S - Signed immediate
|
||||
;;
|
||||
Type_S: ldi 0,R0
|
||||
ldi -123,R0
|
||||
ldi 6543,R0
|
||||
ldi -32768, R0
|
||||
|
||||
;;
|
||||
;; Type T - Integer
|
||||
;;
|
||||
.ifdef TEST_C4X
|
||||
Type_T: stik 0,*AR0
|
||||
stik 12,*AR0
|
||||
stik -5,*AR0
|
||||
.endif
|
||||
|
||||
;;
|
||||
;; Type U - Unsigned integer
|
||||
;;
|
||||
Type_U: and 0,R0
|
||||
and 256,R0
|
||||
and 65535,R0
|
||||
|
||||
;;
|
||||
;; Type V - Vector
|
||||
;;
|
||||
Type_V: trapu 12
|
||||
trapu 0
|
||||
trapu 31
|
||||
.ifdef TEST_C4X
|
||||
trapu 511
|
||||
.endif
|
||||
|
||||
;;
|
||||
;; Type W - Short int
|
||||
;;
|
||||
.ifdef TEST_C4X
|
||||
Type_W: addc3 -3,R0,R0
|
||||
addc3 5,R0,R0
|
||||
.endif
|
||||
|
||||
;;
|
||||
;; Type X - Expansion register
|
||||
;;
|
||||
.ifdef TEST_C4X
|
||||
Type_X: ldep IVTP,R0
|
||||
ldep TVTP,R0
|
||||
.endif
|
||||
|
||||
;;
|
||||
;; Type Y - Address register
|
||||
;;
|
||||
.ifdef TEST_C4X
|
||||
Type_Y: lda R0,AR0
|
||||
lda R0,DP
|
||||
lda R0,SP
|
||||
lda R0,IR0
|
||||
.endif
|
||||
|
||||
;;
|
||||
;; Type Z - Expansion register
|
||||
;;
|
||||
.ifdef TEST_C4X
|
||||
Type_Z: ldpe R0,IVTP
|
||||
ldpe R0,TVTP
|
||||
.endif
|
|
@ -0,0 +1,243 @@
|
|||
#as: -m30 --defsym TEST_C3X=1
|
||||
#objdump: -d -z
|
||||
#name: c3x addressing modes
|
||||
#source: addressing.s
|
||||
|
||||
.*: +file format .*c4x.*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
00000000 <Type_BI>:
|
||||
0: 6a00ffff.*
|
||||
1: 6a01fffe.*
|
||||
2: 6a01fffd.*
|
||||
3: 6a02fffc.*
|
||||
4: 6a03fffb.*
|
||||
5: 6a04fffa.*
|
||||
6: 6a04fff9.*
|
||||
7: 6a05fff8.*
|
||||
8: 6a05fff7.*
|
||||
9: 6a06fff6.*
|
||||
a: 6a06fff5.*
|
||||
b: 6a07fff4.*
|
||||
c: 6a07fff3.*
|
||||
d: 6a08fff2.*
|
||||
e: 6a09fff1.*
|
||||
f: 6a09fff0.*
|
||||
10: 6a0affef.*
|
||||
11: 6a0affee.*
|
||||
12: 6a0cffed.*
|
||||
13: 6a0dffec.*
|
||||
14: 6a0effeb.*
|
||||
15: 6a0fffea.*
|
||||
16: 6a10ffe9.*
|
||||
17: 6a11ffe8.*
|
||||
18: 6a12ffe7.*
|
||||
19: 6a13ffe6.*
|
||||
1a: 6a14ffe5.*
|
||||
1b: 6a00ffe4.*
|
||||
|
||||
0000001c <Type_CI>:
|
||||
1c: 50000000.*
|
||||
1d: 50800000.*
|
||||
1e: 50800000.*
|
||||
1f: 51000000.*
|
||||
20: 51800000.*
|
||||
21: 52000000.*
|
||||
22: 52000000.*
|
||||
23: 52800000.*
|
||||
24: 52800000.*
|
||||
25: 53000000.*
|
||||
26: 53000000.*
|
||||
27: 53800000.*
|
||||
28: 53800000.*
|
||||
29: 54000000.*
|
||||
2a: 54800000.*
|
||||
2b: 54800000.*
|
||||
2c: 55000000.*
|
||||
2d: 55000000.*
|
||||
2e: 56000000.*
|
||||
2f: 56800000.*
|
||||
30: 57000000.*
|
||||
31: 57800000.*
|
||||
32: 58000000.*
|
||||
33: 58800000.*
|
||||
34: 59000000.*
|
||||
35: 59800000.*
|
||||
36: 5a000000.*
|
||||
|
||||
00000037 <Type_ind>:
|
||||
37: 0840c000.*
|
||||
38: 08400005.*
|
||||
39: 08400805.*
|
||||
3a: 08401005.*
|
||||
3b: 08401805.*
|
||||
3c: 08402005.*
|
||||
3d: 08402805.*
|
||||
3e: 08403005.*
|
||||
3f: 08403805.*
|
||||
40: 08404000.*
|
||||
41: 08404800.*
|
||||
42: 08405000.*
|
||||
43: 08405800.*
|
||||
44: 08406000.*
|
||||
45: 08406800.*
|
||||
46: 08407000.*
|
||||
47: 08407800.*
|
||||
48: 0840c800.*
|
||||
49: 08402001.*
|
||||
|
||||
0000004a <Type_ldp>:
|
||||
4a: 5070000c.*
|
||||
4b: 50700000.*
|
||||
4c: 50700000.*
|
||||
|
||||
0000004d <Type_dir>:
|
||||
4d: 08200000.*
|
||||
4e: 08200000.*
|
||||
4f: 08200010.*
|
||||
50: 0820ffff.*
|
||||
|
||||
00000051 <Type_A>:
|
||||
51: 6c010000.*
|
||||
52: 6c810000.*
|
||||
53: 6dc10000.*
|
||||
|
||||
00000054 <Type_B>:
|
||||
54: 60000000.*
|
||||
55: 60809800.*
|
||||
|
||||
00000056 <Type_E>:
|
||||
56: 22000000.*
|
||||
57: 22000008.*
|
||||
58: 20000010.*
|
||||
59: 22000007.*
|
||||
|
||||
0000005a <Type_ee>:
|
||||
5a: 26800007.*
|
||||
5b: 20800000.*
|
||||
5c: 20800007.*
|
||||
5d: 23000007.*
|
||||
|
||||
0000005e <Type_F>:
|
||||
5e: 07608000.*
|
||||
5f: 07601600.*
|
||||
60: 07601a00.*
|
||||
61: 0760eccd.*
|
||||
|
||||
00000062 <Type_G>:
|
||||
62: 22000800.*
|
||||
63: 20001000.*
|
||||
64: 20000000.*
|
||||
65: 22000700.*
|
||||
|
||||
00000066 <Type_gg>:
|
||||
66: 26800700.*
|
||||
67: 20800000.*
|
||||
68: 20800700.*
|
||||
69: 23000700.*
|
||||
|
||||
0000006a <Type_H>:
|
||||
6a: c000c0c0.*
|
||||
6b: c002c0c0.*
|
||||
6c: c007c0c0.*
|
||||
|
||||
0000006d <Type_I>:
|
||||
6d: 20c000c0.*
|
||||
6e: 20c00000.*
|
||||
6f: 20c00008.*
|
||||
70: 20c00010.*
|
||||
71: 20c00018.*
|
||||
72: 20c00020.*
|
||||
73: 20c00028.*
|
||||
74: 20c00030.*
|
||||
75: 20c00038.*
|
||||
76: 20c00040.*
|
||||
77: 20c00048.*
|
||||
78: 20c00050.*
|
||||
79: 20c00058.*
|
||||
7a: 20c00060.*
|
||||
7b: 20c00068.*
|
||||
7c: 20c00070.*
|
||||
7d: 20c00078.*
|
||||
7e: 20c000c8.*
|
||||
7f: 20c00020.*
|
||||
|
||||
00000080 <Type_J>:
|
||||
80: 20a0c000.*
|
||||
81: 20a00000.*
|
||||
82: 20a00800.*
|
||||
83: 20a01000.*
|
||||
84: 20a01800.*
|
||||
85: 20a02000.*
|
||||
86: 20a02800.*
|
||||
87: 20a03000.*
|
||||
88: 20a03800.*
|
||||
89: 20a04000.*
|
||||
8a: 20a04800.*
|
||||
8b: 20a05000.*
|
||||
8c: 20a05800.*
|
||||
8d: 20a06000.*
|
||||
8e: 20a06800.*
|
||||
8f: 20a07000.*
|
||||
90: 20a07800.*
|
||||
91: 20a0c800.*
|
||||
92: 20a02000.*
|
||||
|
||||
00000093 <Type_K>:
|
||||
93: c400c0c0.*
|
||||
94: c410c0c0.*
|
||||
95: c438c0c0.*
|
||||
|
||||
00000096 <Type_L>:
|
||||
96: c000c0c0.*
|
||||
97: c080c0c0.*
|
||||
98: c1c0c0c0.*
|
||||
|
||||
00000099 <Type_M>:
|
||||
99: 8000c0c0.*
|
||||
9a: 8040c0c0.*
|
||||
|
||||
0000009b <Type_N>:
|
||||
9b: 8000c0c0.*
|
||||
9c: 8080c0c0.*
|
||||
|
||||
0000009d <Type_P>:
|
||||
9d: 7201ff62.*
|
||||
9e: 72010001.*
|
||||
|
||||
0000009f <Type_Q>:
|
||||
9f: 08000000.*
|
||||
a0: 08000008.*
|
||||
a1: 08000010.*
|
||||
a2: 08000014.*
|
||||
|
||||
000000a3 <Type_qq>:
|
||||
a3: 05000000.*
|
||||
a4: 05000007.*
|
||||
|
||||
000000a5 <Type_R>:
|
||||
a5: 08000000.*
|
||||
a6: 08080000.*
|
||||
a7: 08100000.*
|
||||
a8: 08140000.*
|
||||
|
||||
000000a9 <Type_rr>:
|
||||
a9: 07000000.*
|
||||
aa: 07070000.*
|
||||
|
||||
000000ab <Type_S>:
|
||||
ab: 08600000.*
|
||||
ac: 0860ff85.*
|
||||
ad: 0860198f.*
|
||||
ae: 08608000.*
|
||||
|
||||
000000af <Type_U>:
|
||||
af: 02e00000.*
|
||||
b0: 02e00100.*
|
||||
b1: 02e0ffff.*
|
||||
|
||||
000000b2 <Type_V>:
|
||||
b2: 7400002c.*
|
||||
b3: 74000020.*
|
||||
b4: 7400003f.*
|
|
@ -0,0 +1,278 @@
|
|||
#as: -m40 --defsym TEST_C4X=1
|
||||
#objdump: -d -z
|
||||
#name: c4x addressing modes
|
||||
#source: addressing.s
|
||||
|
||||
.*: +file format .*c4x.*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
00000000 <Type_BI>:
|
||||
0: 6a00ffff.*
|
||||
1: 6a01fffe.*
|
||||
2: 6a01fffd.*
|
||||
3: 6a02fffc.*
|
||||
4: 6a03fffb.*
|
||||
5: 6a04fffa.*
|
||||
6: 6a04fff9.*
|
||||
7: 6a05fff8.*
|
||||
8: 6a05fff7.*
|
||||
9: 6a06fff6.*
|
||||
a: 6a06fff5.*
|
||||
b: 6a07fff4.*
|
||||
c: 6a07fff3.*
|
||||
d: 6a08fff2.*
|
||||
e: 6a09fff1.*
|
||||
f: 6a09fff0.*
|
||||
10: 6a0affef.*
|
||||
11: 6a0affee.*
|
||||
12: 6a0cffed.*
|
||||
13: 6a0dffec.*
|
||||
14: 6a0effeb.*
|
||||
15: 6a0fffea.*
|
||||
16: 6a10ffe9.*
|
||||
17: 6a11ffe8.*
|
||||
18: 6a12ffe7.*
|
||||
19: 6a13ffe6.*
|
||||
1a: 6a14ffe5.*
|
||||
1b: 6a00ffe4.*
|
||||
|
||||
0000001c <Type_CI>:
|
||||
1c: 50000000.*
|
||||
1d: 50800000.*
|
||||
1e: 50800000.*
|
||||
1f: 51000000.*
|
||||
20: 51800000.*
|
||||
21: 52000000.*
|
||||
22: 52000000.*
|
||||
23: 52800000.*
|
||||
24: 52800000.*
|
||||
25: 53000000.*
|
||||
26: 53000000.*
|
||||
27: 53800000.*
|
||||
28: 53800000.*
|
||||
29: 54000000.*
|
||||
2a: 54800000.*
|
||||
2b: 54800000.*
|
||||
2c: 55000000.*
|
||||
2d: 55000000.*
|
||||
2e: 56000000.*
|
||||
2f: 56800000.*
|
||||
30: 57000000.*
|
||||
31: 57800000.*
|
||||
32: 58000000.*
|
||||
33: 58800000.*
|
||||
34: 59000000.*
|
||||
35: 59800000.*
|
||||
36: 5a000000.*
|
||||
|
||||
00000037 <Type_ind>:
|
||||
37: 0840c000.*
|
||||
38: 08400005.*
|
||||
39: 08400805.*
|
||||
3a: 08401005.*
|
||||
3b: 08401805.*
|
||||
3c: 08402005.*
|
||||
3d: 08402805.*
|
||||
3e: 08403005.*
|
||||
3f: 08403805.*
|
||||
40: 08404000.*
|
||||
41: 08404800.*
|
||||
42: 08405000.*
|
||||
43: 08405800.*
|
||||
44: 08406000.*
|
||||
45: 08406800.*
|
||||
46: 08407000.*
|
||||
47: 08407800.*
|
||||
48: 0840c800.*
|
||||
49: 08402001.*
|
||||
|
||||
0000004a <Type_ldp>:
|
||||
4a: 5070000c.*
|
||||
4b: 50700000.*
|
||||
4c: 50700000.*
|
||||
|
||||
0000004d <Type_dir>:
|
||||
4d: 08200000.*
|
||||
4e: 08200000.*
|
||||
4f: 08200010.*
|
||||
50: 0820ffff.*
|
||||
|
||||
00000051 <Type_A>:
|
||||
51: 6c010000.*
|
||||
52: 6c810000.*
|
||||
53: 6dc10000.*
|
||||
|
||||
00000054 <Type_B>:
|
||||
54: 60ffffab.*
|
||||
55: 60809800.*
|
||||
|
||||
00000056 <Type_C>:
|
||||
56: 30200028.*
|
||||
|
||||
00000057 <Type_E>:
|
||||
57: 22000000.*
|
||||
58: 22000008.*
|
||||
59: 20000010.*
|
||||
5a: 22000007.*
|
||||
|
||||
0000005b <Type_ee>:
|
||||
5b: 26800007.*
|
||||
5c: 20800000.*
|
||||
5d: 20800007.*
|
||||
5e: 23000007.*
|
||||
5f: 2080001f.*
|
||||
|
||||
00000060 <Type_F>:
|
||||
60: 07608000.*
|
||||
61: 07601600.*
|
||||
62: 07601a00.*
|
||||
63: 0760eccd.*
|
||||
|
||||
00000064 <Type_G>:
|
||||
64: 22000800.*
|
||||
65: 20001000.*
|
||||
66: 20000000.*
|
||||
67: 22000700.*
|
||||
|
||||
00000068 <Type_gg>:
|
||||
68: 26800700.*
|
||||
69: 20800000.*
|
||||
6a: 20800700.*
|
||||
6b: 23000700.*
|
||||
6c: 20801f00.*
|
||||
|
||||
0000006d <Type_H>:
|
||||
6d: c000c0c0.*
|
||||
6e: c002c0c0.*
|
||||
6f: c007c0c0.*
|
||||
|
||||
00000070 <Type_I>:
|
||||
70: 20c000c0.*
|
||||
71: 20c00000.*
|
||||
72: 20c00008.*
|
||||
73: 20c00010.*
|
||||
74: 20c00018.*
|
||||
75: 20c00020.*
|
||||
76: 20c00028.*
|
||||
77: 20c00030.*
|
||||
78: 20c00038.*
|
||||
79: 20c00040.*
|
||||
7a: 20c00048.*
|
||||
7b: 20c00050.*
|
||||
7c: 20c00058.*
|
||||
7d: 20c00060.*
|
||||
7e: 20c00068.*
|
||||
7f: 20c00070.*
|
||||
80: 20c00078.*
|
||||
81: 20c000c8.*
|
||||
82: 20c00020.*
|
||||
|
||||
00000083 <Type_J>:
|
||||
83: 20a0c000.*
|
||||
84: 20a00000.*
|
||||
85: 20a00800.*
|
||||
86: 20a01000.*
|
||||
87: 20a01800.*
|
||||
88: 20a02000.*
|
||||
89: 20a02800.*
|
||||
8a: 20a03000.*
|
||||
8b: 20a03800.*
|
||||
8c: 20a04000.*
|
||||
8d: 20a04800.*
|
||||
8e: 20a05000.*
|
||||
8f: 20a05800.*
|
||||
90: 20a06000.*
|
||||
91: 20a06800.*
|
||||
92: 20a07000.*
|
||||
93: 20a07800.*
|
||||
94: 20a0c800.*
|
||||
95: 20a02000.*
|
||||
|
||||
00000096 <Type_K>:
|
||||
96: c400c0c0.*
|
||||
97: c410c0c0.*
|
||||
98: c438c0c0.*
|
||||
|
||||
00000099 <Type_L>:
|
||||
99: c000c0c0.*
|
||||
9a: c080c0c0.*
|
||||
9b: c1c0c0c0.*
|
||||
|
||||
0000009c <Type_M>:
|
||||
9c: 8000c0c0.*
|
||||
9d: 8040c0c0.*
|
||||
|
||||
0000009e <Type_N>:
|
||||
9e: 8000c0c0.*
|
||||
9f: 8080c0c0.*
|
||||
|
||||
000000a0 <Type_O>:
|
||||
a0: 30602828.*
|
||||
|
||||
000000a1 <Type_P>:
|
||||
a1: 7201ff5e.*
|
||||
a2: 72010001.*
|
||||
|
||||
000000a3 <Type_Q>:
|
||||
a3: 08000000.*
|
||||
a4: 08000008.*
|
||||
a5: 08000010.*
|
||||
a6: 08000014.*
|
||||
|
||||
000000a7 <Type_qq>:
|
||||
a7: 05000000.*
|
||||
a8: 05000007.*
|
||||
a9: 0500001f.*
|
||||
aa: 0000001f.*
|
||||
|
||||
000000ab <Type_R>:
|
||||
ab: 08000000.*
|
||||
ac: 08080000.*
|
||||
ad: 08100000.*
|
||||
ae: 08140000.*
|
||||
|
||||
000000af <Type_rr>:
|
||||
af: 07000000.*
|
||||
b0: 07070000.*
|
||||
b1: 071f0000.*
|
||||
|
||||
000000b2 <Type_S>:
|
||||
b2: 08600000.*
|
||||
b3: 0860ff85.*
|
||||
b4: 0860198f.*
|
||||
b5: 08608000.*
|
||||
|
||||
000000b6 <Type_T>:
|
||||
b6: 1560c000.*
|
||||
b7: 156cc000.*
|
||||
b8: 157bc000.*
|
||||
|
||||
000000b9 <Type_U>:
|
||||
b9: 02e00000.*
|
||||
ba: 02e00100.*
|
||||
bb: 02e0ffff.*
|
||||
|
||||
000000bc <Type_V>:
|
||||
bc: 7400000c.*
|
||||
bd: 74000000.*
|
||||
be: 7400001f.*
|
||||
bf: 740001ff.*
|
||||
|
||||
000000c0 <Type_W>:
|
||||
c0: 300000fd.*
|
||||
c1: 30000005.*
|
||||
|
||||
000000c2 <Type_X>:
|
||||
c2: 76000000.*
|
||||
c3: 76000001.*
|
||||
|
||||
000000c4 <Type_Y>:
|
||||
c4: 1e880000.*
|
||||
c5: 1e900000.*
|
||||
c6: 1e940000.*
|
||||
c7: 1e910000.*
|
||||
|
||||
000000c8 <Type_Z>:
|
||||
c8: 76800000.*
|
||||
c9: 76810000.*
|
|
@ -0,0 +1,206 @@
|
|||
;;;
|
||||
;;; Test all opcodes and argument permuation
|
||||
;;; To make our job a lot simpler, we define a couple of
|
||||
;;; insn classes, that we use to generate the proper
|
||||
;;; test output.
|
||||
;;;
|
||||
;;; To rebuild this file you must use
|
||||
;;; ./rebuild.sh
|
||||
;;;
|
||||
#include "opclasses.h"
|
||||
|
||||
.text
|
||||
start: B_CLASS( absf )
|
||||
P_CLASS( absf, stf )
|
||||
A_CLASS( absi )
|
||||
P_CLASS( absi, sti )
|
||||
A_CLASS( addc )
|
||||
TC_CLASS( addc )
|
||||
B_CLASS( addf )
|
||||
SC_CLASS( addf )
|
||||
QC_CLASS( addf, stf )
|
||||
A_CLASS( addi )
|
||||
TC_CLASS( addi )
|
||||
QC_CLASS( addi, sti )
|
||||
AU_CLASS( and )
|
||||
TC_CLASS( and )
|
||||
QC_CLASS( and, sti )
|
||||
AU_CLASS( andn )
|
||||
T_CLASS( andn )
|
||||
A_CLASS( ash )
|
||||
T_CLASS( ash )
|
||||
Q_CLASS( ash, sti )
|
||||
J_CLASS( bC, b )
|
||||
J_CLASS( bCd, bd )
|
||||
br_I: br start
|
||||
brd_I: brd start
|
||||
call_I: call start
|
||||
call_JS: callc R0
|
||||
callc start
|
||||
B_CLASS( cmpf )
|
||||
S2_CLASS( cmpf )
|
||||
A_CLASS( cmpi )
|
||||
T2_CLASS( cmpi )
|
||||
D_CLASS( dbC, db )
|
||||
D_CLASS( dbCd, dbd )
|
||||
AF_CLASS( fix )
|
||||
P_CLASS( fix, sti )
|
||||
BI_CLASS( float )
|
||||
P_CLASS( float, stf )
|
||||
iack_Z: iack @start
|
||||
iack *+AR0(1)
|
||||
idle_Z: idle
|
||||
.ifdef TEST_IDLE2
|
||||
idle2_Z: idle2
|
||||
.endif
|
||||
B_CLASS( lde )
|
||||
B_CLASS( ldf )
|
||||
LL_CLASS( ldf )
|
||||
P_CLASS( ldf, stf )
|
||||
BB_CLASS( ldfC )
|
||||
B6_CLASS( ldfi )
|
||||
A_CLASS( ldi )
|
||||
LL_CLASS( ldi )
|
||||
P_CLASS( ldi, sti )
|
||||
AB_CLASS( ldiC )
|
||||
A6_CLASS( ldii )
|
||||
ldp_Z: ldp start
|
||||
B_CLASS( ldm )
|
||||
.ifdef TEST_LPWR
|
||||
lopower_Z: lopower
|
||||
.endif
|
||||
A_CLASS( lsh )
|
||||
T_CLASS( lsh )
|
||||
Q_CLASS( lsh, sti )
|
||||
.ifdef TEST_LPWR
|
||||
maxspeed_Z: maxspeed
|
||||
.endif
|
||||
B_CLASS( mpyf )
|
||||
SC_CLASS( mpyf )
|
||||
M_CLASS( mpyf, addf )
|
||||
QC_CLASS( mpyf, stf )
|
||||
M_CLASS( mpyf, subf )
|
||||
A_CLASS( mpyi )
|
||||
TC_CLASS( mpyi )
|
||||
M_CLASS( mpyi, addi )
|
||||
QC_CLASS( mpyi, sti )
|
||||
M_CLASS( mpyi, subi )
|
||||
A_CLASS( negb )
|
||||
B_CLASS( negf )
|
||||
P_CLASS( negf, stf )
|
||||
A_CLASS( negi )
|
||||
P_CLASS( negi, sti )
|
||||
A2_CLASS( nop )
|
||||
B_CLASS( norm )
|
||||
AU_CLASS( not )
|
||||
P_CLASS( not, sti )
|
||||
AU_CLASS( or )
|
||||
TC_CLASS( or )
|
||||
QC_CLASS( or, sti )
|
||||
R_CLASS( pop )
|
||||
RF_CLASS( popf )
|
||||
R_CLASS( push )
|
||||
RF_CLASS( pushf )
|
||||
reti_Z: retiC
|
||||
reti
|
||||
rets_Z: retsC
|
||||
rets
|
||||
B_CLASS( rnd )
|
||||
R_CLASS( rol )
|
||||
R_CLASS( rolc )
|
||||
R_CLASS( ror )
|
||||
R_CLASS( rorc )
|
||||
rptb_I2: rptb start
|
||||
A3_CLASS( rpts )
|
||||
sigi_Z: sigi
|
||||
B7_CLASS( stf )
|
||||
LS_CLASS( stf )
|
||||
B7_CLASS( stfi )
|
||||
A7_CLASS( sti )
|
||||
LS_CLASS( sti )
|
||||
A7_CLASS( stii )
|
||||
A_CLASS( subb )
|
||||
T_CLASS( subb )
|
||||
A_CLASS( subc )
|
||||
B_CLASS( subf )
|
||||
S_CLASS( subf )
|
||||
Q_CLASS( subf, stf )
|
||||
A_CLASS( subi )
|
||||
T_CLASS( subi )
|
||||
Q_CLASS( subi, sti )
|
||||
A_CLASS( subrb )
|
||||
B_CLASS( subrf )
|
||||
A_CLASS( subri )
|
||||
swi_Z: swi
|
||||
trap_Z: trapC 10
|
||||
trap 10
|
||||
AU_CLASS( tstb )
|
||||
T2C_CLASS( tstb )
|
||||
AU_CLASS( xor )
|
||||
TC_CLASS( xor )
|
||||
QC_CLASS( xor, sti )
|
||||
|
||||
.ifdef TEST_C4X
|
||||
J_CLASS( bCaf, baf )
|
||||
J_CLASS( bCat, bat )
|
||||
B6_CLASS( frieee )
|
||||
P_CLASS( frieee, stf )
|
||||
laj_I: laj start
|
||||
laj_JS: lajc R0
|
||||
lajc start
|
||||
lat_Z: latC 10
|
||||
A_CLASS( lb0 )
|
||||
A_CLASS( lb1 )
|
||||
A_CLASS( lb2 )
|
||||
A_CLASS( lb3 )
|
||||
AU_CLASS( lbu0 )
|
||||
AU_CLASS( lbu1 )
|
||||
AU_CLASS( lbu2 )
|
||||
AU_CLASS( lbu3 )
|
||||
AY_CLASS( lda )
|
||||
ldep_Z: ldep IVTP, AR0
|
||||
ldhi_Z: ldhi 35, R0
|
||||
ldhi start, R0
|
||||
ldpe_Z: ldpe AR0, IVTP
|
||||
ldpk_Z: ldpk start
|
||||
A_CLASS( lh0 )
|
||||
A_CLASS( lh1 )
|
||||
AU_CLASS( lhu0 )
|
||||
AU_CLASS( lhu1 )
|
||||
A_CLASS( lwl0 )
|
||||
A_CLASS( lwl1 )
|
||||
A_CLASS( lwl2 )
|
||||
A_CLASS( lwl3 )
|
||||
A_CLASS( lwr0 )
|
||||
A_CLASS( lwr1 )
|
||||
A_CLASS( lwr2 )
|
||||
A_CLASS( lwr3 )
|
||||
A_CLASS( mb0 )
|
||||
A_CLASS( mb1 )
|
||||
A_CLASS( mb2 )
|
||||
A_CLASS( mb3 )
|
||||
A_CLASS( mh0 )
|
||||
A_CLASS( mh1 )
|
||||
A_CLASS( mh2 )
|
||||
A_CLASS( mh3 )
|
||||
A_CLASS( mpyshi )
|
||||
TC_CLASS( mpyshi )
|
||||
A_CLASS( mpyuhi )
|
||||
TC_CLASS( mpyuhi )
|
||||
BA_CLASS( rcpf )
|
||||
retid_Z: retiCd
|
||||
retid
|
||||
rptb2_I2: rptb AR0
|
||||
rptbd_I2: rptbd start
|
||||
rptbd AR0
|
||||
B_CLASS( rsqrf )
|
||||
A6_CLASS( sigi )
|
||||
sti2_A7: sti -5, @start
|
||||
sti -5, *+AR0(5)
|
||||
stik_Z: stik -5, @start
|
||||
stik -5, *+AR0(5)
|
||||
B_CLASS( toieee )
|
||||
P_CLASS( toieee, stf )
|
||||
.endif
|
||||
.end
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
#objdump: -dz
|
||||
#name: data tests
|
||||
|
||||
.*: +file format .*c4x.*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
00000000 <BYTE>:
|
||||
0: 0000000a.*
|
||||
1: 000000ff.*
|
||||
2: 00000061.*
|
||||
3: 00000062.*
|
||||
4: 00000063.*
|
||||
5: 00000061.*
|
||||
|
||||
00000006 <HWORD>:
|
||||
6: 0000000a.*
|
||||
7: 0000ffff.*
|
||||
8: 00000061.*
|
||||
9: 00000062.*
|
||||
a: 00000063.*
|
||||
b: 00000061.*
|
||||
|
||||
0000000c <INT>:
|
||||
c: 0000000a.*
|
||||
d: 00000000.*
|
||||
e: ffffffff.*
|
||||
f: 00000061.*
|
||||
10: 00000062.*
|
||||
11: 00000063.*
|
||||
12: 00000061.*
|
||||
|
||||
00000013 <LONG>:
|
||||
13: ffffabcd.*
|
||||
14: 00000141.*
|
||||
|
||||
00000015 <WORD>:
|
||||
15: 00000c80.*
|
||||
16: 00000042.*
|
||||
17: ffffffbf.*
|
||||
18: 0000f410.*
|
||||
19: 00000041.*
|
||||
|
||||
0000001a <STRING>:
|
||||
1a: 44434241.*
|
||||
1b: 54535251.*
|
||||
1c: 73756f48.*
|
||||
1d: 306e6f74.*
|
||||
|
||||
0000001e <ASCII>:
|
||||
1e: 73696854.*
|
||||
1f: 20736920.*
|
||||
20: 65762061.*
|
||||
21: 6c207972.*
|
||||
22: 20676e6f.*
|
||||
23: 74786574.*
|
||||
24: 69685400.*
|
||||
25: 73692073.*
|
||||
26: 6f6e6120.*
|
||||
27: 72656874.*
|
||||
28: 00000000.*
|
||||
|
||||
00000029 <ASCIZ>:
|
||||
29: 73696854.*
|
||||
2a: 20736920.*
|
||||
2b: 65762061.*
|
||||
2c: 6c207972.*
|
||||
2d: 20676e6f.*
|
||||
2e: 74786574.*
|
||||
2f: 73696854.*
|
||||
30: 20736920.*
|
||||
31: 746f6e61.*
|
||||
32: 00726568.*
|
||||
|
||||
00000033 <BLOCK>:
|
||||
33: 00000000.*
|
||||
34: 00000000.*
|
||||
35: 00000000.*
|
||||
36: 00000000.*
|
||||
|
||||
00000037 <SPACE>:
|
||||
37: 00000000.*
|
||||
38: 00000000.*
|
||||
39: 00000000.*
|
||||
3a: 00000000.*
|
||||
|
||||
0000003b <ALIGN>:
|
||||
3b: 08000000.*
|
||||
3c: 0c800000.*
|
||||
3d: 0c800000.*
|
||||
3e: 0c800000.*
|
||||
3f: 0c800000.*
|
||||
40: 08000000.*
|
|
@ -0,0 +1,14 @@
|
|||
.text
|
||||
BYTE: .byte 10,-1,"abc",'a'
|
||||
HWORD: .hword 10,-1,"abc",'a'
|
||||
INT: .int 10,IEEE,-1,"abc",'a'
|
||||
LONG: .long 0FFFFABCDH,'A'+100h
|
||||
WORD: .word 3200,1+'A',-'A',0F410h,'A'
|
||||
STRING: .string "ABCD", 51h, 52h, 53h, 54h, "Houston", 36+12
|
||||
ASCII: .ascii "This is a very long text","This is another"
|
||||
ASCIZ: .asciz "This is a very long text","This is another"
|
||||
BLOCK: .block 4
|
||||
SPACE: .space 4
|
||||
ALIGN: ldi r0,r0
|
||||
.align
|
||||
ldi r0,r0
|
|
@ -0,0 +1,82 @@
|
|||
#objdump: -d -z
|
||||
#name: flonum constants
|
||||
|
||||
.*: +file format .*c4x.*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
00000000 <start>:
|
||||
0: 07608000.*
|
||||
1: 076012cd.*
|
||||
2: 07604580.*
|
||||
3: 0760e0a4.*
|
||||
4: 07604a80.*
|
||||
5: 0760ef5c.*
|
||||
6: 0760f800.*
|
||||
7: 07608000.*
|
||||
8: 07608000.*
|
||||
9: 0760f000.*
|
||||
a: 0760e800.*
|
||||
b: 076012cd.*
|
||||
c: 0760e0a4.*
|
||||
d: 07604a80.*
|
||||
e: 0760ef5c.*
|
||||
|
||||
0000000f <FLOAT>:
|
||||
f: 80000000.*
|
||||
10: 00000000.*
|
||||
11: ff000000.*
|
||||
12: ff800000.*
|
||||
13: 53fba6af.*
|
||||
14: 01400000.*
|
||||
15: 06760000.*
|
||||
16: 01490fdb.*
|
||||
|
||||
00000017 <SINGLE>:
|
||||
17: 80000000.*
|
||||
18: 00000000.*
|
||||
19: ff000000.*
|
||||
1a: ff800000.*
|
||||
1b: 53fba6af.*
|
||||
1c: 01400000.*
|
||||
1d: 06760000.*
|
||||
1e: 01490fdb.*
|
||||
|
||||
0000001f <DOUBLE>:
|
||||
1f: 80000000.*
|
||||
20: 00000000.*
|
||||
21: ff000000.*
|
||||
22: ff800000.*
|
||||
23: 53fba6af.*
|
||||
24: 01400000.*
|
||||
25: 06760000.*
|
||||
26: 01490fdb.*
|
||||
|
||||
00000027 <LDOUBLE>:
|
||||
27: 80000000.*
|
||||
28: 00000000.*
|
||||
29: 00000000.*
|
||||
2a: 00000000.*
|
||||
2b: ff000000.*
|
||||
2c: 00000000.*
|
||||
2d: ff800000.*
|
||||
2e: 80000000.*
|
||||
2f: 53fba6ae.*
|
||||
30: fba6ae9f.*
|
||||
31: 01400000.*
|
||||
32: 40000000.*
|
||||
33: 06760000.*
|
||||
34: 76000000.*
|
||||
35: 01490fda.*
|
||||
36: 490fdaa3.*
|
||||
|
||||
00000037 <IEEE>:
|
||||
37: 00000000.*
|
||||
38: 3f800000.*
|
||||
39: 3f000000.*
|
||||
3a: bf800000.*
|
||||
3b: 00000000.*
|
||||
3c: e9045951.*
|
||||
3d: 40400000.*
|
||||
3e: 42f60000.*
|
||||
3f: 40490fdb.*
|
|
@ -0,0 +1,28 @@
|
|||
;; test float numbers and constants
|
||||
.text
|
||||
;; Standard GAS syntax
|
||||
start: ldf 0e0, f0
|
||||
ldf 0e2.7, f0
|
||||
ldf 0e2.7e1, f0
|
||||
ldf 0e2.7e-1, f0
|
||||
ldf 0e-2.7e1, f0
|
||||
ldf 0e-2.7e-1, f0
|
||||
ldf -0e1.0, f0
|
||||
|
||||
;; Standard TI syntax
|
||||
ldf 0, f0
|
||||
ldf 0.0, f0
|
||||
ldf 0.5, f0
|
||||
ldf -0.5, f0
|
||||
ldf 2.7, f0
|
||||
ldf 2.7e-1, f0
|
||||
ldf -2.7e1, f0
|
||||
ldf -2.7e-1, f0
|
||||
|
||||
FLOAT: .float 0f0, 0f1.0, 0f0.5, 0f-1.0, 0e-1.0e25, 3, 123, 0f3.141592654
|
||||
SINGLE: .single 0f0, 0f1.0, 0f0.5, 0f-1.0, 0e-1.0e25, 3, 123, 0f3.141592654
|
||||
DOUBLE: .double 0f0, 0f1.0, 0f0.5, 0f-1.0, 0e-1.0e25, 3, 123, 0f3.141592654
|
||||
LDOUBLE: .ldouble 0f0, 0f1.0, 0f0.5, 0f-1.0, 0e-1.0e25, 3, 123, 0f3.141592654
|
||||
IEEE: .ieee 0f0, 0f1.0, 0f0.5, 0f-1,0, 0e-1.0e25, 3, 123, 0f3.141592654
|
||||
|
||||
.end
|
|
@ -0,0 +1,804 @@
|
|||
/* Opcode infix
|
||||
B condition 16--20 U,C,Z,LO,HI, etc.
|
||||
C condition 23--27 U,C,Z,LO,HI, etc.
|
||||
|
||||
Arguments
|
||||
, required arg follows
|
||||
; optional arg follows
|
||||
|
||||
General addressing modes
|
||||
* indirect 0--15 *+AR0(5), *++AR0(IR0)
|
||||
# direct (for ldp only) 0--15 @start, start
|
||||
@ direct 0--15 @start, start
|
||||
F short float immediate 0--15 3.5, 0e-3.5e-1
|
||||
Q register 0--15 R0, AR0, DP, SP
|
||||
R register 16--20 R0, AR0, DP, SP
|
||||
S short int immediate 0--15 -5, 5
|
||||
D src and dst same reg
|
||||
|
||||
Three operand addressing modes
|
||||
E register 0--7 R0, R7, R11
|
||||
G register 8--15 R0, R7, R11
|
||||
I indirect(short) 0--7 *+AR0(1), *+AR0(IR0)
|
||||
J indirect(short) 8--15 *+AR0(1), *+AR0(IR0)
|
||||
R register 16--20 R0, R7, R11
|
||||
W short int (C4x) 0--7 -3, 5
|
||||
C indirect(short) (C4x) 0--7 *+AR0(5)
|
||||
O indirect(short) (C4x) 8--15 *+AR0(5)
|
||||
|
||||
Parallel instruction addressing modes
|
||||
E register 0--7 R0, R7, R11
|
||||
G register 8--15 R0, R7, R11
|
||||
H register 18--16 R0, R7
|
||||
I indirect(short) 0--7 *+AR0(1), *+AR0(IR0)
|
||||
J indirect(short) 8--15 *+AR0(1), *+AR0(IR0)
|
||||
K register 19--21 R0, R7
|
||||
L register 22--24 R0, R7
|
||||
M register (R2,R3) 22--22 R2, R3
|
||||
N register (R0,R1) 23--23 R0, R1
|
||||
|
||||
Misc. addressing modes
|
||||
A address register 22--24 AR0, AR7
|
||||
B unsigned integer 0--23 @start, start (absolute on C3x, relative on C4x)
|
||||
P displacement (PC Rel) 0--15 @start, start
|
||||
U unsigned integer 0--15 0, 65535
|
||||
V vector (C4x: 0--8) 0--4 25, 7
|
||||
T integer (C4x) 16--20 -5, 12
|
||||
Y address reg (C4x) 16--20 AR0, DP, SP, IR0
|
||||
X expansion reg (C4x) 0--4 IVTP, TVTP
|
||||
Z expansion reg (C4x) 16--20 IVTP, TVTP
|
||||
*/
|
||||
|
||||
/* A: General 2-operand integer operations
|
||||
Syntax: <i> src, dst
|
||||
src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
|
||||
dst = Register (R)
|
||||
Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI,
|
||||
SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn,
|
||||
MBn, MHn, MPYSHI, MPYUHI
|
||||
*/
|
||||
#define A_CLASS(name) \
|
||||
name##_A: &\
|
||||
name AR1, AR0 /* Q;R */ &\
|
||||
name AR0 /* Q;R */ &\
|
||||
name @start, AR0 /* @,R */ &\
|
||||
name *+AR0(5), AR0 /* *,R */ &\
|
||||
name -5, AR0 /* S,R */
|
||||
|
||||
|
||||
/* AB: General 2-operand integer operation with condition
|
||||
Syntax: <i>c src, dst
|
||||
c = Condition
|
||||
src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
|
||||
dst = Register (R)
|
||||
Instr: 1/0 - LDIc
|
||||
*/
|
||||
#define AB_CLASS(name) \
|
||||
name##_AB: &\
|
||||
name AR1, AR0 /* Q;R */ &\
|
||||
name AR0 /* Q;R */ &\
|
||||
name @start, AR0 /* @,R */ &\
|
||||
name *+AR0(5), AR0 /* *,R */ &\
|
||||
name -5, AR0 /* S,R */
|
||||
|
||||
|
||||
/* AU: General 2-operand unsigned integer operation
|
||||
Syntax: <i> src, dst
|
||||
src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
|
||||
dst = Register (R)
|
||||
Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn
|
||||
*/
|
||||
#define AU_CLASS(name) \
|
||||
name##_AU: &\
|
||||
name AR1, AR0 /* Q;R */ &\
|
||||
name AR0 /* Q;R */ &\
|
||||
name @start, AR0 /* @,R */ &\
|
||||
name *+AR0(5), AR0 /* *,R */ &\
|
||||
name 5, AR0 /* U,R */
|
||||
|
||||
|
||||
/* AF: General 2-operand float to integer operation
|
||||
Syntax: <i> src, dst
|
||||
src = Register 0-11 (Q), Direct (@), Indirect (*), Float immediate (F)
|
||||
dst = Register (R)
|
||||
Instr: 1/0 - FIX
|
||||
*/
|
||||
#define AF_CLASS(name) \
|
||||
name##_AF: &\
|
||||
name R1, R0 /* Q;R */ &\
|
||||
name R0 /* Q;R */ &\
|
||||
name @start, AR0 /* @,R */ &\
|
||||
name *+AR0(5), AR0 /* *,R */ &\
|
||||
name 3.5, AR0 /* F,R */
|
||||
|
||||
|
||||
/* A2: Limited 1-operand (integer) operation
|
||||
Syntax: <i> src
|
||||
src = Register (Q), Indirect (*), None
|
||||
Instr: 1/0 - NOP
|
||||
*/
|
||||
#define A2_CLASS(name) \
|
||||
name##_A2: &\
|
||||
name AR0 /* Q */ &\
|
||||
name *+AR0(5) /* * */ &\
|
||||
name /* */
|
||||
|
||||
|
||||
/* A3: General 1-operand unsigned integer operation
|
||||
Syntax: <i> src
|
||||
src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
|
||||
Instr: 1/0 - RPTS
|
||||
*/
|
||||
#define A3_CLASS(name) \
|
||||
name##_A3: &\
|
||||
name AR1 /* Q */ &\
|
||||
name @start /* @ */ &\
|
||||
name *+AR0(5) /* * */ &\
|
||||
name 5 /* U */
|
||||
|
||||
|
||||
/* A6: Limited 2-operand integer operation
|
||||
Syntax: <i> src, dst
|
||||
src = Direct (@), Indirect (*)
|
||||
dst = Register (R)
|
||||
Instr: 1/1 - LDII, C4x: SIGI
|
||||
*/
|
||||
#define A6_CLASS(name) \
|
||||
name##_A6: &\
|
||||
name @start, AR0 /* @,R */ &\
|
||||
name *+AR0(5), AR0 /* *,R */
|
||||
|
||||
|
||||
/* A7: Limited 2-operand integer store operation
|
||||
Syntax: <i> src, dst
|
||||
src = Register (R)
|
||||
dst = Direct (@), Indirect (*)
|
||||
Instr: 2/0 - STI, STII
|
||||
*/
|
||||
#define A7_CLASS(name) \
|
||||
name##_A7: &\
|
||||
name AR0, @start /* R,@ */ &\
|
||||
name AR0, *+AR0(5) /* R,* */
|
||||
|
||||
|
||||
/* AY: General 2-operand signed address load operation
|
||||
Syntax: <i> src, dst
|
||||
src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
|
||||
dst = Address register - ARx, IRx, DP, BK, SP (Y)
|
||||
Instr: 0/1 - C4x: LDA
|
||||
Note: Q and Y should *never* be the same register
|
||||
*/
|
||||
#define AY_CLASS(name) \
|
||||
name##_AY: &\
|
||||
name AR1, AR0 /* Q,Y */ &\
|
||||
name @start, AR0 /* @,Y */ &\
|
||||
name *+AR0(5), AR0 /* *,Y */ &\
|
||||
name -5, AR0 /* S,Y */
|
||||
|
||||
|
||||
/* B: General 2-operand float operation
|
||||
Syntax: <i> src, dst
|
||||
src = Register 0-11 (Q), Direct (@), Indirect (*), Float immediate (F)
|
||||
dst = Register 0-11 (R)
|
||||
Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND,
|
||||
SUBF, SUBRF, C4x: RSQRF, TOIEEE
|
||||
*/
|
||||
#define B_CLASS(name) \
|
||||
name##_B: &\
|
||||
name R1, R0 /* Q;R */ &\
|
||||
name R0 /* Q;R */ &\
|
||||
name @start, R0 /* @,R */ &\
|
||||
name *+AR0(5), R0 /* *,R */ &\
|
||||
name 3.5, R0 /* F,R */
|
||||
|
||||
|
||||
/* BA: General 2-operand integer to float operation
|
||||
Syntax: <i> src, dst
|
||||
src = Register (Q), Direct (@), Indirect (*), Float immediate (F)
|
||||
dst = Register 0-11 (R)
|
||||
Instr: 0/1 - C4x: CRCPF
|
||||
*/
|
||||
#define BA_CLASS(name) \
|
||||
name##_BA: &\
|
||||
name AR1, R0 /* Q;R */ &\
|
||||
name R0 /* Q;R */ &\
|
||||
name @start, R0 /* @,R */ &\
|
||||
name *+AR0(5), R0 /* *,R */ &\
|
||||
name 3.5, R0 /* F,R */
|
||||
|
||||
|
||||
/* BB: General 2-operand conditional float operation
|
||||
Syntax: <i>c src, dst
|
||||
c = Condition
|
||||
src = Register 0-11 (Q), Direct (@), Indirect (*), Float immediate (F)
|
||||
dst = Register 0-11 (R)
|
||||
Instr: 1/0 - LDFc
|
||||
*/
|
||||
#define BB_CLASS(name) \
|
||||
name##_BB: &\
|
||||
name R1, R0 /* Q;R */ &\
|
||||
name R0 /* Q;R */ &\
|
||||
name @start, R0 /* @,R */ &\
|
||||
name *+AR0(5), R0 /* *,R */ &\
|
||||
name 3.5, R0 /* F,R */
|
||||
|
||||
|
||||
/* BI: General 2-operand integer to float operation (yet different to BA)
|
||||
Syntax: <i> src, dst
|
||||
src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
|
||||
dst = Register 0-11 (R)
|
||||
Instr: 1/0 - FLOAT
|
||||
*/
|
||||
#define BI_CLASS(name) \
|
||||
name##_BI: &\
|
||||
name AR1, R0 /* Q;R */ &\
|
||||
name R0 /* Q;R */ &\
|
||||
name @start, R0 /* @,R */ &\
|
||||
name *+AR0(5), R0 /* *,R */ &\
|
||||
name -5, R0 /* S,R */
|
||||
|
||||
|
||||
/* B6: Limited 2-operand float operation
|
||||
Syntax: <i> src, dst
|
||||
src = Direct (@), Indirect (*)
|
||||
dst = Register 0-11 (R)
|
||||
Instr: 1/1 - LDFI, C4x: FRIEEE
|
||||
*/
|
||||
#define B6_CLASS(name) \
|
||||
name##_B6: &\
|
||||
name @start, R0 /* @,R */ &\
|
||||
name *+AR0(5), R0 /* *,R */
|
||||
|
||||
|
||||
/* B7: Limited 2-operand float store operation
|
||||
Syntax: <i> src, dst
|
||||
src = Register 0-11 (R)
|
||||
dst = Direct (@), Indirect (*)
|
||||
Instr: 2/0 - STF, STFI
|
||||
*/
|
||||
#define B7_CLASS(name) \
|
||||
name##_B7: &\
|
||||
name R0, @start /* R,@ */ &\
|
||||
name R0, *+AR0(5) /* R,* */
|
||||
|
||||
|
||||
/* D: Decrement and brach operations
|
||||
Syntax: <i>c ARn, dst
|
||||
c = condition
|
||||
ARn = AR register 0-11 (A)
|
||||
dst = Register (Q), PC-relative (P)
|
||||
Instr: 2/0 - DBc, DBcD
|
||||
Alias: <name1> <name2>
|
||||
*/
|
||||
#define D_CLASS(name1, name2) \
|
||||
name1##_D: &\
|
||||
name1 AR0, R0 /* A,Q */ &\
|
||||
name1 AR0, start /* A,P */ &\
|
||||
name2##_D: &\
|
||||
name2 AR0, R0 /* A,Q */ &\
|
||||
name2 AR0, start /* A,P */
|
||||
|
||||
|
||||
/* J: General conditional branch operations
|
||||
Syntax: <i>c dst
|
||||
c = Condition
|
||||
dst = Register (Q), PC-relative (P)
|
||||
Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc
|
||||
Alias: <name1> <name2>
|
||||
*/
|
||||
#define J_CLASS(name1, name2) \
|
||||
name1##_J: &\
|
||||
name1 R0 /* Q */ &\
|
||||
name1 start /* P */ &\
|
||||
name2##_J: &\
|
||||
name2 R0 /* Q */ &\
|
||||
name2 start /* P */
|
||||
|
||||
|
||||
/* LL: Load-load parallell operation
|
||||
Syntax: <i> src2, dst2 || <i> src1, dst1
|
||||
src1 = Indirect 0,1,IR0,IR1 (J)
|
||||
dst1 = Register 0-7 (K)
|
||||
src2 = Indirect 0,1,IR0,IR1 (I)
|
||||
dst2 = Register 0-7 (L)
|
||||
Instr: 2/0 - LDF||LDF, LDI||LDI
|
||||
Alias: i||i, i1||i2, i2||i1
|
||||
*/
|
||||
#define LL_CLASS(name) \
|
||||
name##_LL: &\
|
||||
name *+AR0(1), R0 &|| name *+AR1(1), R1 /* I,L|J,K */ &\
|
||||
name##2 *+AR0(1), R0 &|| name##1 *+AR1(1), R1 /* I,L|J,K */ &\
|
||||
name##1 *+AR1(1), R1 &|| name##2 *+AR0(1), R0 /* J,K|I,L */
|
||||
|
||||
|
||||
/* LS: Store-store parallell operation
|
||||
Syntax: <i> src2, dst2 || <i> src1, dst1
|
||||
src1 = Register 0-7 (H)
|
||||
dst1 = Indirect 0,1,IR0,IR1 (J)
|
||||
src2 = Register 0-7 (L)
|
||||
dst2 = Indirect 0,1,IR0,IR1 (I)
|
||||
Instr: 2/0 - STF||STF, STI||STI
|
||||
Alias: i||i, i1||i2, i2||i1.
|
||||
*/
|
||||
#define LS_CLASS(name) \
|
||||
name##_LS: &\
|
||||
name R0, *+AR0(1) &|| name R1, *+AR1(1) /* L,I|H,J */ &\
|
||||
name##2 R0, *+AR0(1) &|| name##1 R1, *+AR1(1) /* L,I|H,J */ &\
|
||||
name##1 R1, *+AR1(1) &|| name##2 R0, *+AR0(1) /* H,J|L,I */
|
||||
|
||||
|
||||
/* M: General multiply and add/sub operations
|
||||
Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual
|
||||
<ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual
|
||||
<ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01]
|
||||
<ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual
|
||||
<ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual
|
||||
<ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03]
|
||||
src1 = Register 0-7 (K)
|
||||
src2 = Register 0-7 (H)
|
||||
src3 = Indirect 0,1,IR0,IR1 (J)
|
||||
src4 = Indirect 0,1,IR0,IR1 (I)
|
||||
dst1 = Register 0-1 (N)
|
||||
dst2 = Register 2-3 (M)
|
||||
Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3
|
||||
Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3
|
||||
*/
|
||||
#define M_CLASS(namea, nameb) \
|
||||
namea##_##nameb##_M: &\
|
||||
namea *+AR0(1), *+AR1(1), R0 &|| nameb R0, R1, R2 /* I,J,N|H,K;M */ &\
|
||||
namea *+AR0(1), *+AR1(1), R0 &|| nameb R0, R2 /* I,J,N|H,K;M */ &\
|
||||
namea *+AR0(1), R0, R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
|
||||
namea *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
|
||||
namea R0, *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\
|
||||
namea R2, R1, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
|
||||
namea R2, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
|
||||
namea *+AR0(1), R1, R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
|
||||
namea *+AR0(1), R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
|
||||
namea *+AR0(1), R1, R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\
|
||||
namea *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\
|
||||
namea R0, *+AR0(1), R0 &|| nameb *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\
|
||||
namea R0, *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* K,J,N|I,H;M */ &\
|
||||
namea##3_##nameb##_M: &\
|
||||
namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb R0, R1, R2 /* I,J,N|H,K;M */ &\
|
||||
namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb R0, R2 /* I,J,N|H,K;M */ &\
|
||||
namea##3 *+AR0(1), R0, R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
|
||||
namea##3 *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
|
||||
namea##3 R0, *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\
|
||||
namea##3 R2, R1, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
|
||||
namea##3 R2, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
|
||||
namea##3 *+AR0(1), R1, R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
|
||||
namea##3 *+AR0(1), R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
|
||||
namea##3 *+AR0(1), R1, R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\
|
||||
namea##3 *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\
|
||||
namea##3 R0, *+AR0(1), R0 &|| nameb *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\
|
||||
namea##3 R0, *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* K,J,N|I,H;M */ &\
|
||||
namea##_##nameb##3_M: &\
|
||||
namea *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R1, R2 /* I,J,N|H,K;M */ &\
|
||||
namea *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R2 /* I,J,N|H,K;M */ &\
|
||||
namea *+AR0(1), R0, R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
|
||||
namea *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
|
||||
namea R0, *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\
|
||||
namea R2, R1, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
|
||||
namea R2, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
|
||||
namea *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
|
||||
namea *+AR0(1), R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
|
||||
namea *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\
|
||||
namea *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\
|
||||
namea R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\
|
||||
namea R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* K,J,N|I,H;M */ &\
|
||||
namea##3_##nameb##3_M: &\
|
||||
namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R1, R2 /* I,J,N|H,K;M */ &\
|
||||
namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R2 /* I,J,N|H,K;M */ &\
|
||||
namea##3 *+AR0(1), R0, R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
|
||||
namea##3 *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
|
||||
namea##3 R0, *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\
|
||||
namea##3 R2, R1, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
|
||||
namea##3 R2, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
|
||||
namea##3 *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
|
||||
namea##3 *+AR0(1), R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
|
||||
namea##3 *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\
|
||||
namea##3 *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\
|
||||
namea##3 R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\
|
||||
namea##3 R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* K,J,N|I,H;M */ &\
|
||||
nameb##_##namea##_M: &\
|
||||
nameb R0, R1, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
|
||||
nameb R0, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
|
||||
nameb R0, *+AR1(1), R2 &|| namea *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\
|
||||
nameb R0, *+AR1(1), R2 &|| namea *+AR0(1), R0 /* H,I,M|J,K;N */ &\
|
||||
nameb R0, *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\
|
||||
nameb *+AR0(1), *+AR1(1), R2 &|| namea R2, R1, R0 /* I,J,M|H,K;N */ &\
|
||||
nameb *+AR0(1), *+AR1(1), R2 &|| namea R2, R0 /* I,J,M|H,K;N */ &\
|
||||
nameb *+AR1(1), R3, R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
|
||||
nameb *+AR1(1), R3, R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\
|
||||
nameb *+AR1(1), R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
|
||||
nameb *+AR1(1), R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\
|
||||
nameb *+AR1(1), R0, R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
|
||||
nameb *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
|
||||
nameb##3_##namea##3_M: &\
|
||||
nameb##3 R0, R1, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
|
||||
nameb##3 R0, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
|
||||
nameb##3 R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\
|
||||
nameb##3 R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* H,I,M|J,K;N */ &\
|
||||
nameb##3 R0, *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\
|
||||
nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R1, R0 /* I,J,M|H,K;N */ &\
|
||||
nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R0 /* I,J,M|H,K;N */ &\
|
||||
nameb##3 *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
|
||||
nameb##3 *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\
|
||||
nameb##3 *+AR1(1), R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
|
||||
nameb##3 *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\
|
||||
nameb##3 *+AR1(1), R0, R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
|
||||
nameb##3 *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
|
||||
nameb##_##namea##3_M: &\
|
||||
nameb R0, R1, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
|
||||
nameb R0, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
|
||||
nameb R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\
|
||||
nameb R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* H,I,M|J,K;N */ &\
|
||||
nameb R0, *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\
|
||||
nameb *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R1, R0 /* I,J,M|H,K;N */ &\
|
||||
nameb *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R0 /* I,J,M|H,K;N */ &\
|
||||
nameb *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
|
||||
nameb *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\
|
||||
nameb *+AR1(1), R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
|
||||
nameb *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\
|
||||
nameb *+AR1(1), R0, R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
|
||||
nameb *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
|
||||
nameb##3_##namea##_M: &\
|
||||
nameb##3 R0, R1, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
|
||||
nameb##3 R0, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
|
||||
nameb##3 R0, *+AR1(1), R2 &|| namea *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\
|
||||
nameb##3 R0, *+AR1(1), R2 &|| namea *+AR0(1), R0 /* H,I,M|J,K;N */ &\
|
||||
nameb##3 R0, *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\
|
||||
nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea R2, R1, R0 /* I,J,M|H,K;N */ &\
|
||||
nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea R2, R0 /* I,J,M|H,K;N */ &\
|
||||
nameb##3 *+AR1(1), R3, R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
|
||||
nameb##3 *+AR1(1), R3, R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\
|
||||
nameb##3 *+AR1(1), R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
|
||||
nameb##3 *+AR1(1), R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\
|
||||
nameb##3 *+AR1(1), R0, R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
|
||||
nameb##3 *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
|
||||
|
||||
|
||||
/* P: General 2-operand operation with parallell store
|
||||
Syntax: <ia> src2, dst1 || <ib> src3, dst2
|
||||
src2 = Indirect 0,1,IR0,IR1 (I)
|
||||
dst1 = Register 0-7 (L)
|
||||
src3 = Register 0-7 (H)
|
||||
dst2 = Indirect 0,1,IR0,IR1 (J)
|
||||
Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF,
|
||||
LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF,
|
||||
TOIEEE||STF
|
||||
Alias: a||b, b||a
|
||||
*/
|
||||
#define P_CLASS(namea, nameb) \
|
||||
namea##_##nameb##_P: &\
|
||||
namea *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* I,L|H,J */ &\
|
||||
nameb R1, *+AR1(1) &|| namea *+AR0(1), R0 /* H,J|I,L */
|
||||
|
||||
|
||||
/* Q: General 3-operand operation with parallell store
|
||||
Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2
|
||||
src1 = Register 0-7 (K)
|
||||
src2 = Indirect 0,1,IR0,IR1 (I)
|
||||
dst1 = Register 0-7 (L)
|
||||
src3 = Register 0-7 (H)
|
||||
dst2 = Indirect 0,1,IR0,IR1 (J)
|
||||
Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI
|
||||
Alias: a||b, b||a, a3||b, b||a3
|
||||
*/
|
||||
#define Q_CLASS(namea, nameb) \
|
||||
namea##_##nameb##_Q: &\
|
||||
namea R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\
|
||||
nameb R1, *+AR1(1) &|| namea R0, *+AR0(1), R0 /* H,J|K,I,L */ &\
|
||||
namea##3_##nameb##_Q: &\
|
||||
namea##3 R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\
|
||||
nameb R1, *+AR1(1) &|| namea##3 R0, *+AR0(1), R0 /* H,J|K,I,L */
|
||||
|
||||
|
||||
/* QC: General commutative 3-operand operation with parallell store
|
||||
Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2
|
||||
<ia> src1, src2, dst1 || <ib> src3, dst2 - Manual
|
||||
src1 = Register 0-7 (K)
|
||||
src2 = Indirect 0,1,IR0,IR1 (I)
|
||||
dst1 = Register 0-7 (L)
|
||||
src3 = Register 0-7 (H)
|
||||
dst2 = Indirect 0,1,IR0,IR1 (J)
|
||||
Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI,
|
||||
OR3||STI, XOR3||STI
|
||||
Alias: a||b, b||a, a3||b, b||a3
|
||||
*/
|
||||
#define QC_CLASS(namea, nameb) \
|
||||
namea##_##nameb##_QC: &\
|
||||
namea *+AR0(1), R1, R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\
|
||||
namea *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\
|
||||
namea R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\
|
||||
nameb R1, *+AR1(1) &|| namea *+AR0(1), R1, R0 /* H,J|I,K;L */ &\
|
||||
nameb R1, *+AR1(1) &|| namea *+AR0(1), R0 /* H,J|I,K;L */ &\
|
||||
nameb R1, *+AR1(1) &|| namea R0, *+AR0(1), R0 /* H,J|K,I,L */ &\
|
||||
namea##3_##nameb##_QC: &\
|
||||
namea##3 *+AR0(1), R1, R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\
|
||||
namea##3 *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\
|
||||
namea##3 R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\
|
||||
nameb R1, *+AR1(1) &|| namea##3 *+AR0(1), R1, R0 /* H,J|I,K;L */ &\
|
||||
nameb R1, *+AR1(1) &|| namea##3 *+AR0(1), R0 /* H,J|I,K;L */ &\
|
||||
nameb R1, *+AR1(1) &|| namea##3 R0, *+AR0(1), R0 /* H,J|K,I,L */
|
||||
|
||||
|
||||
/* R: General register integer operation
|
||||
Syntax: <i> dst
|
||||
dst = Register (R)
|
||||
Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC
|
||||
*/
|
||||
#define R_CLASS(name) \
|
||||
name##_R: &\
|
||||
name AR0 /* R */
|
||||
|
||||
|
||||
/* RF: General register float operation
|
||||
Syntax: <i> dst
|
||||
dst = Register 0-11 (R)
|
||||
Instr: 2/0 - POPF, PUSHF
|
||||
*/
|
||||
#define RF_CLASS(name) \
|
||||
name##_RF: &\
|
||||
name F0 /* R */
|
||||
|
||||
|
||||
/* S: General 3-operand float operation
|
||||
Syntax: <i> src2, src1, dst
|
||||
src2 = Register 0-11 (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
|
||||
src1 = Register 0-11 (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
|
||||
dst = Register 0-11 (R)
|
||||
Instr: 1/0 - SUBF3
|
||||
Alias: i, i3
|
||||
*/
|
||||
#define S_CLASS(name) \
|
||||
name##_S: &\
|
||||
name R2, R1, R0 /* E,G;R */ &\
|
||||
name R1, R0 /* E,G;R */ &\
|
||||
name R1, *+AR0(1), R0 /* E,J,R */ &\
|
||||
name *+AR0(1), R1, R0 /* I,G;R */ &\
|
||||
name *+AR0(1), R0 /* I,G;R */ &\
|
||||
name *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name *+AR0(5), R1, R0 /* C,G;R */ &\
|
||||
name *+AR0(5), R0 /* C,G;R */ &\
|
||||
name *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\
|
||||
.endif &\
|
||||
name##3_S: &\
|
||||
name##3 R2, R1, R0 /* E,G;R */ &\
|
||||
name##3 R1, R0 /* E,G;R */ &\
|
||||
name##3 R1, *+AR0(1), R0 /* E,J,R */ &\
|
||||
name##3 *+AR0(1), R1, R0 /* I,G;R */ &\
|
||||
name##3 *+AR0(1), R0 /* I,G;R */ &\
|
||||
name##3 *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name##3 *+AR0(5), R1, R0 /* C,G;R */ &\
|
||||
name##3 *+AR0(5), R0 /* C,G;R */ &\
|
||||
name##3 *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\
|
||||
.endif
|
||||
|
||||
|
||||
/* SC: General commutative 3-operand float operation
|
||||
Syntax: <i> src2, src1, dst - Manual
|
||||
<i> src1, src2, dst
|
||||
src2 = Register 0-11 (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
|
||||
src1 = Register 0-11 (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
|
||||
dst = Register 0-11 (R)
|
||||
Instr: 2/0 - ADDF3, MPYF3
|
||||
Alias: i, i3
|
||||
*/
|
||||
#define SC_CLASS(name) \
|
||||
name##_SC: &\
|
||||
name R2, R1, R0 /* E,G;R */ &\
|
||||
name R1, R0 /* E,G;R */ &\
|
||||
name R1, *+AR0(1), R0 /* E,J,R */ &\
|
||||
name *+AR0(1), R1, R0 /* I,G;R */ &\
|
||||
name *+AR0(1), R0 /* I,G;R */ &\
|
||||
name *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name *+AR0(5), R1, R0 /* C,G;R */ &\
|
||||
name *+AR0(5), R0 /* C,G;R */ &\
|
||||
name R1, *+AR0(5), R0 /* G,C,R */ &\
|
||||
name *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\
|
||||
.endif &\
|
||||
name##3_SC: &\
|
||||
name##3 R2, R1, R0 /* E,G;R */ &\
|
||||
name##3 R1, R0 /* E,G;R */ &\
|
||||
name##3 R1, *+AR0(1), R0 /* E,J,R */ &\
|
||||
name##3 *+AR0(1), R1, R0 /* I,G;R */ &\
|
||||
name##3 *+AR0(1), R0 /* I,G;R */ &\
|
||||
name##3 *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name##3 *+AR0(5), R1, R0 /* C,G;R */ &\
|
||||
name##3 *+AR0(5), R0 /* C,G;R */ &\
|
||||
name##3 R1, *+AR0(5), R0 /* G,C,R */ &\
|
||||
name##3 *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\
|
||||
.endif
|
||||
|
||||
|
||||
/* S2: General 3-operand float operation with 2 args
|
||||
Syntax: <i> src2, src1
|
||||
src2 = Register 0-11 (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
|
||||
src1 = Register 0-11 (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
|
||||
Instr: 1/0 - CMPF3
|
||||
Alias: i, i3
|
||||
*/
|
||||
#define S2_CLASS(name) \
|
||||
name##_S2: &\
|
||||
name R2, R1 /* E,G */ &\
|
||||
name R1, *+AR0(1) /* E,J */ &\
|
||||
name *+AR0(1), R1 /* I,G */ &\
|
||||
name *+AR0(1), *+AR1(1) /* I,J */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name *+AR0(5), R1 /* C,G */ &\
|
||||
name *+AR0(5), *+AR1(5) /* C,O */ &\
|
||||
.endif &\
|
||||
name##3_S2: &\
|
||||
name##3 R2, R1 /* E,G */ &\
|
||||
name##3 R1, *+AR0(1) /* E,J */ &\
|
||||
name##3 *+AR0(1), R1 /* I,G */ &\
|
||||
name##3 *+AR0(1), *+AR1(1) /* I,J */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name##3 *+AR0(5), R1 /* C,G */ &\
|
||||
name##3 *+AR0(5), *+AR1(5) /* C,O */ &\
|
||||
.endif
|
||||
|
||||
|
||||
/* T: General 3-operand integer operand
|
||||
Syntax: <i> src2, src1, dst
|
||||
src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
|
||||
src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
|
||||
dst = Register (R)
|
||||
Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3
|
||||
Alias: i, i3
|
||||
*/
|
||||
#define T_CLASS(name) \
|
||||
name##_T: &\
|
||||
name AR2, AR1, AR0 /* E,G;R */ &\
|
||||
name AR1, AR0 /* E,G;R */ &\
|
||||
name AR1, *+AR0(1), AR0 /* E,J,R */ &\
|
||||
name *+AR0(1), AR1, AR0 /* I,G;R */ &\
|
||||
name *+AR0(1), AR0 /* I,G;R */ &\
|
||||
name *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name 5, AR1, AR0 /* W,G;R */ &\
|
||||
name 5, AR0 /* W,G;R */ &\
|
||||
name *+AR0(5), AR1, AR0 /* C,G;R */ &\
|
||||
name *+AR0(5), AR0 /* C,G;R */ &\
|
||||
name 5, *+AR0(5), AR0 /* W,O,R */ &\
|
||||
name *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\
|
||||
.endif &\
|
||||
name##3_T: &\
|
||||
name##3 AR2, AR1, AR0 /* E,G;R */ &\
|
||||
name##3 AR1, AR0 /* E,G;R */ &\
|
||||
name##3 AR1, *+AR0(1), AR0 /* E,J,R */ &\
|
||||
name##3 *+AR0(1), AR1, AR0 /* I,G;R */ &\
|
||||
name##3 *+AR0(1), AR0 /* I,G;R */ &\
|
||||
name##3 *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name##3 -5, AR1, AR0 /* W,G;R */ &\
|
||||
name##3 -5, AR0 /* W,G;R */ &\
|
||||
name##3 *+AR0(5), AR1, AR0 /* C,G;R */ &\
|
||||
name##3 *+AR0(5), AR0 /* C,G;R */ &\
|
||||
name##3 -5, *+AR0(5), AR0 /* W,O,R */ &\
|
||||
name##3 *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\
|
||||
.endif
|
||||
|
||||
|
||||
/* TC: General commutative 3-operand integer operation
|
||||
Syntax: <i> src2, src1, dst
|
||||
<i> src1, src2, dst
|
||||
src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
|
||||
src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
|
||||
dst = Register (R)
|
||||
Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI
|
||||
Alias: i, i3
|
||||
*/
|
||||
#define TC_CLASS(name) \
|
||||
name##_TC: &\
|
||||
name AR2, AR1, AR0 /* E,G;R */ &\
|
||||
name AR1, AR0 /* E,G;R */ &\
|
||||
name AR1, *+AR0(1), AR0 /* E,J,R */ &\
|
||||
name *+AR0(1), AR1, AR0 /* I,G;R */ &\
|
||||
name *+AR0(1), AR0 /* I,G;R */ &\
|
||||
name *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name 5, AR1, AR0 /* W,G;R */ &\
|
||||
name 5, AR0 /* W,G;R */ &\
|
||||
name AR1, -5, AR0 /* G,W,R */ &\
|
||||
name *+AR0(5), AR1, AR0 /* C,G;R */ &\
|
||||
name *+AR0(5), AR0 /* C,G;R */ &\
|
||||
name AR1, *+AR0(5), AR0 /* G,C,R */ &\
|
||||
name 5, *+AR0(5), AR0 /* W,O,R */ &\
|
||||
name *+AR0(5), -5, AR0 /* O,W,R */ &\
|
||||
name *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\
|
||||
.endif &\
|
||||
name##3_TC: &\
|
||||
name##3 AR2, AR1, AR0 /* E,G;R */ &\
|
||||
name##3 AR1, AR0 /* E,G;R */ &\
|
||||
name##3 AR1, *+AR0(1), AR0 /* E,J,R */ &\
|
||||
name##3 *+AR0(1), AR1, AR0 /* I,G;R */ &\
|
||||
name##3 *+AR0(1), AR0 /* I,G;R */ &\
|
||||
name##3 *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name##3 -5, AR1, AR0 /* W,G;R */ &\
|
||||
name##3 -5, AR0 /* W,G;R */ &\
|
||||
name##3 AR1, -5, AR0 /* G,W,R */ &\
|
||||
name##3 *+AR0(5), AR1, AR0 /* C,G;R */ &\
|
||||
name##3 *+AR0(5), AR0 /* C,G;R */ &\
|
||||
name##3 AR1, *+AR0(5), AR0 /* G,C,R */ &\
|
||||
name##3 -5, *+AR0(5), AR0 /* W,O,R */ &\
|
||||
name##3 *+AR0(5), -5, AR0 /* O,W,R */ &\
|
||||
name##3 *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\
|
||||
.endif
|
||||
|
||||
|
||||
/* T2: General 3-operand integer operation with 2 args
|
||||
Syntax: <i> src2, src1
|
||||
src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
|
||||
src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
|
||||
Instr: 1/0 - CMPI3
|
||||
Alias: i, i3
|
||||
*/
|
||||
#define T2_CLASS(name) \
|
||||
name##_T2: &\
|
||||
name AR2, AR1 /* E,G */ &\
|
||||
name AR1, *+AR0(1) /* E,J */ &\
|
||||
name *+AR0(1), AR1 /* I,G */ &\
|
||||
name *+AR1(1), *+AR0(1) /* I,J */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name -5, AR1 /* W,G */ &\
|
||||
name *+AR0(5), AR1 /* C,G */ &\
|
||||
name -5, *+AR0(5) /* W,O */ &\
|
||||
name *+AR0(5), *+AR1(5) /* C,O */ &\
|
||||
.endif &\
|
||||
name##3_T2: &\
|
||||
name##3 AR2, AR1 /* E,G */ &\
|
||||
name##3 AR1, *+AR0(1) /* E,J */ &\
|
||||
name##3 *+AR0(1), AR1 /* I,G */ &\
|
||||
name##3 *+AR1(1), *+AR0(1) /* I,J */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name##3 -5, AR1 /* W,G */ &\
|
||||
name##3 *+AR0(5), AR1 /* C,G */ &\
|
||||
name##3 -5, *+AR0(5) /* W,O */ &\
|
||||
name##3 *+AR0(5), *+AR1(5) /* C,O */ &\
|
||||
.endif
|
||||
|
||||
|
||||
/* T2C: General commutative 3-operand integer operation with 2 args
|
||||
Syntax: <i> src2, src1 - Manual
|
||||
<i> src1, src2
|
||||
src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
|
||||
src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0)
|
||||
Instr: 1/0 - TSTB3
|
||||
Alias: i, i3
|
||||
*/
|
||||
#define T2C_CLASS(name) \
|
||||
name##_T2C: &\
|
||||
name AR2, AR1 /* E,G */ &\
|
||||
name AR1, *+AR0(1) /* E,J */ &\
|
||||
name *+AR0(1), AR1 /* I,G */ &\
|
||||
name *+AR1(1), *+AR0(1) /* I,J */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name 5, AR1 /* W,G */ &\
|
||||
name AR1, -5 /* G,W */ &\
|
||||
name *+AR0(5), AR1 /* C,G */ &\
|
||||
name AR1, *+AR0(5) /* G,C */ &\
|
||||
name 5, *+AR0(5) /* W,O */ &\
|
||||
name *+AR0(5), -5 /* O,W */ &\
|
||||
name *+AR0(5), *+AR1(5) /* C,O */ &\
|
||||
.endif &\
|
||||
name##3_T2C: &\
|
||||
name##3 AR2, AR1 /* E,G */ &\
|
||||
name##3 AR1, *+AR0(1) /* E,J */ &\
|
||||
name##3 *+AR0(1), AR1 /* I,G */ &\
|
||||
name##3 *+AR1(1), *+AR0(1) /* I,J */ &\
|
||||
.ifdef TEST_C4X &\
|
||||
name##3 -5, AR1 /* W,G */ &\
|
||||
name##3 AR1, -5 /* G,W */ &\
|
||||
name##3 *+AR0(5), AR1 /* C,G */ &\
|
||||
name##3 AR1, *+AR0(5) /* G,C */ &\
|
||||
name##3 -5, *+AR0(5) /* W,O */ &\
|
||||
name##3 *+AR0(5), -5 /* O,W */ &\
|
||||
name##3 *+AR0(5), *+AR1(5) /* C,O */ &\
|
||||
.endif
|
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,10 @@
|
|||
#!/bin/sh
|
||||
|
||||
echo "Rebuilding opcodes.s from allopcodes.S"
|
||||
cat <<EOF >opcodes.s
|
||||
; File is autogenerated from allopcodes.S - do not edit
|
||||
; Please use ./rebuild.sh to rebuild this file
|
||||
|
||||
EOF
|
||||
|
||||
cpp -P allopcodes.S >>opcodes.s
|
|
@ -0,0 +1,69 @@
|
|||
;; test all register names c3x
|
||||
.text
|
||||
;; Test the base names
|
||||
.ifdef TEST_ALL
|
||||
start: ldi R0,R0
|
||||
ldi R0,R1
|
||||
ldi R0,R2
|
||||
ldi R0,R3
|
||||
ldi R0,R4
|
||||
ldi R0,R5
|
||||
ldi R0,R6
|
||||
ldi R0,R7
|
||||
ldi R0,AR0
|
||||
ldi R0,AR1
|
||||
ldi R0,AR2
|
||||
ldi R0,AR3
|
||||
ldi R0,AR4
|
||||
ldi R0,AR5
|
||||
ldi R0,AR6
|
||||
ldi R0,AR7
|
||||
ldi R0,DP
|
||||
ldi R0,IR0
|
||||
ldi R0,IR1
|
||||
ldi R0,BK
|
||||
ldi R0,SP
|
||||
ldi R0,ST
|
||||
.endif
|
||||
.ifdef TEST_C3X
|
||||
ldi R0,IE
|
||||
ldi R0,IF
|
||||
ldi R0,IOF
|
||||
.endif
|
||||
.ifdef TEST_C4X
|
||||
ldi R0,DIE
|
||||
ldi R0,IIE
|
||||
ldi R0,IIF
|
||||
.endif
|
||||
.ifdef TEST_ALL
|
||||
ldi R0,RS
|
||||
ldi R0,RE
|
||||
ldi R0,RC
|
||||
.endif
|
||||
.ifdef TEST_C4X
|
||||
ldi R0,R8
|
||||
ldi R0,R9
|
||||
ldi R0,R10
|
||||
ldi R0,R11
|
||||
ldpe R0,IVTP
|
||||
ldpe R0,TVTP
|
||||
.endif
|
||||
|
||||
;; Test the alternative names
|
||||
.ifdef TEST_ALL
|
||||
ldf F0,F0
|
||||
ldf F0,F1
|
||||
ldf F0,F2
|
||||
ldf F0,F3
|
||||
ldf F0,F4
|
||||
ldf F0,F5
|
||||
ldf F0,F6
|
||||
ldf F0,F7
|
||||
.endif
|
||||
.ifdef TEST_C4X
|
||||
ldf F0,F8
|
||||
ldf F0,F9
|
||||
ldf F0,F10
|
||||
ldf F0,F11
|
||||
.endif
|
||||
.end
|
|
@ -0,0 +1,46 @@
|
|||
#as: -m30 --defsym TEST_ALL=1 --defsym TEST_C3X=1
|
||||
#objdump: -d -z
|
||||
#name: c3x registers
|
||||
#source: registers.s
|
||||
|
||||
.*: +file format .*c4x.*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
00000000 <start>:
|
||||
0: 08000000.*
|
||||
1: 08010000.*
|
||||
2: 08020000.*
|
||||
3: 08030000.*
|
||||
4: 08040000.*
|
||||
5: 08050000.*
|
||||
6: 08060000.*
|
||||
7: 08070000.*
|
||||
8: 08080000.*
|
||||
9: 08090000.*
|
||||
a: 080a0000.*
|
||||
b: 080b0000.*
|
||||
c: 080c0000.*
|
||||
d: 080d0000.*
|
||||
e: 080e0000.*
|
||||
f: 080f0000.*
|
||||
10: 08100000.*
|
||||
11: 08110000.*
|
||||
12: 08120000.*
|
||||
13: 08130000.*
|
||||
14: 08140000.*
|
||||
15: 08150000.*
|
||||
16: 08160000.*
|
||||
17: 08170000.*
|
||||
18: 08180000.*
|
||||
19: 08190000.*
|
||||
1a: 081a0000.*
|
||||
1b: 081b0000.*
|
||||
1c: 07000000.*
|
||||
1d: 07010000.*
|
||||
1e: 07020000.*
|
||||
1f: 07030000.*
|
||||
20: 07040000.*
|
||||
21: 07050000.*
|
||||
22: 07060000.*
|
||||
23: 07070000.*
|
|
@ -0,0 +1,56 @@
|
|||
#as: -m40 --defsym TEST_ALL=1 --defsym TEST_C4X=1
|
||||
#objdump: -d -z
|
||||
#name: c4x registers
|
||||
#source: registers.s
|
||||
|
||||
.*: +file format .*c4x.*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
00000000 <start>:
|
||||
0: 08000000.*
|
||||
1: 08010000.*
|
||||
2: 08020000.*
|
||||
3: 08030000.*
|
||||
4: 08040000.*
|
||||
5: 08050000.*
|
||||
6: 08060000.*
|
||||
7: 08070000.*
|
||||
8: 08080000.*
|
||||
9: 08090000.*
|
||||
a: 080a0000.*
|
||||
b: 080b0000.*
|
||||
c: 080c0000.*
|
||||
d: 080d0000.*
|
||||
e: 080e0000.*
|
||||
f: 080f0000.*
|
||||
10: 08100000.*
|
||||
11: 08110000.*
|
||||
12: 08120000.*
|
||||
13: 08130000.*
|
||||
14: 08140000.*
|
||||
15: 08150000.*
|
||||
16: 08160000.*
|
||||
17: 08170000.*
|
||||
18: 08180000.*
|
||||
19: 08190000.*
|
||||
1a: 081a0000.*
|
||||
1b: 081b0000.*
|
||||
1c: 081c0000.*
|
||||
1d: 081d0000.*
|
||||
1e: 081e0000.*
|
||||
1f: 081f0000.*
|
||||
20: 76800000.*
|
||||
21: 76810000.*
|
||||
22: 07000000.*
|
||||
23: 07010000.*
|
||||
24: 07020000.*
|
||||
25: 07030000.*
|
||||
26: 07040000.*
|
||||
27: 07050000.*
|
||||
28: 07060000.*
|
||||
29: 07070000.*
|
||||
2a: 071c0000.*
|
||||
2b: 071d0000.*
|
||||
2c: 071e0000.*
|
||||
2d: 071f0000.*
|
|
@ -0,0 +1,64 @@
|
|||
|
||||
#
|
||||
# Test x930509a -- correct assembly of differences involving forward
|
||||
# references.
|
||||
#
|
||||
proc do_930509a_tic4x {} {
|
||||
set testname "difference between forward references (tic4x version)"
|
||||
set x 0
|
||||
gas_start "../all/x930509.s" "-al"
|
||||
while 1 {
|
||||
# We need to accomodate both byte orders here.
|
||||
# If ".long" means an 8-byte value on some target someday, this test will have
|
||||
# to be fixed.
|
||||
expect {
|
||||
-re "^ +1 .... 00 ?00 ?00 ?00" { fail $testname; set x 1 }
|
||||
-re "^ +1 .... 01 ?00 ?00 ?00" { pass $testname; set x 1 }
|
||||
-re "^ +1 .... 00 ?00 ?00 ?01" { pass $testname; set x 1 }
|
||||
-re "\[^\n\]*\n" { }
|
||||
timeout { perror "timeout\n"; break }
|
||||
eof { break }
|
||||
}
|
||||
}
|
||||
gas_finish
|
||||
if !$x then { fail $testname }
|
||||
}
|
||||
|
||||
|
||||
#
|
||||
# TI TMS320C4X tests.
|
||||
#
|
||||
if [istarget *c4x*-*-*] then {
|
||||
do_930509a_tic4x
|
||||
|
||||
# Test zero-based disassemble test
|
||||
run_dump_test "zeros"
|
||||
|
||||
# Test the register names on the c3x and on the c4x
|
||||
run_dump_test "registers_c3x"
|
||||
run_dump_test "registers_c4x"
|
||||
|
||||
# Make sure the c4x registers dont work on c3x
|
||||
gas_test_error "registers.s" "-m30 --defsym TEST_C4X=1" "c4x register usage in c3x"
|
||||
|
||||
# Test data storage
|
||||
run_dump_test "data"
|
||||
|
||||
# Test flonums
|
||||
run_dump_test "float"
|
||||
|
||||
# Test all addressing modes
|
||||
run_dump_test "addressing_c3x"
|
||||
run_dump_test "addressing_c4x"
|
||||
|
||||
# Make sure the c4x addressing dont work on c3x
|
||||
gas_test_error "addressing.s" "-m30 --defsym TEST_C4X=1" "c4x addressing usage in c3x"
|
||||
|
||||
# Test float instructions
|
||||
run_dump_test "opcodes_c3x"
|
||||
run_dump_test "opcodes_c4x"
|
||||
|
||||
# Make sure the c4x ops dont work on c3x
|
||||
#gas_test_error "opcodes.s" "-m30 --defsym TEST_C4X=1" "c4x instruction usage in c3x"
|
||||
# -- for some reason this test crashes dejagnu, hence disabled!
|
||||
}
|
|
@ -0,0 +1,24 @@
|
|||
#objdump: -d
|
||||
#name: zero-value disassemble check
|
||||
|
||||
.*: +file format .*c4x.*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
00000000 <start>:
|
||||
0: 00000000.*
|
||||
1: 00000000.*
|
||||
2: 00000002.*
|
||||
...
|
||||
16: 00000001.*
|
||||
17: 00000001.*
|
||||
18: 00000002.*
|
||||
19: 00000000.*
|
||||
1a: 00000001.*
|
||||
1b: 00000001.*
|
||||
1c: 00000002.*
|
||||
1d: 00000000.*
|
||||
1e: 00000000.*
|
||||
1f: 00000002.*
|
||||
20: 00000000.*
|
||||
21: 00000000.*
|
|
@ -0,0 +1,35 @@
|
|||
.text
|
||||
start: .long 0
|
||||
.long 0
|
||||
.long 2
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 1
|
||||
.long 1
|
||||
.long 2
|
||||
.long 0
|
||||
.long 1
|
||||
.long 1
|
||||
.long 2
|
||||
.long 0
|
||||
.long 0
|
||||
.long 2
|
||||
.long 0
|
||||
.long 0
|
|
@ -1,3 +1,7 @@
|
|||
2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com>
|
||||
|
||||
* testsuite/ld-scripts/script.exp: Setup for tic4x testcase
|
||||
|
||||
2002-11-14 Egor Duda <deo@logos-m.ru>
|
||||
|
||||
* ldmain.c (main): Make runtime relocs disabled by default. Remove
|
||||
|
|
|
@ -42,6 +42,10 @@ proc check_script { } {
|
|||
} else {
|
||||
set text_end 0x104
|
||||
set data_end 0x1004
|
||||
if [istarget *c4x*-*-*] then {
|
||||
set text_end 0x101
|
||||
set data_end 0x1001
|
||||
}
|
||||
if [istarget *c54x*-*-*] then {
|
||||
set text_end 0x102
|
||||
set data_end 0x1002
|
||||
|
|
Loading…
Reference in New Issue