From 49f245127b72d3cc68d6feedecb5be743d0712c1 Mon Sep 17 00:00:00 2001
From: Ian Lance Taylor <ian@airs.com>
Date: Fri, 3 Mar 1995 21:13:37 +0000
Subject: [PATCH] 	* mips.h (INSN_ISA4): Define.

---
 include/opcode/ChangeLog | 8 ++++++++
 include/opcode/mips.h    | 4 ++++
 2 files changed, 12 insertions(+)

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index edfb3ce3d6..840323f384 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,11 @@
+Fri Mar  3 16:10:24 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (INSN_ISA4): Define.
+
+Fri Feb 24 19:13:37 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (M_DLA_AB, M_DLI): Define.
+
 Thu Feb 23 17:33:09 1995  Jeff Law  (law@snake.cs.utah.edu)
 
 	* hppa.h (fstwx): Fix single-bit error.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 664582880a..366e243048 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -230,6 +230,8 @@ struct mips_opcode
 #define INSN_ISA3		    0x20000000
 /* MIPS R4650 instruction.  */
 #define INSN_4650		    0x30000000
+/* MIPS ISA 4 instruction (R8000).  */
+#define INSN_ISA4		    0x40000000
 
 /* Instruction is actually a macro.  It should be ignored by the
    disassembler, and requires special treatment by the assembler.  */
@@ -295,6 +297,8 @@ enum {
     M_DIV_3I,
     M_DIVU_3,
     M_DIVU_3I,
+    M_DLA_AB,
+    M_DLI,
     M_DMUL,
     M_DMUL_I, 
     M_DMULO,