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New sim testsuite for Fujitsu FRV. Contributed by Red Hat.

This commit is contained in:
Dave Brolley 2003-08-29 16:41:31 +00:00
parent b34f6357d0
commit 4a30611667
794 changed files with 113410 additions and 0 deletions
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34
sim/testsuite/frv-elf/ChangeLog Normal file
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2000-07-26 Dave Brolley <brolley@redhat.com>
* Makefile.in (TESTS): Don't run cache.ok
* cache.s: Use softune syntax for jmpl.
2000-07-19 Dave Brolley <brolley@redhat.com>
* cache.s (pass): Use softune syntax for tira.
* exit47.s (pass): Use softune syntax for tira.
* grloop.s (pass): Use softune syntax for tira.
* hello.s (pass): Use softune syntax for tira.
Thu Aug 19 18:00:16 1999 Dave Brolley <brolley@cygnus.com>
* hello.s: Fix sethi, setlo insn usage.
Mon Jun 21 17:33:37 1999 Dave Brolley <brolley@cygnus.com>
* Makefile.in (TESTS): Add grloop.ok.
* grloop.s: New testcase.
Fri Jun 18 17:55:02 1999 Dave Brolley <brolley@cygnus.com>
* exit47.s: Use proper syscalls interface.
* hello.s: Use proper syscalls interface.
Mon May 31 12:03:38 1999 Dave Brolley <brolley@cygnus.com>
* hello.s,loop.s,exit47.s: Convert to frv insn set.
Thu May 6 16:36:30 1999 Dave Brolley <brolley@cygnus.com>
* Directory created.

159
sim/testsuite/frv-elf/Makefile.in Normal file
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# Makefile for regression testing the frv simulator.
# Copyright (C) 1998 Free Software Foundation, Inc.
# This file is part of GDB.
# GDB is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
# GDB is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
VPATH = @srcdir@
srcdir = @srcdir@
srcroot = $(srcdir)/../../..
prefix = @prefix@
exec_prefix = @exec_prefix@
host_alias = @host_alias@
target_alias = @target_alias@
program_transform_name = @program_transform_name@
build_canonical = @build@
host_canonical = @host@
target_canonical = @target@
target_cpu = @target_cpu@
SHELL = @SHELL@
SUBDIRS = @subdirs@
RPATH_ENVVAR = @RPATH_ENVVAR@
EXPECT = `if [ -f ../../../expect/expect ] ; then \
echo ../../../expect/expect ; \
else echo expect ; fi`
RUNTEST = $(RUNTEST_FOR_TARGET)
RUNTESTFLAGS =
RUNTEST_FOR_TARGET = `\
if [ -f $${srcroot}/dejagnu/runtest ]; then \
echo $${srcroot}/dejagnu/runtest; \
else \
if [ "$(host_canonical)" = "$(target_canonical)" ]; then \
echo runtest; \
else \
t='$(program_transform_name)'; echo runtest | sed -e '' $$t; \
fi; \
fi`
AS_FOR_TARGET = `\
if [ -x ../../../gas/as-new ]; then \
echo ../../../gas/as-new ; \
else \
echo $(target_alias)-as ; \
fi`
LD_FOR_TARGET = `\
if [ -x ../../../ld/ld-new ]; then \
echo ../../../ld/ld-new ; \
else \
echo $(target_alias)-ld ; \
fi`
RUN_FOR_TARGET = `\
if [ -x ../../../sim/${target_cpu}/run ]; then \
echo ../../../sim/${target_cpu}/run ; \
else \
echo $(target_alias)-run ; \
fi`
TESTS = \
exit47.ko \
grloop.ok \
hello.ok
check: sanity $(TESTS)
sanity:
@eval echo AS_FOR_TARGET = $(AS_FOR_TARGET)
@eval echo LD_FOR_TARGET = $(LD_FOR_TARGET)
@eval echo RUN_FOR_TARGET = $(RUN_FOR_TARGET)
# Rules for running all the tests, put into three types
# exit success, exit fail, print "Hello World"
.u.log:
uudecode $*.u
$(RUN_FOR_TARGET) $* > $*.log
# Rules for running the tests
.SUFFIXES: .u .ok .run .hi .ko
.run.ok:
rm -f tmp-$* $*.hi
ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$*
mv tmp-$* $*.ok
.run.hi:
rm -f tmp-$* $*.hi diff-$*
ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$*
echo "Hello World" | diff - tmp-$* > diff-$*
cat tmp-$* diff-$* > $*.hi
.run.ko:
rm -f tmp-$* $*.ko
set +e ; \
ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* ; \
if [ $$? -eq 47 ] ; then \
exit 0 ; \
else \
exit 1 ; \
fi
mv tmp-$* $*.ko
# Rules for building all the tests and packing them into
# uuencoded files.
uuencode: em-pstr.u em-e0.u em-e47.u em-pchr.u
.SUFFIXES: .u .s .run
.s.u:
rm -f $*.o $*.run
$(AS_FOR_TARGET) $(srcdir)/$*.s -o $*.o
$(LD_FOR_TARGET) -o $* $*.o
uuencode < $* $* > $*.u
rm -f $*.o $*
.s.run:
rm -f $*.o $*.run
$(AS_FOR_TARGET) $(srcdir)/$*.s -o $*.o
$(LD_FOR_TARGET) -o $*.run $*.o
rm -f $*.o $*
clean mostlyclean:
rm -f *~ core *.o a.out
rm -f $(TESTS)
distclean maintainer-clean realclean: clean
rm -f *~ core
rm -f Makefile config.status *-init.exp
rm -fr *.log summary detail *.plog *.sum *.psum site.*
Makefile : Makefile.in config.status
$(SHELL) config.status
config.status: configure
$(SHELL) config.status --recheck

164
sim/testsuite/frv-elf/cache.s Normal file
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# run with --memory-region 0xff000000,4 --memory-region 0xfe000000,00404000
; Exit with return code
.macro exit rc
setlos.p #1,gr7
setlos \rc,gr8
tira gr0,#0
.endm
; Pass the test case
.macro pass
pass:
setlos.p #5,gr10
setlos #1,gr8
setlos #5,gr7
sethi.p %hi(passmsg),gr9
setlo %lo(passmsg),gr9
tira gr0,#0
exit #0
.endm
; Fail the testcase
.macro fail
fail\@:
setlos.p #5,gr10
setlos #1,gr8
setlos #5,gr7
sethi.p %hi(failmsg),gr9
setlo %lo(failmsg),gr9
tira gr0,#0
exit #1
.endm
.data
failmsg:
.ascii "fail\n"
passmsg:
.ascii "pass\n"
.text
.global _start
_start:
movsg hsr0,gr10 ; enable insn and data caches
sethi.p 0xc800,gr11 ; in copy-back mode
setlo 0x0000,gr11
or gr10,gr11,gr10
movgs gr10,hsr0
sethi.p 0x7,sp
setlo 0x0000,sp
; fill the cache
sethi.p %hi(done1),gr10
setlo %lo(done1),gr10
movgs gr10,lr
setlos.p 0x1000,gr10
setlos 0x0,gr11
movgs gr10,lcr
write1: st.p gr11,@(sp,gr11)
addi.p gr11,4,gr11
bctrlr.p 1,0
bra write1
done1:
; read it back
sethi.p %hi(done2),gr10
setlo %lo(done2),gr10
movgs gr10,lr
setlos.p 0x1000,gr10
setlos 0x0,gr11
movgs gr10,lcr
read1: ld @(sp,gr11),gr12
cmp gr11,gr12,icc0
bne icc0,1,fail
addi.p gr11,4,gr11
bctrlr.p 1,0
bra read1
done2:
; fill the cache twice
sethi.p %hi(done3),gr10
setlo %lo(done3),gr10
movgs gr10,lr
setlos.p 0x2000,gr10
setlos 0x0,gr11
movgs gr10,lcr
write3: st.p gr11,@(sp,gr11)
addi.p gr11,4,gr11
bctrlr.p 1,0
bra write3
done3:
; read it back
sethi.p %hi(done4),gr10
setlo %lo(done4),gr10
movgs gr10,lr
setlos.p 0x2000,gr10
setlos 0x0,gr11
movgs gr10,lcr
read4: ld @(sp,gr11),gr12
cmp gr11,gr12,icc0
bne icc0,1,fail
addi.p gr11,4,gr11
bctrlr.p 1,0
bra read4
done4:
; read it back in reverse
sethi.p %hi(done5),gr10
setlo %lo(done5),gr10
movgs gr10,lr
setlos.p 0x2000,gr10
setlos 0x7ffc,gr11
movgs gr10,lcr
read5: ld @(sp,gr11),gr12
cmp gr11,gr12,icc0
bne icc0,1,fail
subi.p gr11,4,gr11
bctrlr.p 1,0
bra read5
done5:
; access data and insns in non-cache areas
sethi.p 0x8038,gr11 ; bctrlr 0,0
setlo 0x2000,gr11
sethi.p 0xff00,gr10 ; documented area
setlo 0x0000,gr10
sti gr11,@(gr10,0)
jmpl @(gr10,gr0)
; enable RAM mode
movsg hsr0,gr10
sethi.p 0x0040,gr12
setlo 0x0000,gr12
or gr10,gr12,gr10
movgs gr10,hsr0
sethi.p 0xfe00,gr10 ; documented area
setlo 0x0400,gr10
sti gr11,@(gr10,0)
jmpl @(gr10,gr0)
sethi.p 0xfe40,gr10 ; documented area
setlo 0x0400,gr10
sti gr11,@(gr10,0)
dcf @(gr10,gr0)
jmpl @(gr10,gr0)
sethi.p 0x0007,gr10 ; non RAM area
setlo 0x0000,gr10
sti gr11,@(gr10,0)
jmpl @(gr10,gr0)
sethi.p 0xfe00,gr10 ; insn RAM area
setlo 0x0000,gr10
sti gr11,@(gr10,0)
jmpl @(gr10,gr0)
sethi.p 0xfe40,gr10 ; data RAM area
setlo 0x0000,gr10
sti gr11,@(gr10,0)
dcf @(gr10,gr0)
jmpl @(gr10,gr0)
pass
fail:
fail

905
sim/testsuite/frv-elf/configure vendored Executable file
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#! /bin/sh
# Guess values for system-dependent variables and create Makefiles.
# Generated automatically using autoconf version 2.13
# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.
#
# This configure script is free software; the Free Software Foundation
# gives unlimited permission to copy, distribute and modify it.
# Defaults:
ac_help=
ac_default_prefix=/usr/local
# Any additions from configure.in:
# Initialize some variables set by options.
# The variables have the same names as the options, with
# dashes changed to underlines.
build=NONE
cache_file=./config.cache
exec_prefix=NONE
host=NONE
no_create=
nonopt=NONE
no_recursion=
prefix=NONE
program_prefix=NONE
program_suffix=NONE
program_transform_name=s,x,x,
silent=
site=
srcdir=
target=NONE
verbose=
x_includes=NONE
x_libraries=NONE
bindir='${exec_prefix}/bin'
sbindir='${exec_prefix}/sbin'
libexecdir='${exec_prefix}/libexec'
datadir='${prefix}/share'
sysconfdir='${prefix}/etc'
sharedstatedir='${prefix}/com'
localstatedir='${prefix}/var'
libdir='${exec_prefix}/lib'
includedir='${prefix}/include'
oldincludedir='/usr/include'
infodir='${prefix}/info'
mandir='${prefix}/man'
# Initialize some other variables.
subdirs=
MFLAGS= MAKEFLAGS=
SHELL=${CONFIG_SHELL-/bin/sh}
# Maximum number of lines to put in a shell here document.
ac_max_here_lines=12
ac_prev=
for ac_option
do
# If the previous option needs an argument, assign it.
if test -n "$ac_prev"; then
eval "$ac_prev=\$ac_option"
ac_prev=
continue
fi
case "$ac_option" in
-*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;;
*) ac_optarg= ;;
esac
# Accept the important Cygnus configure options, so we can diagnose typos.
case "$ac_option" in
-bindir | --bindir | --bindi | --bind | --bin | --bi)
ac_prev=bindir ;;
-bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
bindir="$ac_optarg" ;;
-build | --build | --buil | --bui | --bu)
ac_prev=build ;;
-build=* | --build=* | --buil=* | --bui=* | --bu=*)
build="$ac_optarg" ;;
-cache-file | --cache-file | --cache-fil | --cache-fi \
| --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
ac_prev=cache_file ;;
-cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
| --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
cache_file="$ac_optarg" ;;
-datadir | --datadir | --datadi | --datad | --data | --dat | --da)
ac_prev=datadir ;;
-datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
| --da=*)
datadir="$ac_optarg" ;;
-disable-* | --disable-*)
ac_feature=`echo $ac_option|sed -e 's/-*disable-//'`
# Reject names that are not valid shell variable names.
if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then
{ echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
fi
ac_feature=`echo $ac_feature| sed 's/-/_/g'`
eval "enable_${ac_feature}=no" ;;
-enable-* | --enable-*)
ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'`
# Reject names that are not valid shell variable names.
if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then
{ echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
fi
ac_feature=`echo $ac_feature| sed 's/-/_/g'`
case "$ac_option" in
*=*) ;;
*) ac_optarg=yes ;;
esac
eval "enable_${ac_feature}='$ac_optarg'" ;;
-exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
| --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
| --exec | --exe | --ex)
ac_prev=exec_prefix ;;
-exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
| --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
| --exec=* | --exe=* | --ex=*)
exec_prefix="$ac_optarg" ;;
-gas | --gas | --ga | --g)
# Obsolete; use --with-gas.
with_gas=yes ;;
-help | --help | --hel | --he)
# Omit some internal or obsolete options to make the list less imposing.
# This message is too long to be a string in the A/UX 3.1 sh.
cat << EOF
Usage: configure [options] [host]
Options: [defaults in brackets after descriptions]
Configuration:
--cache-file=FILE cache test results in FILE
--help print this message
--no-create do not create output files
--quiet, --silent do not print \`checking...' messages
--version print the version of autoconf that created configure
Directory and file names:
--prefix=PREFIX install architecture-independent files in PREFIX
[$ac_default_prefix]
--exec-prefix=EPREFIX install architecture-dependent files in EPREFIX
[same as prefix]
--bindir=DIR user executables in DIR [EPREFIX/bin]
--sbindir=DIR system admin executables in DIR [EPREFIX/sbin]
--libexecdir=DIR program executables in DIR [EPREFIX/libexec]
--datadir=DIR read-only architecture-independent data in DIR
[PREFIX/share]
--sysconfdir=DIR read-only single-machine data in DIR [PREFIX/etc]
--sharedstatedir=DIR modifiable architecture-independent data in DIR
[PREFIX/com]
--localstatedir=DIR modifiable single-machine data in DIR [PREFIX/var]
--libdir=DIR object code libraries in DIR [EPREFIX/lib]
--includedir=DIR C header files in DIR [PREFIX/include]
--oldincludedir=DIR C header files for non-gcc in DIR [/usr/include]
--infodir=DIR info documentation in DIR [PREFIX/info]
--mandir=DIR man documentation in DIR [PREFIX/man]
--srcdir=DIR find the sources in DIR [configure dir or ..]
--program-prefix=PREFIX prepend PREFIX to installed program names
--program-suffix=SUFFIX append SUFFIX to installed program names
--program-transform-name=PROGRAM
run sed PROGRAM on installed program names
EOF
cat << EOF
Host type:
--build=BUILD configure for building on BUILD [BUILD=HOST]
--host=HOST configure for HOST [guessed]
--target=TARGET configure for TARGET [TARGET=HOST]
Features and packages:
--disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no)
--enable-FEATURE[=ARG] include FEATURE [ARG=yes]
--with-PACKAGE[=ARG] use PACKAGE [ARG=yes]
--without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no)
--x-includes=DIR X include files are in DIR
--x-libraries=DIR X library files are in DIR
EOF
if test -n "$ac_help"; then
echo "--enable and --with options recognized:$ac_help"
fi
exit 0 ;;
-host | --host | --hos | --ho)
ac_prev=host ;;
-host=* | --host=* | --hos=* | --ho=*)
host="$ac_optarg" ;;
-includedir | --includedir | --includedi | --included | --include \
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ac_prev=includedir ;;
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includedir="$ac_optarg" ;;
-infodir | --infodir | --infodi | --infod | --info | --inf)
ac_prev=infodir ;;
-infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
infodir="$ac_optarg" ;;
-libdir | --libdir | --libdi | --libd)
ac_prev=libdir ;;
-libdir=* | --libdir=* | --libdi=* | --libd=*)
libdir="$ac_optarg" ;;
-libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
| --libexe | --libex | --libe)
ac_prev=libexecdir ;;
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| --libexe=* | --libex=* | --libe=*)
libexecdir="$ac_optarg" ;;
-localstatedir | --localstatedir | --localstatedi | --localstated \
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ac_prev=localstatedir ;;
-localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
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localstatedir="$ac_optarg" ;;
-mandir | --mandir | --mandi | --mand | --man | --ma | --m)
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mandir="$ac_optarg" ;;
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# Obsolete; use --without-fp.
with_fp=no ;;
-no-create | --no-create | --no-creat | --no-crea | --no-cre \
| --no-cr | --no-c)
no_create=yes ;;
-no-recursion | --no-recursion | --no-recursio | --no-recursi \
| --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
no_recursion=yes ;;
-oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
| --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
| --oldin | --oldi | --old | --ol | --o)
ac_prev=oldincludedir ;;
-oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
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| --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
oldincludedir="$ac_optarg" ;;
-prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
ac_prev=prefix ;;
-prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
prefix="$ac_optarg" ;;
-program-prefix | --program-prefix | --program-prefi | --program-pref \
| --program-pre | --program-pr | --program-p)
ac_prev=program_prefix ;;
-program-prefix=* | --program-prefix=* | --program-prefi=* \
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-program-suffix | --program-suffix | --program-suffi | --program-suff \
| --program-suf | --program-su | --program-s)
ac_prev=program_suffix ;;
-program-suffix=* | --program-suffix=* | --program-suffi=* \
| --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
program_suffix="$ac_optarg" ;;
-program-transform-name | --program-transform-name \
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| --program-transform-n | --program-transform- \
| --program-transform | --program-transfor \
| --program-transfo | --program-transf \
| --program-trans | --program-tran \
| --progr-tra | --program-tr | --program-t)
ac_prev=program_transform_name ;;
-program-transform-name=* | --program-transform-name=* \
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| --program-transform=* | --program-transfor=* \
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| --program-trans=* | --program-tran=* \
| --progr-tra=* | --program-tr=* | --program-t=*)
program_transform_name="$ac_optarg" ;;
-q | -quiet | --quiet | --quie | --qui | --qu | --q \
| -silent | --silent | --silen | --sile | --sil)
silent=yes ;;
-sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
ac_prev=sbindir ;;
-sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
| --sbi=* | --sb=*)
sbindir="$ac_optarg" ;;
-sharedstatedir | --sharedstatedir | --sharedstatedi \
| --sharedstated | --sharedstate | --sharedstat | --sharedsta \
| --sharedst | --shareds | --shared | --share | --shar \
| --sha | --sh)
ac_prev=sharedstatedir ;;
-sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
| --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
| --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
| --sha=* | --sh=*)
sharedstatedir="$ac_optarg" ;;
-site | --site | --sit)
ac_prev=site ;;
-site=* | --site=* | --sit=*)
site="$ac_optarg" ;;
-srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
ac_prev=srcdir ;;
-srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
srcdir="$ac_optarg" ;;
-sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
| --syscon | --sysco | --sysc | --sys | --sy)
ac_prev=sysconfdir ;;
-sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
| --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
sysconfdir="$ac_optarg" ;;
-target | --target | --targe | --targ | --tar | --ta | --t)
ac_prev=target ;;
-target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
target="$ac_optarg" ;;
-v | -verbose | --verbose | --verbos | --verbo | --verb)
verbose=yes ;;
-version | --version | --versio | --versi | --vers)
echo "configure generated by autoconf version 2.13"
exit 0 ;;
-with-* | --with-*)
ac_package=`echo $ac_option|sed -e 's/-*with-//' -e 's/=.*//'`
# Reject names that are not valid shell variable names.
if test -n "`echo $ac_package| sed 's/[-_a-zA-Z0-9]//g'`"; then
{ echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; }
fi
ac_package=`echo $ac_package| sed 's/-/_/g'`
case "$ac_option" in
*=*) ;;
*) ac_optarg=yes ;;
esac
eval "with_${ac_package}='$ac_optarg'" ;;
-without-* | --without-*)
ac_package=`echo $ac_option|sed -e 's/-*without-//'`
# Reject names that are not valid shell variable names.
if test -n "`echo $ac_package| sed 's/[-a-zA-Z0-9_]//g'`"; then
{ echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; }
fi
ac_package=`echo $ac_package| sed 's/-/_/g'`
eval "with_${ac_package}=no" ;;
--x)
# Obsolete; use --with-x.
with_x=yes ;;
-x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
| --x-incl | --x-inc | --x-in | --x-i)
ac_prev=x_includes ;;
-x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
| --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
x_includes="$ac_optarg" ;;
-x-libraries | --x-libraries | --x-librarie | --x-librari \
| --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
ac_prev=x_libraries ;;
-x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
| --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
x_libraries="$ac_optarg" ;;
-*) { echo "configure: error: $ac_option: invalid option; use --help to show usage" 1>&2; exit 1; }
;;
*)
if test -n "`echo $ac_option| sed 's/[-a-z0-9.]//g'`"; then
echo "configure: warning: $ac_option: invalid host type" 1>&2
fi
if test "x$nonopt" != xNONE; then
{ echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; }
fi
nonopt="$ac_option"
;;
esac
done
if test -n "$ac_prev"; then
{ echo "configure: error: missing argument to --`echo $ac_prev | sed 's/_/-/g'`" 1>&2; exit 1; }
fi
trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
# File descriptor usage:
# 0 standard input
# 1 file creation
# 2 errors and warnings
# 3 some systems may open it to /dev/tty
# 4 used on the Kubota Titan
# 6 checking for... messages and results
# 5 compiler messages saved in config.log
if test "$silent" = yes; then
exec 6>/dev/null
else
exec 6>&1
fi
exec 5>./config.log
echo "\
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
" 1>&5
# Strip out --no-create and --no-recursion so they do not pile up.
# Also quote any args containing shell metacharacters.
ac_configure_args=
for ac_arg
do
case "$ac_arg" in
-no-create | --no-create | --no-creat | --no-crea | --no-cre \
| --no-cr | --no-c) ;;
-no-recursion | --no-recursion | --no-recursio | --no-recursi \
| --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ;;
*" "*|*" "*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?]*)
ac_configure_args="$ac_configure_args '$ac_arg'" ;;
*) ac_configure_args="$ac_configure_args $ac_arg" ;;
esac
done
# NLS nuisances.
# Only set these to C if already set. These must not be set unconditionally
# because not all systems understand e.g. LANG=C (notably SCO).
# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'!
# Non-C LC_CTYPE values break the ctype check.
if test "${LANG+set}" = set; then LANG=C; export LANG; fi
if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi
if test "${LC_MESSAGES+set}" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi
if test "${LC_CTYPE+set}" = set; then LC_CTYPE=C; export LC_CTYPE; fi
# confdefs.h avoids OS command line length limits that DEFS can exceed.
rm -rf conftest* confdefs.h
# AIX cpp loses on an empty file, so make sure it contains at least a newline.
echo > confdefs.h
# A filename unique to this package, relative to the directory that
# configure is in, which we can look for to find out if srcdir is correct.
ac_unique_file=Makefile.in
# Find the source files, if location was not specified.
if test -z "$srcdir"; then
ac_srcdir_defaulted=yes
# Try the directory containing this script, then its parent.
ac_prog=$0
ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'`
test "x$ac_confdir" = "x$ac_prog" && ac_confdir=.
srcdir=$ac_confdir
if test ! -r $srcdir/$ac_unique_file; then
srcdir=..
fi
else
ac_srcdir_defaulted=no
fi
if test ! -r $srcdir/$ac_unique_file; then
if test "$ac_srcdir_defaulted" = yes; then
{ echo "configure: error: can not find sources in $ac_confdir or .." 1>&2; exit 1; }
else
{ echo "configure: error: can not find sources in $srcdir" 1>&2; exit 1; }
fi
fi
srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'`
# Prefer explicitly selected file to automatically selected ones.
if test -z "$CONFIG_SITE"; then
if test "x$prefix" != xNONE; then
CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
else
CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
fi
fi
for ac_site_file in $CONFIG_SITE; do
if test -r "$ac_site_file"; then
echo "loading site script $ac_site_file"
. "$ac_site_file"
fi
done
if test -r "$cache_file"; then
echo "loading cache $cache_file"
. $cache_file
else
echo "creating cache $cache_file"
> $cache_file
fi
ac_ext=c
# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
ac_cpp='$CPP $CPPFLAGS'
ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
cross_compiling=$ac_cv_prog_cc_cross
ac_exeext=
ac_objext=o
if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then
# Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu.
if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then
ac_n= ac_c='
' ac_t=' '
else
ac_n=-n ac_c= ac_t=
fi
else
ac_n= ac_c='\c' ac_t=
fi
CC=${CC-cc}
ac_aux_dir=
for ac_dir in `cd $srcdir;pwd`/../../.. $srcdir/`cd $srcdir;pwd`/../../..; do
if test -f $ac_dir/install-sh; then
ac_aux_dir=$ac_dir
ac_install_sh="$ac_aux_dir/install-sh -c"
break
elif test -f $ac_dir/install.sh; then
ac_aux_dir=$ac_dir
ac_install_sh="$ac_aux_dir/install.sh -c"
break
fi
done
if test -z "$ac_aux_dir"; then
{ echo "configure: error: can not find install-sh or install.sh in `cd $srcdir;pwd`/../../.. $srcdir/`cd $srcdir;pwd`/../../.." 1>&2; exit 1; }
fi
ac_config_guess=$ac_aux_dir/config.guess
ac_config_sub=$ac_aux_dir/config.sub
ac_configure=$ac_aux_dir/configure # This should be Cygnus configure.
# Do some error checking and defaulting for the host and target type.
# The inputs are:
# configure --host=HOST --target=TARGET --build=BUILD NONOPT
#
# The rules are:
# 1. You are not allowed to specify --host, --target, and nonopt at the
# same time.
# 2. Host defaults to nonopt.
# 3. If nonopt is not specified, then host defaults to the current host,
# as determined by config.guess.
# 4. Target and build default to nonopt.
# 5. If nonopt is not specified, then target and build default to host.
# The aliases save the names the user supplied, while $host etc.
# will get canonicalized.
case $host---$target---$nonopt in
NONE---*---* | *---NONE---* | *---*---NONE) ;;
*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;;
esac
# Make sure we can run config.sub.
if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then :
else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
fi
echo $ac_n "checking host system type""... $ac_c" 1>&6
echo "configure:575: checking host system type" >&5
host_alias=$host
case "$host_alias" in
NONE)
case $nonopt in
NONE)
if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then :
else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; }
fi ;;
*) host_alias=$nonopt ;;
esac ;;
esac
host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias`
host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
echo "$ac_t""$host" 1>&6
echo $ac_n "checking target system type""... $ac_c" 1>&6
echo "configure:596: checking target system type" >&5
target_alias=$target
case "$target_alias" in
NONE)
case $nonopt in
NONE) target_alias=$host_alias ;;
*) target_alias=$nonopt ;;
esac ;;
esac
target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias`
target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
echo "$ac_t""$target" 1>&6
echo $ac_n "checking build system type""... $ac_c" 1>&6
echo "configure:614: checking build system type" >&5
build_alias=$build
case "$build_alias" in
NONE)
case $nonopt in
NONE) build_alias=$host_alias ;;
*) build_alias=$nonopt ;;
esac ;;
esac
build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias`
build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
echo "$ac_t""$build" 1>&6
test "$host_alias" != "$target_alias" &&
test "$program_prefix$program_suffix$program_transform_name" = \
NONENONEs,x,x, &&
program_prefix=${target_alias}-
trap '' 1 2 15
cat > confcache <<\EOF
# This file is a shell script that caches the results of configure
# tests run on this system so they can be shared between configure
# scripts and configure runs. It is not useful on other systems.
# If it contains results you don't want to keep, you may remove or edit it.
#
# By default, configure uses ./config.cache as the cache file,
# creating it if it does not exist already. You can give configure
# the --cache-file=FILE option to use a different cache file; that is
# what configure does when it calls configure scripts in
# subdirectories, so they share the cache.
# Giving --cache-file=/dev/null disables caching, for debugging configure.
# config.status only pays attention to the cache file if you give it the
# --recheck option to rerun configure.
#
EOF
# The following way of writing the cache mishandles newlines in values,
# but we know of no workaround that is simple, portable, and efficient.
# So, don't put newlines in cache variables' values.
# Ultrix sh set writes to stderr and can't be redirected directly,
# and sets the high bit in the cache file unless we assign to the vars.
(set) 2>&1 |
case `(ac_space=' '; set | grep ac_space) 2>&1` in
*ac_space=\ *)
# `set' does not quote correctly, so add quotes (double-quote substitution
# turns \\\\ into \\, and sed turns \\ into \).
sed -n \
-e "s/'/'\\\\''/g" \
-e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p"
;;
*)
# `set' quotes correctly as required by POSIX, so do not add quotes.
sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p'
;;
esac >> confcache
if cmp -s $cache_file confcache; then
:
else
if test -w $cache_file; then
echo "updating cache $cache_file"
cat confcache > $cache_file
else
echo "not updating unwritable cache $cache_file"
fi
fi
rm -f confcache
trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
test "x$prefix" = xNONE && prefix=$ac_default_prefix
# Let make expand exec_prefix.
test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
# Any assignment to VPATH causes Sun make to only execute
# the first set of double-colon rules, so remove it if not needed.
# If there is a colon in the path, we need to keep it.
if test "x$srcdir" = x.; then
ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d'
fi
trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15
# Transform confdefs.h into DEFS.
# Protect against shell expansion while executing Makefile rules.
# Protect against Makefile macro expansion.
cat > conftest.defs <<\EOF
s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g
s%[ `~#$^&*(){}\\|;'"<>?]%\\&%g
s%\[%\\&%g
s%\]%\\&%g
s%\$%$$%g
EOF
DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '`
rm -f conftest.defs
# Without the "./", some shells look in PATH for config.status.
: ${CONFIG_STATUS=./config.status}
echo creating $CONFIG_STATUS
rm -f $CONFIG_STATUS
cat > $CONFIG_STATUS <<EOF
#! /bin/sh
# Generated automatically by configure.
# Run this file to recreate the current configuration.
# This directory was configured as follows,
# on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
#
# $0 $ac_configure_args
#
# Compiler output produced by configure, useful for debugging
# configure, is in ./config.log if it exists.
ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]"
for ac_option
do
case "\$ac_option" in
-recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion"
exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;
-version | --version | --versio | --versi | --vers | --ver | --ve | --v)
echo "$CONFIG_STATUS generated by autoconf version 2.13"
exit 0 ;;
-help | --help | --hel | --he | --h)
echo "\$ac_cs_usage"; exit 0 ;;
*) echo "\$ac_cs_usage"; exit 1 ;;
esac
done
ac_given_srcdir=$srcdir
trap 'rm -fr `echo "Makefile" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15
EOF
cat >> $CONFIG_STATUS <<EOF
# Protect against being on the right side of a sed subst in config.status.
sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g;
s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF
$ac_vpsub
$extrasub
s%@SHELL@%$SHELL%g
s%@CFLAGS@%$CFLAGS%g
s%@CPPFLAGS@%$CPPFLAGS%g
s%@CXXFLAGS@%$CXXFLAGS%g
s%@FFLAGS@%$FFLAGS%g
s%@DEFS@%$DEFS%g
s%@LDFLAGS@%$LDFLAGS%g
s%@LIBS@%$LIBS%g
s%@exec_prefix@%$exec_prefix%g
s%@prefix@%$prefix%g
s%@program_transform_name@%$program_transform_name%g
s%@bindir@%$bindir%g
s%@sbindir@%$sbindir%g
s%@libexecdir@%$libexecdir%g
s%@datadir@%$datadir%g
s%@sysconfdir@%$sysconfdir%g
s%@sharedstatedir@%$sharedstatedir%g
s%@localstatedir@%$localstatedir%g
s%@libdir@%$libdir%g
s%@includedir@%$includedir%g
s%@oldincludedir@%$oldincludedir%g
s%@infodir@%$infodir%g
s%@mandir@%$mandir%g
s%@CC@%$CC%g
s%@host@%$host%g
s%@host_alias@%$host_alias%g
s%@host_cpu@%$host_cpu%g
s%@host_vendor@%$host_vendor%g
s%@host_os@%$host_os%g
s%@target@%$target%g
s%@target_alias@%$target_alias%g
s%@target_cpu@%$target_cpu%g
s%@target_vendor@%$target_vendor%g
s%@target_os@%$target_os%g
s%@build@%$build%g
s%@build_alias@%$build_alias%g
s%@build_cpu@%$build_cpu%g
s%@build_vendor@%$build_vendor%g
s%@build_os@%$build_os%g
CEOF
EOF
cat >> $CONFIG_STATUS <<\EOF
# Split the substitutions into bite-sized pieces for seds with
# small command number limits, like on Digital OSF/1 and HP-UX.
ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.
ac_file=1 # Number of current file.
ac_beg=1 # First line for current file.
ac_end=$ac_max_sed_cmds # Line after last line for current file.
ac_more_lines=:
ac_sed_cmds=""
while $ac_more_lines; do
if test $ac_beg -gt 1; then
sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file
else
sed "${ac_end}q" conftest.subs > conftest.s$ac_file
fi
if test ! -s conftest.s$ac_file; then
ac_more_lines=false
rm -f conftest.s$ac_file
else
if test -z "$ac_sed_cmds"; then
ac_sed_cmds="sed -f conftest.s$ac_file"
else
ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file"
fi
ac_file=`expr $ac_file + 1`
ac_beg=$ac_end
ac_end=`expr $ac_end + $ac_max_sed_cmds`
fi
done
if test -z "$ac_sed_cmds"; then
ac_sed_cmds=cat
fi
EOF
cat >> $CONFIG_STATUS <<EOF
CONFIG_FILES=\${CONFIG_FILES-"Makefile"}
EOF
cat >> $CONFIG_STATUS <<\EOF
for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
# Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
case "$ac_file" in
*:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
*) ac_file_in="${ac_file}.in" ;;
esac
# Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.
# Remove last slash and all that follows it. Not all systems have dirname.
ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
# The file is in a subdirectory.
test ! -d "$ac_dir" && mkdir "$ac_dir"
ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
# A "../" for each directory in $ac_dir_suffix.
ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
else
ac_dir_suffix= ac_dots=
fi
case "$ac_given_srcdir" in
.) srcdir=.
if test -z "$ac_dots"; then top_srcdir=.
else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;;
/*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;;
*) # Relative path.
srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix"
top_srcdir="$ac_dots$ac_given_srcdir" ;;
esac
echo creating "$ac_file"
rm -f "$ac_file"
configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
case "$ac_file" in
*Makefile*) ac_comsub="1i\\
# $configure_input" ;;
*) ac_comsub= ;;
esac
ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
sed -e "$ac_comsub
s%@configure_input@%$configure_input%g
s%@srcdir@%$srcdir%g
s%@top_srcdir@%$top_srcdir%g
" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
fi; done
rm -f conftest.s*
EOF
cat >> $CONFIG_STATUS <<EOF
EOF
cat >> $CONFIG_STATUS <<\EOF
exit 0
EOF
chmod +x $CONFIG_STATUS
rm -fr confdefs* $ac_clean_files
test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1

19
sim/testsuite/frv-elf/configure.in Normal file
View File

@ -0,0 +1,19 @@
dnl Process this file file with autoconf to produce a configure script.
dnl This file is a shell script fragment that supplies the information
dnl necessary to tailor a template configure script into the configure
dnl script appropriate for this directory. For more information, check
dnl any existing configure script.
AC_PREREQ(2.5)
dnl FIXME - think of a truly uniq file to this directory
AC_INIT(Makefile.in)
CC=${CC-cc}
AC_SUBST(CC)
AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../../..)
AC_CANONICAL_SYSTEM
AC_SUBST(target_cpu)
AC_OUTPUT(Makefile)

5
sim/testsuite/frv-elf/exit47.s Normal file
View File

@ -0,0 +1,5 @@
.global _start
_start:
setlos #47,gr8
setlos #1,gr7
tira gr0,#0

10
sim/testsuite/frv-elf/grloop.s Normal file
View File

@ -0,0 +1,10 @@
.global _start
_start:
setlo 0x0400,gr10
loop:
addicc gr10,-1,gr10,icc0
bne icc0,0,loop
; exit (0)
setlos #0,gr8
setlos #1,gr7
tira gr0,#0

16
sim/testsuite/frv-elf/hello.s Normal file
View File

@ -0,0 +1,16 @@
.global _start
_start:
; write (hello world)
setlos #14,gr10
sethi %hi(hello),gr9
setlo %lo(hello),gr9
setlos #1,gr8
setlos #5,gr7
tira gr0,#0
; exit (0)
setlos #0,gr8
setlos #1,gr7
tira gr0,#0
hello: .ascii "Hello World!\r\n"

2
sim/testsuite/frv-elf/loop.s Normal file
View File

@ -0,0 +1,2 @@
.global _start
_start: bra icc0,0,_start

23
sim/testsuite/sim/frv/add.cgs Normal file
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# frv testcase for add $GRi,$GRj,$GRk
# mach: all
.include "testutils.inc"
start
.global add
add:
set_gr_immed 1,gr7
set_gr_immed 2,gr8
add gr7,gr8,gr8
test_gr_immed 3,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
add gr7,gr8,gr8
test_gr_limmed 0x8000,0x0000,gr8
add gr8,gr8,gr8
test_gr_immed 0,gr8
pass

25
sim/testsuite/sim/frv/add.pcgs Normal file
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# frv parallel testcase for add $GRi,$GRj,$GRk
# mach: all
.include "testutils.inc"
start
.global add
add:
set_gr_immed 1,gr7
set_gr_immed 2,gr8
add.p gr7,gr8,gr8
add gr7,gr8,gr9
add.p gr7,gr8,gr10
add gr7,gr8,gr11
add.p gr7,gr8,gr12
add gr7,gr8,gr13
test_gr_immed 3,gr8
test_gr_immed 3,gr9
test_gr_immed 4,gr10
test_gr_immed 4,gr11
test_gr_immed 4,gr12
test_gr_immed 4,gr13
pass

36
sim/testsuite/sim/frv/addcc.cgs Normal file
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# frv testcase for addcc $GRi,$GRj,$GRk,$ICCi_1
# mach: all
.include "testutils.inc"
start
.global addcc
addcc:
set_gr_immed 1,gr7
set_gr_immed 2,gr8
set_icc 0x0f,0 ; Set mask opposite of expected
addcc gr7,gr8,gr8,icc0
test_icc 0 0 0 0 icc0
test_gr_immed 3,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
set_icc 0x05,0 ; Set mask opposite of expected
addcc gr7,gr8,gr8,icc0
test_icc 1 0 1 0 icc0
test_gr_limmed 0x8000,0x0000,gr8
set_icc 0x08,0 ; Set mask opposite of expected
addcc gr8,gr8,gr8,icc0
test_icc 0 1 1 1 icc0
test_gr_immed 0,gr8
set_gr_limmed 0x8000,0x0000,gr8
set_icc 0x08,0 ; Set mask opposite of expected
addcc gr8,gr8,gr8,icc0; test zero, carry and overflow bits
test_icc 0 1 1 1 icc0
test_gr_immed 0,gr8
pass

25
sim/testsuite/sim/frv/addi.cgs Normal file
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# frv testcase for addi $GRi,$s12,$GRk
# mach: all
.include "testutils.inc"
start
.global addi
addi:
set_gr_immed 4,gr8
addi gr8,0,gr8
test_gr_immed 4,gr8
addi gr8,1,gr8
test_gr_immed 5,gr8
addi gr8,15,gr8
test_gr_immed 20,gr8
set_gr_limmed 0x7fff,0xffff,gr8
addi gr8,1,gr8
test_gr_limmed 0x8000,0x0000,gr8
addi gr8,0x7ff,gr8
test_gr_limmed 0x8000,0x07ff,gr8
addi gr8,-2048,gr8
test_gr_limmed 0x7fff,0xffff,gr8
pass

30
sim/testsuite/sim/frv/addicc.cgs Normal file
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# frv testcase for addicc $GRi,$s10,$GRk,$ICCi_1
# mach: all
.include "testutils.inc"
start
.global addicc
addicc:
; Test add $u4Ri
set_gr_immed 4,gr8
set_icc 0x0f,0 ; Set mask opposite of expected
addicc gr8,0,gr8,icc0
test_icc 0 0 0 0 icc0
test_gr_immed 4,gr8
set_icc 0x0f,0 ; Set mask opposite of expected
addicc gr8,1,gr8,icc0
test_icc 0 0 0 0 icc0
test_gr_immed 5,gr8
set_icc 0x0f,0 ; Set mask opposite of expected
addicc gr8,15,gr8,icc0
test_icc 0 0 0 0 icc0
test_gr_immed 20,gr8
set_gr_limmed 0x7fff,0xffff,gr8 ; test neg and overflow bits
set_icc 0x05,0 ; Set mask opposite of expected
addicc gr8,1,gr8,icc0
test_icc 1 0 1 0 icc0
test_gr_limmed 0x8000,0x0000,gr8
pass

49
sim/testsuite/sim/frv/addx.cgs Normal file
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# frv testcase for addx $GRi,$GRj,$GRk,$ICCi_1
# mach: all
.include "testutils.inc"
start
.global addx
addx:
set_gr_immed 1,gr7
set_gr_immed 2,gr8
set_icc 0x0e,0 ; Make sure carry bit is off
addx gr7,gr8,gr8,icc0
test_icc 1 1 1 0 icc0
test_gr_immed 3,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
set_icc 0x04,0 ; Make sure carry bit is off
addx gr7,gr8,gr8,icc0
test_icc 0 1 0 0 icc0
test_gr_limmed 0x8000,0x0000,gr8
set_icc 0x08,0 ; Make sure carry bit is off
addx gr8,gr8,gr8,icc0
test_icc 1 0 0 0 icc0
test_gr_immed 0,gr8
set_gr_immed 1,gr7
set_gr_immed 2,gr8
set_icc 0x0f,0 ; Make sure carry bit is on
addx gr7,gr8,gr8,icc0
test_icc 1 1 1 1 icc0
test_gr_immed 4,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 0,gr8
set_icc 0x05,0 ; Make sure carry bit is on
addx gr7,gr8,gr8,icc0
test_icc 0 1 0 1 icc0
test_gr_limmed 0x8000,0x0000,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_icc 0x0b,0 ; Make sure carry bit is on
addx gr7,gr8,gr8,icc0
test_icc 1 0 1 1 icc0
test_gr_immed 0,gr8
pass

49
sim/testsuite/sim/frv/addxcc.cgs Normal file
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# frv testcase for addxcc $GRi,$GRj,$GRk,$ICCi_1
# mach: all
.include "testutils.inc"
start
.global addxcc
addxcc:
set_gr_immed 1,gr7
set_gr_immed 2,gr8
set_icc 0x0e,0 ; Make sure carry bit is off
addxcc gr7,gr8,gr8,icc0
test_icc 0 0 0 0 icc0
test_gr_immed 3,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
set_icc 0x04,0 ; Make sure carry bit is off
addxcc gr7,gr8,gr8,icc0
test_icc 1 0 1 0 icc0
test_gr_limmed 0x8000,0x0000,gr8
set_icc 0x08,0 ; Make sure carry bit is off
addxcc gr8,gr8,gr8,icc0
test_icc 0 1 1 1 icc0
test_gr_immed 0,gr8
set_gr_immed 1,gr7
set_gr_immed 2,gr8
set_icc 0x0f,0 ; Make sure carry bit is on
addxcc gr7,gr8,gr8,icc0
test_icc 0 0 0 0 icc0
test_gr_immed 4,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 0,gr8
set_icc 0x05,0 ; Make sure carry bit is on
addxcc gr7,gr8,gr8,icc0
test_icc 1 0 1 0 icc0
test_gr_limmed 0x8000,0x0000,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_icc 0x0b,0 ; Make sure carry bit is on
addxcc gr7,gr8,gr8,icc0
test_icc 0 1 0 1 icc0
test_gr_immed 0,gr8
pass

46
sim/testsuite/sim/frv/addxi.cgs Normal file
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# frv testcase for addxi $GRi,$s10,$GRk,$ICCi_1
# mach: all
.include "testutils.inc"
start
.global addxi
addxi:
set_gr_immed 2,gr8
set_icc 0x0e,0 ; Make sure carry bit is off
addxi gr8,1,gr8,icc0
test_icc 1 1 1 0 icc0
test_gr_immed 3,gr8
set_gr_limmed 0x7fff,0xffff,gr8
set_icc 0x04,0 ; Make sure carry bit is off
addxi gr8,1,gr8,icc0
test_icc 0 1 0 0 icc0
test_gr_limmed 0x8000,0x0000,gr8
set_gr_limmed 0xffff,0xff00,gr8
set_icc 0x08,0 ; Make sure carry bit is off
addxi gr8,0x100,gr8,icc0
test_icc 1 0 0 0 icc0
test_gr_immed 0,gr8
set_gr_immed 2,gr8
set_icc 0x0f,0 ; Make sure carry bit is on
addxi gr8,1,gr8,icc0
test_icc 1 1 1 1 icc0
test_gr_immed 4,gr8
set_gr_limmed 0x7fff,0xffff,gr8
set_icc 0x05,0 ; Make sure carry bit is on
addxi gr8,0,gr8,icc0
test_icc 0 1 0 1 icc0
test_gr_limmed 0x8000,0x0000,gr8
set_gr_limmed 0xffff,0xfeff,gr8
set_icc 0x0b,0 ; Make sure carry bit is on
addxi gr8,0x100,gr8,icc0
test_icc 1 0 1 1 icc0
test_gr_immed 0,gr8
pass

46
sim/testsuite/sim/frv/addxicc.cgs Normal file
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# frv testcase for addxicc $GRi,$s10,$GRk,$ICCi_1
# mach: all
.include "testutils.inc"
start
.global addxicc
addxicc:
set_gr_immed 2,gr8
set_icc 0x0e,0 ; Make sure carry bit is off
addxicc gr8,1,gr8,icc0
test_icc 0 0 0 0 icc0
test_gr_immed 3,gr8
set_gr_limmed 0x7fff,0xffff,gr8
set_icc 0x04,0 ; Make sure carry bit is off
addxicc gr8,1,gr8,icc0
test_icc 1 0 1 0 icc0
test_gr_limmed 0x8000,0x0000,gr8
set_gr_limmed 0xffff,0xff00,gr8
set_icc 0x08,0 ; Make sure carry bit is off
addxicc gr8,0x100,gr8,icc0
test_icc 0 1 0 1 icc0
test_gr_immed 0,gr8
set_gr_immed 2,gr8
set_icc 0x0f,0 ; Make sure carry bit is on
addxicc gr8,1,gr8,icc0
test_icc 0 0 0 0 icc0
test_gr_immed 4,gr8
set_gr_limmed 0x7fff,0xffff,gr8
set_icc 0x05,0 ; Make sure carry bit is on
addxicc gr8,0,gr8,icc0
test_icc 1 0 1 0 icc0
test_gr_limmed 0x8000,0x0000,gr8
set_gr_limmed 0xffff,0xfeff,gr8
set_icc 0x0b,0 ; Make sure carry bit is on
addxicc gr8,0x100,gr8,icc0
test_icc 0 1 0 1 icc0
test_gr_immed 0,gr8
pass

19
sim/testsuite/sim/frv/allinsn.exp Normal file
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# FRV simulator testsuite.
if [istarget frv*-*] {
# load support procs (none yet)
# load_lib cgen.exp
# all machines
set all_machs "frv fr500 fr400"
set cpu_option -mcpu
# The .cgs suffix is for "cgen .s".
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
# If we're only testing specific files and this isn't one of them,
# skip it.
if ![runtest_file_p $runtests $src] {
continue
}
run_sim_test $src $all_machs
}
}

29
sim/testsuite/sim/frv/and.cgs Normal file
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# frv testcase for and $GRi,$GRj,$GRk
# mach: all
.include "testutils.inc"
start
.global and
and:
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,0 ; Set mask opposite of expected
and gr7,gr8,gr8
test_icc 1 0 1 1 icc0
test_gr_immed 0,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,0 ; Set mask opposite of expected
and gr7,gr8,gr8
test_icc 0 1 0 0 icc0
test_gr_limmed 0xaaaa,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,0 ; Set mask opposite of expected
and gr7,gr8,gr8
test_icc 1 1 0 1 icc0
test_gr_limmed 0x0000,0xaaaa,gr8
pass

29
sim/testsuite/sim/frv/andcc.cgs Normal file
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# frv testcase for andcc $GRi,$GRj,$GRk,$ICCi_1
# mach: all
.include "testutils.inc"
start
.global andcc
andcc:
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,0 ; Set mask opposite of expected
andcc gr7,gr8,gr8,icc0
test_icc 0 1 1 1 icc0
test_gr_immed 0,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,0 ; Set mask opposite of expected
andcc gr7,gr8,gr8,icc0
test_icc 1 0 0 0 icc0
test_gr_limmed 0xaaaa,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,0 ; Set mask opposite of expected
andcc gr7,gr8,gr8,icc0
test_icc 0 0 0 1 icc0
test_gr_limmed 0x0000,0xaaaa,gr8
pass

59
sim/testsuite/sim/frv/andcr.cgs Normal file
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# frv testcase for andcr $CCi,$CCj,$CCk
# mach: all
.include "testutils.inc"
start
.global andcr
andcr:
set_spr_immed 0x1b1b,cccr
andcr cc7,cc7,cc3
test_spr_immed 0x1b1b,cccr
andcr cc7,cc6,cc3
test_spr_immed 0x1b1b,cccr
andcr cc7,cc5,cc3
test_spr_immed 0x1b1b,cccr
andcr cc7,cc4,cc3
test_spr_immed 0x1b1b,cccr
andcr cc6,cc7,cc3
test_spr_immed 0x1b1b,cccr
andcr cc6,cc6,cc3
test_spr_immed 0x1b1b,cccr
andcr cc6,cc5,cc3
test_spr_immed 0x1b1b,cccr
andcr cc6,cc4,cc3
test_spr_immed 0x1b1b,cccr
andcr cc5,cc7,cc3
test_spr_immed 0x1b1b,cccr
andcr cc5,cc6,cc3
test_spr_immed 0x1b1b,cccr
andcr cc5,cc5,cc3
test_spr_immed 0x1b1b,cccr
andcr cc5,cc4,cc3
test_spr_immed 0x1b1b,cccr
andcr cc4,cc7,cc3
test_spr_immed 0x1b1b,cccr
andcr cc4,cc6,cc3
test_spr_immed 0x1b1b,cccr
andcr cc4,cc5,cc3
test_spr_immed 0x1b9b,cccr
andcr cc4,cc4,cc3
test_spr_immed 0x1bdb,cccr
pass

26
sim/testsuite/sim/frv/andi.cgs Normal file
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# frv testcase for andi $GRi,$s12,$GRk
# mach: all
.include "testutils.inc"
start
.global andi
andi:
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_icc 0x0b,0 ; Set mask opposite of expected
andi gr7,0x555,gr8
test_icc 1 0 1 1 icc0
test_gr_immed 0,gr8
set_icc 0x04,0 ; Set mask opposite of expected
andi gr7,-2048,gr8
test_icc 0 1 0 0 icc0
test_gr_limmed 0xaaaa,0xa800,gr8
set_icc 0x0d,0 ; Set mask opposite of expected
andi gr7,-1,gr8
test_icc 1 1 0 1 icc0
test_gr_limmed 0xaaaa,0xaaaa,gr8
pass

26
sim/testsuite/sim/frv/andicc.cgs Normal file
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# frv testcase for andicc $GRi,$s10,$GRk,$ICCi_1
# mach: all
.include "testutils.inc"
start
.global andicc
andicc:
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_icc 0x0b,0 ; Set mask opposite of expected
andicc gr7,0x155,gr8,icc0
test_icc 0 1 1 1 icc0
test_gr_immed 0,gr8
set_icc 0x04,0 ; Set mask opposite of expected
andicc gr7,-512,gr8,icc0
test_icc 1 0 0 0 icc0
test_gr_limmed 0xaaaa,0xaa00,gr8
set_icc 0x05,0 ; Set mask opposite of expected
andicc gr7,-1,gr8,icc0
test_icc 1 0 0 1 icc0
test_gr_limmed 0xaaaa,0xaaaa,gr8
pass

59
sim/testsuite/sim/frv/andncr.cgs Normal file
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# frv testcase for andncr $CCi,$CCj,$CCk
# mach: all
.include "testutils.inc"
start
.global andncr
andncr:
set_spr_immed 0x1b1b,cccr
andncr cc7,cc7,cc3
test_spr_immed 0x1b1b,cccr
andncr cc7,cc6,cc3
test_spr_immed 0x1b1b,cccr
andncr cc7,cc5,cc3
test_spr_immed 0x1b1b,cccr
andncr cc7,cc4,cc3
test_spr_immed 0x1b1b,cccr
andncr cc6,cc7,cc3
test_spr_immed 0x1b1b,cccr
andncr cc6,cc6,cc3
test_spr_immed 0x1b1b,cccr
andncr cc6,cc5,cc3
test_spr_immed 0x1b1b,cccr
andncr cc6,cc4,cc3
test_spr_immed 0x1b1b,cccr
andncr cc5,cc7,cc3
test_spr_immed 0x1b1b,cccr
andncr cc5,cc6,cc3
test_spr_immed 0x1b1b,cccr
andncr cc5,cc5,cc3
test_spr_immed 0x1b9b,cccr
andncr cc5,cc4,cc3
test_spr_immed 0x1bdb,cccr
andncr cc4,cc7,cc3
test_spr_immed 0x1b1b,cccr
andncr cc4,cc6,cc3
test_spr_immed 0x1b1b,cccr
andncr cc4,cc5,cc3
test_spr_immed 0x1b1b,cccr
andncr cc4,cc4,cc3
test_spr_immed 0x1b1b,cccr
pass

12
sim/testsuite/sim/frv/bar.cgs Normal file
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# frv testcase for bar
# mach: all
.include "testutils.inc"
start
.global bar
bar:
bar
pass

61
sim/testsuite/sim/frv/bc.cgs Normal file
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# frv testcase for bc $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bc
bc:
set_icc 0x0 0
bc icc0,0,bad
set_icc 0x1 1
bc icc1,1,ok2
fail
ok2:
set_icc 0x2 2
bc icc2,2,bad
set_icc 0x3 3
bc icc3,3,ok4
fail
ok4:
set_icc 0x4 0
bc icc0,0,bad
set_icc 0x5 1
bc icc1,1,ok6
fail
ok6:
set_icc 0x6 2
bc icc2,2,bad
set_icc 0x7 3
bc icc3,3,ok8
fail
ok8:
set_icc 0x8 0
bc icc0,0,bad
set_icc 0x9 1
bc icc1,1,oka
fail
oka:
set_icc 0xa 2
bc icc2,2,bad
set_icc 0xb 3
bc icc3,3,okc
fail
okc:
set_icc 0xc 0
bc icc0,0,bad
set_icc 0xd 1
bc icc1,1,oke
fail
oke:
set_icc 0xe 2
bc icc2,2,bad
set_icc 0xf 3
bc icc3,3,okg
fail
okg:
pass
bad:
fail

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sim/testsuite/sim/frv/bcclr.cgs Normal file
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# frv testcase for bcclr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bcclr
bcclr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcclr icc0,0,0
set_spr_addr ok2,lr
set_icc 0x1 1
bcclr icc1,0,1
fail
ok2:
set_spr_addr bad,lr
set_icc 0x2 2
bcclr icc2,0,2
set_spr_addr ok4,lr
set_icc 0x3 3
bcclr icc3,0,3
fail
ok4:
set_spr_addr bad,lr
set_icc 0x4 0
bcclr icc0,0,0
set_spr_addr ok6,lr
set_icc 0x5 1
bcclr icc1,0,1
fail
ok6:
set_spr_addr bad,lr
set_icc 0x6 2
bcclr icc2,0,2
set_spr_addr ok8,lr
set_icc 0x7 3
bcclr icc3,0,3
fail
ok8:
set_spr_addr bad,lr
set_icc 0x8 0
bcclr icc0,0,0
set_spr_addr oka,lr
set_icc 0x9 1
bcclr icc1,0,1
fail
oka:
set_spr_addr bad,lr
set_icc 0xa 2
bcclr icc2,0,2
set_spr_addr okc,lr
set_icc 0xb 3
bcclr icc3,0,3
fail
okc:
set_spr_addr bad,lr
set_icc 0xc 0
bcclr icc0,0,0
set_spr_addr oke,lr
set_icc 0xd 1
bcclr icc1,0,1
fail
oke:
set_spr_addr bad,lr
set_icc 0xe 2
bcclr icc2,0,2
set_spr_addr okg,lr
set_icc 0xf 3
bcclr icc3,0,3
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcclr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr oki,lr
set_icc 0x1 1
bcclr icc1,1,1
fail
oki:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x2 2
bcclr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr okk,lr
set_icc 0x3 3
bcclr icc3,1,3
fail
okk:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x4 0
bcclr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr okm,lr
set_icc 0x5 1
bcclr icc1,1,1
fail
okm:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x6 2
bcclr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr oko,lr
set_icc 0x7 3
bcclr icc3,1,3
fail
oko:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x8 0
bcclr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr okq,lr
set_icc 0x9 1
bcclr icc1,1,1
fail
okq:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xa 2
bcclr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_icc 0xb 3
bcclr icc3,1,3
fail
oks:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xc 0
bcclr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_icc 0xd 1
bcclr icc1,1,1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xe 2
bcclr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_icc 0xf 3
bcclr icc3,1,3
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcclr icc0,1,0
set_icc 0x1 1
bcclr icc1,1,1
set_icc 0x2 2
bcclr icc2,1,2
set_icc 0x3 3
bcclr icc3,1,3
set_icc 0x4 0
bcclr icc0,1,0
set_icc 0x5 1
bcclr icc1,1,1
set_icc 0x6 2
bcclr icc2,1,2
set_icc 0x7 3
bcclr icc3,1,3
set_icc 0x8 0
bcclr icc0,1,0
set_icc 0x9 1
bcclr icc1,1,1
set_icc 0xa 2
bcclr icc2,1,2
set_icc 0xb 3
bcclr icc3,1,3
set_icc 0xc 0
bcclr icc0,1,0
set_icc 0xd 1
bcclr icc1,1,1
set_icc 0xe 2
bcclr icc2,1,2
set_icc 0xf 3
bcclr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcclr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bcclr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bcclr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bcclr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bcclr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bcclr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bcclr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bcclr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bcclr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bcclr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bcclr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bcclr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bcclr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bcclr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bcclr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bcclr icc3,0,3
pass
bad:
fail

293
sim/testsuite/sim/frv/bceqlr.cgs Normal file
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# frv testcase for bceqlr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bceqlr
bceqlr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bceqlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x1 1
bceqlr icc1,0,1
set_spr_addr bad,lr
set_icc 0x2 2
bceqlr icc2,0,2
set_spr_addr bad,lr
set_icc 0x3 3
bceqlr icc3,0,3
set_spr_addr ok5,lr
set_icc 0x4 0
bceqlr icc0,0,0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
bceqlr icc1,0,1
fail
ok6:
set_spr_addr ok7,lr
set_icc 0x6 2
bceqlr icc2,0,2
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
bceqlr icc3,0,3
fail
ok8:
set_spr_addr bad,lr
set_icc 0x8 0
bceqlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x9 1
bceqlr icc1,0,1
set_spr_addr bad,lr
set_icc 0xa 2
bceqlr icc2,0,2
set_spr_addr bad,lr
set_icc 0xb 3
bceqlr icc3,0,3
set_spr_addr okd,lr
set_icc 0xc 0
bceqlr icc0,0,0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bceqlr icc1,0,1
fail
oke:
set_spr_addr okf,lr
set_icc 0xe 2
bceqlr icc2,0,2
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bceqlr icc3,0,3
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bceqlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x1 1
bceqlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x2 2
bceqlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x3 3
bceqlr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okl,lr
set_icc 0x4 0
bceqlr icc0,1,0
fail
okl:
set_spr_immed 1,lcr
set_spr_addr okm,lr
set_icc 0x5 1
bceqlr icc1,1,1
fail
okm:
set_spr_immed 1,lcr
set_spr_addr okn,lr
set_icc 0x6 2
bceqlr icc2,1,2
fail
okn:
set_spr_immed 1,lcr
set_spr_addr oko,lr
set_icc 0x7 3
bceqlr icc3,1,3
fail
oko:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x8 0
bceqlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x9 1
bceqlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xa 2
bceqlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xb 3
bceqlr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okt,lr
set_icc 0xc 0
bceqlr icc0,1,0
fail
okt:
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_icc 0xd 1
bceqlr icc1,1,1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr okv,lr
set_icc 0xe 2
bceqlr icc2,1,2
fail
okv:
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_icc 0xf 3
bceqlr icc3,1,3
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bceqlr icc0,1,0
set_icc 0x1 1
bceqlr icc1,1,1
set_icc 0x2 2
bceqlr icc2,1,2
set_icc 0x3 3
bceqlr icc3,1,3
set_icc 0x4 0
bceqlr icc0,1,0
set_icc 0x5 1
bceqlr icc1,1,1
set_icc 0x6 2
bceqlr icc2,1,2
set_icc 0x7 3
bceqlr icc3,1,3
set_icc 0x8 0
bceqlr icc0,1,0
set_icc 0x9 1
bceqlr icc1,1,1
set_icc 0xa 2
bceqlr icc2,1,2
set_icc 0xb 3
bceqlr icc3,1,3
set_icc 0xc 0
bceqlr icc0,1,0
set_icc 0xd 1
bceqlr icc1,1,1
set_icc 0xe 2
bceqlr icc2,1,2
set_icc 0xf 3
bceqlr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bceqlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bceqlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bceqlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bceqlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bceqlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bceqlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bceqlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bceqlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bceqlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bceqlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bceqlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bceqlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bceqlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bceqlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bceqlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bceqlr icc3,0,3
pass
bad:
fail

293
sim/testsuite/sim/frv/bcgelr.cgs Normal file
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# frv testcase for bcgelr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bcgelr
bcgelr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_icc 0x0 0
bcgelr icc0,0,0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bcgelr icc1,0,1
fail
ok2:
set_spr_addr bad,lr
set_icc 0x2 2
bcgelr icc2,0,2
set_spr_addr bad,lr
set_icc 0x3 3
bcgelr icc3,0,3
set_spr_addr ok5,lr
set_icc 0x4 0
bcgelr icc0,0,0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
bcgelr icc1,0,1
fail
ok6:
set_spr_addr bad,lr
set_icc 0x6 2
bcgelr icc2,0,2
set_spr_addr bad,lr
set_icc 0x7 3
bcgelr icc3,0,3
set_spr_addr bad,lr
set_icc 0x8 0
bcgelr icc0,0,0
set_spr_addr bad,lr
set_icc 0x9 1
bcgelr icc1,0,1
set_spr_addr okb,lr
set_icc 0xa 2
bcgelr icc2,0,2
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bcgelr icc3,0,3
fail
okc:
set_spr_addr bad,lr
set_icc 0xc 0
bcgelr icc0,0,0
set_spr_addr bad,lr
set_icc 0xd 1
bcgelr icc1,0,1
set_spr_addr okf,lr
set_icc 0xe 2
bcgelr icc2,0,2
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bcgelr icc3,0,3
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr okh,lr
set_icc 0x0 0
bcgelr icc0,1,0
fail
okh:
set_spr_immed 1,lcr
set_spr_addr oki,lr
set_icc 0x1 1
bcgelr icc1,1,1
fail
oki:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x2 2
bcgelr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x3 3
bcgelr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okl,lr
set_icc 0x4 0
bcgelr icc0,1,0
fail
okl:
set_spr_immed 1,lcr
set_spr_addr okm,lr
set_icc 0x5 1
bcgelr icc1,1,1
fail
okm:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x6 2
bcgelr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x7 3
bcgelr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x8 0
bcgelr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x9 1
bcgelr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okr,lr
set_icc 0xa 2
bcgelr icc2,1,2
fail
okr:
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_icc 0xb 3
bcgelr icc3,1,3
fail
oks:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xc 0
bcgelr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xd 1
bcgelr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okv,lr
set_icc 0xe 2
bcgelr icc2,1,2
fail
okv:
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_icc 0xf 3
bcgelr icc3,1,3
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcgelr icc0,1,0
set_icc 0x1 1
bcgelr icc1,1,1
set_icc 0x2 2
bcgelr icc2,1,2
set_icc 0x3 3
bcgelr icc3,1,3
set_icc 0x4 0
bcgelr icc0,1,0
set_icc 0x5 1
bcgelr icc1,1,1
set_icc 0x6 2
bcgelr icc2,1,2
set_icc 0x7 3
bcgelr icc3,1,3
set_icc 0x8 0
bcgelr icc0,1,0
set_icc 0x9 1
bcgelr icc1,1,1
set_icc 0xa 2
bcgelr icc2,1,2
set_icc 0xb 3
bcgelr icc3,1,3
set_icc 0xc 0
bcgelr icc0,1,0
set_icc 0xd 1
bcgelr icc1,1,1
set_icc 0xe 2
bcgelr icc2,1,2
set_icc 0xf 3
bcgelr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcgelr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bcgelr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bcgelr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bcgelr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bcgelr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bcgelr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bcgelr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bcgelr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bcgelr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bcgelr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bcgelr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bcgelr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bcgelr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bcgelr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bcgelr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bcgelr icc3,0,3
pass
bad:
fail

284
sim/testsuite/sim/frv/bcgtlr.cgs Normal file
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# frv testcase for bcgtlr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bcgtlr
bcgtlr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_icc 0x0 0
bcgtlr icc0,0,0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bcgtlr icc1,0,1
fail
ok2:
set_spr_addr bad,lr
set_icc 0x2 2
bcgtlr icc2,0,2
set_spr_addr bad,lr
set_icc 0x3 3
bcgtlr icc3,0,3
set_spr_addr bad,lr
set_icc 0x4 0
bcgtlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x5 1
bcgtlr icc1,0,1
set_spr_addr bad,lr
set_icc 0x6 2
bcgtlr icc2,0,2
set_spr_addr bad,lr
set_icc 0x7 3
bcgtlr icc3,0,3
set_spr_addr bad,lr
set_icc 0x8 0
bcgtlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x9 1
bcgtlr icc1,0,1
set_spr_addr okb,lr
set_icc 0xa 2
bcgtlr icc2,0,2
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bcgtlr icc3,0,3
fail
okc:
set_spr_addr bad,lr
set_icc 0xc 0
bcgtlr icc0,0,0
set_spr_addr bad,lr
set_icc 0xd 1
bcgtlr icc1,0,1
set_spr_addr bad,lr
set_icc 0xe 2
bcgtlr icc2,0,2
set_spr_addr bad,lr
set_icc 0xf 3
bcgtlr icc3,0,3
; ccond is true
set_spr_immed 1,lcr
set_spr_addr okh,lr
set_icc 0x0 0
bcgtlr icc0,1,0
fail
okh:
set_spr_immed 1,lcr
set_spr_addr oki,lr
set_icc 0x1 1
bcgtlr icc1,1,1
fail
oki:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x2 2
bcgtlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x3 3
bcgtlr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x4 0
bcgtlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x5 1
bcgtlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x6 2
bcgtlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x7 3
bcgtlr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x8 0
bcgtlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x9 1
bcgtlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okr,lr
set_icc 0xa 2
bcgtlr icc2,1,2
fail
okr:
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_icc 0xb 3
bcgtlr icc3,1,3
fail
oks:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xc 0
bcgtlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xd 1
bcgtlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xe 2
bcgtlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xf 3
bcgtlr icc3,1,3
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcgtlr icc0,1,0
set_icc 0x1 1
bcgtlr icc1,1,1
set_icc 0x2 2
bcgtlr icc2,1,2
set_icc 0x3 3
bcgtlr icc3,1,3
set_icc 0x4 0
bcgtlr icc0,1,0
set_icc 0x5 1
bcgtlr icc1,1,1
set_icc 0x6 2
bcgtlr icc2,1,2
set_icc 0x7 3
bcgtlr icc3,1,3
set_icc 0x8 0
bcgtlr icc0,1,0
set_icc 0x9 1
bcgtlr icc1,1,1
set_icc 0xa 2
bcgtlr icc2,1,2
set_icc 0xb 3
bcgtlr icc3,1,3
set_icc 0xc 0
bcgtlr icc0,1,0
set_icc 0xd 1
bcgtlr icc1,1,1
set_icc 0xe 2
bcgtlr icc2,1,2
set_icc 0xf 3
bcgtlr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcgtlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bcgtlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bcgtlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bcgtlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bcgtlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bcgtlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bcgtlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bcgtlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bcgtlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bcgtlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bcgtlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bcgtlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bcgtlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bcgtlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bcgtlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bcgtlr icc3,0,3
pass
bad:
fail

284
sim/testsuite/sim/frv/bchilr.cgs Normal file
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# frv testcase for bchilr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bchilr
bchilr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_icc 0x0 0
bchilr icc0,0,0
fail
ok1:
set_spr_addr bad,lr
set_icc 0x1 1
bchilr icc1,0,1
set_spr_addr ok3,lr
set_icc 0x2 2
bchilr icc2,0,2
fail
ok3:
set_spr_addr bad,lr
set_icc 0x3 3
bchilr icc3,0,3
set_spr_addr bad,lr
set_icc 0x4 0
bchilr icc0,0,0
set_spr_addr bad,lr
set_icc 0x5 1
bchilr icc1,0,1
set_spr_addr bad,lr
set_icc 0x6 2
bchilr icc2,0,2
set_spr_addr bad,lr
set_icc 0x7 3
bchilr icc3,0,3
set_spr_addr ok9,lr
set_icc 0x8 0
bchilr icc0,0,0
fail
ok9:
set_spr_addr bad,lr
set_icc 0x9 1
bchilr icc1,0,1
set_spr_addr okb,lr
set_icc 0xa 2
bchilr icc2,0,2
fail
okb:
set_spr_addr bad,lr
set_icc 0xb 3
bchilr icc3,0,3
set_spr_addr bad,lr
set_icc 0xc 0
bchilr icc0,0,0
set_spr_addr bad,lr
set_icc 0xd 1
bchilr icc1,0,1
set_spr_addr bad,lr
set_icc 0xe 2
bchilr icc2,0,2
set_spr_addr bad,lr
set_icc 0xf 3
bchilr icc3,0,3
; ccond is true
set_spr_immed 1,lcr
set_spr_addr okh,lr
set_icc 0x0 0
bchilr icc0,1,0
fail
okh:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x1 1
bchilr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okj,lr
set_icc 0x2 2
bchilr icc2,1,2
fail
okj:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x3 3
bchilr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x4 0
bchilr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x5 1
bchilr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x6 2
bchilr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x7 3
bchilr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okp,lr
set_icc 0x8 0
bchilr icc0,1,0
fail
okp:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x9 1
bchilr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okr,lr
set_icc 0xa 2
bchilr icc2,1,2
fail
okr:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xb 3
bchilr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xc 0
bchilr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xd 1
bchilr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xe 2
bchilr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xf 3
bchilr icc3,1,3
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bchilr icc0,1,0
set_icc 0x1 1
bchilr icc1,1,1
set_icc 0x2 2
bchilr icc2,1,2
set_icc 0x3 3
bchilr icc3,1,3
set_icc 0x4 0
bchilr icc0,1,0
set_icc 0x5 1
bchilr icc1,1,1
set_icc 0x6 2
bchilr icc2,1,2
set_icc 0x7 3
bchilr icc3,1,3
set_icc 0x8 0
bchilr icc0,1,0
set_icc 0x9 1
bchilr icc1,1,1
set_icc 0xa 2
bchilr icc2,1,2
set_icc 0xb 3
bchilr icc3,1,3
set_icc 0xc 0
bchilr icc0,1,0
set_icc 0xd 1
bchilr icc1,1,1
set_icc 0xe 2
bchilr icc2,1,2
set_icc 0xf 3
bchilr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bchilr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bchilr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bchilr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bchilr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bchilr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bchilr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bchilr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bchilr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bchilr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bchilr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bchilr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bchilr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bchilr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bchilr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bchilr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bchilr icc3,0,3
pass
bad:
fail

301
sim/testsuite/sim/frv/bclelr.cgs Normal file
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# frv testcase for bclelr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bclelr
bclelr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bclelr icc0,0,0
set_spr_addr bad,lr
set_icc 0x1 1
bclelr icc1,0,1
set_spr_addr ok3,lr
set_icc 0x2 2
bclelr icc2,0,2
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
bclelr icc3,0,3
fail
ok4:
set_spr_addr ok5,lr
set_icc 0x4 0
bclelr icc0,0,0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
bclelr icc1,0,1
fail
ok6:
set_spr_addr ok7,lr
set_icc 0x6 2
bclelr icc2,0,2
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
bclelr icc3,0,3
fail
ok8:
set_spr_addr ok9,lr
set_icc 0x8 0
bclelr icc0,0,0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bclelr icc1,0,1
fail
oka:
set_spr_addr bad,lr
set_icc 0xa 2
bclelr icc2,0,2
set_spr_addr bad,lr
set_icc 0xb 3
bclelr icc3,0,3
set_spr_addr okd,lr
set_icc 0xc 0
bclelr icc0,0,0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bclelr icc1,0,1
fail
oke:
set_spr_addr okf,lr
set_icc 0xe 2
bclelr icc2,0,2
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bclelr icc3,0,3
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bclelr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x1 1
bclelr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okj,lr
set_icc 0x2 2
bclelr icc2,1,2
fail
okj:
set_spr_immed 1,lcr
set_spr_addr okk,lr
set_icc 0x3 3
bclelr icc3,1,3
fail
okk:
set_spr_immed 1,lcr
set_spr_addr okl,lr
set_icc 0x4 0
bclelr icc0,1,0
fail
okl:
set_spr_immed 1,lcr
set_spr_addr okm,lr
set_icc 0x5 1
bclelr icc1,1,1
fail
okm:
set_spr_immed 1,lcr
set_spr_addr okn,lr
set_icc 0x6 2
bclelr icc2,1,2
fail
okn:
set_spr_immed 1,lcr
set_spr_addr oko,lr
set_icc 0x7 3
bclelr icc3,1,3
fail
oko:
set_spr_immed 1,lcr
set_spr_addr okp,lr
set_icc 0x8 0
bclelr icc0,1,0
fail
okp:
set_spr_immed 1,lcr
set_spr_addr okq,lr
set_icc 0x9 1
bclelr icc1,1,1
fail
okq:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xa 2
bclelr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xb 3
bclelr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okt,lr
set_icc 0xc 0
bclelr icc0,1,0
fail
okt:
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_icc 0xd 1
bclelr icc1,1,1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr okv,lr
set_icc 0xe 2
bclelr icc2,1,2
fail
okv:
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_icc 0xf 3
bclelr icc3,1,3
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bclelr icc0,1,0
set_icc 0x1 1
bclelr icc1,1,1
set_icc 0x2 2
bclelr icc2,1,2
set_icc 0x3 3
bclelr icc3,1,3
set_icc 0x4 0
bclelr icc0,1,0
set_icc 0x5 1
bclelr icc1,1,1
set_icc 0x6 2
bclelr icc2,1,2
set_icc 0x7 3
bclelr icc3,1,3
set_icc 0x8 0
bclelr icc0,1,0
set_icc 0x9 1
bclelr icc1,1,1
set_icc 0xa 2
bclelr icc2,1,2
set_icc 0xb 3
bclelr icc3,1,3
set_icc 0xc 0
bclelr icc0,1,0
set_icc 0xd 1
bclelr icc1,1,1
set_icc 0xe 2
bclelr icc2,1,2
set_icc 0xf 3
bclelr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bclelr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bclelr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bclelr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bclelr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bclelr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bclelr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bclelr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bclelr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bclelr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bclelr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bclelr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bclelr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bclelr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bclelr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bclelr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bclelr icc3,0,3
pass
bad:
fail

84
sim/testsuite/sim/frv/bclr.cgs Normal file
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# frv testcase for bclr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global bclr
bclr:
set_spr_addr bad,lr
set_icc 0x0 0
bclr icc0,0
set_spr_addr ok2,lr
set_icc 0x1 1
bclr icc1,1
fail
ok2:
set_spr_addr bad,lr
set_icc 0x2 2
bclr icc2,2
set_spr_addr ok4,lr
set_icc 0x3 3
bclr icc3,3
fail
ok4:
set_spr_addr bad,lr
set_icc 0x4 0
bclr icc0,0
set_spr_addr ok6,lr
set_icc 0x5 1
bclr icc1,1
fail
ok6:
set_spr_addr bad,lr
set_icc 0x6 2
bclr icc2,2
set_spr_addr ok8,lr
set_icc 0x7 3
bclr icc3,3
fail
ok8:
set_spr_addr bad,lr
set_icc 0x8 0
bclr icc0,0
set_spr_addr oka,lr
set_icc 0x9 1
bclr icc1,1
fail
oka:
set_spr_addr bad,lr
set_icc 0xa 2
bclr icc2,2
set_spr_addr okc,lr
set_icc 0xb 3
bclr icc3,3
fail
okc:
set_spr_addr bad,lr
set_icc 0xc 0
bclr icc0,0
set_spr_addr oke,lr
set_icc 0xd 1
bclr icc1,1
fail
oke:
set_spr_addr bad,lr
set_icc 0xe 2
bclr icc2,2
set_spr_addr okg,lr
set_icc 0xf 3
bclr icc3,3
fail
okg:
pass
bad:
fail

301
sim/testsuite/sim/frv/bclslr.cgs Normal file
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# frv testcase for bclslr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bclslr
bclslr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bclslr icc0,0,0
set_spr_addr ok2,lr
set_icc 0x1 1
bclslr icc1,0,1
fail
ok2:
set_spr_addr bad,lr
set_icc 0x2 2
bclslr icc2,0,2
set_spr_addr ok4,lr
set_icc 0x3 3
bclslr icc3,0,3
fail
ok4:
set_spr_addr ok5,lr
set_icc 0x4 0
bclslr icc0,0,0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
bclslr icc1,0,1
fail
ok6:
set_spr_addr ok7,lr
set_icc 0x6 2
bclslr icc2,0,2
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
bclslr icc3,0,3
fail
ok8:
set_spr_addr bad,lr
set_icc 0x8 0
bclslr icc0,0,0
set_spr_addr oka,lr
set_icc 0x9 1
bclslr icc1,0,1
fail
oka:
set_spr_addr bad,lr
set_icc 0xa 2
bclslr icc2,0,2
set_spr_addr okc,lr
set_icc 0xb 3
bclslr icc3,0,3
fail
okc:
set_spr_addr okd,lr
set_icc 0xc 0
bclslr icc0,0,0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bclslr icc1,0,1
fail
oke:
set_spr_addr okf,lr
set_icc 0xe 2
bclslr icc2,0,2
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bclslr icc3,0,3
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bclslr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr oki,lr
set_icc 0x1 1
bclslr icc1,1,1
fail
oki:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x2 2
bclslr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr okk,lr
set_icc 0x3 3
bclslr icc3,1,3
fail
okk:
set_spr_immed 1,lcr
set_spr_addr okl,lr
set_icc 0x4 0
bclslr icc0,1,0
fail
okl:
set_spr_immed 1,lcr
set_spr_addr okm,lr
set_icc 0x5 1
bclslr icc1,1,1
fail
okm:
set_spr_immed 1,lcr
set_spr_addr okn,lr
set_icc 0x6 2
bclslr icc2,1,2
fail
okn:
set_spr_immed 1,lcr
set_spr_addr oko,lr
set_icc 0x7 3
bclslr icc3,1,3
fail
oko:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x8 0
bclslr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr okq,lr
set_icc 0x9 1
bclslr icc1,1,1
fail
okq:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xa 2
bclslr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_icc 0xb 3
bclslr icc3,1,3
fail
oks:
set_spr_immed 1,lcr
set_spr_addr okt,lr
set_icc 0xc 0
bclslr icc0,1,0
fail
okt:
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_icc 0xd 1
bclslr icc1,1,1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr okv,lr
set_icc 0xe 2
bclslr icc2,1,2
fail
okv:
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_icc 0xf 3
bclslr icc3,1,3
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bclslr icc0,1,0
set_icc 0x1 1
bclslr icc1,1,1
set_icc 0x2 2
bclslr icc2,1,2
set_icc 0x3 3
bclslr icc3,1,3
set_icc 0x4 0
bclslr icc0,1,0
set_icc 0x5 1
bclslr icc1,1,1
set_icc 0x6 2
bclslr icc2,1,2
set_icc 0x7 3
bclslr icc3,1,3
set_icc 0x8 0
bclslr icc0,1,0
set_icc 0x9 1
bclslr icc1,1,1
set_icc 0xa 2
bclslr icc2,1,2
set_icc 0xb 3
bclslr icc3,1,3
set_icc 0xc 0
bclslr icc0,1,0
set_icc 0xd 1
bclslr icc1,1,1
set_icc 0xe 2
bclslr icc2,1,2
set_icc 0xf 3
bclslr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bclslr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bclslr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bclslr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bclslr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bclslr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bclslr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bclslr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bclslr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bclslr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bclslr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bclslr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bclslr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bclslr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bclslr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bclslr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bclslr icc3,0,3
pass
bad:
fail

292
sim/testsuite/sim/frv/bcltlr.cgs Normal file
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# frv testcase for bcltlr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bcltlr
bcltlr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcltlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x1 1
bcltlr icc1,0,1
set_spr_addr ok3,lr
set_icc 0x2 2
bcltlr icc2,0,2
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
bcltlr icc3,0,3
fail
ok4:
set_spr_addr bad,lr
set_icc 0x4 0
bcltlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x5 1
bcltlr icc1,0,1
set_spr_addr ok7,lr
set_icc 0x6 2
bcltlr icc2,0,2
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
bcltlr icc3,0,3
fail
ok8:
set_spr_addr ok9,lr
set_icc 0x8 0
bcltlr icc0,0,0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bcltlr icc1,0,1
fail
oka:
set_spr_addr bad,lr
set_icc 0xa 2
bcltlr icc2,0,2
set_spr_addr bad,lr
set_icc 0xb 3
bcltlr icc3,0,3
set_spr_addr okd,lr
set_icc 0xc 0
bcltlr icc0,0,0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bcltlr icc1,0,1
fail
oke:
set_spr_addr bad,lr
set_icc 0xe 2
bcltlr icc2,0,2
set_spr_addr bad,lr
set_icc 0xf 3
bcltlr icc3,0,3
; ccond is true
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcltlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x1 1
bcltlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okj,lr
set_icc 0x2 2
bcltlr icc2,1,2
fail
okj:
set_spr_immed 1,lcr
set_spr_addr okk,lr
set_icc 0x3 3
bcltlr icc3,1,3
fail
okk:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x4 0
bcltlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x5 1
bcltlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okn,lr
set_icc 0x6 2
bcltlr icc2,1,2
fail
okn:
set_spr_immed 1,lcr
set_spr_addr oko,lr
set_icc 0x7 3
bcltlr icc3,1,3
fail
oko:
set_spr_immed 1,lcr
set_spr_addr okp,lr
set_icc 0x8 0
bcltlr icc0,1,0
fail
okp:
set_spr_immed 1,lcr
set_spr_addr okq,lr
set_icc 0x9 1
bcltlr icc1,1,1
fail
okq:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xa 2
bcltlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xb 3
bcltlr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okt,lr
set_icc 0xc 0
bcltlr icc0,1,0
fail
okt:
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_icc 0xd 1
bcltlr icc1,1,1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xe 2
bcltlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xf 3
bcltlr icc3,1,3
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcltlr icc0,1,0
set_icc 0x1 1
bcltlr icc1,1,1
set_icc 0x2 2
bcltlr icc2,1,2
set_icc 0x3 3
bcltlr icc3,1,3
set_icc 0x4 0
bcltlr icc0,1,0
set_icc 0x5 1
bcltlr icc1,1,1
set_icc 0x6 2
bcltlr icc2,1,2
set_icc 0x7 3
bcltlr icc3,1,3
set_icc 0x8 0
bcltlr icc0,1,0
set_icc 0x9 1
bcltlr icc1,1,1
set_icc 0xa 2
bcltlr icc2,1,2
set_icc 0xb 3
bcltlr icc3,1,3
set_icc 0xc 0
bcltlr icc0,1,0
set_icc 0xd 1
bcltlr icc1,1,1
set_icc 0xe 2
bcltlr icc2,1,2
set_icc 0xf 3
bcltlr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcltlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bcltlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bcltlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bcltlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bcltlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bcltlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bcltlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bcltlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bcltlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bcltlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bcltlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bcltlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bcltlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bcltlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bcltlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bcltlr icc3,0,3
pass
bad:
fail

293
sim/testsuite/sim/frv/bcnclr.cgs Normal file
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# frv testcase for bcnclr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bcnclr
bcnclr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_icc 0x0 0
bcnclr icc0,0,0
fail
ok1:
set_spr_addr bad,lr
set_icc 0x1 1
bcnclr icc1,0,1
set_spr_addr ok3,lr
set_icc 0x2 2
bcnclr icc2,0,2
fail
ok3:
set_spr_addr bad,lr
set_icc 0x3 3
bcnclr icc3,0,3
set_spr_addr ok5,lr
set_icc 0x4 0
bcnclr icc0,0,0
fail
ok5:
set_spr_addr bad,lr
set_icc 0x5 1
bcnclr icc1,0,1
set_spr_addr ok7,lr
set_icc 0x6 2
bcnclr icc2,0,2
fail
ok7:
set_spr_addr bad,lr
set_icc 0x7 3
bcnclr icc3,0,3
set_spr_addr ok9,lr
set_icc 0x8 0
bcnclr icc0,0,0
fail
ok9:
set_spr_addr bad,lr
set_icc 0x9 1
bcnclr icc1,0,1
set_spr_addr okb,lr
set_icc 0xa 2
bcnclr icc2,0,2
fail
okb:
set_spr_addr bad,lr
set_icc 0xb 3
bcnclr icc3,0,3
set_spr_addr okd,lr
set_icc 0xc 0
bcnclr icc0,0,0
fail
okd:
set_spr_addr bad,lr
set_icc 0xd 1
bcnclr icc1,0,1
set_spr_addr okf,lr
set_icc 0xe 2
bcnclr icc2,0,2
fail
okf:
set_spr_addr bad,lr
set_icc 0xf 3
bcnclr icc3,0,3
; ccond is true
set_spr_immed 1,lcr
set_spr_addr okh,lr
set_icc 0x0 0
bcnclr icc0,1,0
fail
okh:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x1 1
bcnclr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okj,lr
set_icc 0x2 2
bcnclr icc2,1,2
fail
okj:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x3 3
bcnclr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okl,lr
set_icc 0x4 0
bcnclr icc0,1,0
fail
okl:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x5 1
bcnclr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okn,lr
set_icc 0x6 2
bcnclr icc2,1,2
fail
okn:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x7 3
bcnclr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okp,lr
set_icc 0x8 0
bcnclr icc0,1,0
fail
okp:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x9 1
bcnclr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okr,lr
set_icc 0xa 2
bcnclr icc2,1,2
fail
okr:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xb 3
bcnclr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okt,lr
set_icc 0xc 0
bcnclr icc0,1,0
fail
okt:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xd 1
bcnclr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okv,lr
set_icc 0xe 2
bcnclr icc2,1,2
fail
okv:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xf 3
bcnclr icc3,1,3
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnclr icc0,1,0
set_icc 0x1 1
bcnclr icc1,1,1
set_icc 0x2 2
bcnclr icc2,1,2
set_icc 0x3 3
bcnclr icc3,1,3
set_icc 0x4 0
bcnclr icc0,1,0
set_icc 0x5 1
bcnclr icc1,1,1
set_icc 0x6 2
bcnclr icc2,1,2
set_icc 0x7 3
bcnclr icc3,1,3
set_icc 0x8 0
bcnclr icc0,1,0
set_icc 0x9 1
bcnclr icc1,1,1
set_icc 0xa 2
bcnclr icc2,1,2
set_icc 0xb 3
bcnclr icc3,1,3
set_icc 0xc 0
bcnclr icc0,1,0
set_icc 0xd 1
bcnclr icc1,1,1
set_icc 0xe 2
bcnclr icc2,1,2
set_icc 0xf 3
bcnclr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnclr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bcnclr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bcnclr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bcnclr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bcnclr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bcnclr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bcnclr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bcnclr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bcnclr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bcnclr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bcnclr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bcnclr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bcnclr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bcnclr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bcnclr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bcnclr icc3,0,3
pass
bad:
fail

292
sim/testsuite/sim/frv/bcnelr.cgs Normal file
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# frv testcase for bcnelr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bcnelr
bcnelr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_icc 0x0 0
bcnelr icc0,0,0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bcnelr icc1,0,1
fail
ok2:
set_spr_addr ok3,lr
set_icc 0x2 2
bcnelr icc2,0,2
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
bcnelr icc3,0,3
fail
ok4:
set_spr_addr bad,lr
set_icc 0x4 0
bcnelr icc0,0,0
set_spr_addr bad,lr
set_icc 0x5 1
bcnelr icc1,0,1
set_spr_addr bad,lr
set_icc 0x6 2
bcnelr icc2,0,2
set_spr_addr bad,lr
set_icc 0x7 3
bcnelr icc3,0,3
set_spr_addr ok9,lr
set_icc 0x8 0
bcnelr icc0,0,0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bcnelr icc1,0,1
fail
oka:
set_spr_addr okb,lr
set_icc 0xa 2
bcnelr icc2,0,2
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bcnelr icc3,0,3
fail
okc:
set_spr_addr bad,lr
set_icc 0xc 0
bcnelr icc0,0,0
set_spr_addr bad,lr
set_icc 0xd 1
bcnelr icc1,0,1
set_spr_addr bad,lr
set_icc 0xe 2
bcnelr icc2,0,2
set_spr_addr bad,lr
set_icc 0xf 3
bcnelr icc3,0,3
; ccond is true
set_spr_immed 1,lcr
set_spr_addr okh,lr
set_icc 0x0 0
bcnelr icc0,1,0
fail
okh:
set_spr_immed 1,lcr
set_spr_addr oki,lr
set_icc 0x1 1
bcnelr icc1,1,1
fail
oki:
set_spr_immed 1,lcr
set_spr_addr okj,lr
set_icc 0x2 2
bcnelr icc2,1,2
fail
okj:
set_spr_immed 1,lcr
set_spr_addr okk,lr
set_icc 0x3 3
bcnelr icc3,1,3
fail
okk:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x4 0
bcnelr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x5 1
bcnelr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x6 2
bcnelr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x7 3
bcnelr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okp,lr
set_icc 0x8 0
bcnelr icc0,1,0
fail
okp:
set_spr_immed 1,lcr
set_spr_addr okq,lr
set_icc 0x9 1
bcnelr icc1,1,1
fail
okq:
set_spr_immed 1,lcr
set_spr_addr okr,lr
set_icc 0xa 2
bcnelr icc2,1,2
fail
okr:
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_icc 0xb 3
bcnelr icc3,1,3
fail
oks:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xc 0
bcnelr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xd 1
bcnelr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xe 2
bcnelr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xf 3
bcnelr icc3,1,3
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnelr icc0,1,0
set_icc 0x1 1
bcnelr icc1,1,1
set_icc 0x2 2
bcnelr icc2,1,2
set_icc 0x3 3
bcnelr icc3,1,3
set_icc 0x4 0
bcnelr icc0,1,0
set_icc 0x5 1
bcnelr icc1,1,1
set_icc 0x6 2
bcnelr icc2,1,2
set_icc 0x7 3
bcnelr icc3,1,3
set_icc 0x8 0
bcnelr icc0,1,0
set_icc 0x9 1
bcnelr icc1,1,1
set_icc 0xa 2
bcnelr icc2,1,2
set_icc 0xb 3
bcnelr icc3,1,3
set_icc 0xc 0
bcnelr icc0,1,0
set_icc 0xd 1
bcnelr icc1,1,1
set_icc 0xe 2
bcnelr icc2,1,2
set_icc 0xf 3
bcnelr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnelr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bcnelr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bcnelr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bcnelr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bcnelr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bcnelr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bcnelr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bcnelr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bcnelr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bcnelr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bcnelr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bcnelr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bcnelr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bcnelr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bcnelr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bcnelr icc3,0,3
pass
bad:
fail

293
sim/testsuite/sim/frv/bcnlr.cgs Normal file
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# frv testcase for bcnlr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bcnlr
bcnlr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x1 1
bcnlr icc1,0,1
set_spr_addr bad,lr
set_icc 0x2 2
bcnlr icc2,0,2
set_spr_addr bad,lr
set_icc 0x3 3
bcnlr icc3,0,3
set_spr_addr bad,lr
set_icc 0x4 0
bcnlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x5 1
bcnlr icc1,0,1
set_spr_addr bad,lr
set_icc 0x6 2
bcnlr icc2,0,2
set_spr_addr bad,lr
set_icc 0x7 3
bcnlr icc3,0,3
set_spr_addr ok9,lr
set_icc 0x8 0
bcnlr icc0,0,0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bcnlr icc1,0,1
fail
oka:
set_spr_addr okb,lr
set_icc 0xa 2
bcnlr icc2,0,2
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bcnlr icc3,0,3
fail
okc:
set_spr_addr okd,lr
set_icc 0xc 0
bcnlr icc0,0,0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bcnlr icc1,0,1
fail
oke:
set_spr_addr okf,lr
set_icc 0xe 2
bcnlr icc2,0,2
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bcnlr icc3,0,3
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x1 1
bcnlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x2 2
bcnlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x3 3
bcnlr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x4 0
bcnlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x5 1
bcnlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x6 2
bcnlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x7 3
bcnlr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okp,lr
set_icc 0x8 0
bcnlr icc0,1,0
fail
okp:
set_spr_immed 1,lcr
set_spr_addr okq,lr
set_icc 0x9 1
bcnlr icc1,1,1
fail
okq:
set_spr_immed 1,lcr
set_spr_addr okr,lr
set_icc 0xa 2
bcnlr icc2,1,2
fail
okr:
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_icc 0xb 3
bcnlr icc3,1,3
fail
oks:
set_spr_immed 1,lcr
set_spr_addr okt,lr
set_icc 0xc 0
bcnlr icc0,1,0
fail
okt:
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_icc 0xd 1
bcnlr icc1,1,1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr okv,lr
set_icc 0xe 2
bcnlr icc2,1,2
fail
okv:
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_icc 0xf 3
bcnlr icc3,1,3
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnlr icc0,1,0
set_icc 0x1 1
bcnlr icc1,1,1
set_icc 0x2 2
bcnlr icc2,1,2
set_icc 0x3 3
bcnlr icc3,1,3
set_icc 0x4 0
bcnlr icc0,1,0
set_icc 0x5 1
bcnlr icc1,1,1
set_icc 0x6 2
bcnlr icc2,1,2
set_icc 0x7 3
bcnlr icc3,1,3
set_icc 0x8 0
bcnlr icc0,1,0
set_icc 0x9 1
bcnlr icc1,1,1
set_icc 0xa 2
bcnlr icc2,1,2
set_icc 0xb 3
bcnlr icc3,1,3
set_icc 0xc 0
bcnlr icc0,1,0
set_icc 0xd 1
bcnlr icc1,1,1
set_icc 0xe 2
bcnlr icc2,1,2
set_icc 0xf 3
bcnlr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bcnlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bcnlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bcnlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bcnlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bcnlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bcnlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bcnlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bcnlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bcnlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bcnlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bcnlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bcnlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bcnlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bcnlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bcnlr icc3,0,3
pass
bad:
fail

246
sim/testsuite/sim/frv/bcnolr.cgs Normal file
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# frv testcase for bcnolr
# mach: all
.include "testutils.inc"
start
.global bcnolr
bcnolr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnolr
set_icc 0x1 1
bcnolr
set_icc 0x2 2
bcnolr
set_icc 0x3 3
bcnolr
set_icc 0x4 0
bcnolr
set_icc 0x5 1
bcnolr
set_icc 0x6 2
bcnolr
set_icc 0x7 3
bcnolr
set_icc 0x8 0
bcnolr
set_icc 0x9 1
bcnolr
set_icc 0xa 2
bcnolr
set_icc 0xb 3
bcnolr
set_icc 0xc 0
bcnolr
set_icc 0xd 1
bcnolr
set_icc 0xe 2
bcnolr
set_icc 0xf 3
bcnolr
; ccond is true
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnolr
set_spr_immed 1,lcr
set_icc 0x1 1
bcnolr
set_spr_immed 1,lcr
set_icc 0x2 2
bcnolr
set_spr_immed 1,lcr
set_icc 0x3 3
bcnolr
set_spr_immed 1,lcr
set_icc 0x4 0
bcnolr
set_spr_immed 1,lcr
set_icc 0x5 1
bcnolr
set_spr_immed 1,lcr
set_icc 0x6 2
bcnolr
set_spr_immed 1,lcr
set_icc 0x7 3
bcnolr
set_spr_immed 1,lcr
set_icc 0x8 0
bcnolr
set_spr_immed 1,lcr
set_icc 0x9 1
bcnolr
set_spr_immed 1,lcr
set_icc 0xa 2
bcnolr
set_spr_immed 1,lcr
set_icc 0xb 3
bcnolr
set_spr_immed 1,lcr
set_icc 0xc 0
bcnolr
set_spr_immed 1,lcr
set_icc 0xd 1
bcnolr
set_spr_immed 1,lcr
set_icc 0xe 2
bcnolr
set_spr_immed 1,lcr
set_icc 0xf 3
bcnolr
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnolr
set_icc 0x1 1
bcnolr
set_icc 0x2 2
bcnolr
set_icc 0x3 3
bcnolr
set_icc 0x4 0
bcnolr
set_icc 0x5 1
bcnolr
set_icc 0x6 2
bcnolr
set_icc 0x7 3
bcnolr
set_icc 0x8 0
bcnolr
set_icc 0x9 1
bcnolr
set_icc 0xa 2
bcnolr
set_icc 0xb 3
bcnolr
set_icc 0xc 0
bcnolr
set_icc 0xd 1
bcnolr
set_icc 0xe 2
bcnolr
set_icc 0xf 3
bcnolr
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnolr
set_spr_immed 1,lcr
set_icc 0x1 1
bcnolr
set_spr_immed 1,lcr
set_icc 0x2 2
bcnolr
set_spr_immed 1,lcr
set_icc 0x3 3
bcnolr
set_spr_immed 1,lcr
set_icc 0x4 0
bcnolr
set_spr_immed 1,lcr
set_icc 0x5 1
bcnolr
set_spr_immed 1,lcr
set_icc 0x6 2
bcnolr
set_spr_immed 1,lcr
set_icc 0x7 3
bcnolr
set_spr_immed 1,lcr
set_icc 0x8 0
bcnolr
set_spr_immed 1,lcr
set_icc 0x9 1
bcnolr
set_spr_immed 1,lcr
set_icc 0xa 2
bcnolr
set_spr_immed 1,lcr
set_icc 0xb 3
bcnolr
set_spr_immed 1,lcr
set_icc 0xc 0
bcnolr
set_spr_immed 1,lcr
set_icc 0xd 1
bcnolr
set_spr_immed 1,lcr
set_icc 0xe 2
bcnolr
set_spr_immed 1,lcr
set_icc 0xf 3
bcnolr
pass
bad:
fail

292
sim/testsuite/sim/frv/bcnvlr.cgs Normal file
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# frv testcase for bcnvlr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bcnvlr
bcnvlr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_icc 0x0 0
bcnvlr icc0,0,0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bcnvlr icc1,0,1
fail
ok2:
set_spr_addr bad,lr
set_icc 0x2 2
bcnvlr icc2,0,2
set_spr_addr bad,lr
set_icc 0x3 3
bcnvlr icc3,0,3
set_spr_addr ok5,lr
set_icc 0x4 0
bcnvlr icc0,0,0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
bcnvlr icc1,0,1
fail
ok6:
set_spr_addr bad,lr
set_icc 0x6 2
bcnvlr icc2,0,2
set_spr_addr bad,lr
set_icc 0x7 3
bcnvlr icc3,0,3
set_spr_addr ok9,lr
set_icc 0x8 0
bcnvlr icc0,0,0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bcnvlr icc1,0,1
fail
oka:
set_spr_addr bad,lr
set_icc 0xa 2
bcnvlr icc2,0,2
set_spr_addr bad,lr
set_icc 0xb 3
bcnvlr icc3,0,3
set_spr_addr okd,lr
set_icc 0xc 0
bcnvlr icc0,0,0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bcnvlr icc1,0,1
fail
oke:
set_spr_addr bad,lr
set_icc 0xe 2
bcnvlr icc2,0,2
set_spr_addr bad,lr
set_icc 0xf 3
bcnvlr icc3,0,3
; ccond is true
set_spr_immed 1,lcr
set_spr_addr okh,lr
set_icc 0x0 0
bcnvlr icc0,1,0
fail
okh:
set_spr_immed 1,lcr
set_spr_addr oki,lr
set_icc 0x1 1
bcnvlr icc1,1,1
fail
oki:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x2 2
bcnvlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x3 3
bcnvlr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okl,lr
set_icc 0x4 0
bcnvlr icc0,1,0
fail
okl:
set_spr_immed 1,lcr
set_spr_addr okm,lr
set_icc 0x5 1
bcnvlr icc1,1,1
fail
okm:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x6 2
bcnvlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x7 3
bcnvlr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okp,lr
set_icc 0x8 0
bcnvlr icc0,1,0
fail
okp:
set_spr_immed 1,lcr
set_spr_addr okq,lr
set_icc 0x9 1
bcnvlr icc1,1,1
fail
okq:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xa 2
bcnvlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xb 3
bcnvlr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr okt,lr
set_icc 0xc 0
bcnvlr icc0,1,0
fail
okt:
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_icc 0xd 1
bcnvlr icc1,1,1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xe 2
bcnvlr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xf 3
bcnvlr icc3,1,3
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnvlr icc0,1,0
set_icc 0x1 1
bcnvlr icc1,1,1
set_icc 0x2 2
bcnvlr icc2,1,2
set_icc 0x3 3
bcnvlr icc3,1,3
set_icc 0x4 0
bcnvlr icc0,1,0
set_icc 0x5 1
bcnvlr icc1,1,1
set_icc 0x6 2
bcnvlr icc2,1,2
set_icc 0x7 3
bcnvlr icc3,1,3
set_icc 0x8 0
bcnvlr icc0,1,0
set_icc 0x9 1
bcnvlr icc1,1,1
set_icc 0xa 2
bcnvlr icc2,1,2
set_icc 0xb 3
bcnvlr icc3,1,3
set_icc 0xc 0
bcnvlr icc0,1,0
set_icc 0xd 1
bcnvlr icc1,1,1
set_icc 0xe 2
bcnvlr icc2,1,2
set_icc 0xf 3
bcnvlr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcnvlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bcnvlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bcnvlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bcnvlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bcnvlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bcnvlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bcnvlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bcnvlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bcnvlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bcnvlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bcnvlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bcnvlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bcnvlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bcnvlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bcnvlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bcnvlr icc3,0,3
pass
bad:
fail

292
sim/testsuite/sim/frv/bcplr.cgs Normal file
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# frv testcase for bcplr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bcplr
bcplr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_icc 0x0 0
bcplr icc0,0,0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bcplr icc1,0,1
fail
ok2:
set_spr_addr ok3,lr
set_icc 0x2 2
bcplr icc2,0,2
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
bcplr icc3,0,3
fail
ok4:
set_spr_addr ok5,lr
set_icc 0x4 0
bcplr icc0,0,0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
bcplr icc1,0,1
fail
ok6:
set_spr_addr ok7,lr
set_icc 0x6 2
bcplr icc2,0,2
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
bcplr icc3,0,3
fail
ok8:
set_spr_addr bad,lr
set_icc 0x8 0
bcplr icc0,0,0
set_spr_addr bad,lr
set_icc 0x9 1
bcplr icc1,0,1
set_spr_addr bad,lr
set_icc 0xa 2
bcplr icc2,0,2
set_spr_addr bad,lr
set_icc 0xb 3
bcplr icc3,0,3
set_spr_addr bad,lr
set_icc 0xc 0
bcplr icc0,0,0
set_spr_addr bad,lr
set_icc 0xd 1
bcplr icc1,0,1
set_spr_addr bad,lr
set_icc 0xe 2
bcplr icc2,0,2
set_spr_addr bad,lr
set_icc 0xf 3
bcplr icc3,0,3
; ccond is true
set_spr_immed 1,lcr
set_spr_addr okh,lr
set_icc 0x0 0
bcplr icc0,1,0
fail
okh:
set_spr_immed 1,lcr
set_spr_addr oki,lr
set_icc 0x1 1
bcplr icc1,1,1
fail
oki:
set_spr_immed 1,lcr
set_spr_addr okj,lr
set_icc 0x2 2
bcplr icc2,1,2
fail
okj:
set_spr_immed 1,lcr
set_spr_addr okk,lr
set_icc 0x3 3
bcplr icc3,1,3
fail
okk:
set_spr_immed 1,lcr
set_spr_addr okl,lr
set_icc 0x4 0
bcplr icc0,1,0
fail
okl:
set_spr_immed 1,lcr
set_spr_addr okm,lr
set_icc 0x5 1
bcplr icc1,1,1
fail
okm:
set_spr_immed 1,lcr
set_spr_addr okn,lr
set_icc 0x6 2
bcplr icc2,1,2
fail
okn:
set_spr_immed 1,lcr
set_spr_addr oko,lr
set_icc 0x7 3
bcplr icc3,1,3
fail
oko:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x8 0
bcplr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x9 1
bcplr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xa 2
bcplr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xb 3
bcplr icc3,1,3
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xc 0
bcplr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xd 1
bcplr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xe 2
bcplr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xf 3
bcplr icc3,1,3
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcplr icc0,1,0
set_icc 0x1 1
bcplr icc1,1,1
set_icc 0x2 2
bcplr icc2,1,2
set_icc 0x3 3
bcplr icc3,1,3
set_icc 0x4 0
bcplr icc0,1,0
set_icc 0x5 1
bcplr icc1,1,1
set_icc 0x6 2
bcplr icc2,1,2
set_icc 0x7 3
bcplr icc3,1,3
set_icc 0x8 0
bcplr icc0,1,0
set_icc 0x9 1
bcplr icc1,1,1
set_icc 0xa 2
bcplr icc2,1,2
set_icc 0xb 3
bcplr icc3,1,3
set_icc 0xc 0
bcplr icc0,1,0
set_icc 0xd 1
bcplr icc1,1,1
set_icc 0xe 2
bcplr icc2,1,2
set_icc 0xf 3
bcplr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcplr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bcplr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bcplr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bcplr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bcplr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bcplr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bcplr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bcplr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bcplr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bcplr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bcplr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bcplr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bcplr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bcplr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bcplr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bcplr icc3,0,3
pass
bad:
fail

309
sim/testsuite/sim/frv/bcralr.cgs Normal file
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# frv testcase for bcralr $ccond
# mach: all
.include "testutils.inc"
start
.global bcralr
bcralr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr ok1,lr
set_icc 0x0 0
bcralr 0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bcralr 0
fail
ok2:
set_spr_addr ok3,lr
set_icc 0x2 2
bcralr 0
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
bcralr 0
fail
ok4:
set_spr_addr ok5,lr
set_icc 0x4 0
bcralr 0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
bcralr 0
fail
ok6:
set_spr_addr ok7,lr
set_icc 0x6 2
bcralr 0
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
bcralr 0
fail
ok8:
set_spr_addr ok9,lr
set_icc 0x8 0
bcralr 0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bcralr 0
fail
oka:
set_spr_addr okb,lr
set_icc 0xa 2
bcralr 0
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bcralr 0
fail
okc:
set_spr_addr okd,lr
set_icc 0xc 0
bcralr 0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bcralr 0
fail
oke:
set_spr_addr okf,lr
set_icc 0xe 2
bcralr 0
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bcralr 0
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr okh,lr
set_icc 0x0 0
bcralr 1
fail
okh:
set_spr_immed 1,lcr
set_spr_addr oki,lr
set_icc 0x1 1
bcralr 1
fail
oki:
set_spr_immed 1,lcr
set_spr_addr okj,lr
set_icc 0x2 2
bcralr 1
fail
okj:
set_spr_immed 1,lcr
set_spr_addr okk,lr
set_icc 0x3 3
bcralr 1
fail
okk:
set_spr_immed 1,lcr
set_spr_addr okl,lr
set_icc 0x4 0
bcralr 1
fail
okl:
set_spr_immed 1,lcr
set_spr_addr okm,lr
set_icc 0x5 1
bcralr 1
fail
okm:
set_spr_immed 1,lcr
set_spr_addr okn,lr
set_icc 0x6 2
bcralr 1
fail
okn:
set_spr_immed 1,lcr
set_spr_addr oko,lr
set_icc 0x7 3
bcralr 1
fail
oko:
set_spr_immed 1,lcr
set_spr_addr okp,lr
set_icc 0x8 0
bcralr 1
fail
okp:
set_spr_immed 1,lcr
set_spr_addr okq,lr
set_icc 0x9 1
bcralr 1
fail
okq:
set_spr_immed 1,lcr
set_spr_addr okr,lr
set_icc 0xa 2
bcralr 1
fail
okr:
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_icc 0xb 3
bcralr 1
fail
oks:
set_spr_immed 1,lcr
set_spr_addr okt,lr
set_icc 0xc 0
bcralr 1
fail
okt:
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_icc 0xd 1
bcralr 1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr okv,lr
set_icc 0xe 2
bcralr 1
fail
okv:
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_icc 0xf 3
bcralr 1
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcralr 1
set_icc 0x1 1
bcralr 1
set_icc 0x2 2
bcralr 1
set_icc 0x3 3
bcralr 1
set_icc 0x4 0
bcralr 1
set_icc 0x5 1
bcralr 1
set_icc 0x6 2
bcralr 1
set_icc 0x7 3
bcralr 1
set_icc 0x8 0
bcralr 1
set_icc 0x9 1
bcralr 1
set_icc 0xa 2
bcralr 1
set_icc 0xb 3
bcralr 1
set_icc 0xc 0
bcralr 1
set_icc 0xd 1
bcralr 1
set_icc 0xe 2
bcralr 1
set_icc 0xf 3
bcralr 1
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcralr 0
set_spr_immed 1,lcr
set_icc 0x1 1
bcralr 0
set_spr_immed 1,lcr
set_icc 0x2 2
bcralr 0
set_spr_immed 1,lcr
set_icc 0x3 3
bcralr 0
set_spr_immed 1,lcr
set_icc 0x4 0
bcralr 0
set_spr_immed 1,lcr
set_icc 0x5 1
bcralr 0
set_spr_immed 1,lcr
set_icc 0x6 2
bcralr 0
set_spr_immed 1,lcr
set_icc 0x7 3
bcralr 0
set_spr_immed 1,lcr
set_icc 0x8 0
bcralr 0
set_spr_immed 1,lcr
set_icc 0x9 1
bcralr 0
set_spr_immed 1,lcr
set_icc 0xa 2
bcralr 0
set_spr_immed 1,lcr
set_icc 0xb 3
bcralr 0
set_spr_immed 1,lcr
set_icc 0xc 0
bcralr 0
set_spr_immed 1,lcr
set_icc 0xd 1
bcralr 0
set_spr_immed 1,lcr
set_icc 0xe 2
bcralr 0
set_spr_immed 1,lcr
set_icc 0xf 3
bcralr 0
pass
bad:
fail

29
sim/testsuite/sim/frv/bctrlr.cgs Normal file
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# frv testcase for bctrlr $ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bctrlr
bctrlr:
set_spr_addr bad,lr
set_spr_immed 1,lcr
bctrlr 0,0
set_spr_addr ok1,lr
set_spr_immed 2,lcr
bctrlr 0,0
fail
ok1:
set_spr_addr bad,lr
set_spr_immed 2,lcr
bctrlr 1,0
set_spr_addr ok2,lr
bctrlr 1,0
fail
ok2:
pass
bad:
fail

293
sim/testsuite/sim/frv/bcvlr.cgs Normal file
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# frv testcase for bcvlr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bcvlr
bcvlr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcvlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x1 1
bcvlr icc1,0,1
set_spr_addr ok3,lr
set_icc 0x2 2
bcvlr icc2,0,2
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
bcvlr icc3,0,3
fail
ok4:
set_spr_addr bad,lr
set_icc 0x4 0
bcvlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x5 1
bcvlr icc1,0,1
set_spr_addr ok7,lr
set_icc 0x6 2
bcvlr icc2,0,2
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
bcvlr icc3,0,3
fail
ok8:
set_spr_addr bad,lr
set_icc 0x8 0
bcvlr icc0,0,0
set_spr_addr bad,lr
set_icc 0x9 1
bcvlr icc1,0,1
set_spr_addr okb,lr
set_icc 0xa 2
bcvlr icc2,0,2
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bcvlr icc3,0,3
fail
okc:
set_spr_addr bad,lr
set_icc 0xc 0
bcvlr icc0,0,0
set_spr_addr bad,lr
set_icc 0xd 1
bcvlr icc1,0,1
set_spr_addr okf,lr
set_icc 0xe 2
bcvlr icc2,0,2
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bcvlr icc3,0,3
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcvlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x1 1
bcvlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okj,lr
set_icc 0x2 2
bcvlr icc2,1,2
fail
okj:
set_spr_immed 1,lcr
set_spr_addr okk,lr
set_icc 0x3 3
bcvlr icc3,1,3
fail
okk:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x4 0
bcvlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x5 1
bcvlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okn,lr
set_icc 0x6 2
bcvlr icc2,1,2
fail
okn:
set_spr_immed 1,lcr
set_spr_addr oko,lr
set_icc 0x7 3
bcvlr icc3,1,3
fail
oko:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x8 0
bcvlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x9 1
bcvlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okr,lr
set_icc 0xa 2
bcvlr icc2,1,2
fail
okr:
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_icc 0xb 3
bcvlr icc3,1,3
fail
oks:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xc 0
bcvlr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xd 1
bcvlr icc1,1,1
set_spr_immed 1,lcr
set_spr_addr okv,lr
set_icc 0xe 2
bcvlr icc2,1,2
fail
okv:
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_icc 0xf 3
bcvlr icc3,1,3
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcvlr icc0,1,0
set_icc 0x1 1
bcvlr icc1,1,1
set_icc 0x2 2
bcvlr icc2,1,2
set_icc 0x3 3
bcvlr icc3,1,3
set_icc 0x4 0
bcvlr icc0,1,0
set_icc 0x5 1
bcvlr icc1,1,1
set_icc 0x6 2
bcvlr icc2,1,2
set_icc 0x7 3
bcvlr icc3,1,3
set_icc 0x8 0
bcvlr icc0,1,0
set_icc 0x9 1
bcvlr icc1,1,1
set_icc 0xa 2
bcvlr icc2,1,2
set_icc 0xb 3
bcvlr icc3,1,3
set_icc 0xc 0
bcvlr icc0,1,0
set_icc 0xd 1
bcvlr icc1,1,1
set_icc 0xe 2
bcvlr icc2,1,2
set_icc 0xf 3
bcvlr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcvlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bcvlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bcvlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bcvlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bcvlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bcvlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bcvlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bcvlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bcvlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bcvlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bcvlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bcvlr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bcvlr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bcvlr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bcvlr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bcvlr icc3,0,3
pass
bad:
fail

61
sim/testsuite/sim/frv/beq.cgs Normal file
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# frv testcase for beq $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global beq
beq:
set_icc 0x0 0
beq icc0,0,bad
set_icc 0x1 1
beq icc1,1,bad
set_icc 0x2 2
beq icc2,2,bad
set_icc 0x3 3
beq icc3,3,bad
set_icc 0x4 0
beq icc0,0,ok1
fail
ok1:
set_icc 0x5 1
beq icc1,1,ok2
fail
ok2:
set_icc 0x6 2
beq icc2,2,ok3
fail
ok3:
set_icc 0x7 3
beq icc3,3,ok4
fail
ok4:
set_icc 0x8 0
beq icc0,0,bad
set_icc 0x9 1
beq icc1,1,bad
set_icc 0xa 2
beq icc2,2,bad
set_icc 0xb 3
beq icc3,3,bad
set_icc 0xc 0
beq icc0,0,ok5
fail
ok5:
set_icc 0xd 1
beq icc1,1,ok6
fail
ok6:
set_icc 0xe 2
beq icc2,2,ok7
fail
ok7:
set_icc 0xf 3
beq icc3,3,ok8
fail
ok8:
pass
bad:
fail

71
sim/testsuite/sim/frv/beqlr.cgs Normal file
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# frv testcase for beqlr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global beqlr
beqlr:
set_spr_addr bad,lr
set_icc 0x0 0
beqlr icc0,0
set_icc 0x1 1
beqlr icc1,1
set_icc 0x2 2
beqlr icc2,2
set_icc 0x3 3
beqlr icc3,3
set_spr_addr ok1,lr
set_icc 0x4 0
beqlr icc0,0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x5 1
beqlr icc1,1
fail
ok2:
set_spr_addr ok3,lr
set_icc 0x6 2
beqlr icc2,2
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x7 3
beqlr icc3,3
fail
ok4:
set_spr_addr bad,lr
set_icc 0x8 0
beqlr icc0,0
set_icc 0x9 1
beqlr icc1,1
set_icc 0xa 2
beqlr icc2,2
set_icc 0xb 3
beqlr icc3,3
set_spr_addr ok5,lr
set_icc 0xc 0
beqlr icc0,0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0xd 1
beqlr icc1,1
fail
ok6:
set_spr_addr ok7,lr
set_icc 0xe 2
beqlr icc2,2
fail
ok7:
set_spr_addr ok8,lr
set_icc 0xf 3
beqlr icc3,3
fail
ok8:
pass
bad:
fail

61
sim/testsuite/sim/frv/bge.cgs Normal file
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# frv testcase for bge $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bge
bge:
set_icc 0x0 0
bge icc0,0,ok1
fail
ok1:
set_icc 0x1 1
bge icc1,1,ok2
fail
ok2:
set_icc 0x2 2
bge icc2,2,bad
set_icc 0x3 3
bge icc3,3,bad
set_icc 0x4 0
bge icc0,0,ok5
fail
ok5:
set_icc 0x5 1
bge icc1,1,ok6
fail
ok6:
set_icc 0x6 2
bge icc2,2,bad
set_icc 0x7 3
bge icc3,3,bad
set_icc 0x8 0
bge icc0,0,bad
set_icc 0x9 1
bge icc1,1,bad
set_icc 0xa 2
bge icc2,2,okb
fail
okb:
set_icc 0xb 3
bge icc3,3,okc
fail
okc:
set_icc 0xc 0
bge icc0,0,bad
set_icc 0xd 1
bge icc1,1,bad
set_icc 0xe 2
bge icc2,2,okf
fail
okf:
set_icc 0xf 3
bge icc3,3,okg
fail
okg:
pass
bad:
fail

84
sim/testsuite/sim/frv/bgelr.cgs Normal file
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# frv testcase for bgelr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global bgelr
bgelr:
set_spr_addr ok1,lr
set_icc 0x0 0
bgelr icc0,0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bgelr icc1,1
fail
ok2:
set_spr_addr bad,lr
set_icc 0x2 2
bgelr icc2,2
set_spr_addr bad,lr
set_icc 0x3 3
bgelr icc3,3
set_spr_addr ok5,lr
set_icc 0x4 0
bgelr icc0,0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
bgelr icc1,1
fail
ok6:
set_spr_addr bad,lr
set_icc 0x6 2
bgelr icc2,2
set_spr_addr bad,lr
set_icc 0x7 3
bgelr icc3,3
set_spr_addr bad,lr
set_icc 0x8 0
bgelr icc0,0
set_spr_addr bad,lr
set_icc 0x9 1
bgelr icc1,1
set_spr_addr okb,lr
set_icc 0xa 2
bgelr icc2,2
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bgelr icc3,3
fail
okc:
set_spr_addr bad,lr
set_icc 0xc 0
bgelr icc0,0
set_spr_addr bad,lr
set_icc 0xd 1
bgelr icc1,1
set_spr_addr okf,lr
set_icc 0xe 2
bgelr icc2,2
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bgelr icc3,3
fail
okg:
pass
bad:
fail

53
sim/testsuite/sim/frv/bgt.cgs Normal file
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# frv testcase for bgt $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bgt
bgt:
set_icc 0x0 0
bgt icc0,0,ok1
fail
ok1:
set_icc 0x1 1
bgt icc1,1,ok2
fail
ok2:
set_icc 0x2 2
bgt icc2,2,bad
set_icc 0x3 3
bgt icc3,3,bad
set_icc 0x4 0
bgt icc0,0,bad
set_icc 0x5 1
bgt icc1,1,bad
set_icc 0x6 2
bgt icc2,2,bad
set_icc 0x7 3
bgt icc3,3,bad
set_icc 0x8 0
bgt icc0,0,bad
set_icc 0x9 1
bgt icc1,1,bad
set_icc 0xa 2
bgt icc2,2,okb
fail
okb:
set_icc 0xb 3
bgt icc3,3,okc
fail
okc:
set_icc 0xc 0
bgt icc0,0,bad
set_icc 0xd 1
bgt icc1,1,bad
set_icc 0xe 2
bgt icc2,2,bad
set_icc 0xf 3
bgt icc3,3,bad
pass
bad:
fail

80
sim/testsuite/sim/frv/bgtlr.cgs Normal file
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# frv testcase for bgtlr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global bgtlr
bgtlr:
set_spr_addr ok1,lr
set_icc 0x0 0
bgtlr icc0,0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bgtlr icc1,1
fail
ok2:
set_spr_addr bad,lr
set_icc 0x2 2
bgtlr icc2,2
set_spr_addr bad,lr
set_icc 0x3 3
bgtlr icc3,3
set_spr_addr bad,lr
set_icc 0x4 0
bgtlr icc0,0
set_spr_addr bad,lr
set_icc 0x5 1
bgtlr icc1,1
set_spr_addr bad,lr
set_icc 0x6 2
bgtlr icc2,2
set_spr_addr bad,lr
set_icc 0x7 3
bgtlr icc3,3
set_spr_addr bad,lr
set_icc 0x8 0
bgtlr icc0,0
set_spr_addr bad,lr
set_icc 0x9 1
bgtlr icc1,1
set_spr_addr okb,lr
set_icc 0xa 2
bgtlr icc2,2
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bgtlr icc3,3
fail
okc:
set_spr_addr bad,lr
set_icc 0xc 0
bgtlr icc0,0
set_spr_addr bad,lr
set_icc 0xd 1
bgtlr icc1,1
set_spr_addr bad,lr
set_icc 0xe 2
bgtlr icc2,2
set_spr_addr bad,lr
set_icc 0xf 3
bgtlr icc3,3
pass
bad:
fail

53
sim/testsuite/sim/frv/bhi.cgs Normal file
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# frv testcase for bhi $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bhi
bhi:
set_icc 0x0 0
bhi icc0,0,ok1
fail
ok1:
set_icc 0x1 1
bhi icc1,1,bad
set_icc 0x2 2
bhi icc2,2,ok3
fail
ok3:
set_icc 0x3 3
bhi icc3,3,bad
set_icc 0x4 0
bhi icc0,0,bad
set_icc 0x5 1
bhi icc1,1,bad
set_icc 0x6 2
bhi icc2,2,bad
set_icc 0x7 3
bhi icc3,3,bad
set_icc 0x8 0
bhi icc0,0,ok9
fail
ok9:
set_icc 0x9 1
bhi icc1,1,bad
set_icc 0xa 2
bhi icc2,2,okb
fail
okb:
set_icc 0xb 3
bhi icc3,3,bad
set_icc 0xc 0
bhi icc0,0,bad
set_icc 0xd 1
bhi icc1,1,bad
set_icc 0xe 2
bhi icc2,2,bad
set_icc 0xf 3
bhi icc3,3,bad
pass
bad:
fail

80
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# frv testcase for bhilr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global bhilr
bhilr:
set_spr_addr ok1,lr
set_icc 0x0 0
bhilr icc0,0
fail
ok1:
set_spr_addr bad,lr
set_icc 0x1 1
bhilr icc1,1
set_spr_addr ok3,lr
set_icc 0x2 2
bhilr icc2,2
fail
ok3:
set_spr_addr bad,lr
set_icc 0x3 3
bhilr icc3,3
set_spr_addr bad,lr
set_icc 0x4 0
bhilr icc0,0
set_spr_addr bad,lr
set_icc 0x5 1
bhilr icc1,1
set_spr_addr bad,lr
set_icc 0x6 2
bhilr icc2,2
set_spr_addr bad,lr
set_icc 0x7 3
bhilr icc3,3
set_spr_addr ok9,lr
set_icc 0x8 0
bhilr icc0,0
fail
ok9:
set_spr_addr bad,lr
set_icc 0x9 1
bhilr icc1,1
set_spr_addr okb,lr
set_icc 0xa 2
bhilr icc2,2
fail
okb:
set_spr_addr bad,lr
set_icc 0xb 3
bhilr icc3,3
set_spr_addr bad,lr
set_icc 0xc 0
bhilr icc0,0
set_spr_addr bad,lr
set_icc 0xd 1
bhilr icc1,1
set_spr_addr bad,lr
set_icc 0xe 2
bhilr icc2,2
set_spr_addr bad,lr
set_icc 0xf 3
bhilr icc3,3
pass
bad:
fail

69
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# frv testcase for ble $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global ble
ble:
set_icc 0x0 0
ble icc0,0,bad
set_icc 0x1 1
ble icc1,1,bad
set_icc 0x2 2
ble icc2,2,ok3
fail
ok3:
set_icc 0x3 3
ble icc3,3,ok4
fail
ok4:
set_icc 0x4 0
ble icc0,0,ok5
fail
ok5:
set_icc 0x5 1
ble icc1,1,ok6
fail
ok6:
set_icc 0x6 2
ble icc2,2,ok7
fail
ok7:
set_icc 0x7 3
ble icc3,3,ok8
fail
ok8:
set_icc 0x8 0
ble icc0,0,ok9
fail
ok9:
set_icc 0x9 1
ble icc1,1,oka
fail
oka:
set_icc 0xa 2
ble icc2,2,bad
set_icc 0xb 3
ble icc3,3,bad
set_icc 0xc 0
ble icc0,0,okd
fail
okd:
set_icc 0xd 1
ble icc1,1,oke
fail
oke:
set_icc 0xe 2
ble icc2,2,okf
fail
okf:
set_icc 0xf 3
ble icc3,3,okg
fail
okg:
pass
bad:
fail

88
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# frv testcase for blelr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global blelr
blelr:
set_spr_addr bad,lr
set_icc 0x0 0
blelr icc0,0
set_spr_addr bad,lr
set_icc 0x1 1
blelr icc1,1
set_spr_addr ok3,lr
set_icc 0x2 2
blelr icc2,2
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
blelr icc3,3
fail
ok4:
set_spr_addr ok5,lr
set_icc 0x4 0
blelr icc0,0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
blelr icc1,1
fail
ok6:
set_spr_addr ok7,lr
set_icc 0x6 2
blelr icc2,2
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
blelr icc3,3
fail
ok8:
set_spr_addr ok9,lr
set_icc 0x8 0
blelr icc0,0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
blelr icc1,1
fail
oka:
set_spr_addr bad,lr
set_icc 0xa 2
blelr icc2,2
set_spr_addr bad,lr
set_icc 0xb 3
blelr icc3,3
set_spr_addr okd,lr
set_icc 0xc 0
blelr icc0,0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
blelr icc1,1
fail
oke:
set_spr_addr okf,lr
set_icc 0xe 2
blelr icc2,2
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
blelr icc3,3
fail
okg:
pass
bad:
fail

69
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# frv testcase for bls $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bls
bls:
set_icc 0x0 0
bls icc0,0,bad
set_icc 0x1 1
bls icc1,1,ok2
fail
ok2:
set_icc 0x2 2
bls icc2,2,bad
set_icc 0x3 3
bls icc3,3,ok4
fail
ok4:
set_icc 0x4 0
bls icc0,0,ok5
fail
ok5:
set_icc 0x5 1
bls icc1,1,ok6
fail
ok6:
set_icc 0x6 2
bls icc2,2,ok7
fail
ok7:
set_icc 0x7 3
bls icc3,3,ok8
fail
ok8:
set_icc 0x8 0
bls icc0,0,bad
set_icc 0x9 1
bls icc1,1,oka
fail
oka:
set_icc 0xa 2
bls icc2,2,bad
set_icc 0xb 3
bls icc3,3,okc
fail
okc:
set_icc 0xc 0
bls icc0,0,okd
fail
okd:
set_icc 0xd 1
bls icc1,1,oke
fail
oke:
set_icc 0xe 2
bls icc2,2,okf
fail
okf:
set_icc 0xf 3
bls icc3,3,okg
fail
okg:
pass
bad:
fail

88
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# frv testcase for blslr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global blslr
blslr:
set_spr_addr bad,lr
set_icc 0x0 0
blslr icc0,0
set_spr_addr ok2,lr
set_icc 0x1 1
blslr icc1,1
fail
ok2:
set_spr_addr bad,lr
set_icc 0x2 2
blslr icc2,2
set_spr_addr ok4,lr
set_icc 0x3 3
blslr icc3,3
fail
ok4:
set_spr_addr ok5,lr
set_icc 0x4 0
blslr icc0,0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
blslr icc1,1
fail
ok6:
set_spr_addr ok7,lr
set_icc 0x6 2
blslr icc2,2
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
blslr icc3,3
fail
ok8:
set_spr_addr bad,lr
set_icc 0x8 0
blslr icc0,0
set_spr_addr oka,lr
set_icc 0x9 1
blslr icc1,1
fail
oka:
set_spr_addr bad,lr
set_icc 0xa 2
blslr icc2,2
set_spr_addr okc,lr
set_icc 0xb 3
blslr icc3,3
fail
okc:
set_spr_addr okd,lr
set_icc 0xc 0
blslr icc0,0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
blslr icc1,1
fail
oke:
set_spr_addr okf,lr
set_icc 0xe 2
blslr icc2,2
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
blslr icc3,3
fail
okg:
pass
bad:
fail

61
sim/testsuite/sim/frv/blt.cgs Normal file
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# frv testcase for blt $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global blt
blt:
set_icc 0x0 0
blt icc0,0,bad
set_icc 0x1 1
blt icc1,1,bad
set_icc 0x2 2
blt icc2,2,ok3
fail
ok3:
set_icc 0x3 3
blt icc3,3,ok4
fail
ok4:
set_icc 0x4 0
blt icc0,0,bad
set_icc 0x5 1
blt icc1,1,bad
set_icc 0x6 2
blt icc2,2,ok7
fail
ok7:
set_icc 0x7 3
blt icc3,3,ok8
fail
ok8:
set_icc 0x8 0
blt icc0,0,ok9
fail
ok9:
set_icc 0x9 1
blt icc1,1,oka
fail
oka:
set_icc 0xa 2
blt icc2,2,bad
set_icc 0xb 3
blt icc3,3,bad
set_icc 0xc 0
blt icc0,0,okd
fail
okd:
set_icc 0xd 1
blt icc1,1,oke
fail
oke:
set_icc 0xe 2
blt icc2,2,bad
set_icc 0xf 3
blt icc3,3,bad
pass
bad:
fail

84
sim/testsuite/sim/frv/bltlr.cgs Normal file
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# frv testcase for bltlr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global bltlr
bltlr:
set_spr_addr bad,lr
set_icc 0x0 0
bltlr icc0,0
set_spr_addr bad,lr
set_icc 0x1 1
bltlr icc1,1
set_spr_addr ok3,lr
set_icc 0x2 2
bltlr icc2,2
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
bltlr icc3,3
fail
ok4:
set_spr_addr bad,lr
set_icc 0x4 0
bltlr icc0,0
set_spr_addr bad,lr
set_icc 0x5 1
bltlr icc1,1
set_spr_addr ok7,lr
set_icc 0x6 2
bltlr icc2,2
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
bltlr icc3,3
fail
ok8:
set_spr_addr ok9,lr
set_icc 0x8 0
bltlr icc0,0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bltlr icc1,1
fail
oka:
set_spr_addr bad,lr
set_icc 0xa 2
bltlr icc2,2
set_spr_addr bad,lr
set_icc 0xb 3
bltlr icc3,3
set_spr_addr okd,lr
set_icc 0xc 0
bltlr icc0,0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bltlr icc1,1
fail
oke:
set_spr_addr bad,lr
set_icc 0xe 2
bltlr icc2,2
set_spr_addr bad,lr
set_icc 0xf 3
bltlr icc3,3
pass
bad:
fail

61
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# frv testcase for bn $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bn
bn:
set_icc 0x0 0
bn icc0,0,bad
set_icc 0x1 1
bn icc1,1,bad
set_icc 0x2 2
bn icc2,2,bad
set_icc 0x3 3
bn icc3,3,bad
set_icc 0x4 0
bn icc0,0,bad
set_icc 0x5 1
bn icc1,1,bad
set_icc 0x6 2
bn icc2,2,bad
set_icc 0x7 3
bn icc3,3,bad
set_icc 0x8 0
bn icc0,0,ok9
fail
ok9:
set_icc 0x9 1
bn icc1,1,oka
fail
oka:
set_icc 0xa 2
bn icc2,2,okb
fail
okb:
set_icc 0xb 3
bn icc3,3,okc
fail
okc:
set_icc 0xc 0
bn icc0,0,okd
fail
okd:
set_icc 0xd 1
bn icc1,1,oke
fail
oke:
set_icc 0xe 2
bn icc2,2,okf
fail
okf:
set_icc 0xf 3
bn icc3,3,okg
fail
okg:
pass
bad:
fail

61
sim/testsuite/sim/frv/bnc.cgs Normal file
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# frv testcase for bnc $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bnc
bnc:
set_icc 0x0 0
bnc icc0,0,ok1
fail
ok1:
set_icc 0x1 1
bnc icc1,1,bad
set_icc 0x2 2
bnc icc2,2,ok3
fail
ok3:
set_icc 0x3 3
bnc icc3,3,bad
set_icc 0x4 0
bnc icc0,0,ok5
fail
ok5:
set_icc 0x5 1
bnc icc1,1,bad
set_icc 0x6 2
bnc icc2,2,ok7
fail
ok7:
set_icc 0x7 3
bnc icc3,3,bad
set_icc 0x8 0
bnc icc0,0,ok9
fail
ok9:
set_icc 0x9 1
bnc icc1,1,bad
set_icc 0xa 2
bnc icc2,2,okb
fail
okb:
set_icc 0xb 3
bnc icc3,3,bad
set_icc 0xc 0
bnc icc0,0,okd
fail
okd:
set_icc 0xd 1
bnc icc1,1,bad
set_icc 0xe 2
bnc icc2,2,okf
fail
okf:
set_icc 0xf 3
bnc icc3,3,bad
pass
bad:
fail

84
sim/testsuite/sim/frv/bnclr.cgs Normal file
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# frv testcase for bnclr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global bnclr
bnclr:
set_spr_addr ok1,lr
set_icc 0x0 0
bnclr icc0,0
fail
ok1:
set_spr_addr bad,lr
set_icc 0x1 1
bnclr icc1,1
set_spr_addr ok3,lr
set_icc 0x2 2
bnclr icc2,2
fail
ok3:
set_spr_addr bad,lr
set_icc 0x3 3
bnclr icc3,3
set_spr_addr ok5,lr
set_icc 0x4 0
bnclr icc0,0
fail
ok5:
set_spr_addr bad,lr
set_icc 0x5 1
bnclr icc1,1
set_spr_addr ok7,lr
set_icc 0x6 2
bnclr icc2,2
fail
ok7:
set_spr_addr bad,lr
set_icc 0x7 3
bnclr icc3,3
set_spr_addr ok9,lr
set_icc 0x8 0
bnclr icc0,0
fail
ok9:
set_spr_addr bad,lr
set_icc 0x9 1
bnclr icc1,1
set_spr_addr okb,lr
set_icc 0xa 2
bnclr icc2,2
fail
okb:
set_spr_addr bad,lr
set_icc 0xb 3
bnclr icc3,3
set_spr_addr okd,lr
set_icc 0xc 0
bnclr icc0,0
fail
okd:
set_spr_addr bad,lr
set_icc 0xd 1
bnclr icc1,1
set_spr_addr okf,lr
set_icc 0xe 2
bnclr icc2,2
fail
okf:
set_spr_addr bad,lr
set_icc 0xf 3
bnclr icc3,3
pass
bad:
fail

61
sim/testsuite/sim/frv/bne.cgs Normal file
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# frv testcase for bne $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bne
bne:
set_icc 0x0 0
bne icc0,0,ok1
fail
ok1:
set_icc 0x1 1
bne icc1,1,ok2
fail
ok2:
set_icc 0x2 2
bne icc2,2,ok3
fail
ok3:
set_icc 0x3 3
bne icc3,3,ok4
fail
ok4:
set_icc 0x4 0
bne icc0,0,bad
set_icc 0x5 1
bne icc1,1,bad
set_icc 0x6 2
bne icc2,2,bad
set_icc 0x7 3
bne icc3,3,bad
set_icc 0x8 0
bne icc0,0,ok9
fail
ok9:
set_icc 0x9 1
bne icc1,1,oka
fail
oka:
set_icc 0xa 2
bne icc2,2,okb
fail
okb:
set_icc 0xb 3
bne icc3,3,okc
fail
okc:
set_icc 0xc 0
bne icc0,0,bad
set_icc 0xd 1
bne icc1,1,bad
set_icc 0xe 2
bne icc2,2,bad
set_icc 0xf 3
bne icc3,3,bad
pass
bad:
fail

84
sim/testsuite/sim/frv/bnelr.cgs Normal file
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# frv testcase for bnelr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global bnelr
bnelr:
set_spr_addr ok1,lr
set_icc 0x0 0
bnelr icc0,0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bnelr icc1,1
fail
ok2:
set_spr_addr ok3,lr
set_icc 0x2 2
bnelr icc2,2
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
bnelr icc3,3
fail
ok4:
set_spr_addr bad,lr
set_icc 0x4 0
bnelr icc0,0
set_spr_addr bad,lr
set_icc 0x5 1
bnelr icc1,1
set_spr_addr bad,lr
set_icc 0x6 2
bnelr icc2,2
set_spr_addr bad,lr
set_icc 0x7 3
bnelr icc3,3
set_spr_addr ok9,lr
set_icc 0x8 0
bnelr icc0,0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bnelr icc1,1
fail
oka:
set_spr_addr okb,lr
set_icc 0xa 2
bnelr icc2,2
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bnelr icc3,3
fail
okc:
set_spr_addr bad,lr
set_icc 0xc 0
bnelr icc0,0
set_spr_addr bad,lr
set_icc 0xd 1
bnelr icc1,1
set_spr_addr bad,lr
set_icc 0xe 2
bnelr icc2,2
set_spr_addr bad,lr
set_icc 0xf 3
bnelr icc3,3
pass
bad:
fail

84
sim/testsuite/sim/frv/bnlr.cgs Normal file
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# frv testcase for bnlr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global bnlr
bnlr:
set_spr_addr bad,lr
set_icc 0x0 0
bnlr icc0,0
set_spr_addr bad,lr
set_icc 0x1 1
bnlr icc1,1
set_spr_addr bad,lr
set_icc 0x2 2
bnlr icc2,2
set_spr_addr bad,lr
set_icc 0x3 3
bnlr icc3,3
set_spr_addr bad,lr
set_icc 0x4 0
bnlr icc0,0
set_spr_addr bad,lr
set_icc 0x5 1
bnlr icc1,1
set_spr_addr bad,lr
set_icc 0x6 2
bnlr icc2,2
set_spr_addr bad,lr
set_icc 0x7 3
bnlr icc3,3
set_spr_addr ok9,lr
set_icc 0x8 0
bnlr icc0,0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bnlr icc1,1
fail
oka:
set_spr_addr okb,lr
set_icc 0xa 2
bnlr icc2,2
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bnlr icc3,3
fail
okc:
set_spr_addr okd,lr
set_icc 0xc 0
bnlr icc0,0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bnlr icc1,1
fail
oke:
set_spr_addr okf,lr
set_icc 0xe 2
bnlr icc2,2
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bnlr icc3,3
fail
okg:
pass
bad:
fail

45
sim/testsuite/sim/frv/bno.cgs Normal file
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# frv testcase for bno $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bno
bno:
set_icc 0x0 0
bno
set_icc 0x1 1
bno
set_icc 0x2 2
bno
set_icc 0x3 3
bno
set_icc 0x4 0
bno
set_icc 0x5 1
bno
set_icc 0x6 2
bno
set_icc 0x7 3
bno
set_icc 0x8 0
bno
set_icc 0x9 1
bno
set_icc 0xa 2
bno
set_icc 0xb 3
bno
set_icc 0xc 0
bno
set_icc 0xd 1
bno
set_icc 0xe 2
bno
set_icc 0xf 3
bno
pass
bad:
fail

61
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# frv testcase for bnolr
# mach: all
.include "testutils.inc"
start
.global bnolr
bnolr:
set_spr_addr bad,lr
set_icc 0x0 0
bnolr
set_icc 0x1 1
bnolr
set_icc 0x2 2
bnolr
set_icc 0x3 3
bnolr
set_icc 0x4 0
bnolr
set_icc 0x5 1
bnolr
set_icc 0x6 2
bnolr
set_icc 0x7 3
bnolr
set_icc 0x8 0
bnolr
set_icc 0x9 1
bnolr
set_icc 0xa 2
bnolr
set_icc 0xb 3
bnolr
set_icc 0xc 0
bnolr
set_icc 0xd 1
bnolr
set_icc 0xe 2
bnolr
set_icc 0xf 3
bnolr
pass
bad:
fail

61
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# frv testcase for bnv $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bnv
bnv:
set_icc 0x0 0
bnv icc0,0,ok1
fail
ok1:
set_icc 0x1 1
bnv icc1,1,ok2
fail
ok2:
set_icc 0x2 2
bnv icc2,2,bad
set_icc 0x3 3
bnv icc3,3,bad
set_icc 0x4 0
bnv icc0,0,ok5
fail
ok5:
set_icc 0x5 1
bnv icc1,1,ok6
fail
ok6:
set_icc 0x6 2
bnv icc2,2,bad
set_icc 0x7 3
bnv icc3,3,bad
set_icc 0x8 0
bnv icc0,0,ok9
fail
ok9:
set_icc 0x9 1
bnv icc1,1,oka
fail
oka:
set_icc 0xa 2
bnv icc2,2,bad
set_icc 0xb 3
bnv icc3,3,bad
set_icc 0xc 0
bnv icc0,0,okd
fail
okd:
set_icc 0xd 1
bnv icc1,1,oke
fail
oke:
set_icc 0xe 2
bnv icc2,2,bad
set_icc 0xf 3
bnv icc3,3,bad
pass
bad:
fail

84
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# frv testcase for bnvlr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global bnvlr
bnvlr:
set_spr_addr ok1,lr
set_icc 0x0 0
bnvlr icc0,0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bnvlr icc1,1
fail
ok2:
set_spr_addr bad,lr
set_icc 0x2 2
bnvlr icc2,2
set_spr_addr bad,lr
set_icc 0x3 3
bnvlr icc3,3
set_spr_addr ok5,lr
set_icc 0x4 0
bnvlr icc0,0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
bnvlr icc1,1
fail
ok6:
set_spr_addr bad,lr
set_icc 0x6 2
bnvlr icc2,2
set_spr_addr bad,lr
set_icc 0x7 3
bnvlr icc3,3
set_spr_addr ok9,lr
set_icc 0x8 0
bnvlr icc0,0
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bnvlr icc1,1
fail
oka:
set_spr_addr bad,lr
set_icc 0xa 2
bnvlr icc2,2
set_spr_addr bad,lr
set_icc 0xb 3
bnvlr icc3,3
set_spr_addr okd,lr
set_icc 0xc 0
bnvlr icc0,0
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bnvlr icc1,1
fail
oke:
set_spr_addr bad,lr
set_icc 0xe 2
bnvlr icc2,2
set_spr_addr bad,lr
set_icc 0xf 3
bnvlr icc3,3
pass
bad:
fail

61
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# frv testcase for bp $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bp
bp:
set_icc 0x0 0
bp icc0,0,ok1
fail
ok1:
set_icc 0x1 1
bp icc1,1,ok2
fail
ok2:
set_icc 0x2 2
bp icc2,2,ok3
fail
ok3:
set_icc 0x3 3
bp icc3,3,ok4
fail
ok4:
set_icc 0x4 0
bp icc0,0,ok5
fail
ok5:
set_icc 0x5 1
bp icc1,1,ok6
fail
ok6:
set_icc 0x6 2
bp icc2,2,ok7
fail
ok7:
set_icc 0x7 3
bp icc3,3,ok8
fail
ok8:
set_icc 0x8 0
bp icc0,0,bad
set_icc 0x9 1
bp icc1,1,bad
set_icc 0xa 2
bp icc2,2,bad
set_icc 0xb 3
bp icc3,3,bad
set_icc 0xc 0
bp icc0,0,bad
set_icc 0xd 1
bp icc1,1,bad
set_icc 0xe 2
bp icc2,2,bad
set_icc 0xf 3
bp icc3,3,bad
pass
bad:
fail

84
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# frv testcase for bplr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global bplr
bplr:
set_spr_addr ok1,lr
set_icc 0x0 0
bplr icc0,0
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bplr icc1,1
fail
ok2:
set_spr_addr ok3,lr
set_icc 0x2 2
bplr icc2,2
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
bplr icc3,3
fail
ok4:
set_spr_addr ok5,lr
set_icc 0x4 0
bplr icc0,0
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
bplr icc1,1
fail
ok6:
set_spr_addr ok7,lr
set_icc 0x6 2
bplr icc2,2
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
bplr icc3,3
fail
ok8:
set_spr_addr bad,lr
set_icc 0x8 0
bplr icc0,0
set_spr_addr bad,lr
set_icc 0x9 1
bplr icc1,1
set_spr_addr bad,lr
set_icc 0xa 2
bplr icc2,2
set_spr_addr bad,lr
set_icc 0xb 3
bplr icc3,3
set_spr_addr bad,lr
set_icc 0xc 0
bplr icc0,0
set_spr_addr bad,lr
set_icc 0xd 1
bplr icc1,1
set_spr_addr bad,lr
set_icc 0xe 2
bplr icc2,2
set_spr_addr bad,lr
set_icc 0xf 3
bplr icc3,3
pass
bad:
fail

75
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# frv testcase for bra $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bra
bra:
set_icc 0x0 0
bra ok1
fail
ok1:
set_icc 0x1 1
bra ok2
fail
ok2:
set_icc 0x2 2
bra ok3
fail
ok3:
set_icc 0x3 3
bra ok4
fail
ok4:
set_icc 0x4 0
bra ok5
fail
ok5:
set_icc 0x5 1
bra ok6
fail
ok6:
set_icc 0x6 2
bra ok7
fail
ok7:
set_icc 0x7 3
bra ok8
fail
ok8:
set_icc 0x8 0
bra ok9
fail
ok9:
set_icc 0x9 1
bra oka
fail
oka:
set_icc 0xa 2
bra okb
fail
okb:
set_icc 0xb 3
bra okc
fail
okc:
set_icc 0xc 0
bra okd
fail
okd:
set_icc 0xd 1
bra oke
fail
oke:
set_icc 0xe 2
bra okf
fail
okf:
set_icc 0xf 3
bra okg
fail
okg:
pass

91
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# frv testcase for bralr
# mach: all
.include "testutils.inc"
start
.global bralr
bralr:
set_spr_addr ok1,lr
set_icc 0x0 0
bralr
fail
ok1:
set_spr_addr ok2,lr
set_icc 0x1 1
bralr
fail
ok2:
set_spr_addr ok3,lr
set_icc 0x2 2
bralr
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
bralr
fail
ok4:
set_spr_addr ok5,lr
set_icc 0x4 0
bralr
fail
ok5:
set_spr_addr ok6,lr
set_icc 0x5 1
bralr
fail
ok6:
set_spr_addr ok7,lr
set_icc 0x6 2
bralr
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
bralr
fail
ok8:
set_spr_addr ok9,lr
set_icc 0x8 0
bralr
fail
ok9:
set_spr_addr oka,lr
set_icc 0x9 1
bralr
fail
oka:
set_spr_addr okb,lr
set_icc 0xa 2
bralr
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bralr
fail
okc:
set_spr_addr okd,lr
set_icc 0xc 0
bralr
fail
okd:
set_spr_addr oke,lr
set_icc 0xd 1
bralr
fail
oke:
set_spr_addr okf,lr
set_icc 0xe 2
bralr
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bralr
fail
okg:
pass

63
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# frv parallel testcase for branching
# mach: fr500 frv
.include "testutils.inc"
start
.global branch
branch: ; All insns in VLIW execute
setlos.p 1,gr1
setlos 0,gr2
setlos.p 0,gr3
bra ok1
setlos.p 2,gr2
setlos 3,gr3
fail
ok1:
test_gr_immed 1,gr1
test_gr_immed 0,gr2
test_gr_immed 0,gr3
; 1st branch is taken
bra.p ok5
bra ok4
bra.p ok3
bra ok2
fail
ok2:
fail
ok3:
fail
ok4:
fail
ok5:
; 1st true branch is taken
set_icc 0x4 1
bne.p icc1,1,ok6
blt icc1,1,ok7
beq.p icc1,1,ok9
ble icc1,1,ok8
fail
ok6:
fail
ok7:
fail
ok8:
fail
ok9:
; combination of the above
set_icc 0x4 1
setlos.p 4,gr4
setlos.p 0,gr5
bne.p icc1,1,oka
beq icc1,1,okb
setlos 5,gr5
fail
oka:
fail
okb:
test_gr_immed 4,gr4
test_gr_immed 0,gr5
pass

58
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# FRV testcase for break
# mach: all
.include "testutils.inc"
start
.global tra
tra:
; Can't test break anymore in the user environment because it is the
; debugger's breakpoint insn. Just pass this test for now.
pass
set_gr_spr tbr,gr7
and_gr_immed -4081,gr7 ; clear tbr.tt
inc_gr_immed 0xff0,gr7 ; break handler
set_bctrlr_0_0 gr7
set_spr_immed 128,lcr
test_spr_bits 0x4,2,0x1,psr ; psr.s is set
test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
set_spr_addr ok1,lr
break
ret:
or_spr_immed 0x00000001,psr ; turn on psr.et
and_spr_immed 0xfffffffb,psr ; turn off psr.s
test_spr_bits 0x4,2,0x0,psr ; psr.s is clear
test_spr_bits 0x1,0,0x1,psr ; psr.et is set
set_spr_addr ok0,lr
break
ret1:
test_spr_bits 0x4,2,0x0,psr ; psr.s is clear
test_spr_bits 0x1,0,0x1,psr ; psr.et is set
pass
; check interrupt for second break
ok0: test_spr_addr ret1,bpcsr
test_spr_bits 0x1000,12,0x0,bpsr ; bpsr.bs is clear
test_spr_bits 0x0001,0,0x1,bpsr ; bpsr.et is set
test_spr_bits 0x4,2,0x1,psr ; psr.s is set
test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
rett 0 ; nop
rett 1
; check interrupt for first break
ok1: test_spr_addr ret,bpcsr
test_spr_bits 0x1000,12,0x1,bpsr ; bpsr.bs is set
test_spr_bits 0x0001,0,0x0,bpsr ; bpsr.et is clear
test_spr_bits 0x4,2,0x1,psr ; psr.s is set
test_spr_bits 0x1,0,0x0,psr ; psr.et is clear
rett 0 ; nop
rett 1

61
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# frv testcase for bv $ICCi,$hint,$label16
# mach: all
.include "testutils.inc"
start
.global bv
bv:
set_icc 0x0 0
bv icc0,0,bad
set_icc 0x1 1
bv icc1,1,bad
set_icc 0x2 2
bv icc2,2,ok3
fail
ok3:
set_icc 0x3 3
bv icc3,3,ok4
fail
ok4:
set_icc 0x4 0
bv icc0,0,bad
set_icc 0x5 1
bv icc1,1,bad
set_icc 0x6 2
bv icc2,2,ok7
fail
ok7:
set_icc 0x7 3
bv icc3,3,ok8
fail
ok8:
set_icc 0x8 0
bv icc0,0,bad
set_icc 0x9 1
bv icc1,1,bad
set_icc 0xa 2
bv icc2,2,okb
fail
okb:
set_icc 0xb 3
bv icc3,3,okc
fail
okc:
set_icc 0xc 0
bv icc0,0,bad
set_icc 0xd 1
bv icc1,1,bad
set_icc 0xe 2
bv icc2,2,okf
fail
okf:
set_icc 0xf 3
bv icc3,3,okg
fail
okg:
pass
bad:
fail

84
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# frv testcase for bvlr $ICCi,$hint
# mach: all
.include "testutils.inc"
start
.global bvlr
bvlr:
set_spr_addr bad,lr
set_icc 0x0 0
bvlr icc0,0
set_spr_addr bad,lr
set_icc 0x1 1
bvlr icc1,1
set_spr_addr ok3,lr
set_icc 0x2 2
bvlr icc2,2
fail
ok3:
set_spr_addr ok4,lr
set_icc 0x3 3
bvlr icc3,3
fail
ok4:
set_spr_addr bad,lr
set_icc 0x4 0
bvlr icc0,0
set_spr_addr bad,lr
set_icc 0x5 1
bvlr icc1,1
set_spr_addr ok7,lr
set_icc 0x6 2
bvlr icc2,2
fail
ok7:
set_spr_addr ok8,lr
set_icc 0x7 3
bvlr icc3,3
fail
ok8:
set_spr_addr bad,lr
set_icc 0x8 0
bvlr icc0,0
set_spr_addr bad,lr
set_icc 0x9 1
bvlr icc1,1
set_spr_addr okb,lr
set_icc 0xa 2
bvlr icc2,2
fail
okb:
set_spr_addr okc,lr
set_icc 0xb 3
bvlr icc3,3
fail
okc:
set_spr_addr bad,lr
set_icc 0xc 0
bvlr icc0,0
set_spr_addr bad,lr
set_icc 0xd 1
bvlr icc1,1
set_spr_addr okf,lr
set_icc 0xe 2
bvlr icc2,2
fail
okf:
set_spr_addr okg,lr
set_icc 0xf 3
bvlr icc3,3
fail
okg:
pass
bad:
fail

90
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# frv testcase for cadd $GRi,$GRj,$GRk,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global cadd
cadd:
set_spr_immed 0x1b1b,cccr
set_gr_immed 1,gr7
set_gr_immed 2,gr8
cadd gr7,gr8,gr8,cc4,1
test_gr_immed 3,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
cadd gr7,gr8,gr8,cc4,1
test_gr_limmed 0x8000,0x0000,gr8
cadd gr8,gr8,gr8,cc4,1
test_gr_immed 0,gr8
set_gr_immed 1,gr7
set_gr_immed 2,gr8
cadd gr7,gr8,gr8,cc4,0
test_gr_immed 2,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
cadd gr7,gr8,gr8,cc4,0
test_gr_immed 1,gr8
cadd gr8,gr8,gr8,cc4,0
test_gr_immed 1,gr8
set_gr_immed 1,gr7
set_gr_immed 2,gr8
cadd gr7,gr8,gr8,cc5,0
test_gr_immed 3,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
cadd gr7,gr8,gr8,cc5,0
test_gr_limmed 0x8000,0x0000,gr8
cadd gr8,gr8,gr8,cc5,0
test_gr_immed 0,gr8
set_gr_immed 1,gr7
set_gr_immed 2,gr8
cadd gr7,gr8,gr8,cc5,1
test_gr_immed 2,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
cadd gr7,gr8,gr8,cc5,1
test_gr_immed 1,gr8
cadd gr8,gr8,gr8,cc5,1
test_gr_immed 1,gr8
set_gr_immed 1,gr7
set_gr_immed 2,gr8
cadd gr7,gr8,gr8,cc6,1
test_gr_immed 2,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
cadd gr7,gr8,gr8,cc6,0
test_gr_immed 1,gr8
cadd gr8,gr8,gr8,cc6,1
test_gr_immed 1,gr8
set_gr_immed 1,gr7
set_gr_immed 2,gr8
cadd gr7,gr8,gr8,cc7,0
test_gr_immed 2,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
cadd gr7,gr8,gr8,cc7,1
test_gr_immed 1,gr8
cadd gr8,gr8,gr8,cc7,0
test_gr_immed 1,gr8
pass

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# frv testcase for caddcc $GRi,$GRj,$GRk,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global caddcc
caddcc:
set_spr_immed 0x1b1b,cccr
set_gr_immed 1,gr7
set_gr_immed 2,gr8
set_icc 0x0f,0 ; Set mask opposite of expected
caddcc gr7,gr8,gr8,cc0,1
test_icc 0 0 0 0 icc0
test_gr_immed 3,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
set_icc 0x05,0 ; Set mask opposite of expected
caddcc gr7,gr8,gr8,cc0,1
test_icc 1 0 1 0 icc0
test_gr_limmed 0x8000,0x0000,gr8
set_icc 0x08,0 ; Set mask opposite of expected
caddcc gr8,gr8,gr8,cc4,1
test_icc 0 1 1 1 icc0
test_gr_immed 0,gr8
set_gr_limmed 0x8000,0x0000,gr8
set_icc 0x08,0 ; Set mask opposite of expected
caddcc gr8,gr8,gr8,cc4,1; test zero, carry and overflow bits
test_icc 0 1 1 1 icc0
test_gr_immed 0,gr8
set_gr_immed 1,gr7
set_gr_immed 2,gr8
set_icc 0x0f,0 ; Set mask opposite of expected
caddcc gr7,gr8,gr8,cc0,0
test_icc 1 1 1 1 icc0
test_gr_immed 2,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
set_icc 0x05,0 ; Set mask opposite of expected
caddcc gr7,gr8,gr8,cc0,0
test_icc 0 1 0 1 icc0
test_gr_immed 1,gr8
set_icc 0x08,0 ; Set mask opposite of expected
caddcc gr8,gr8,gr8,cc4,0
test_icc 1 0 0 0 icc0
test_gr_immed 1,gr8
set_gr_limmed 0x8000,0x0000,gr8
set_icc 0x08,0 ; Set mask opposite of expected
caddcc gr8,gr8,gr8,cc4,0; test zero, carry and overflow bits
test_icc 1 0 0 0 icc0
test_gr_limmed 0x8000,0x0000,gr8
set_gr_immed 1,gr7
set_gr_immed 2,gr8
set_icc 0x0f,1 ; Set mask opposite of expected
caddcc gr7,gr8,gr8,cc1,0
test_icc 0 0 0 0 icc1
test_gr_immed 3,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
set_icc 0x05,1 ; Set mask opposite of expected
caddcc gr7,gr8,gr8,cc1,0
test_icc 1 0 1 0 icc1
test_gr_limmed 0x8000,0x0000,gr8
set_icc 0x08,1 ; Set mask opposite of expected
caddcc gr8,gr8,gr8,cc5,0
test_icc 0 1 1 1 icc1
test_gr_immed 0,gr8
set_gr_limmed 0x8000,0x0000,gr8
set_icc 0x08,1 ; Set mask opposite of expected
caddcc gr8,gr8,gr8,cc5,0; test zero, carry and overflow bits
test_icc 0 1 1 1 icc1
test_gr_immed 0,gr8
set_gr_immed 1,gr7
set_gr_immed 2,gr8
set_icc 0x0f,1 ; Set mask opposite of expected
caddcc gr7,gr8,gr8,cc1,1
test_icc 1 1 1 1 icc1
test_gr_immed 2,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
set_icc 0x05,1 ; Set mask opposite of expected
caddcc gr7,gr8,gr8,cc1,1
test_icc 0 1 0 1 icc1
test_gr_immed 1,gr8
set_icc 0x08,1 ; Set mask opposite of expected
caddcc gr8,gr8,gr8,cc5,1
test_icc 1 0 0 0 icc1
test_gr_immed 1,gr8
set_gr_limmed 0x8000,0x0000,gr8
set_icc 0x08,1 ; Set mask opposite of expected
caddcc gr8,gr8,gr8,cc5,1; test zero, carry and overflow bits
test_icc 1 0 0 0 icc1
test_gr_limmed 0x8000,0x0000,gr8
set_gr_immed 1,gr7
set_gr_immed 2,gr8
set_icc 0x0f,2 ; Set mask opposite of expected
caddcc gr7,gr8,gr8,cc2,0
test_icc 1 1 1 1 icc2
test_gr_immed 2,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
set_icc 0x05,2 ; Set mask opposite of expected
caddcc gr7,gr8,gr8,cc2,0
test_icc 0 1 0 1 icc2
test_gr_immed 1,gr8
set_icc 0x08,2 ; Set mask opposite of expected
caddcc gr8,gr8,gr8,cc6,1
test_icc 1 0 0 0 icc2
test_gr_immed 1,gr8
set_gr_limmed 0x8000,0x0000,gr8
set_icc 0x08,2 ; Set mask opposite of expected
caddcc gr8,gr8,gr8,cc6,1; test zero, carry and overflow bits
test_icc 1 0 0 0 icc2
test_gr_limmed 0x8000,0x0000,gr8
set_gr_immed 1,gr7
set_gr_immed 2,gr8
set_icc 0x0f,3 ; Set mask opposite of expected
caddcc gr7,gr8,gr8,cc3,0
test_icc 1 1 1 1 icc3
test_gr_immed 2,gr8
set_gr_limmed 0x7fff,0xffff,gr7
set_gr_immed 1,gr8
set_icc 0x05,3 ; Set mask opposite of expected
caddcc gr7,gr8,gr8,cc3,0
test_icc 0 1 0 1 icc3
test_gr_immed 1,gr8
set_icc 0x08,3 ; Set mask opposite of expected
caddcc gr8,gr8,gr8,cc7,1
test_icc 1 0 0 0 icc3
test_gr_immed 1,gr8
set_gr_limmed 0x8000,0x0000,gr8
set_icc 0x08,3 ; Set mask opposite of expected
caddcc gr8,gr8,gr8,cc7,1; test zero, carry and overflow bits
test_icc 1 0 0 0 icc3
test_gr_limmed 0x8000,0x0000,gr8
pass

17
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# frv testcase for call $label24
# mach: all
.include "testutils.inc"
start
.global call
call:
set_spr_immed 0,lr
call ok1
bad1:
fail
ok1:
test_spr_addr bad1,lr
pass

30
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# frv parallel testcase for call $label24
# mach: fr500 frv
.include "testutils.inc"
start
.global call
call:
set_spr_immed 0,lr
call ok1
bad1:
fail
ok1:
test_spr_addr bad1,lr
set_spr_immed 0,lr
setlos.p 0,gr5
call.p ok2
bra bad3
bad2:
setlos 5,gr5
fail
bad3:
fail
ok2:
test_spr_addr bad2,lr
test_gr_immed 0,gr5
pass

26
sim/testsuite/sim/frv/callil.cgs Normal file
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# frv testcase for callil @($GRi,$d12),$LI
# mach: all
.include "testutils.inc"
start
.global callil
callil:
set_gr_addr ok2,gr8
inc_gr_immed -2047,gr8
callil @(gr8,0x7ff)
bad2:
fail
ok2:
test_spr_addr bad2,lr
set_gr_addr ok3,gr8
inc_gr_immed 2048,gr8
callil @(gr8,-2048)
bad3:
fail
ok3:
test_spr_addr bad3,lr
pass

28
sim/testsuite/sim/frv/calll.cgs Normal file
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# frv testcase for calll @($GRi,$GRj)
# mach: all
.include "testutils.inc"
start
.global calll
calll:
set_gr_addr ok2,gr8
inc_gr_immed -4,gr8
inc_gr_immed 4,gr9
calll @(gr8,gr9)
bad2:
fail
ok2:
test_spr_addr bad2,lr
set_gr_addr ok3,gr8
inc_gr_immed 4,gr8
set_gr_immed -4,gr9
calll @(gr8,gr9)
bad3:
fail
ok3:
test_spr_addr bad3,lr
pass

126
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# frv testcase for cand $GRi,$GRj,$GRk
# mach: all
.include "testutils.inc"
start
.global cand
cand:
set_spr_immed 0x1b1b,cccr
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,0 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc0,1
test_icc 1 0 1 1 icc0
test_gr_immed 0,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,0 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc0,1
test_icc 0 1 0 0 icc0
test_gr_limmed 0xaaaa,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,0 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc4,1
test_icc 1 1 0 1 icc0
test_gr_limmed 0x0000,0xaaaa,gr8
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,0 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc0,0
test_icc 1 0 1 1 icc0
test_gr_limmed 0x5555,0x5555,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,0 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc0,0
test_icc 0 1 0 0 icc0
test_gr_limmed 0xffff,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,0 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc4,0
test_icc 1 1 0 1 icc0
test_gr_limmed 0x0000,0xffff,gr8
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,1 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc1,0
test_icc 1 0 1 1 icc1
test_gr_immed 0,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,1 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc1,0
test_icc 0 1 0 0 icc1
test_gr_limmed 0xaaaa,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,1 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc5,0
test_icc 1 1 0 1 icc1
test_gr_limmed 0x0000,0xaaaa,gr8
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,1 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc1,1
test_icc 1 0 1 1 icc1
test_gr_limmed 0x5555,0x5555,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,1 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc1,1
test_icc 0 1 0 0 icc1
test_gr_limmed 0xffff,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,1 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc5,1
test_icc 1 1 0 1 icc1
test_gr_limmed 0x0000,0xffff,gr8
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,2 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc2,0
test_icc 1 0 1 1 icc2
test_gr_limmed 0x5555,0x5555,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,2 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc2,0
test_icc 0 1 0 0 icc2
test_gr_limmed 0xffff,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,2 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc6,1
test_icc 1 1 0 1 icc2
test_gr_limmed 0x0000,0xffff,gr8
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,3 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc3,0
test_icc 1 0 1 1 icc3
test_gr_limmed 0x5555,0x5555,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,3 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc3,0
test_icc 0 1 0 0 icc3
test_gr_limmed 0xffff,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,3 ; Set mask opposite of expected
cand gr7,gr8,gr8,cc7,1
test_icc 1 1 0 1 icc3
test_gr_limmed 0x0000,0xffff,gr8
pass

126
sim/testsuite/sim/frv/candcc.cgs Normal file
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# frv testcase for candcc $GRi,$GRj,$GRk,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global candcc
candcc:
set_spr_immed 0x1b1b,cccr
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,0 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc0,1
test_icc 0 1 1 1 icc0
test_gr_immed 0,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,0 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc0,1
test_icc 1 0 0 0 icc0
test_gr_limmed 0xaaaa,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,0 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc4,1
test_icc 0 0 0 1 icc0
test_gr_limmed 0x0000,0xaaaa,gr8
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,0 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc0,0
test_icc 1 0 1 1 icc0
test_gr_limmed 0x5555,0x5555,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,0 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc0,0
test_icc 0 1 0 0 icc0
test_gr_limmed 0xffff,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,0 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc4,0
test_icc 1 1 0 1 icc0
test_gr_limmed 0x0000,0xffff,gr8
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,1 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc1,0
test_icc 0 1 1 1 icc1
test_gr_immed 0,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,1 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc1,0
test_icc 1 0 0 0 icc1
test_gr_limmed 0xaaaa,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,1 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc5,0
test_icc 0 0 0 1 icc1
test_gr_limmed 0x0000,0xaaaa,gr8
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,1 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc1,1
test_icc 1 0 1 1 icc1
test_gr_limmed 0x5555,0x5555,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,1 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc1,1
test_icc 0 1 0 0 icc1
test_gr_limmed 0xffff,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,1 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc5,1
test_icc 1 1 0 1 icc1
test_gr_limmed 0x0000,0xffff,gr8
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,2 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc2,0
test_icc 1 0 1 1 icc2
test_gr_limmed 0x5555,0x5555,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,2 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc2,0
test_icc 0 1 0 0 icc2
test_gr_limmed 0xffff,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,2 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc6,1
test_icc 1 1 0 1 icc2
test_gr_limmed 0x0000,0xffff,gr8
set_gr_limmed 0xaaaa,0xaaaa,gr7
set_gr_limmed 0x5555,0x5555,gr8
set_icc 0x0b,3 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc3,0
test_icc 1 0 1 1 icc3
test_gr_limmed 0x5555,0x5555,gr8
set_gr_limmed 0xffff,0x0000,gr8
set_icc 0x04,3 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc3,0
test_icc 0 1 0 0 icc3
test_gr_limmed 0xffff,0x0000,gr8
set_gr_limmed 0x0000,0xffff,gr8
set_icc 0x0d,3 ; Set mask opposite of expected
candcc gr7,gr8,gr8,cc7,1
test_icc 1 1 0 1 icc3
test_gr_limmed 0x0000,0xffff,gr8
pass

101
sim/testsuite/sim/frv/ccalll.cgs Normal file
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# frv testcase for ccalll @($GRi,$GRj),$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global ccalll
ccalll:
set_spr_immed 0x1b1b,cccr
set_gr_addr ok2,gr8
inc_gr_immed -4,gr8
inc_gr_immed 4,gr9
ccalll @(gr8,gr9),cc0,1
bad2:
fail
ok2:
test_spr_addr bad2,lr
set_gr_addr ok3,gr8
inc_gr_immed 4,gr8
set_gr_immed -4,gr9
ccalll @(gr8,gr9),cc4,1
bad3:
fail
ok3:
test_spr_addr bad3,lr
set_spr_immed 0,lr
set_gr_addr bad,gr8
inc_gr_immed -4,gr8
set_gr_immed 4,gr9
ccalll @(gr8,gr9),cc0,0
test_spr_addr 0,lr
set_gr_addr bad,gr8
inc_gr_immed 4,gr8
set_gr_immed -4,gr9
ccalll @(gr8,gr9),cc4,0
test_spr_addr 0,lr
set_gr_addr ok5,gr8
inc_gr_immed -4,gr8
set_gr_immed 4,gr9
ccalll @(gr8,gr9),cc1,0
bad5:
fail
ok5:
test_spr_addr bad5,lr
set_gr_addr ok6,gr8
inc_gr_immed 4,gr8
set_gr_immed -4,gr9
ccalll @(gr8,gr9),cc5,0
bad6:
fail
ok6:
test_spr_addr bad6,lr
set_spr_immed 0,lr
set_gr_addr bad,gr8
inc_gr_immed -4,gr8
set_gr_immed 4,gr9
ccalll @(gr8,gr9),cc1,1
test_spr_addr 0,lr
set_gr_addr bad,gr8
inc_gr_immed 4,gr8
set_gr_immed -4,gr9
ccalll @(gr8,gr9),cc5,1
test_spr_addr 0,lr
set_gr_addr bad,gr8
inc_gr_immed -4,gr8
set_gr_immed 4,gr9
ccalll @(gr8,gr9),cc2,1
test_spr_addr 0,lr
set_gr_addr bad,gr8
inc_gr_immed 4,gr8
set_gr_immed -4,gr9
ccalll @(gr8,gr9),cc6,0
test_spr_addr 0,lr
set_gr_addr bad,gr8
inc_gr_immed -4,gr8
set_gr_immed 4,gr9
ccalll @(gr8,gr9),cc3,0
test_spr_addr 0,lr
set_gr_addr bad,gr8
inc_gr_immed 4,gr8
set_gr_immed -4,gr9
ccalll @(gr8,gr9),cc7,1
test_spr_addr 0,lr
pass
bad:
fail

490
sim/testsuite/sim/frv/cckc.cgs Normal file
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# frv testcase for cckc $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global cckc
cckc:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckc icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckc icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckc icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckc icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckc icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckc icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckc icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckc icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckc icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckc icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckc icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckc icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckc icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckc icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckc icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckc icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckc icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckc icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckc icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckc icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckc icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckc icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckc icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckc icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckc icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckc icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckc icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckc icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckc icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckc icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckc icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckc icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckc icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckc icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckc icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckc icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckc icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckc icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckc icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckc icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckc icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckc icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckc icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckc icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckc icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckc icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckc icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckc icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckc icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckc icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckc icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckc icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckc icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckc icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckc icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckc icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckc icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckc icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckc icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckc icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckc icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckc icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckc icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckc icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
pass

490
sim/testsuite/sim/frv/cckeq.cgs Normal file
View File

@ -0,0 +1,490 @@
# frv testcase for cckeq $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global cckeq
cckeq:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckeq icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckeq icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckeq icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckeq icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckeq icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckeq icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckeq icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckeq icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckeq icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckeq icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckeq icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckeq icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckeq icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckeq icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckeq icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckeq icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckeq icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckeq icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckeq icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckeq icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckeq icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckeq icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckeq icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckeq icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckeq icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckeq icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckeq icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckeq icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckeq icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckeq icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckeq icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckeq icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckeq icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckeq icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckeq icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckeq icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckeq icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckeq icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckeq icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckeq icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckeq icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckeq icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckeq icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckeq icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckeq icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckeq icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckeq icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckeq icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckeq icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckeq icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckeq icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckeq icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckeq icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckeq icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckeq icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckeq icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckeq icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckeq icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckeq icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckeq icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckeq icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckeq icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckeq icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckeq icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckeq icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckeq icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckeq icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckeq icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckeq icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckeq icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckeq icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckeq icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckeq icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckeq icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckeq icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckeq icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckeq icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckeq icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckeq icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckeq icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckeq icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckeq icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckeq icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckeq icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckeq icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckeq icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckeq icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckeq icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckeq icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckeq icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckeq icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckeq icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckeq icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckeq icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckeq icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckeq icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
pass

490
sim/testsuite/sim/frv/cckge.cgs Normal file
View File

@ -0,0 +1,490 @@
# frv testcase for cckge $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global cckge
cckge:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckge icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckge icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckge icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckge icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckge icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckge icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckge icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckge icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckge icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckge icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckge icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckge icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckge icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckge icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckge icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckge icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckge icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckge icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckge icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckge icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckge icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckge icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckge icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckge icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckge icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckge icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckge icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckge icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckge icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckge icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckge icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckge icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckge icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckge icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckge icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckge icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckge icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckge icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckge icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckge icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckge icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckge icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckge icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckge icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckge icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckge icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckge icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckge icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckge icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckge icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckge icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckge icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckge icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckge icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckge icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckge icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckge icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckge icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckge icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckge icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckge icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckge icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckge icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckge icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckge icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckge icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckge icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckge icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckge icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckge icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckge icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckge icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckge icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckge icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckge icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckge icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckge icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckge icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckge icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckge icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckge icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckge icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckge icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckge icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckge icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckge icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckge icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckge icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckge icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckge icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckge icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckge icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckge icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckge icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckge icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckge icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
pass

490
sim/testsuite/sim/frv/cckgt.cgs Normal file
View File

@ -0,0 +1,490 @@
# frv testcase for cckgt $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global cckgt
cckgt:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckgt icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckgt icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckgt icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckgt icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckgt icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckgt icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckgt icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckgt icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckgt icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckgt icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckgt icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckgt icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckgt icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckgt icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckgt icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckgt icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckgt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckgt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckgt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckgt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckgt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckgt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckgt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckgt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckgt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckgt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckgt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckgt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckgt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckgt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckgt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckgt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckgt icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckgt icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckgt icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckgt icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckgt icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckgt icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckgt icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckgt icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckgt icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckgt icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckgt icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckgt icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckgt icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckgt icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckgt icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckgt icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckgt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckgt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckgt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckgt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckgt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckgt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckgt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckgt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckgt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckgt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckgt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckgt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckgt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckgt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckgt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckgt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckgt icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckgt icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckgt icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckgt icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckgt icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckgt icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckgt icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckgt icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckgt icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckgt icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckgt icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckgt icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckgt icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckgt icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckgt icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckgt icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckgt icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckgt icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckgt icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckgt icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckgt icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckgt icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckgt icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckgt icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckgt icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckgt icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckgt icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckgt icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckgt icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckgt icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckgt icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckgt icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
pass

490
sim/testsuite/sim/frv/cckhi.cgs Normal file
View File

@ -0,0 +1,490 @@
# frv testcase for cckhi $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global cckhi
cckhi:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckhi icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckhi icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckhi icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckhi icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckhi icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckhi icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckhi icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckhi icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckhi icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckhi icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckhi icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckhi icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckhi icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckhi icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckhi icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckhi icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckhi icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckhi icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckhi icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckhi icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckhi icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckhi icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckhi icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckhi icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckhi icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckhi icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckhi icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckhi icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckhi icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckhi icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckhi icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckhi icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckhi icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckhi icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckhi icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckhi icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckhi icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckhi icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckhi icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckhi icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckhi icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckhi icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckhi icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckhi icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckhi icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckhi icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckhi icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckhi icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckhi icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckhi icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckhi icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckhi icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckhi icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckhi icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckhi icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckhi icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckhi icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckhi icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckhi icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckhi icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckhi icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckhi icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckhi icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckhi icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckhi icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckhi icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckhi icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckhi icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckhi icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckhi icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckhi icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckhi icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckhi icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckhi icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckhi icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckhi icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckhi icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckhi icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckhi icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckhi icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckhi icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckhi icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckhi icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckhi icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckhi icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckhi icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckhi icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckhi icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckhi icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckhi icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckhi icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckhi icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckhi icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckhi icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckhi icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckhi icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
pass

490
sim/testsuite/sim/frv/cckle.cgs Normal file
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# frv testcase for cckle $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global cckle
cckle:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckle icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckle icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckle icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckle icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckle icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckle icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckle icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckle icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckle icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckle icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckle icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckle icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckle icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckle icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckle icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckle icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckle icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckle icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckle icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckle icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckle icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckle icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckle icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckle icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckle icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckle icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckle icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckle icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckle icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckle icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckle icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckle icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckle icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckle icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckle icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckle icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckle icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckle icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckle icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckle icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckle icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckle icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckle icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckle icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckle icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckle icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckle icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckle icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckle icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckle icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckle icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckle icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckle icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckle icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckle icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckle icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckle icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckle icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckle icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckle icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckle icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckle icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckle icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckle icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckle icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckle icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckle icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckle icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckle icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckle icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckle icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckle icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckle icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckle icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckle icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckle icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckle icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckle icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckle icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckle icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckle icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckle icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckle icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckle icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckle icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckle icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckle icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckle icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckle icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckle icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckle icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckle icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckle icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckle icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckle icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckle icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
pass

490
sim/testsuite/sim/frv/cckls.cgs Normal file
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# frv testcase for cckls $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global cckls
cckls:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckls icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckls icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckls icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckls icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckls icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckls icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckls icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckls icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckls icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckls icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckls icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckls icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckls icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckls icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckls icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckls icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckls icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckls icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckls icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckls icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckls icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckls icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckls icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckls icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckls icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckls icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckls icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckls icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckls icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckls icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckls icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckls icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckls icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckls icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckls icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckls icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckls icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckls icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckls icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckls icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckls icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckls icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckls icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckls icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckls icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckls icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckls icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckls icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckls icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckls icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckls icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckls icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckls icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckls icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckls icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckls icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckls icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckls icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckls icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckls icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckls icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckls icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckls icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckls icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckls icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckls icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckls icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckls icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckls icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckls icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckls icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckls icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckls icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckls icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckls icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckls icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckls icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckls icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckls icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckls icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckls icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckls icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckls icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckls icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckls icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckls icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckls icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckls icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckls icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckls icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckls icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckls icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckls icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckls icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckls icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckls icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
pass

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sim/testsuite/sim/frv/ccklt.cgs Normal file
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# frv testcase for ccklt $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global ccklt
ccklt:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccklt icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccklt icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccklt icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccklt icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccklt icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccklt icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccklt icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccklt icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccklt icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccklt icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccklt icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccklt icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccklt icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccklt icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccklt icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccklt icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccklt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccklt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccklt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccklt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccklt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccklt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccklt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccklt icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccklt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccklt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccklt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccklt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccklt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccklt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccklt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccklt icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccklt icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccklt icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccklt icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccklt icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccklt icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccklt icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccklt icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccklt icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccklt icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccklt icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccklt icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccklt icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccklt icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccklt icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccklt icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccklt icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccklt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccklt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccklt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccklt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccklt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccklt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccklt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccklt icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccklt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccklt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccklt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccklt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccklt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccklt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccklt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccklt icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccklt icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccklt icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccklt icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccklt icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccklt icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccklt icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccklt icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccklt icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccklt icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccklt icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccklt icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccklt icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccklt icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccklt icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccklt icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccklt icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccklt icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccklt icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccklt icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccklt icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccklt icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccklt icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccklt icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccklt icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccklt icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccklt icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccklt icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccklt icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccklt icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccklt icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccklt icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccklt icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
pass

490
sim/testsuite/sim/frv/cckn.cgs Normal file
View File

@ -0,0 +1,490 @@
# frv testcase for cckn $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global cckn
cckn:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckn icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckn icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckn icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckn icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckn icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckn icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckn icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckn icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckn icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckn icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckn icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckn icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckn icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckn icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckn icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckn icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckn icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckn icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckn icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckn icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckn icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckn icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckn icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckn icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckn icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckn icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckn icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckn icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckn icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckn icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckn icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckn icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckn icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckn icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckn icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckn icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckn icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckn icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckn icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckn icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckn icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckn icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckn icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckn icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckn icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckn icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckn icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckn icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckn icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckn icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckn icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckn icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckn icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckn icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckn icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckn icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckn icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckn icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckn icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckn icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckn icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckn icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckn icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckn icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckn icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckn icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckn icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckn icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckn icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckn icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckn icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckn icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckn icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckn icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckn icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckn icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckn icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckn icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckn icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckn icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckn icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckn icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckn icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckn icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckn icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckn icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckn icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckn icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckn icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckn icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckn icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckn icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckn icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckn icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckn icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckn icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
pass

490
sim/testsuite/sim/frv/ccknc.cgs Normal file
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@ -0,0 +1,490 @@
# frv testcase for ccknc $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global ccknc
ccknc:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccknc icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccknc icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccknc icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccknc icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccknc icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccknc icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccknc icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccknc icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccknc icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccknc icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccknc icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccknc icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccknc icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccknc icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccknc icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccknc icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccknc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccknc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccknc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccknc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccknc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccknc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccknc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccknc icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccknc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccknc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccknc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccknc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccknc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccknc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccknc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccknc icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccknc icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccknc icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccknc icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccknc icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccknc icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccknc icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccknc icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccknc icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccknc icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccknc icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccknc icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccknc icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccknc icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccknc icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccknc icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccknc icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccknc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccknc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccknc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccknc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccknc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccknc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccknc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccknc icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccknc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccknc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccknc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccknc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccknc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccknc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccknc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccknc icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccknc icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccknc icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccknc icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccknc icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccknc icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccknc icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccknc icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccknc icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccknc icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccknc icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccknc icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccknc icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccknc icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccknc icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccknc icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccknc icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccknc icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccknc icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccknc icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccknc icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccknc icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccknc icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccknc icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccknc icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccknc icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccknc icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccknc icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccknc icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccknc icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccknc icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccknc icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccknc icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
pass

490
sim/testsuite/sim/frv/cckne.cgs Normal file
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@ -0,0 +1,490 @@
# frv testcase for cckne $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global cckne
cckne:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckne icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckne icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckne icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckne icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckne icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckne icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckne icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckne icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckne icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckne icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckne icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckne icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckne icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckne icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckne icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckne icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckne icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckne icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckne icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckne icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckne icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckne icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckne icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckne icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckne icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckne icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckne icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckne icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckne icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckne icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckne icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckne icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckne icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckne icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckne icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckne icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckne icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckne icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckne icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckne icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckne icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckne icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckne icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckne icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckne icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckne icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckne icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckne icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckne icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckne icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckne icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckne icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckne icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckne icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckne icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckne icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckne icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckne icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckne icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckne icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckne icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckne icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckne icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckne icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckne icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckne icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckne icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckne icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckne icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckne icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckne icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckne icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckne icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckne icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckne icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckne icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckne icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckne icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckne icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckne icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckne icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckne icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckne icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckne icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckne icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckne icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckne icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckne icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckne icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckne icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckne icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckne icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckne icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckne icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckne icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckne icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
pass

490
sim/testsuite/sim/frv/cckno.cgs Normal file
View File

@ -0,0 +1,490 @@
# frv testcase for cckno $CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global cckno
cckno:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckno cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckno cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckno cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckno cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckno cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckno cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckno cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckno cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckno cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckno cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckno cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckno cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckno cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckno cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckno cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckno cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckno cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckno cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckno cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckno cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckno cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckno cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckno cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckno cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckno cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckno cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckno cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckno cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckno cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckno cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckno cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckno cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckno cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckno cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckno cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckno cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckno cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckno cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckno cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckno cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckno cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckno cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckno cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckno cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckno cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckno cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckno cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckno cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckno cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckno cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckno cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckno cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckno cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckno cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckno cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckno cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckno cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckno cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckno cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckno cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckno cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckno cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckno cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckno cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckno cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckno cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckno cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckno cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckno cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckno cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckno cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckno cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckno cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckno cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckno cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckno cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckno cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckno cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckno cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckno cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckno cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckno cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckno cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckno cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckno cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckno cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckno cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckno cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckno cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckno cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckno cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckno cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckno cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckno cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckno cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckno cc7,cc7,1
test_spr_immed 0x1b1b,cccr
pass

490
sim/testsuite/sim/frv/ccknv.cgs Normal file
View File

@ -0,0 +1,490 @@
# frv testcase for ccknv $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global ccknv
ccknv:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccknv icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccknv icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccknv icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccknv icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccknv icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccknv icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccknv icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccknv icc0,cc7,cc0,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccknv icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccknv icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccknv icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccknv icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccknv icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccknv icc0,cc7,cc4,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccknv icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccknv icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccknv icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccknv icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccknv icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccknv icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccknv icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccknv icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccknv icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccknv icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccknv icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccknv icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccknv icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccknv icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccknv icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccknv icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccknv icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccknv icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccknv icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccknv icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccknv icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccknv icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccknv icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccknv icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccknv icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccknv icc0,cc7,cc1,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccknv icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccknv icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccknv icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccknv icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccknv icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccknv icc0,cc7,cc5,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccknv icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccknv icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccknv icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccknv icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccknv icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccknv icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccknv icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccknv icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccknv icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccknv icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccknv icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccknv icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccknv icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccknv icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccknv icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccknv icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccknv icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccknv icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccknv icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccknv icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccknv icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccknv icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccknv icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccknv icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccknv icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccknv icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccknv icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccknv icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccknv icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccknv icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccknv icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccknv icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccknv icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccknv icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
ccknv icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
ccknv icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
ccknv icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
ccknv icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
ccknv icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
ccknv icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
ccknv icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
ccknv icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
ccknv icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
ccknv icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
ccknv icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
ccknv icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
ccknv icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
ccknv icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
ccknv icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
ccknv icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
pass

490
sim/testsuite/sim/frv/cckp.cgs Normal file
View File

@ -0,0 +1,490 @@
# frv testcase for cckp $ICCi,$CCj_int,$CCi,$cond
# mach: all
.include "testutils.inc"
start
.global cckp
cckp:
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckp icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckp icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckp icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckp icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckp icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckp icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckp icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckp icc0,cc7,cc0,1
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckp icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckp icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckp icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckp icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckp icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckp icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckp icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckp icc0,cc7,cc4,1
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckp icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckp icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckp icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckp icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckp icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckp icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckp icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckp icc0,cc7,cc0,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckp icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckp icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckp icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckp icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckp icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckp icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckp icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckp icc0,cc7,cc4,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckp icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckp icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckp icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckp icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckp icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckp icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckp icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckp icc0,cc7,cc1,0
test_spr_immed 0xdb1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckp icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckp icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckp icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckp icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckp icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckp icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckp icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckp icc0,cc7,cc5,0
test_spr_immed 0x9b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckp icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckp icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckp icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckp icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckp icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckp icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckp icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckp icc0,cc7,cc1,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckp icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckp icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckp icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckp icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckp icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckp icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckp icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckp icc0,cc7,cc5,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckp icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckp icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckp icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckp icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckp icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckp icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckp icc0,cc7,cc2,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckp icc0,cc7,cc2,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckp icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckp icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckp icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckp icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckp icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckp icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckp icc0,cc7,cc6,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckp icc0,cc7,cc6,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x0 0
cckp icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x1 0
cckp icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x2 0
cckp icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x3 0
cckp icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x4 0
cckp icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x5 0
cckp icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x6 0
cckp icc0,cc7,cc3,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x7 0
cckp icc0,cc7,cc3,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x8 0
cckp icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0x9 0
cckp icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xa 0
cckp icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xb 0
cckp icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xc 0
cckp icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xd 0
cckp icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xe 0
cckp icc0,cc7,cc7,0
test_spr_immed 0x1b1b,cccr
set_spr_immed 0x5b1b,cccr
set_icc 0xf 0
cckp icc0,cc7,cc7,1
test_spr_immed 0x1b1b,cccr
pass

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