[binutils, ARM, 13/16] Add support for CLRM
Given the similarity between LDM/STM and CLRM register lists, most of the changes in this patch aim at sharing code between those two sets of instruction. Sharing is achieved both in parsing and encoding of those instructions. In terms of parsing, parse_reg_list () is extended to take a type that describe what type of instruction is being parsed. The reg_list_els used for parse_vfp_reg_list () is reused for the type and that function is added an assert for the new REGLIST_CLRM and REGLIST_RN enumerators. parse_reg_list () is then taught to accept APSR and reject SP and PC when parsing for a CLRM instruction. At last, caller of parse_reg_list () is updated accordingly and logic is added for the new OP_CLRMLST operand. Encoding-wise, encode_thumb2_ldmstm () is reused to encode the variable bits of CLRM and is thus renamed encode_thumb2_multi (). A new do_io parameter is added to distinguish between LDM/STM and CLRM which guard all the LDM/STM specific code of the function. Finally objdump is told how to disassemble CLRM, again reusing the logic to print the LDM/STM register list (format specifier 'm'). Tests are also added in the form of negative tests to check parsing and encoding/disassembling tests. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (enum reg_list_els): Define earlier and add REGLIST_RN and REGLIST_CLRM enumerators. (parse_reg_list): Add etype parameter to distinguish between regular core register list and CLRM register list. Add logic to recognize CLRM register list. (parse_vfp_reg_list): Assert type is not for core register list. (s_arm_unwind_save_core): Update call to parse_reg_list to new prototype. (enum operand_parse_code): Declare OP_CLRMLST enumerator. (parse_operands): Update call to parse_reg_list to new prototype. Add logic for OP_CLRMLST. (encode_thumb2_ldmstm): Rename into ... (encode_thumb2_multi): This. Add do_io parameter. Add logic to encode CLRM and guard LDM/STM only code by do_io. (do_t_ldmstm): Adapt to use encode_thumb2_multi. (do_t_push_pop): Likewise. (do_t_clrm): New function. (insns): Define CLRM. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for CLRM. (print_insn_thumb32): Add logic to print %n CLRM register list.
This commit is contained in:
Andre Vieira
parent
60f993ce17
commit
4b5a202f10
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@ -1,3 +1,29 @@
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* config/tc-arm.c (enum reg_list_els): Define earlier and add
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REGLIST_RN and REGLIST_CLRM enumerators.
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(parse_reg_list): Add etype parameter to distinguish between regular
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core register list and CLRM register list. Add logic to
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recognize CLRM register list.
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(parse_vfp_reg_list): Assert type is not for core register list.
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(s_arm_unwind_save_core): Update call to parse_reg_list to new
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prototype.
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(enum operand_parse_code): Declare OP_CLRMLST enumerator.
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(parse_operands): Update call to parse_reg_list to new prototype. Add
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logic for OP_CLRMLST.
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(encode_thumb2_ldmstm): Rename into ...
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(encode_thumb2_multi): This. Add do_io parameter. Add logic to
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encode CLRM and guard LDM/STM only code by do_io.
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(do_t_ldmstm): Adapt to use encode_thumb2_multi.
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(do_t_push_pop): Likewise.
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(do_t_clrm): New function.
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(insns): Define CLRM.
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* testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file.
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* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise.
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* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise.
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* testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise.
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* testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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Andre Vieira <andre.simoesdiasvieira@arm.com>
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@ -1688,14 +1688,27 @@ parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
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return reg * 16 + atype.index;
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}
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/* Types of registers in a list. */
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enum reg_list_els
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{
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REGLIST_RN,
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REGLIST_CLRM,
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REGLIST_VFP_S,
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REGLIST_VFP_D,
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REGLIST_NEON_D
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};
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/* Parse an ARM register list. Returns the bitmask, or FAIL. */
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static long
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parse_reg_list (char ** strp)
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parse_reg_list (char ** strp, enum reg_list_els etype)
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{
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char * str = * strp;
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long range = 0;
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int another_range;
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char *str = *strp;
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long range = 0;
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int another_range;
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gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM);
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/* We come back here if we get ranges concatenated by '+' or '|'. */
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do
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@ -1713,11 +1726,35 @@ parse_reg_list (char ** strp)
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do
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{
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int reg;
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const char apsr_str[] = "apsr";
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int apsr_str_len = strlen (apsr_str);
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if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
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reg = arm_reg_parse (&str, REGLIST_RN);
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if (etype == REGLIST_CLRM)
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{
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first_error (_(reg_expected_msgs[REG_TYPE_RN]));
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return FAIL;
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if (reg == REG_SP || reg == REG_PC)
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reg = FAIL;
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else if (reg == FAIL
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&& !strncasecmp (str, apsr_str, apsr_str_len)
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&& !ISALPHA (*(str + apsr_str_len)))
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{
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reg = 15;
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str += apsr_str_len;
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}
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if (reg == FAIL)
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{
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first_error (_("r0-r12, lr or APSR expected"));
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return FAIL;
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}
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}
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else /* etype == REGLIST_RN. */
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{
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if (reg == FAIL)
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{
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first_error (_(reg_expected_msgs[REGLIST_RN]));
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return FAIL;
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}
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}
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if (in_range)
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@ -1761,7 +1798,7 @@ parse_reg_list (char ** strp)
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return FAIL;
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}
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}
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else
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else if (etype == REGLIST_RN)
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{
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expressionS exp;
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@ -1816,15 +1853,6 @@ parse_reg_list (char ** strp)
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return range;
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}
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/* Types of registers in a list. */
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enum reg_list_els
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{
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REGLIST_VFP_S,
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REGLIST_VFP_D,
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REGLIST_NEON_D
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};
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/* Parse a VFP register list. If the string is invalid return FAIL.
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Otherwise return the number of registers, and set PBASE to the first
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register. Parses registers of type ETYPE.
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@ -1873,6 +1901,9 @@ parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
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case REGLIST_NEON_D:
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regtype = REG_TYPE_NDQ;
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break;
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default:
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gas_assert (0);
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}
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if (etype != REGLIST_VFP_S)
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@ -3988,7 +4019,7 @@ s_arm_unwind_save_core (void)
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long range;
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int n;
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range = parse_reg_list (&input_line_pointer);
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range = parse_reg_list (&input_line_pointer, REGLIST_RN);
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if (range == FAIL)
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{
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as_bad (_("expected register list"));
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@ -6548,6 +6579,7 @@ enum operand_parse_code
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OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
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OP_REGLST, /* ARM register list */
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OP_CLRMLST, /* CLRM register list */
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OP_VRSLST, /* VFP single-precision register list */
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OP_VRDLST, /* VFP double-precision register list */
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OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
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@ -7173,7 +7205,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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/* Register lists. */
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case OP_REGLST:
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val = parse_reg_list (&str);
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val = parse_reg_list (&str, REGLIST_RN);
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if (*str == '^')
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{
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inst.operands[i].writeback = 1;
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@ -7181,6 +7213,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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}
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break;
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case OP_CLRMLST:
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val = parse_reg_list (&str, REGLIST_CLRM);
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break;
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case OP_VRSLST:
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val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
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break;
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@ -7304,6 +7340,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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case OP_COND:
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case OP_oBARRIER_I15:
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case OP_REGLST:
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case OP_CLRMLST:
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case OP_VRSLST:
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case OP_VRDLST:
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case OP_VRSDLST:
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@ -11489,16 +11526,19 @@ do_t_it (void)
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/* Helper function used for both push/pop and ldm/stm. */
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static void
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encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
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encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask,
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bfd_boolean writeback)
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{
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bfd_boolean load;
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bfd_boolean load, store;
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load = (inst.instruction & (1 << 20)) != 0;
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gas_assert (base != -1 || !do_io);
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load = do_io && ((inst.instruction & (1 << 20)) != 0);
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store = do_io && !load;
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if (mask & (1 << 13))
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inst.error = _("SP not allowed in register list");
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if ((mask & (1 << base)) != 0
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if (do_io && (mask & (1 << base)) != 0
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&& writeback)
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inst.error = _("having the base register in the register list when "
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"using write back is UNPREDICTABLE");
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@ -11513,13 +11553,13 @@ encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
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set_it_insn_type_last ();
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}
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}
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else
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else if (store)
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{
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if (mask & (1 << 15))
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inst.error = _("PC not allowed in register list");
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}
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if ((mask & (mask - 1)) == 0)
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if (do_io && ((mask & (mask - 1)) == 0))
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{
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/* Single register transfers implemented as str/ldr. */
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if (writeback)
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@ -11548,7 +11588,8 @@ encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
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inst.instruction |= WRITE_BACK;
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inst.instruction |= mask;
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inst.instruction |= base << 16;
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if (do_io)
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inst.instruction |= base << 16;
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}
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static void
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@ -11643,8 +11684,9 @@ do_t_ldmstm (void)
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if (inst.instruction < 0xffff)
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inst.instruction = THUMB_OP32 (inst.instruction);
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encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
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inst.operands[0].writeback);
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encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg,
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inst.operands[1].imm,
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inst.operands[0].writeback);
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}
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}
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else
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@ -12751,7 +12793,7 @@ do_t_push_pop (void)
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else if (unified_syntax)
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{
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inst.instruction = THUMB_OP32 (inst.instruction);
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encode_thumb2_ldmstm (13, mask, TRUE);
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encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE);
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}
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else
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{
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@ -12760,6 +12802,18 @@ do_t_push_pop (void)
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}
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}
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static void
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do_t_clrm (void)
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{
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if (unified_syntax)
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encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE);
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else
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{
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inst.error = _("invalid register list to push/pop instruction");
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return;
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}
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}
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static void
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do_t_rbit (void)
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{
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@ -21834,6 +21888,8 @@ static const struct asm_opcode insns[] =
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toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop),
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toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
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toU("le", _le, 2, (oLR, EXP), t_loloop),
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ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm)
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};
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#undef ARM_VARIANT
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#undef THUMB_VARIANT
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@ -0,0 +1,4 @@
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#name: Invalid Armv8.1-M Mainline Security Extensions instructions
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#source: archv8m_1m-cmse-main-bad.s
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#as: -march=armv8.1-m.main
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#error_output: archv8m_1m-cmse-main-bad.l
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@ -0,0 +1,4 @@
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[^:]*: Assembler messages:
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[^:]*:6: Error: r0-r12, lr or APSR expected -- `clrm {}'
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[^:]*:7: Error: r0-r12, lr or APSR expected -- `clrm {sp}'
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[^:]*:8: Error: r0-r12, lr or APSR expected -- `clrm {pc}'
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@ -0,0 +1,8 @@
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.thumb
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.syntax unified
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T:
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clrm {} @ Rejects empty list
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clrm {sp} @ Rejects SP in list
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clrm {pc} @ Reject PC in list
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@ -0,0 +1,14 @@
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#name: Armv8.1-M Mainline Security Extensions instructions
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#source: archv8m_1m-cmse-main.s
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#as: -march=armv8.1-m.main -mimplicit-it=always
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#objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+.* <[^>]*> e89f 0005 clrm {r0, r2}
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0+.* <[^>]*> e89f 8000 clrm {APSR}
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0+.* <[^>]*> e89f 8008 clrm {r3, APSR}
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0+.* <[^>]*> bf08 it eq
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0+.* <[^>]*> e89f 0010 clrmeq {r4}
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#...
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@ -0,0 +1,9 @@
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.thumb
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.syntax unified
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T:
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clrm {r0, r2} @ Accepts list without APSR
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clrm {APSR} @ Accepts APSR alone
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clrm {r3, APSR} @ Accepts core register and APSR together
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clrmeq {r4} @ Accepts conditional execution
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@ -1,3 +1,9 @@
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2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
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CLRM.
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(print_insn_thumb32): Add logic to print %n CLRM register list.
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2019-04-15 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (print_insn_thumb32): Updated to accept new %P
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@ -2710,6 +2710,7 @@ static const struct opcode16 thumb_opcodes[] =
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%a print the address of a plain load/store
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%w print the width and signedness of a core load/store
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%m print register mask for ldm/stm
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%n print register mask for clrm
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%E print the lsb and width fields of a bfc/bfi instruction
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%F print the lsb and width fields of a sbfx/ubfx instruction
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@ -2751,7 +2752,8 @@ static const struct opcode16 thumb_opcodes[] =
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makes heavy use of special-case bit patterns. */
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static const struct opcode32 thumb32_opcodes[] =
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{
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/* Armv8.1-M Mainline instructions. */
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/* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
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instructions. */
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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@ -2772,6 +2774,8 @@ static const struct opcode32 thumb32_opcodes[] =
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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0xe89f0000, 0xffff2000, "clrm%c\t%n"},
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/* ARMv8-M and ARMv8-M Security Extensions instructions. */
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
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@ -5556,6 +5560,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
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for (insn = thumb32_opcodes; insn->assembler; insn++)
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if ((given & insn->mask) == insn->value)
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{
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bfd_boolean is_clrm = FALSE;
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bfd_boolean is_unpredictable = FALSE;
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signed long value_in_comment = 0;
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const char *c = insn->assembler;
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@ -5851,6 +5856,9 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
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}
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||||
break;
|
||||
|
||||
case 'n':
|
||||
is_clrm = TRUE;
|
||||
/* Fall through. */
|
||||
case 'm':
|
||||
{
|
||||
int started = 0;
|
||||
|
|
@ -5863,7 +5871,12 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
|
|||
if (started)
|
||||
func (stream, ", ");
|
||||
started = 1;
|
||||
func (stream, "%s", arm_regnames[reg]);
|
||||
if (is_clrm && reg == 13)
|
||||
func (stream, "(invalid: %s)", arm_regnames[reg]);
|
||||
else if (is_clrm && reg == 15)
|
||||
func (stream, "%s", "APSR");
|
||||
else
|
||||
func (stream, "%s", arm_regnames[reg]);
|
||||
}
|
||||
func (stream, "}");
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue