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[PowerPC] Document requirements for VSX feature 

As suggested in
https://sourceware.org/ml/gdb-patches/2018-10/msg00510.html, this
patch changes the documentation for the VSX tdesc feature to make it
clear that the altivec and FPU features are requirements.

gdb/doc/ChangeLog:
2018-11-09  Pedro Franco de Carvalho  <pedromfc@linux.ibm.com>

	* gdb.texinfo (PowerPC Features): Document the altivec and fpu
	requirements for the org.gnu.gdb.power.vsx feature.
This commit is contained in:
Pedro Franco de Carvalho 2018-11-09 16:09:03 -02:00
parent 5d762de01c
commit 4b905ae1b4
2 changed files with 12 additions and 5 deletions
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5
gdb/doc/ChangeLog
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@ -1,3 +1,8 @@
2018-11-09 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.texinfo (PowerPC Features): Document the altivec and fpu
requirements for the org.gnu.gdb.power.vsx feature.
2018-11-01 Joel Brobecker <brobecker@adacore.com>
* gdb.texinfo (Ada Tasks): Update the "info task 2" example

12
gdb/doc/gdb.texinfo
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@ -43230,11 +43230,13 @@ contain registers @samp{vr0} through @samp{vr31}, @samp{vscr},
and @samp{vrsave}.
The @samp{org.gnu.gdb.power.vsx} feature is optional. It should
contain registers @samp{vs0h} through @samp{vs31h}. @value{GDBN}
will combine these registers with the floating point registers
(@samp{f0} through @samp{f31}) and the altivec registers (@samp{vr0}
through @samp{vr31}) to present the 128-bit wide registers @samp{vs0}
through @samp{vs63}, the set of vector registers for POWER7.
contain registers @samp{vs0h} through @samp{vs31h}. @value{GDBN} will
combine these registers with the floating point registers (@samp{f0}
through @samp{f31}) and the altivec registers (@samp{vr0} through
@samp{vr31}) to present the 128-bit wide registers @samp{vs0} through
@samp{vs63}, the set of vector-scalar registers for POWER7.
Therefore, this feature requires both @samp{org.gnu.gdb.power.fpu} and
@samp{org.gnu.gdb.power.altivec}.
The @samp{org.gnu.gdb.power.spe} feature is optional. It should
contain registers @samp{ev0h} through @samp{ev31h}, @samp{acc}, and