Add new sparc options to control instruction availability.
gas/ * config/tc-sparc.c (hwcap_allowed): New. (struct sparc_arch): New field 'hwcap_allowed' containing a bitmask of F_FOO flags which are enabled by the particular arch setting. Add new options that provide explicit access to new instructions. (md_parse_option): Only bump max_architecture if the requested one is larger, or this is the first explicit request. (get_hwcap_name): New function. (sparc_ip): Validate that hwcaps used by an instruction have actually been enabled. * doc/c-sparc.texi: Document new sparc options.
This commit is contained in:
David S. Miller
parent
a3a129def5
commit
4bafe00ecf
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@ -1,3 +1,16 @@
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2011-09-21 David S. Miller <davem@davemloft.net>
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* config/tc-sparc.c (hwcap_allowed): New.
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(struct sparc_arch): New field 'hwcap_allowed' containing a bitmask
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of F_FOO flags which are enabled by the particular arch setting.
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Add new options that provide explicit access to new instructions.
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(md_parse_option): Only bump max_architecture if the requested one
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is larger, or this is the first explicit request.
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(get_hwcap_name): New function.
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(sparc_ip): Validate that hwcaps used by an instruction have actually
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been enabled.
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* doc/c-sparc.texi: Document new sparc options.
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2011-09-21 David S. Miller <davem@davemloft.net>
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* config/tc-sparc.c (hwcap_seen): New bitmask, defined when
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@ -84,6 +84,8 @@ static int hwcap_seen;
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#endif
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#endif
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static int hwcap_allowed;
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static int architecture_requested;
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static int warn_on_bump;
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@ -231,23 +233,38 @@ static struct sparc_arch {
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int default_arch_size;
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/* Allowable arg to -A? */
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int user_option_p;
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int hwcap_allowed;
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} sparc_arch_table[] = {
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{ "v6", "v6", v6, 0, 1 },
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{ "v7", "v7", v7, 0, 1 },
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{ "v8", "v8", v8, 32, 1 },
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{ "sparclet", "sparclet", sparclet, 32, 1 },
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{ "sparclite", "sparclite", sparclite, 32, 1 },
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{ "sparc86x", "sparclite", sparc86x, 32, 1 },
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{ "v8plus", "v9", v9, 0, 1 },
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{ "v8plusa", "v9a", v9, 0, 1 },
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{ "v8plusb", "v9b", v9, 0, 1 },
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{ "v9", "v9", v9, 0, 1 },
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{ "v9a", "v9a", v9, 0, 1 },
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{ "v9b", "v9b", v9, 0, 1 },
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{ "v6", "v6", v6, 0, 1, 0 },
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{ "v7", "v7", v7, 0, 1, 0 },
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{ "v8", "v8", v8, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
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{ "v8a", "v8", v8, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
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{ "sparc", "v9", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS },
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{ "sparcvis", "v9a", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS },
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{ "sparcvis2", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2 },
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{ "sparcfmaf", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF },
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{ "sparcima", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_IMA },
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{ "sparcvis3", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_VIS3|F_HPC },
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{ "sparcvis3r", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU },
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{ "sparclet", "sparclet", sparclet, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
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{ "sparclite", "sparclite", sparclite, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
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{ "sparc86x", "sparclite", sparc86x, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
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{ "v8plus", "v9", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS },
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{ "v8plusa", "v9a", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS },
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{ "v8plusb", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2 },
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{ "v8plusc", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2|F_ASI_BLK_INIT },
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{ "v8plusd", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC },
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{ "v8plusv", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU|F_IMA|F_ASI_CACHE_SPARING },
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{ "v9", "v9", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC },
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{ "v9a", "v9a", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS },
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{ "v9b", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2 },
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{ "v9c", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_ASI_BLK_INIT },
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{ "v9d", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC },
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{ "v9v", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU|F_IMA|F_ASI_CACHE_SPARING },
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/* This exists to allow configure.in/Makefile.in to pass one
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value to specify both the default machine and default word size. */
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{ "v9-64", "v9", v9, 64, 0 },
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{ NULL, NULL, v8, 0, 0 }
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{ "v9-64", "v9", v9, 64, 0, F_MUL32|F_DIV32|F_FSMULD|F_POPC },
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{ NULL, NULL, v8, 0, 0, 0 }
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};
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/* Variant of default_arch */
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@ -487,7 +504,10 @@ md_parse_option (int c, char *arg)
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if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
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as_fatal (_("Bad opcode table, broken assembler."));
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max_architecture = opcode_arch;
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if (!architecture_requested
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|| opcode_arch > max_architecture)
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max_architecture = opcode_arch;
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hwcap_allowed |= sa->hwcap_allowed;
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architecture_requested = 1;
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}
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break;
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@ -1417,6 +1437,44 @@ md_assemble (char *str)
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}
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}
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static const char *
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get_hwcap_name (int mask)
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{
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if (mask & F_MUL32)
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return "mul32";
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if (mask & F_DIV32)
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return "div32";
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if (mask & F_FSMULD)
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return "fsmuld";
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if (mask & F_V8PLUS)
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return "v8plus";
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if (mask & F_POPC)
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return "popc";
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if (mask & F_VIS)
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return "vis";
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if (mask & F_VIS2)
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return "vis2";
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if (mask & F_ASI_BLK_INIT)
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return "ASIBlkInit";
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if (mask & F_FMAF)
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return "fmaf";
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if (mask & F_VIS3)
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return "vis3";
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if (mask & F_HPC)
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return "hpc";
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if (mask & F_RANDOM)
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return "random";
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if (mask & F_TRANS)
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return "trans";
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if (mask & F_FJFMAU)
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return "fjfmau";
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if (mask & F_IMA)
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return "ima";
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if (mask & F_ASI_CACHE_SPARING)
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return "cspare";
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return "UNKNOWN";
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}
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/* Subroutine of md_assemble to do the actual parsing. */
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static int
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@ -2792,9 +2850,9 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
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{
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/* We have a match. Now see if the architecture is OK. */
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int needed_arch_mask = insn->architecture;
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#if defined(OBJ_ELF) && !defined(TE_SOLARIS)
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int hwcaps = insn->flags & F_HWCAP_MASK;
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#if defined(OBJ_ELF) && !defined(TE_SOLARIS)
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if (hwcaps)
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hwcap_seen |= hwcaps;
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#endif
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@ -2865,6 +2923,17 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
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sparc_opcode_archs[max_architecture].name);
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return special_case;
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}
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/* Make sure the the hwcaps used by the instruction are
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currently enabled. */
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if (hwcaps & ~hwcap_allowed)
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{
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const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed);
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as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
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hwcap_name, str);
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return special_case;
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}
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} /* If no match. */
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break;
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@ -52,31 +52,91 @@ is explicitly requested. SPARC v9 is always incompatible with sparclite.
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@table @code
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@kindex -Av6
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@kindex Av7
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@kindex -Av7
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@kindex -Av8
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@kindex -Asparclet
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@kindex -Asparclite
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@kindex -Av9
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@kindex -Av9a
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@kindex -Av9b
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@kindex -Av9c
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@kindex -Av9d
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@kindex -Av9v
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@kindex -Asparc
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@kindex -Asparcvis
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@kindex -Asparcvis2
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@kindex -Asparcfmaf
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@kindex -Asparcima
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@kindex -Asparcvis3
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@kindex -Asparcvis3r
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@item -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
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@itemx -Av8plus | -Av8plusa | -Av9 | -Av9a
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@itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv
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@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v
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@itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
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@itemx -Asparcvis3 | -Asparcvis3r
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Use one of the @samp{-A} options to select one of the SPARC
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architectures explicitly. If you select an architecture explicitly,
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@code{@value{AS}} reports a fatal error if it encounters an instruction
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or feature requiring an incompatible or higher level.
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@samp{-Av8plus} and @samp{-Av8plusa} select a 32 bit environment.
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@samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc},
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@samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment.
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@samp{-Av9} and @samp{-Av9a} select a 64 bit environment and are not
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available unless GAS is explicitly configured with 64 bit environment
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support.
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@samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, and
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@samp{-Av9v} select a 64 bit environment and are not available unless GAS
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is explicitly configured with 64 bit environment support.
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@samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
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UltraSPARC extensions.
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UltraSPARC VIS 1.0 extensions.
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@item -xarch=v8plus | -xarch=v8plusa
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@samp{-Av8plusb} and @samp{-Av9b} enable the UltraSPARC VIS 2.0 instructions,
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as well as the instructions enabled by @samp{-Av8plusa} and @samp{-Av9a}.
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@samp{-Av8plusc} and @samp{-Av9c} enable the UltraSPARC Niagara instructions,
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as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}.
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@samp{-Av8plusd} and @samp{-Av9d} enable the floating point fused
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multiply-add, VIS 3.0, and HPC extension instructions, as well as the
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instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
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@samp{-Av8plusv} and @samp{-Av9v} enable the 'random', transactional
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memory, floating point unfused multiply-add, integer multiply-add, and
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cache sparing store instructions, as well as the instructions enabled
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by @samp{-Av8plusd} and @samp{-Av9d}.
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@samp{-Asparc} specifies a v9 environment. It is equivalent to
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@samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
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@samp{-Asparcvis} specifies a v9a environment. It is equivalent to
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@samp{-Av9a} if the word size is 64-bit, and @samp{-Av8plusa} otherwise.
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@samp{-Asparcvis2} specifies a v9b environment. It is equivalent to
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@samp{-Av9b} if the word size is 64-bit, and @samp{-Av8plusb} otherwise.
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@samp{-Asparcfmaf} specifies a v9b environment with the floating point
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fused multiply-add instructions enabled.
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@samp{-Asparcima} specifies a v9b environment with the integer
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multiply-add instructions enabled.
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@samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0,
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HPC , and floating point fused multiply-add instructions enabled.
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@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0,
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HPC, transactional memory, random, and floating point unfused multiply-add
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instructions enabled.
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@item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
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@itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a
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@itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v
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@itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
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@itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
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@itemx -xarch=sparcvis3r
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For compatibility with the SunOS v9 assembler. These options are
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equivalent to -Av8plus and -Av8plusa, respectively.
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equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
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-Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis,
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-Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r,
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respectively.
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@item -bump
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Warn whenever it is necessary to switch to another level.
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@ -8,6 +8,8 @@
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* gas/sparc/ticc-imm-reg.d: Likewise, add -32 to options.
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* gas/sparc/v8-movwr-imm.d: Likewise.
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* gas/sparc/hpcvis3.d: Pass '-Av9v'.
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2011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
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* gas/sparc/imm-plus-rreg.[sd]: New test.
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@ -1,4 +1,4 @@
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#as: -Av9b
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#as: -Av9v
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#objdump: -dr
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#name: sparc HPC+VIS3
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Loading…
Reference in New Issue