[AArch64] Don't warn on XZR/SP overlapping when it's in load/store
2015-03-13 Jiong Wang <jiong.wang@arm.com> gas/ * config/tc-aarch64.c (warn_unpredictable_ldst): Don't warn on reg number 31. gas/testsuite/ * gas/aarch64/diagnostic.s: New testcases. * gas/aarch64/diagnostic.l: New error match.
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Jiong Wang
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@ -1,3 +1,8 @@
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2015-03-13 Jiong Wang <jiong.wang@arm.com>
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* config/tc-aarch64.c (warn_unpredictable_ldst): Don't warn on reg
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number 31.
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2015-03-13 Jiong Wang <jiong.wang@arm.com>
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* config/tc-aarch64.h (SUB_SEGMENT_ALIGN): Define to be zero.
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@ -5585,6 +5585,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
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if ((aarch64_get_operand_class (opnds[0].type)
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== AARCH64_OPND_CLASS_INT_REG)
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&& opnds[0].reg.regno == opnds[1].addr.base_regno
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&& opnds[1].addr.base_regno != REG_SP
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&& opnds[1].addr.writeback)
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as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
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break;
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@ -5596,6 +5597,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
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== AARCH64_OPND_CLASS_INT_REG)
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&& (opnds[0].reg.regno == opnds[2].addr.base_regno
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|| opnds[1].reg.regno == opnds[2].addr.base_regno)
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&& opnds[2].addr.base_regno != REG_SP
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&& opnds[2].addr.writeback)
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as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
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/* Load operations must load different registers. */
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@ -1,3 +1,8 @@
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2015-03-13 Jiong Wang <jiong.wang@arm.com>
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* gas/aarch64/diagnostic.s: New testcases.
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* gas/aarch64/diagnostic.l: New error match.
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2015-03-13 Jiong Wang <jiong.wang@arm.com>
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* gas/aarch64/tail_padding.s: New testcase.
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@ -116,3 +116,7 @@
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[^:]*:125: Warning: unpredictable transfer with writeback -- `ldp x0,x1,\[x1\],#16'
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[^:]*:126: Error: this relocation modifier is not allowed on this instruction at operand 2 -- `adr x2,:got:s1'
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[^:]*:127: Error: this relocation modifier is not allowed on this instruction at operand 2 -- `ldr x0,\[x0,:got:s1\]'
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[^:]*:130: Error: integer 64-bit register expected at operand 2 -- `ldr x1,\[wsp,#8\]!'
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[^:]*:131: Error: integer 64-bit register expected at operand 3 -- `ldp x6,x29,\[w7,#8\]!'
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[^:]*:132: Error: integer 64-bit register expected at operand 2 -- `str x30,\[w11,#8\]!'
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[^:]*:133: Error: integer 64-bit register expected at operand 3 -- `stp x8,x27,\[wsp,#8\]!'
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@ -125,3 +125,87 @@
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ldp x0, x1, [x1], #16
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adr x2, :got:s1
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ldr x0, [x0, :got:s1]
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# Test error of 32-bit base reg
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ldr x1, [wsp, #8]!
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ldp x6, x29, [w7, #8]!
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str x30, [w11, #8]!
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stp x8, x27, [wsp, #8]!
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# Test various valid load/store reg combination.
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# especially we shouldn't warn on xzr, although
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# xzr is with the same encoding 31 as sp.
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.macro ldst_pair_wb_2 op, reg1, reg2
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.irp base x3, x6, x25, sp
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\op \reg1, \reg2, [\base], #16
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\op \reg1, \reg2, [\base, #32]!
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\op \reg2, \reg1, [\base], #32
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\op \reg2, \reg1, [\base, #16]!
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.endr
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.endm
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.macro ldst_pair_wb_1 op, reg1, width
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.irp reg2 0, 14, 21, 23, 29
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ldst_pair_wb_2 \op, \reg1, \width\reg2
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.endr
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.endm
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.macro ldst_pair_wb_64 op
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.irp reg1 x2, x15, x16, x27, x30, xzr
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ldst_pair_wb_1 \op, \reg1, x
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.endr
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.endm
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.macro ldst_pair_wb_32 op
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.irp reg1 w1, w12, w16, w19, w30, wzr
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ldst_pair_wb_1 \op, \reg1, w
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.endr
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.endm
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.macro ldst_single_wb_1 op, reg
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.irp base x1, x4, x13, x26, sp
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\op \reg, [\base], #16
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.endr
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.endm
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.macro ldst_single_wb_32 op
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.irp reg w0, w3, w12, w21, w28, w30, wzr
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ldst_single_wb_1 \op, \reg
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.endr
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.endm
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.macro ldst_single_wb_64 op
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.irp reg x2, x5, x17, x23, x24, x30, xzr
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ldst_single_wb_1 \op, \reg
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.endr
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.endm
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ldst_pair_wb_32 stp
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ldst_pair_wb_64 stp
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ldst_pair_wb_32 ldp
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ldst_pair_wb_64 ldp
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ldst_pair_wb_64 ldpsw
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ldst_single_wb_32 str
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ldst_single_wb_64 str
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ldst_single_wb_32 strb
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ldst_single_wb_32 strh
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ldst_single_wb_32 ldr
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ldst_single_wb_64 ldr
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ldst_single_wb_32 ldrb
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ldst_single_wb_32 ldrh
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ldst_single_wb_32 ldrsb
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ldst_single_wb_64 ldrsb
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ldst_single_wb_32 ldrsh
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ldst_single_wb_64 ldrsh
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ldst_single_wb_64 ldrsw
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