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Fix 68HC11 SPI simulator

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This commit is contained in:
Stephane Carrez 2000-09-05 20:49:46 +00:00
parent 188ac6625b
commit 4d72d17a49
2 changed files with 38 additions and 8 deletions
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8
sim/m68hc11/ChangeLog
View File

@ -1,3 +1,11 @@
2000-09-06 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* dv-m68hc11spi.c (m68hc11spi_io_read_buffer): Clear the interrupts.
(m68hc11spi_io_write_buffer): Likewise and fix the spi frame.
(m68hc11spi_info): Clarify the status report
of the SPI when a byte is being sent.
(m68hc11spi_clock): Fix the spi send frame.
2000-08-11 Stephane Carrez <Stephane.Carrez@worldnet.fr>
* sim-main.h (m68hc11_map_level): Define level of address mappings.

38
sim/m68hc11/dv-m68hc11spi.c
View File

@ -229,8 +229,9 @@ set_bit_port (struct hw *me, sim_cpu *cpu, int port, int mask, int value)
*/
#define SPI_START_BIT 0
#define SPI_MIDDLE_BIT 1
#define SPI_START_BYTE 0
#define SPI_START_BIT 1
#define SPI_MIDDLE_BIT 2
void
m68hc11spi_clock (struct hw *me, void *data)
@ -260,15 +261,27 @@ m68hc11spi_clock (struct hw *me, void *data)
controller->tx_bit--;
controller->mode = SPI_MIDDLE_BIT;
}
else
else if (controller->mode == SPI_MIDDLE_BIT)
{
controller->mode = SPI_START_BIT;
}
/* Change the SPI clock at each event on bit 4 of port D. */
controller->clk_pin = ~controller->clk_pin;
set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
if (controller->mode == SPI_START_BYTE)
{
/* Start a new SPI transfer. */
/* TBD: clear SS output. */
controller->mode = SPI_START_BIT;
controller->tx_bit = 7;
set_bit_port (me, cpu, M6811_PORTD, (1 << 4), ~controller->clk_pin);
}
else
{
/* Change the SPI clock at each event on bit 4 of port D. */
controller->clk_pin = ~controller->clk_pin;
set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
}
/* Transmit is now complete for this byte. */
if (controller->mode == SPI_START_BIT && controller->tx_bit < 0)
{
@ -339,6 +352,8 @@ m68hc11spi_info (struct hw *me)
{
signed64 t;
sim_io_printf (sd, " SPI has %d bits to send\n",
controller->tx_bit + 1);
t = hw_event_remain_time (me, controller->spi_event);
sim_io_printf (sd, " SPI operation finished in %ld cycles\n",
(long) t);
@ -389,6 +404,7 @@ m68hc11spi_io_read_buffer (struct hw *me,
{
cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
controller->rx_clear_scsr = 0;
interrupts_update_pending (&cpu->cpu_interrupts);
}
val = controller->rx_char;
break;
@ -466,6 +482,13 @@ m68hc11spi_io_write_buffer (struct hw *me,
return 0;
}
if (controller->rx_clear_scsr)
{
cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
controller->rx_clear_scsr = 0;
interrupts_update_pending (&cpu->cpu_interrupts);
}
/* If transfer is taking place, a write to SPDR
generates a collision. */
if (controller->spi_event)
@ -479,8 +502,7 @@ m68hc11spi_io_write_buffer (struct hw *me,
/* Prepare to send a byte. */
controller->tx_char = val;
controller->tx_bit = 7;
controller->mode = 0;
controller->mode = SPI_START_BYTE;
/* Toggle clock pin internal value when CPHA is 0 so that
it will really change in the middle of a bit. */