Fix 68HC11 SPI simulator
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188ac6625b
commit
4d72d17a49
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@ -1,3 +1,11 @@
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2000-09-06 Stephane Carrez <Stephane.Carrez@worldnet.fr>
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* dv-m68hc11spi.c (m68hc11spi_io_read_buffer): Clear the interrupts.
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(m68hc11spi_io_write_buffer): Likewise and fix the spi frame.
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(m68hc11spi_info): Clarify the status report
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of the SPI when a byte is being sent.
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(m68hc11spi_clock): Fix the spi send frame.
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2000-08-11 Stephane Carrez <Stephane.Carrez@worldnet.fr>
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2000-08-11 Stephane Carrez <Stephane.Carrez@worldnet.fr>
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* sim-main.h (m68hc11_map_level): Define level of address mappings.
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* sim-main.h (m68hc11_map_level): Define level of address mappings.
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@ -229,8 +229,9 @@ set_bit_port (struct hw *me, sim_cpu *cpu, int port, int mask, int value)
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*/
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*/
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#define SPI_START_BIT 0
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#define SPI_START_BYTE 0
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#define SPI_MIDDLE_BIT 1
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#define SPI_START_BIT 1
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#define SPI_MIDDLE_BIT 2
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void
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void
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m68hc11spi_clock (struct hw *me, void *data)
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m68hc11spi_clock (struct hw *me, void *data)
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@ -260,14 +261,26 @@ m68hc11spi_clock (struct hw *me, void *data)
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controller->tx_bit--;
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controller->tx_bit--;
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controller->mode = SPI_MIDDLE_BIT;
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controller->mode = SPI_MIDDLE_BIT;
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}
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}
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else
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else if (controller->mode == SPI_MIDDLE_BIT)
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{
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{
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controller->mode = SPI_START_BIT;
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controller->mode = SPI_START_BIT;
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}
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}
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if (controller->mode == SPI_START_BYTE)
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{
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/* Start a new SPI transfer. */
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/* TBD: clear SS output. */
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controller->mode = SPI_START_BIT;
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controller->tx_bit = 7;
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set_bit_port (me, cpu, M6811_PORTD, (1 << 4), ~controller->clk_pin);
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}
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else
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{
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/* Change the SPI clock at each event on bit 4 of port D. */
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/* Change the SPI clock at each event on bit 4 of port D. */
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controller->clk_pin = ~controller->clk_pin;
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controller->clk_pin = ~controller->clk_pin;
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set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
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set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
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}
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/* Transmit is now complete for this byte. */
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/* Transmit is now complete for this byte. */
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if (controller->mode == SPI_START_BIT && controller->tx_bit < 0)
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if (controller->mode == SPI_START_BIT && controller->tx_bit < 0)
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@ -339,6 +352,8 @@ m68hc11spi_info (struct hw *me)
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{
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{
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signed64 t;
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signed64 t;
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sim_io_printf (sd, " SPI has %d bits to send\n",
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controller->tx_bit + 1);
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t = hw_event_remain_time (me, controller->spi_event);
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t = hw_event_remain_time (me, controller->spi_event);
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sim_io_printf (sd, " SPI operation finished in %ld cycles\n",
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sim_io_printf (sd, " SPI operation finished in %ld cycles\n",
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(long) t);
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(long) t);
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@ -389,6 +404,7 @@ m68hc11spi_io_read_buffer (struct hw *me,
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{
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{
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cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
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cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
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controller->rx_clear_scsr = 0;
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controller->rx_clear_scsr = 0;
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interrupts_update_pending (&cpu->cpu_interrupts);
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}
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}
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val = controller->rx_char;
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val = controller->rx_char;
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break;
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break;
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@ -466,6 +482,13 @@ m68hc11spi_io_write_buffer (struct hw *me,
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return 0;
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return 0;
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}
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}
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if (controller->rx_clear_scsr)
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{
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cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
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controller->rx_clear_scsr = 0;
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interrupts_update_pending (&cpu->cpu_interrupts);
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}
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/* If transfer is taking place, a write to SPDR
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/* If transfer is taking place, a write to SPDR
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generates a collision. */
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generates a collision. */
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if (controller->spi_event)
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if (controller->spi_event)
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@ -479,8 +502,7 @@ m68hc11spi_io_write_buffer (struct hw *me,
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/* Prepare to send a byte. */
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/* Prepare to send a byte. */
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controller->tx_char = val;
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controller->tx_char = val;
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controller->tx_bit = 7;
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controller->mode = SPI_START_BYTE;
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controller->mode = 0;
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/* Toggle clock pin internal value when CPHA is 0 so that
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/* Toggle clock pin internal value when CPHA is 0 so that
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it will really change in the middle of a bit. */
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it will really change in the middle of a bit. */
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