This file was not removed last time. Why??
This commit is contained in:
Ian Lance Taylor
parent
918692a5cc
commit
4e2e8744c5
@ -1,656 +0,0 @@
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/*
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* @OSF_COPYRIGHT@
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*/
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/*
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* HISTORY
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* $Log$
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* Revision 1.1 1993/02/08 19:20:26 raeburn
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* from Ralph Campbell's work
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*
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* Revision 1.10.1.2 1992/02/05 21:37:06 kmk
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* Defined the M_LA_AB enumeral in support of the "la t,A(b)"
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* instruction.
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*
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* Eliminated the abbreviated patterns employing the v, w, r,
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* V, and W specifiers. The meaning of these specifiers has been
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* changed to represent an optional register in a single pattern.
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*
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* Revision 1.10 1991/05/22 15:50:46 devrcs
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* Remove unnecessary macros. No longer need a special macro to do 32-bit
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* operands for instructions that specify 16-bit immediates.
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* Modify the way delays are done. Missing some coprocessor instruction delay slots.
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* [91/05/07 09:34:07 duthie]
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*
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* Bob Setzer fixes + mtcN opcode table fixes
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* [91/03/06 14:37:06 boot]
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*
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* Merged changes from Bob Setzer.
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* [90/11/14 16:02:22 boot]
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*
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* Fixed several problems including bad code generated for the slt,sltu,
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* bal, bgezal and bltzal instructions. Also the delay problem with the
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* mfhi and mflo instructions.
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* [90/10/11 16:42:42 setzer]
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*
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* Revision 1.7 90/10/07 21:01:04 devrcs
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* fixed bug 1231 l.d Illegal operands.
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* Also implemented similar missing macros.
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* [90/10/02 12:38:56 setzer]
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*
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* Fixed several bugs including 855 (plumhall ansi test)
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* and 708 (the alignment problem). Also implemented many
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* previously unimplemented macro instructions.
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* [90/09/27 13:41:34 setzer]
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*
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* Revision 1.6 90/09/23 16:46:24 devrcs
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* Updated flags mainly so a nop would be inserted after the ctc1 instruction.
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* [90/09/12 17:08:41 setzer]
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*
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* Fixed register ordering of xori instruction. Extended all cpu
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* instruction masks to include MBZ fields.
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* [90/09/09 07:40:01 gm]
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*
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* Fixed floating point bugs.
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* [90/09/04 15:13:55 setzer]
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*
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* Revision 1.5 90/08/09 14:31:26 devrcs
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* Works Well.
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* [90/08/03 13:03:04 setzer]
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*
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* Revision 1.4 90/07/06 00:31:56 devrcs
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* Empty submission: clean up any loose ends
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* [90/06/29 20:45:43 kim]
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*
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* $EndLog$
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*/
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/*
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* mips-opcode.h
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*
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*/
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#if !defined(__STDC__) && !defined(const)
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#define const
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#endif
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#define INSN_WRITE_GPR_D 0x00000001
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#define INSN_WRITE_GPR_S 0x00000002
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#define INSN_WRITE_GPR_T 0x00000004
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#define INSN_WRITE_GPR_31 0x00000008
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#define INSN_WRITE_FPR_D 0x00000010
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#define INSN_WRITE_FPR_S 0x00000020
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#define INSN_WRITE_FPR_T 0x00000040
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#define INSN_READ_GPR_D 0x00000080
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#define INSN_READ_GPR_S 0x00000100
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#define INSN_READ_GPR_T 0x00000200
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#define INSN_READ_GPR_31 0x00000400
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#define INSN_READ_FPR_D 0x00000800
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#define INSN_READ_FPR_S 0x00001000
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#define INSN_READ_FPR_T 0x00002000
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#define INSN_TRAP 0x00004000
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#define INSN_COND_CODE 0x00008000
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#define INSN_TLB 0x00010000
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#define INSN_RFE 0x00020000
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#define INSN_COP 0x00040000
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#define INSN_LOAD_DELAY 0x00080000
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#define INSN_UNCOND_BRANCH_DELAY 0x00100000
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#define INSN_COND_BRANCH_DELAY 0x00200000
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#define INSN_COPROC_DELAY 0x00400000
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#define INSN_STORE_DELAY 0x00800000
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#define INSN_EXTRA_DELAY 0x01000000
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#define INSN_R4000 0x80000000
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#define INSN_MACRO 0xffffffff
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/*
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* This is a list of macro expanded instructions.
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*
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* _I appended means immeadiate
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* _A appended means address
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*/
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enum {
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M_ABS,
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M_ABSU,
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M_ADD_I,
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M_ADDU_I,
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M_AND_I,
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M_BEQ_I,
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M_BGE,
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M_BGE_I,
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M_BGEU,
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M_BGEU_I,
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M_BGT,
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M_BGT_I,
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M_BGTU,
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M_BGTU_I,
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M_BLE,
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M_BLE_I,
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M_BLEU,
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M_BLEU_I,
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M_BLT,
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M_BLT_I,
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M_BLTU,
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M_BLTU_I,
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M_BNE_I,
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M_DIV_3,
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M_DIV_3I,
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M_DIVU_3,
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M_DIVU_3I,
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M_L_D,
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M_L_DOB,
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M_L_DAB,
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M_LA,
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M_LA_AB,
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M_LB_A,
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M_LB_AB,
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M_LBU_A,
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M_LBU_AB,
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M_LD_A,
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M_LD_OB,
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M_LD_AB,
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M_LH_A,
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M_LH_AB,
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M_LHU_A,
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M_LHU_AB,
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M_LI,
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M_LI_D,
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M_LI_DD,
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M_LS_A,
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M_LW_A,
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M_LW_AB,
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M_LWC0_A,
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M_LWC0_AB,
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M_LWC1_A,
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M_LWC1_AB,
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M_LWC2_A,
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M_LWC2_AB,
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M_LWC3_A,
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M_LWC3_AB,
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M_LWL_A,
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M_LWL_AB,
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M_LWR_A,
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M_LWR_AB,
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M_MUL,
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M_MUL_I,
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M_MULO,
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M_MULO_I,
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M_MULOU,
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M_MULOU_I,
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M_NOR_I,
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M_OR_I,
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M_REM_3,
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M_REM_3I,
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M_REMU_3,
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M_REMU_3I,
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M_ROL,
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M_ROL_I,
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M_ROR,
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M_ROR_I,
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M_S_DA,
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M_S_DOB,
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M_S_DAB,
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M_S_S,
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M_SD_A,
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M_SD_OB,
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M_SD_AB,
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M_SEQ,
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M_SEQ_I,
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M_SGE,
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M_SGE_I,
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M_SGEU,
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M_SGEU_I,
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M_SGT,
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M_SGT_I,
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M_SGTU,
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M_SGTU_I,
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M_SLE,
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M_SLE_I,
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M_SLEU,
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M_SLEU_I,
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M_SLT_I,
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M_SLTU_I,
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M_SNE,
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M_SNE_I,
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M_SB_A,
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M_SB_AB,
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M_SH_A,
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M_SH_AB,
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M_SW_A,
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M_SW_AB,
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M_SWC0_A,
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M_SWC0_AB,
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M_SWC1_A,
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M_SWC1_AB,
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M_SWC2_A,
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M_SWC2_AB,
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M_SWC3_A,
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M_SWC3_AB,
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M_SWL_A,
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M_SWL_AB,
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M_SWR_A,
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M_SWR_AB,
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M_SUB_I,
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M_SUBU_I,
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M_TRUNCWD,
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M_TRUNCWS,
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M_ULH,
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M_ULH_A,
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M_ULHU,
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M_ULHU_A,
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M_ULW,
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M_ULW_A,
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M_USH,
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M_USH_A,
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M_USW,
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M_USW_A,
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M_XOR_I
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};
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/*
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Kinds of operands:
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a - 26 bit address
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b - base register
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c - break code
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d - destination register
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i - 16 bit unsigned immediate
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j - 16 bit signed immediate
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o - 16 bit offset
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p - pc relative offset
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s - source register
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t - target register
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r - both source and target register
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v - both source and destination register
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w - both target and destination register
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u - upper 16 bits
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x - temporary register (usually $at).
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D - floating point destination register
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S - floating point source register
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T - floating point target register
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V - both floating source and destination register
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W - both floating target and destination register
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I - 32 bit immediate (built in macro instrs only)
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F - Floating point constant (li.d only).
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< - Shift constant
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*/
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/* Short hand so the lines aren't too long. */
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/* ANY_DELAY is used in mips.c to determine if we need to add
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nop's in the delay slots */
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/* load delays */
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#define LDD INSN_LOAD_DELAY
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/* branch delays */
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#define BD INSN_UNCOND_BRANCH_DELAY|INSN_COND_BRANCH_DELAY
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/* coprocessor delays */
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#define COD INSN_COPROC_DELAY
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/* instructions that require and extra delay */
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#define EXD INSN_EXTRA_DELAY
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#define ANY_DELAY (LDD|BD|COD|EXD)
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/* None of these are ever referenced in the code??? */
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/* There is really no need to distinguish between ALL these
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different types of load delays ...USE THE ABOVE MACROS INSTEAD*/
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#define WR_d INSN_WRITE_GPR_D
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#define WR_s INSN_WRITE_GPR_S
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#define WR_t INSN_WRITE_GPR_T
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#define WR_31 INSN_WRITE_GPR_31
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#define WR_D INSN_WRITE_FPR_D
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#define WR_S INSN_WRITE_FPR_S
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#define WR_T INSN_WRITE_FPR_T
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#define RD_d INSN_READ_GPR_D
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#define RD_s INSN_READ_GPR_S
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#define RD_b INSN_READ_GPR_S
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#define RD_t INSN_READ_GPR_T
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#define ST_t INSN_READ_GPR_T
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#define RD_31 INSN_READ_GPR_31
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#define RD_D INSN_READ_FPR_D
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#define RD_S INSN_READ_FPR_S
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#define RD_T INSN_READ_FPR_T
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#define CC (INSN_COND_CODE|INSN_LOAD_DELAY)
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#define ST_T INSN_READ_FPR_T
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#define ST_C0 INSN_COP
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#define ST_C1 INSN_READ_FPR_T
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#define ST_C2 INSN_COP
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#define ST_C3 INSN_COP
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#define RD_C0 INSN_COP
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#define RD_C1 INSN_READ_FPR_T
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#define RD_C2 INSN_COP
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#define RD_C3 INSN_COP
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#define WR_C0 INSN_COP
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#define WR_C1 INSN_READ_FPR_T
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#define WR_C2 INSN_COP
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#define WR_C3 INSN_COP
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/*
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The order of overloaded instructions matters.
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Label arguments and register arguments look
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the same. Instructions that can have either for arguments
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must apear in the correct order in this table for the assembler
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to pick the right one. In other words, entries with immediate
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operands must apear after the same instruction with registers.
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Many instructions are short hand for other instructions
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(i.e., The jal <register> instruction is short for jalr <register>).
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*/
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static const struct mips_opcode mips_opcodes[] = {
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{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO },
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{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S },
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{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S },
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{"absu", "d,s", 0, (int) M_ABSU, INSN_MACRO },
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{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t },
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{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO },
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{"add.s", "D,V,T", 0x46000000, 0xfff0003f, WR_D|RD_S|RD_T },
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{"add.d", "D,V,T", 0x46200000, 0xfff0003f, WR_D|RD_S|RD_T },
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{"addi", "t,r,j", 0x20000000, 0xfe000000, WR_t|RD_s },
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{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s },
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{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t },
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{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO },
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{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t },
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{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO },
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{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s },
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{"b", "p", 0x10000000, 0xfc000000, BD|RD_s|RD_t }, /* beq 0,0 */
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{"bal", "p", 0x04110000, 0xfc1f0000, BD|RD_s }, /* bgezal 0 */
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{"bc0f", "p", 0x41000000, 0xffff0000, BD },
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{"bc1f", "p", 0x45000000, 0xffff0000, BD },
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{"bc2f", "p", 0x49000000, 0xffff0000, BD },
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{"bc3f", "p", 0x4d000000, 0xffff0000, BD },
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{"bc0t", "p", 0x41010000, 0xffff0000, BD },
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{"bc1t", "p", 0x45010000, 0xffff0000, BD },
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{"bc2t", "p", 0x49010000, 0xffff0000, BD },
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{"bc3t", "p", 0x4d010000, 0xffff0000, BD },
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{"beq", "s,t,p", 0x10000000, 0xfc000000, BD|RD_s|RD_t },
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{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO },
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{"beqz", "s,p", 0x10000000, 0xfc000000, BD|RD_s|RD_t },
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{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO },
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{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO },
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{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO },
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{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO },
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{"bgez", "s,p", 0x04010000, 0xfc0f0000, BD|RD_s },
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{"bgezal", "s,p", 0x04110000, 0xfc1f0000, BD|RD_s },
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{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO },
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{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO },
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{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO },
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{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO },
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{"bgtz", "s,p", 0x1c000000, 0xfc000000, BD|RD_s },
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{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO },
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{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO },
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{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO },
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{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO },
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{"blez", "s,p", 0x18000000, 0xfc000000, BD|RD_s },
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{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO },
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{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO },
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{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO },
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{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO },
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{"bltz", "s,p", 0x04000000, 0xfc0f0000, BD|RD_s },
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{"bltzal", "s,p", 0x04100000, 0xfc1f0000, BD|RD_s },
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{"bne", "s,t,p", 0x14000000, 0xfc000000, BD|RD_s|RD_t },
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{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO },
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{"bnez", "s,p", 0x14000000, 0xfc000000, BD|RD_s|RD_t },
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{"break", "", 0x0000000d, 0xffffffff, INSN_TRAP },
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{"break", "c", 0x0000000d, 0xffffffff, INSN_TRAP },
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{"c.f.d", "S,T", 0x46200030, 0xfff003ff, RD_S|RD_T|CC },
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{"c.f.s", "S,T", 0x46000030, 0xfff003ff, RD_S|RD_T|CC },
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{"c.un.d", "S,T", 0x46200031, 0xfff003ff, RD_S|RD_T|CC },
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{"c.un.s", "S,T", 0x46000031, 0xfff003ff, RD_S|RD_T|CC },
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{"c.eq.d", "S,T", 0x46200032, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.eq.s", "S,T", 0x46000032, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ueq.d", "S,T", 0x46200033, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ueq.s", "S,T", 0x46000033, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.olt.d", "S,T", 0x46200034, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.olt.s", "S,T", 0x46000034, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ult.d", "S,T", 0x46200035, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ult.s", "S,T", 0x46000035, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ole.d", "S,T", 0x46200036, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ole.s", "S,T", 0x46000036, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ule.d", "S,T", 0x46200037, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ule.s", "S,T", 0x46000037, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.sf.d", "S,T", 0x46200038, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.sf.s", "S,T", 0x46000038, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ngle.d","S,T", 0x46200039, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ngle.s","S,T", 0x46000039, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.seq.d", "S,T", 0x4620003a, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.seq.s", "S,T", 0x4600003a, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ngl.d", "S,T", 0x4620003b, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ngl.s", "S,T", 0x4600003b, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.lt.d", "S,T", 0x4620003c, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.lt.s", "S,T", 0x4600003c, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.nge.d", "S,T", 0x4620003d, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.nge.s", "S,T", 0x4600003d, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.le.d", "S,T", 0x4620003e, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.le.s", "S,T", 0x4600003e, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ngt.d", "S,T", 0x4620003f, 0xfff003ff, RD_S|RD_T|CC },
|
||||
{"c.ngt.s", "S,T", 0x4600003f, 0xfff003ff, RD_S|RD_T|CC },
|
||||
#if 0
|
||||
/* these are not very safe to use, no bounds checking. */
|
||||
{"c0", "I", 0x42000000, 0xfff00000, 0 },
|
||||
{"c1", "I", 0x46000000, 0xfff00000, 0 },
|
||||
{"c2", "I", 0x4a000000, 0xfff00000, 0 },
|
||||
{"c3", "I", 0x4e000000, 0xfff00000, 0 },
|
||||
#endif
|
||||
{"cfc0", "t,d", 0x40400000, 0xfff00000, COD|RD_d },
|
||||
{"cfc1", "t,d", 0x44400000, 0xfff00000, COD|RD_S },
|
||||
{"cfc1", "t,S", 0x44400000, 0xfff00000, COD|RD_S },
|
||||
{"cfc2", "t,d", 0x48400000, 0xfff00000, COD|RD_d },
|
||||
{"cfc3", "t,d", 0x4c400000, 0xfff00000, COD|RD_d },
|
||||
{"ctc0", "t,d", 0x40c00000, 0xfff00000, COD|RD_t|RD_d },
|
||||
{"ctc1", "t,d", 0x44c00000, 0xfff00000, COD|RD_t },
|
||||
{"ctc1", "t,S", 0x44c00000, 0xfff00000, COD|RD_t },
|
||||
{"ctc2", "t,d", 0x48c00000, 0xfff00000, COD|RD_t|RD_d },
|
||||
{"ctc3", "t,d", 0x4cc00000, 0xfff00000, COD|RD_t|RD_d },
|
||||
{"cvt.d.s", "D,S", 0x46000021, 0xfff0003f, WR_D|RD_S },
|
||||
{"cvt.d.w", "D,S", 0x46800021, 0xfff0003f, WR_D|RD_S },
|
||||
{"cvt.s.d", "D,S", 0x46200020, 0xfff0003f, WR_D|RD_S },
|
||||
{"cvt.s.w", "D,S", 0x46800020, 0xfff0003f, WR_D|RD_S },
|
||||
{"cvt.w.d", "D,S", 0x46200024, 0xfff0003f, WR_D|RD_S },
|
||||
{"cvt.w.s", "D,S", 0x46000024, 0xfff0003f, WR_D|RD_S },
|
||||
{"div", "s,t", 0x0000001a, 0xfc00003f, RD_s|RD_t|EXD },
|
||||
{"div", "d,s,t", 0, (int) M_DIV_3, INSN_MACRO },
|
||||
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO },
|
||||
{"div.d", "D,V,T", 0x46200003, 0xfff0003f, WR_D|RD_S|RD_T },
|
||||
{"div.s", "D,V,T", 0x46000003, 0xfff0003f, WR_D|RD_S|RD_T },
|
||||
{"divu", "s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|EXD },
|
||||
{"divu", "d,s,t", 0, (int) M_DIVU_3, INSN_MACRO },
|
||||
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO },
|
||||
{"j", "s", 0x00000008, 0xfc1fffff, BD|RD_s },
|
||||
{"j", "a", 0x08000000, 0xfc000000, BD },
|
||||
{"jal", "d,s", 0x00000009, 0xfc1f07ff, BD|RD_s|WR_d },/* jalr */
|
||||
{"jal", "s", 0x0000f809, 0xfc00ff3f, BD|RD_s|WR_d },/* jalr $ra */
|
||||
{"jal", "a", 0x0c000000, 0xfc000000, BD|WR_31 },
|
||||
{"jalr", "s", 0x0000f809, 0xfc00f83f, BD|RD_s|WR_31 },
|
||||
{"jalr", "d,s", 0x00000009, 0xfc1f07ff, BD|RD_s|WR_d },
|
||||
{"jr", "s", 0x00000008, 0xfc1fffff, BD|RD_s },
|
||||
{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO },
|
||||
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO },
|
||||
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, COD|RD_b }, /* lwc1 */
|
||||
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
|
||||
{"la", "t,A", 0, (int) M_LA, INSN_MACRO },
|
||||
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO },
|
||||
{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b },
|
||||
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO },
|
||||
{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b },
|
||||
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO },
|
||||
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO },
|
||||
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO },
|
||||
{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b },
|
||||
{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO },
|
||||
{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b },
|
||||
{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO },
|
||||
{"li", "t,I", 0, (int) M_LI, INSN_MACRO },
|
||||
{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO },
|
||||
{"li.d", "S,F", 0, (int) M_LI_DD, INSN_MACRO },
|
||||
{"lui", "t,u", 0x3c000000, 0xfff00000, WR_t },
|
||||
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b },
|
||||
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO },
|
||||
{"lwc0", "t,o(b)", 0xc0000000, 0xfc000000, COD|RD_b },
|
||||
{"lwc0", "t,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO },
|
||||
{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, COD|RD_b },
|
||||
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
|
||||
{"lwc2", "t,o(b)", 0xc8000000, 0xfc000000, COD|RD_b },
|
||||
{"lwc2", "t,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO },
|
||||
{"lwc3", "t,o(b)", 0xcc000000, 0xfc000000, COD|RD_b },
|
||||
{"lwc3", "t,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO },
|
||||
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b },
|
||||
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO },
|
||||
{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b },
|
||||
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO },
|
||||
{"mfc0", "t,d", 0x40000000, 0xfff007ff, COD|WR_t|RD_C0 },
|
||||
{"mfc1", "t,S", 0x44000000, 0xfff007ff, COD|RD_S },
|
||||
{"mfc1", "t,d", 0x44000000, 0xfff007ff, COD|RD_C1 },
|
||||
{"mfc2", "t,d", 0x48000000, 0xfff007ff, COD|WR_t|RD_C2 },
|
||||
{"mfc3", "t,d", 0x4c000000, 0xfff007ff, COD|WR_t|RD_C3 },
|
||||
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|EXD },
|
||||
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|EXD },
|
||||
{"mov.d", "D,S", 0x46200006, 0xfff0003f, WR_t|RD_S },
|
||||
{"mov.s", "D,S", 0x46000006, 0xfff0003f, WR_t|RD_S },
|
||||
{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s }, /* addu */
|
||||
{"mtc0", "t,d", 0x40800000, 0xfff007ff, COD|RD_t|WR_C0 },
|
||||
{"mtc1", "t,d", 0x44800000, 0xfff007ff, COD|RD_t|WR_C1 },
|
||||
{"mtc1", "t,S", 0x44800000, 0xfff007ff, COD|RD_t },
|
||||
{"mtc2", "t,d", 0x48800000, 0xfff007ff, COD|RD_t|WR_C2 },
|
||||
{"mtc3", "t,d", 0x4c800000, 0xfff007ff, COD|RD_t|WR_C3 },
|
||||
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|EXD },
|
||||
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|EXD },
|
||||
{"mul.d", "D,V,T", 0x46200002, 0xfff0003f, WR_D|RD_S|RD_T },
|
||||
{"mul.s", "D,V,T", 0x46000002, 0xfff0003f, WR_D|RD_S|RD_T },
|
||||
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO },
|
||||
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO },
|
||||
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO },
|
||||
{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO },
|
||||
{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO },
|
||||
{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO },
|
||||
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|EXD },
|
||||
{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|EXD },
|
||||
{"neg", "d,w", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t }, /* sub 0 */
|
||||
{"negu", "d,w", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t }, /* subu 0 */
|
||||
{"neg.d", "D,V", 0x46200007, 0xfff0003f, WR_D|RD_S },
|
||||
{"neg.s", "D,V", 0x46000007, 0xfff0003f, WR_D|RD_S },
|
||||
{"nop", "", 0x00000000, 0xffffffff, 0 },
|
||||
{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t },
|
||||
{"nor", "d,v,I", 0, (int) M_NOR_I, INSN_MACRO },
|
||||
{"not", "d,v", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t }, /* nor d,s,zero */
|
||||
{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t },
|
||||
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO },
|
||||
{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s },
|
||||
{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO },
|
||||
{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO },
|
||||
{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO },
|
||||
{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO },
|
||||
{"rfe", "", 0x42000010, 0xffffffff, INSN_RFE },
|
||||
{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO },
|
||||
{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO },
|
||||
{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO },
|
||||
{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO },
|
||||
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO },
|
||||
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO },
|
||||
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, ST_T|RD_b }, /* swc1 */
|
||||
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
|
||||
{"sb", "t,o(b)", 0xa0000000, 0xfc000000, ST_t|RD_b },
|
||||
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO },
|
||||
{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO },
|
||||
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO },
|
||||
{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO },
|
||||
{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO },
|
||||
{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO },
|
||||
{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO },
|
||||
{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO },
|
||||
{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO },
|
||||
{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO },
|
||||
{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO },
|
||||
{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO },
|
||||
{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO },
|
||||
{"sh", "t,o(b)", 0xa4000000, 0xfc000000, ST_t|RD_b },
|
||||
{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO },
|
||||
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO },
|
||||
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO },
|
||||
{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO },
|
||||
{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO },
|
||||
{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s }, /* sllv */
|
||||
{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t },
|
||||
{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s },
|
||||
{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t },
|
||||
{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO },
|
||||
{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s },
|
||||
{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s },
|
||||
{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t },
|
||||
{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO },
|
||||
{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO },
|
||||
{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO },
|
||||
{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s }, /* srav */
|
||||
{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_t|RD_d },
|
||||
{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s },
|
||||
{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s }, /* srlv */
|
||||
{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t },
|
||||
{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s },
|
||||
{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t },
|
||||
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO },
|
||||
{"sub.d", "D,V,T", 0x46200001, 0xfff0003f, WR_D|RD_S|RD_T },
|
||||
{"sub.s", "D,V,T", 0x46000001, 0xfff0003f, WR_D|RD_S|RD_T },
|
||||
{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t },
|
||||
{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO },
|
||||
{"sw", "t,o(b)", 0xac000000, 0xfc000000, ST_t|RD_b },
|
||||
{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO },
|
||||
{"swc0", "t,o(b)", 0xe0000000, 0xfc000000, ST_C0|RD_b },
|
||||
{"swc0", "t,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO },
|
||||
{"swc1", "t,o(b)", 0xe4000000, 0xfc000000, ST_C1|RD_b },
|
||||
{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, ST_T|RD_b },
|
||||
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
|
||||
{"swc2", "t,o(b)", 0xe8000000, 0xfc000000, ST_C2|RD_b },
|
||||
{"swc2", "t,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO },
|
||||
{"swc3", "t,o(b)", 0xec000000, 0xfc000000, ST_C3|RD_b },
|
||||
{"swc3", "t,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO },
|
||||
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, ST_t|RD_b },
|
||||
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO },
|
||||
{"swr", "t,o(b)", 0xb8000000, 0xfc000000, ST_t|RD_b },
|
||||
{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO },
|
||||
{"syscall", "", 0x0000000c, 0xffffffff, INSN_TRAP },
|
||||
{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB },
|
||||
{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB },
|
||||
{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB },
|
||||
{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB },
|
||||
{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO },
|
||||
{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO },
|
||||
{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO },
|
||||
{"ulh", "t,A", 0, (int) M_ULH_A, INSN_MACRO },
|
||||
{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO },
|
||||
{"ulhu", "t,A", 0, (int) M_ULHU_A, INSN_MACRO },
|
||||
{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO },
|
||||
{"ulw", "t,A", 0, (int) M_ULW_A, INSN_MACRO },
|
||||
{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO },
|
||||
{"ush", "t,A", 0, (int) M_USH_A, INSN_MACRO },
|
||||
{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO },
|
||||
{"usw", "t,A", 0, (int) M_USW_A, INSN_MACRO },
|
||||
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t },
|
||||
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO },
|
||||
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s },
|
||||
};
|
||||
|
||||
#define NUMOPCODES (sizeof(mips_opcodes)/sizeof(*mips_opcodes))
|
||||
|
||||
#if 0
|
||||
int
|
||||
main(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < NUMOPCODES; ++i) {
|
||||
if ((mips_opcodes[i].mask & mips_opcodes[i].match) !=
|
||||
mips_opcodes[i].match) {
|
||||
printf("error i = %d, opcode= %s\n", i, mips_opcodes[i].name);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user