Allow bit-patterns in the immediate field of ARM neon mov instructions.
* config/tc-arm.c (do_neon_mov): When converting an integer immediate into a floating point value, check that the conversion is valid. Also warn if the immediate is valid as both a floating point value and a bit pattern. * testsuite/gas/arm/vfp-mov-enc.s: Add instructions that use floating point bit patterns. * testsuite/gas/arm/vfp-mov-enc.d: Add regexps for the disassembly of the new insns.
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@ -1,3 +1,14 @@
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2018-07-13 Nick Clifton <nickc@redhat.com>
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* config/tc-arm.c (do_neon_mov): When converting an integer
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immediate into a floating point value, check that the conversion
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is valid. Also warn if the immediate is valid as both a floating
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point value and a bit pattern.
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* testsuite/gas/arm/vfp-mov-enc.s: Add instructions that use
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floating point bit patterns.
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* testsuite/gas/arm/vfp-mov-enc.d: Add regexps for the disassembly
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of the new insns.
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2018-07-12 Sudakshina Das <sudi.das@arm.com>
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* testsuite/gas/aarch64/system.s: Add test for ssbb
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@ -16692,13 +16692,24 @@ do_neon_mov (void)
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case NS_HI:
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case NS_FI: /* case 10 (fconsts). */
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ldconst = "fconsts";
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encode_fconstd:
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encode_fconstd:
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if (!inst.operands[1].immisfloat)
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{
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unsigned new_imm;
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/* Immediate has to fit in 8 bits so float is enough. */
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float imm = (float)inst.operands[1].imm;
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memcpy (&inst.operands[1].imm, &imm, sizeof (float));
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inst.operands[1].immisfloat = 1;
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float imm = (float) inst.operands[1].imm;
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memcpy (&new_imm, &imm, sizeof (float));
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/* But the assembly may have been written to provide an integer
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bit pattern that equates to a float, so check that the
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conversion has worked. */
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if (is_quarter_float (new_imm))
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{
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if (is_quarter_float (inst.operands[1].imm))
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as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
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inst.operands[1].imm = new_imm;
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inst.operands[1].immisfloat = 1;
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}
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}
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if (is_quarter_float (inst.operands[1].imm))
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@ -11,3 +11,6 @@ Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> 4ef7da00 vmovmi.f32 s27, #112 ; 0x3f800000 1.0
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0[0-9a-f]+ <[^>]+> cebb1b04 vmovgt.f64 d1, #180 ; 0xc1a00000 -20.0
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0[0-9a-f]+ <[^>]+> ceb81b00 vmovgt.f64 d1, #128 ; 0xc0000000 -2.0
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0[0-9a-f]+ <[^>]+> eef0aa00 vmov.f32 s21, #0 ; 0x40000000 2.0
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0[0-9a-f]+ <[^>]+> eef97a07 vmov.f32 s15, #151 ; 0xc0b80000 -5.750
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0[0-9a-f]+ <[^>]+> eefc4a05 vmov.f32 s9, #197 ; 0xbe280000 -0.1640625
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@ -4,3 +4,7 @@ VMOVMI.F32 s27,#1
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VMOVMI.F32 s27,#1.0
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VMOVGT.F64 d1,#-20
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VMOVGT.F64 d1,#-2
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@ Check that integer-encoded floating-point bit-patterns still work
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vmov s21,#0x40000000
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vmov s15,#0xc0b80000
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vmov s9,#0xbe280000
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