2012-08-19 Andrew Pinski <apinski@cavium.com>
* mips-tdep.c (mips32_next_pc): Consolidate calls to itype_op.
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@ -1,3 +1,7 @@
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2012-08-19 Andrew Pinski <apinski@cavium.com>
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* mips-tdep.c (mips32_next_pc): Consolidate calls to itype_op.
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2012-08-19 Keith Seitz <keiths@redhat.com>
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PR c++/14365
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@ -1475,14 +1475,14 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
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unsigned long inst;
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int op;
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inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
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op = itype_op (inst);
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if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch
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instruction. */
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{
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if (itype_op (inst) >> 2 == 5)
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if (op >> 2 == 5)
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/* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
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{
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op = (itype_op (inst) & 0x03);
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switch (op)
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switch (op & 0x03)
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{
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case 0: /* BEQL */
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goto equal_branch;
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@ -1496,18 +1496,18 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
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pc += 4;
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}
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}
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else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
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else if (op == 17 && itype_rs (inst) == 8)
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/* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
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pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1);
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else if (itype_op (inst) == 17 && itype_rs (inst) == 9
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else if (op == 17 && itype_rs (inst) == 9
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&& (itype_rt (inst) & 2) == 0)
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/* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
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pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2);
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else if (itype_op (inst) == 17 && itype_rs (inst) == 10
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else if (op == 17 && itype_rs (inst) == 10
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&& (itype_rt (inst) & 2) == 0)
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/* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
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pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4);
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else if (itype_op (inst) == 29)
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else if (op == 29)
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/* JALX: 011101 */
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/* The new PC will be alternate mode. */
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{
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@ -1524,7 +1524,7 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc)
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{ /* This gets way messy. */
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/* Further subdivide into SPECIAL, REGIMM and other. */
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switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */
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switch (op & 0x07) /* Extract bits 28,27,26. */
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{
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case 0: /* SPECIAL */
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op = rtype_funct (inst);
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