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* v850-dis.c (v850_reg_names): Define.

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(v850_sreg_names, v850_cc_names): Likewise.
        (disassemble): Very rough cut at printing operands (unformatted).
One step at a time.

        * v850-opc.c (BOP_MASK): Fix.
        (v850_opcodes): Fix mask for jarl and jr.
Bugs exposed by disassembler testing.
This commit is contained in:
Jeff Law 1996-08-31 20:56:05 +00:00
parent a0a36aa085
commit 502535cff7
3 changed files with 62 additions and 3 deletions
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7
opcodes/ChangeLog
View File

@ -1,6 +1,13 @@
start-sanitize-v850
Sat Aug 31 01:27:26 1996 Jeffrey A Law (law@cygnus.com)
* v850-dis.c (v850_reg_names): Define.
(v850_sreg_names, v850_cc_names): Likewise.
(disassemble): Very rough cut at printing operands (unformatted).
* v850-opc.c (BOP_MASK): Fix.
(v850_opcodes): Fix mask for jarl and jr.
* v850-dis.c: New file. Skeleton for disassembler support.
* Makefile.in Remove v850 references, they're not needed here
and they weren't being sanitized away.

52
opcodes/v850-dis.c
View File

@ -22,6 +22,23 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "opcode/v850.h"
#include "dis-asm.h"
static const char *const v850_reg_names[] =
{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "ep", "r31" };
static const char *const v850_sreg_names[] =
{ "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
"sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
"sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
"sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31" };
static const char *const v850_cc_names[] =
{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le",
"nv", "nc/nl", "nz", "h", "ns/p", "sa", "lt", "ge",
"le", "gt" };
int
print_insn_v850 (memaddr, info)
bfd_vma memaddr;
@ -51,6 +68,7 @@ disassemble (insn, info)
struct disassemble_info *info;
{
struct v850_opcode *op = (struct v850_opcode *)v850_opcodes;
const struct v850_operand *operand;
int match = 0;
/* If this is a two byte insn, then mask off the high bits. */
if ((insn & 0x0600) != 0x0600)
@ -61,8 +79,42 @@ disassemble (insn, info)
{
if ((op->mask & insn) == op->opcode)
{
const unsigned char *opindex_ptr;
match = 1;
(*info->fprintf_func) (info->stream, "%s\t", op->name);
/* Now print the operands. */
for (opindex_ptr = op->operands; *opindex_ptr != 0; opindex_ptr++)
{
unsigned long value;
operand = &v850_operands[*opindex_ptr];
if (operand->extract)
value = (operand->extract) (insn, 0);
else
value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
if ((operand->flags & V850_OPERAND_SIGNED) != 0)
value = ((signed long)(value << (32 - operand->bits))
>> (32 - operand->bits));
if ((operand->flags & V850_OPERAND_REG) != 0)
(*info->fprintf_func) (info->stream, "%s",
v850_reg_names[value]);
else if ((operand->flags & V850_OPERAND_SRG) != 0)
(*info->fprintf_func) (info->stream, "%s",
v850_sreg_names[value]);
else if ((operand->flags & V850_OPERAND_CC) != 0)
(*info->fprintf_func) (info->stream, "%s",
v850_cc_names[value]);
else if ((operand->flags & V850_OPERAND_EP) != 0)
(*info->fprintf_func) (info->stream, "ep");
else
(*info->fprintf_func) (info->stream, "%d", value);
}
/* All done. */
break;
}
op++;

6
opcodes/v850-opc.c
View File

@ -20,7 +20,7 @@ static long extract_d8_6 PARAMS ((unsigned long, int *));
/* conditional branch opcode */
#define BOP(x) ((0x0b << 7) | (x & 0x0f))
#define BOP_MASK ((0x0b << 7) | 0x0f)
#define BOP_MASK ((0x0f << 7) | 0x0f)
/* one-word opcodes */
#define one(x) ((unsigned int) (x))
@ -247,8 +247,8 @@ const struct v850_opcode v850_opcodes[] = {
{ "bsa", BOP(0xd), BOP_MASK, IF3, 2 },
{ "jmp", one(0x0060), one(0xffe0), { R1}, 2 },
{ "jarl", one(0x0780), one(0xf83f), { D22, R2 }, 4 },
{ "jr", one(0x0780), one(0xffe0), { D22 }, 4 },
{ "jarl", one(0x0780), two(0x07c0,0x0001),{ D22, R2 }, 4 },
{ "jr", one(0x0780), two(0xffc0,0x0001),{ D22 }, 4 },
/* bit manipulation instructions */
{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },