OpenE2K
/
binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Don't handle lret/iret when -mlfence-before-ret=[or|not|shl|yes] since they are invalid in SGX enclaves. 

gas/ChangeLog
	* gas/config/tc-i386.c: Not handle lret/iret.
	* gas/testsuite/gas/i386/lfence-ret-a.d: Adjust testcase.
	* gas/testsuite/gas/i386/lfence-ret-b.d: Ditto.
	* gas/testsuite/gas/i386/lfence-ret-c.d: Ditto.
	* gas/testsuite/gas/i386/lfence-ret-d.d: Ditto.
	* gas/testsuite/gas/i386/lfence-ret.s: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-a.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-b.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-c.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-d.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret-e.d: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret.s: Ditto.
	* gas/testsuite/gas/i386/x86-64-lfence-ret.e: Deleted.
This commit is contained in:
liuhongt 2020-05-09 15:02:50 +08:00
parent 07a78c5956
commit 503648e41e
14 changed files with 22 additions and 182 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
gas/ChangeLog
View File

@ -1,3 +1,19 @@
2020-05-18 Hongtao Liu <hongtao.liu@intel.com>
* config/tc-i386.c: Not handle lret/iret.
* testsuite/gas/i386/lfence-ret-a.d: Adjust testcase.
* testsuite/gas/i386/lfence-ret-b.d: Ditto.
* testsuite/gas/i386/lfence-ret-c.d: Ditto.
* testsuite/gas/i386/lfence-ret-d.d: Ditto.
* testsuite/gas/i386/lfence-ret.s: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret-a.d: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret-b.d: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret-c.d: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret-d.d: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret-e.d: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret.s: Ditto.
* testsuite/gas/i386/x86-64-lfence-ret.e: Deleted.
2020-05-15 Alan Modra <amodra@gmail.com>
Alex Coplan <alex.coplan@arm.com>

20
gas/config/tc-i386.c
View File

@ -4591,13 +4591,10 @@ insert_lfence_before (void)
return;
}
/* Output or/not/shl and lfence before ret/lret/iret. */
/* Output or/not/shl and lfence before near ret. */
if (lfence_before_ret != lfence_before_ret_none
&& (i.tm.base_opcode == 0xc2
|| i.tm.base_opcode == 0xc3
|| i.tm.base_opcode == 0xca
|| i.tm.base_opcode == 0xcb
|| i.tm.base_opcode == 0xcf))
|| i.tm.base_opcode == 0xc3))
{
if (last_insn.kind != last_insn_other
&& last_insn.seg == now_seg)
@ -4608,17 +4605,10 @@ insert_lfence_before (void)
return;
}
/* lret or iret. */
bfd_boolean lret = (i.tm.base_opcode | 0x5) == 0xcf;
bfd_boolean has_rexw = i.prefix[REX_PREFIX] & REX_W;
char prefix = 0x0;
/* Default operand size for far return is 32 bits,
64 bits for near return. */
/* Near ret ingore operand size override under CPU64. */
if ((!lret && flag_code == CODE_64BIT) || has_rexw)
prefix = 0x48;
else if (i.prefix[DATA_PREFIX])
prefix = 0x66;
char prefix = flag_code == CODE_64BIT
? 0x48
: i.prefix[DATA_PREFIX] ? 0x66 : 0x0;
if (lfence_before_ret == lfence_before_ret_not)
{

12
gas/testsuite/gas/i386/lfence-ret-a.d
View File

@ -21,16 +21,4 @@ Disassembly of section .text:
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: c2 1e 00 ret \$0x1e
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 cb lretw
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: cb lret
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: ca 28 00 lret \$0x28
#pass

16
gas/testsuite/gas/i386/lfence-ret-b.d
View File

@ -25,20 +25,4 @@ Disassembly of section .text:
+[a-f0-9]+: f7 14 24 notl \(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: c2 1e 00 ret \$0x1e
+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 cb lretw
+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
+[a-f0-9]+: f7 14 24 notl \(%esp\)
+[a-f0-9]+: f7 14 24 notl \(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: cb lret
+[a-f0-9]+: f7 14 24 notl \(%esp\)
+[a-f0-9]+: f7 14 24 notl \(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: ca 28 00 lret \$0x28
#pass

14
gas/testsuite/gas/i386/lfence-ret-c.d
View File

@ -1,7 +1,7 @@
#source: lfence-ret.s
#as: -mlfence-before-ret=or -mlfence-before-indirect-branch=all
#objdump: -dw
#name -mlfence-before-ret=or -mlfence-before-indirect-branch=all
.*: +file format .*
@ -20,16 +20,4 @@ Disassembly of section .text:
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: c2 1e 00 ret \$0x1e
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 cb lretw
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: cb lret
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: ca 28 00 lret \$0x28
#pass

12
gas/testsuite/gas/i386/lfence-ret-d.d
View File

@ -21,16 +21,4 @@ Disassembly of section .text:
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: c2 1e 00 ret \$0x1e
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 cb lretw
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: cb lret
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%esp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: ca 28 00 lret \$0x28
#pass

4
gas/testsuite/gas/i386/lfence-ret.s
View File

@ -4,7 +4,3 @@ _start:
retw $20
ret
ret $30
lretw
lretw $40
lret
lret $40

19
gas/testsuite/gas/i386/x86-64-lfence-ret-a.d
View File

@ -1,6 +1,5 @@
#source: x86-64-lfence-ret.s
#as: -mlfence-before-ret=or
#warning_output: x86-64-lfence-ret.e
#objdump: -dw -Mintel64
#name: x86-64 -mlfence-before-ret=or
@ -28,22 +27,4 @@ Disassembly of section .text:
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 cb lretw
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: cb lret
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: ca 28 00 lret \$0x28
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 48 cb lretq
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
#pass

25
gas/testsuite/gas/i386/x86-64-lfence-ret-b.d
View File

@ -1,6 +1,5 @@
#source: x86-64-lfence-ret.s
#as: -mlfence-before-ret=not
#warning_output: x86-64-lfence-ret.e
#objdump: -dw -Mintel64
#name: x86-64 -mlfence-before-ret=not
@ -34,28 +33,4 @@ Disassembly of section .text:
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
+[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
+[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 cb lretw
+[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
+[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
+[a-f0-9]+: f7 14 24 notl \(%rsp\)
+[a-f0-9]+: f7 14 24 notl \(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: cb lret
+[a-f0-9]+: f7 14 24 notl \(%rsp\)
+[a-f0-9]+: f7 14 24 notl \(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: ca 28 00 lret \$0x28
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 48 cb lretq
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
#pass

19
gas/testsuite/gas/i386/x86-64-lfence-ret-c.d
View File

@ -1,6 +1,5 @@
#source: x86-64-lfence-ret.s
#as: -mlfence-before-ret=or -mlfence-before-indirect-branch=all
#warning_output: x86-64-lfence-ret.e
#objdump: -dw -Mintel64
.*: +file format .*
@ -27,22 +26,4 @@ Disassembly of section .text:
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 cb lretw
+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: cb lret
+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: ca 28 00 lret \$0x28
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 48 cb lretq
+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
#pass

19
gas/testsuite/gas/i386/x86-64-lfence-ret-d.d
View File

@ -1,6 +1,5 @@
#source: x86-64-lfence-ret.s
#as: -mlfence-before-ret=shl
#warning_output: x86-64-lfence-ret.e
#objdump: -dw -Mintel64
#name: x86-64 -mlfence-before-ret=shl
@ -28,22 +27,4 @@ Disassembly of section .text:
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 cb lretw
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: cb lret
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: ca 28 00 lret \$0x28
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 48 cb lretq
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
#pass

19
gas/testsuite/gas/i386/x86-64-lfence-ret-e.d
View File

@ -1,6 +1,5 @@
#source: x86-64-lfence-ret.s
#as: -mlfence-before-ret=shl
#warning_output: x86-64-lfence-ret.e
#objdump: -dw -Mintel64
#name: x86-64 -mlfence-before-ret=yes
@ -28,22 +27,4 @@ Disassembly of section .text:
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 cb lretw
+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: cb lret
+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: ca 28 00 lret \$0x28
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 48 cb lretq
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
#pass

3
gas/testsuite/gas/i386/x86-64-lfence-ret.e
View File

@ -1,3 +0,0 @@
.*: Assembler messages:
.*:??: Warning: no instruction mnemonic suffix given and no register operands; using default for `lret'
.*:??: Warning: no instruction mnemonic suffix given and no register operands; using default for `lret'

6
gas/testsuite/gas/i386/x86-64-lfence-ret.s
View File

@ -6,9 +6,3 @@ _start:
ret $30
data16 rex.w ret
data16 rex.w ret $40
lretw
lretw $40
lret
lret $40
lretq
lretq $40