Don't handle lret/iret when -mlfence-before-ret=[or|not|shl|yes] since they are invalid in SGX enclaves.
gas/ChangeLog * gas/config/tc-i386.c: Not handle lret/iret. * gas/testsuite/gas/i386/lfence-ret-a.d: Adjust testcase. * gas/testsuite/gas/i386/lfence-ret-b.d: Ditto. * gas/testsuite/gas/i386/lfence-ret-c.d: Ditto. * gas/testsuite/gas/i386/lfence-ret-d.d: Ditto. * gas/testsuite/gas/i386/lfence-ret.s: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-a.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-b.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-c.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-d.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret-e.d: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret.s: Ditto. * gas/testsuite/gas/i386/x86-64-lfence-ret.e: Deleted.
This commit is contained in:
parent
07a78c5956
commit
503648e41e
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@ -1,3 +1,19 @@
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2020-05-18 Hongtao Liu <hongtao.liu@intel.com>
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* config/tc-i386.c: Not handle lret/iret.
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* testsuite/gas/i386/lfence-ret-a.d: Adjust testcase.
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* testsuite/gas/i386/lfence-ret-b.d: Ditto.
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* testsuite/gas/i386/lfence-ret-c.d: Ditto.
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* testsuite/gas/i386/lfence-ret-d.d: Ditto.
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* testsuite/gas/i386/lfence-ret.s: Ditto.
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* testsuite/gas/i386/x86-64-lfence-ret-a.d: Ditto.
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* testsuite/gas/i386/x86-64-lfence-ret-b.d: Ditto.
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* testsuite/gas/i386/x86-64-lfence-ret-c.d: Ditto.
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* testsuite/gas/i386/x86-64-lfence-ret-d.d: Ditto.
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* testsuite/gas/i386/x86-64-lfence-ret-e.d: Ditto.
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* testsuite/gas/i386/x86-64-lfence-ret.s: Ditto.
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* testsuite/gas/i386/x86-64-lfence-ret.e: Deleted.
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2020-05-15 Alan Modra <amodra@gmail.com>
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Alex Coplan <alex.coplan@arm.com>
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@ -4591,13 +4591,10 @@ insert_lfence_before (void)
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return;
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}
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/* Output or/not/shl and lfence before ret/lret/iret. */
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/* Output or/not/shl and lfence before near ret. */
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if (lfence_before_ret != lfence_before_ret_none
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&& (i.tm.base_opcode == 0xc2
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|| i.tm.base_opcode == 0xc3
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|| i.tm.base_opcode == 0xca
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|| i.tm.base_opcode == 0xcb
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|| i.tm.base_opcode == 0xcf))
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|| i.tm.base_opcode == 0xc3))
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{
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if (last_insn.kind != last_insn_other
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&& last_insn.seg == now_seg)
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@ -4608,17 +4605,10 @@ insert_lfence_before (void)
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return;
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}
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/* lret or iret. */
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bfd_boolean lret = (i.tm.base_opcode | 0x5) == 0xcf;
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bfd_boolean has_rexw = i.prefix[REX_PREFIX] & REX_W;
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char prefix = 0x0;
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/* Default operand size for far return is 32 bits,
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64 bits for near return. */
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/* Near ret ingore operand size override under CPU64. */
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if ((!lret && flag_code == CODE_64BIT) || has_rexw)
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prefix = 0x48;
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else if (i.prefix[DATA_PREFIX])
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prefix = 0x66;
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char prefix = flag_code == CODE_64BIT
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? 0x48
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: i.prefix[DATA_PREFIX] ? 0x66 : 0x0;
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if (lfence_before_ret == lfence_before_ret_not)
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{
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@ -21,16 +21,4 @@ Disassembly of section .text:
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+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: c2 1e 00 ret \$0x1e
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+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 cb lretw
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+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
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+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: cb lret
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+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: ca 28 00 lret \$0x28
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#pass
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@ -25,20 +25,4 @@ Disassembly of section .text:
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+[a-f0-9]+: f7 14 24 notl \(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: c2 1e 00 ret \$0x1e
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+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
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+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 cb lretw
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+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
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+[a-f0-9]+: 66 f7 14 24 notw \(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
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+[a-f0-9]+: f7 14 24 notl \(%esp\)
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+[a-f0-9]+: f7 14 24 notl \(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: cb lret
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+[a-f0-9]+: f7 14 24 notl \(%esp\)
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+[a-f0-9]+: f7 14 24 notl \(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: ca 28 00 lret \$0x28
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#pass
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@ -1,7 +1,7 @@
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#source: lfence-ret.s
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#as: -mlfence-before-ret=or -mlfence-before-indirect-branch=all
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#objdump: -dw
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#name -mlfence-before-ret=or -mlfence-before-indirect-branch=all
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.*: +file format .*
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@ -20,16 +20,4 @@ Disassembly of section .text:
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+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: c2 1e 00 ret \$0x1e
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+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 cb lretw
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+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
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+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: cb lret
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+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: ca 28 00 lret \$0x28
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#pass
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@ -21,16 +21,4 @@ Disassembly of section .text:
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+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: c2 1e 00 ret \$0x1e
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+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 cb lretw
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+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
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+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: cb lret
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+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%esp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: ca 28 00 lret \$0x28
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#pass
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@ -4,7 +4,3 @@ _start:
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retw $20
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ret
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ret $30
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lretw
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lretw $40
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lret
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lret $40
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@ -1,6 +1,5 @@
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#source: x86-64-lfence-ret.s
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#as: -mlfence-before-ret=or
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#warning_output: x86-64-lfence-ret.e
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#objdump: -dw -Mintel64
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#name: x86-64 -mlfence-before-ret=or
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@ -28,22 +27,4 @@ Disassembly of section .text:
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+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
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+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 cb lretw
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+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
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+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: cb lret
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+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: ca 28 00 lret \$0x28
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+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 48 cb lretq
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+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
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#pass
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@ -1,6 +1,5 @@
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#source: x86-64-lfence-ret.s
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#as: -mlfence-before-ret=not
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#warning_output: x86-64-lfence-ret.e
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#objdump: -dw -Mintel64
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#name: x86-64 -mlfence-before-ret=not
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@ -34,28 +33,4 @@ Disassembly of section .text:
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+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
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+[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
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+[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 cb lretw
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+[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
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+[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
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+[a-f0-9]+: f7 14 24 notl \(%rsp\)
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+[a-f0-9]+: f7 14 24 notl \(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: cb lret
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+[a-f0-9]+: f7 14 24 notl \(%rsp\)
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+[a-f0-9]+: f7 14 24 notl \(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: ca 28 00 lret \$0x28
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+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
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+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 48 cb lretq
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+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
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+[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
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#pass
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@ -1,6 +1,5 @@
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#source: x86-64-lfence-ret.s
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#as: -mlfence-before-ret=or -mlfence-before-indirect-branch=all
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#warning_output: x86-64-lfence-ret.e
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#objdump: -dw -Mintel64
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.*: +file format .*
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@ -27,22 +26,4 @@ Disassembly of section .text:
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+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
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+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 cb lretw
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+[a-f0-9]+: 66 83 0c 24 00 orw \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
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+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: cb lret
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+[a-f0-9]+: 83 0c 24 00 orl \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: ca 28 00 lret \$0x28
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+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 48 cb lretq
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+[a-f0-9]+: 48 83 0c 24 00 orq \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
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#pass
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|
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@ -1,6 +1,5 @@
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#source: x86-64-lfence-ret.s
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#as: -mlfence-before-ret=shl
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#warning_output: x86-64-lfence-ret.e
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#objdump: -dw -Mintel64
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#name: x86-64 -mlfence-before-ret=shl
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@ -28,22 +27,4 @@ Disassembly of section .text:
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+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
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+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\)
|
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+[a-f0-9]+: 0f ae e8 lfence
|
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+[a-f0-9]+: 66 cb lretw
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+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
|
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+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
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+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
|
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+[a-f0-9]+: cb lret
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+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: ca 28 00 lret \$0x28
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+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 48 cb lretq
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+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
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#pass
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|
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|
@ -1,6 +1,5 @@
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#source: x86-64-lfence-ret.s
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#as: -mlfence-before-ret=shl
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#warning_output: x86-64-lfence-ret.e
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#objdump: -dw -Mintel64
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#name: x86-64 -mlfence-before-ret=yes
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|
@ -28,22 +27,4 @@ Disassembly of section .text:
|
|||
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||
+[a-f0-9]+: 0f ae e8 lfence
|
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+[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
|
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+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\)
|
||||
+[a-f0-9]+: 0f ae e8 lfence
|
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+[a-f0-9]+: 66 cb lretw
|
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+[a-f0-9]+: 66 c1 24 24 00 shlw \$0x0,\(%rsp\)
|
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+[a-f0-9]+: 0f ae e8 lfence
|
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+[a-f0-9]+: 66 ca 28 00 lretw \$0x28
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+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\)
|
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+[a-f0-9]+: 0f ae e8 lfence
|
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+[a-f0-9]+: cb lret
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+[a-f0-9]+: c1 24 24 00 shll \$0x0,\(%rsp\)
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+[a-f0-9]+: 0f ae e8 lfence
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+[a-f0-9]+: ca 28 00 lret \$0x28
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+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||
+[a-f0-9]+: 0f ae e8 lfence
|
||||
+[a-f0-9]+: 48 cb lretq
|
||||
+[a-f0-9]+: 48 c1 24 24 00 shlq \$0x0,\(%rsp\)
|
||||
+[a-f0-9]+: 0f ae e8 lfence
|
||||
+[a-f0-9]+: 48 ca 28 00 lretq \$0x28
|
||||
#pass
|
||||
|
|
|
@ -1,3 +0,0 @@
|
|||
.*: Assembler messages:
|
||||
.*:??: Warning: no instruction mnemonic suffix given and no register operands; using default for `lret'
|
||||
.*:??: Warning: no instruction mnemonic suffix given and no register operands; using default for `lret'
|
|
@ -6,9 +6,3 @@ _start:
|
|||
ret $30
|
||||
data16 rex.w ret
|
||||
data16 rex.w ret $40
|
||||
lretw
|
||||
lretw $40
|
||||
lret
|
||||
lret $40
|
||||
lretq
|
||||
lretq $40
|
||||
|
|
Loading…
Reference in New Issue