[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A Memory Tagging Extensions which is an optional extension to ARMv8.5-A and is enabled using the +memtag command line option. This patch add support to the Bulk Allocation Tag instructions from MTE. These are the following instructions added in this patch: - LDGV <Xt>, [<Xn|SP>]! - STGV <Xt>, [<Xn|SP>]! This needed a new kind of operand for the new addressing [<Xn|SP>]! since this has no offset and only takes a pre-indexed version. Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced. (AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does not allow writeback). We also needed new encoding and decoding functions to be able to do the same. where <Xt> : Is the 64-bit destination GPR. <Xn|SP> : Is the 64-bit first source GPR or Stack pointer. *** include/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2. (aarch64_insn_class): Add ldstgv_indexed. *** opcodes/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * aarch64-asm.c (aarch64_ins_addr_simple_2): New. * aarch64-asm.h (ins_addr_simple_2): Declare the above. * aarch64-dis.c (aarch64_ext_addr_simple_2): New. * aarch64-dis.h (ext_addr_simple_2): Declare the above. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed. (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv. (AARCH64_OPERANDS): Define ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. *** gas/ChangeLog *** 2018-11-12 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add switch case for AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it. (warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
This commit is contained in:
Sudakshina Das
parent
e6025b546c
commit
503ba60025
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@ -1,3 +1,13 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* config/tc-aarch64.c (parse_operands): Add switch case for
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AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
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(warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv.
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* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv.
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* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
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* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
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* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldg.
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@ -3372,6 +3372,7 @@ parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
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[base,Wm,(S|U)XTW {#imm}]
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Pre-indexed
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[base,#imm]!
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[base]! // in ld/stgv
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Post-indexed
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[base],#imm
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[base],Xm // in SIMD ld/st structure
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@ -3680,10 +3681,11 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
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}
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/* If at this point neither .preind nor .postind is set, we have a
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bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
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bare [Rn]{!}; reject [Rn]! except for ld/stgv but accept [Rn]
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as a shorthand for [Rn,#0]. */
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if (operand->addr.preind == 0 && operand->addr.postind == 0)
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{
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if (operand->addr.writeback)
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if (operand->type != AARCH64_OPND_ADDR_SIMPLE_2 && operand->addr.writeback)
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{
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/* Reject [Rn]! */
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set_syntax_error (_("missing offset in the pre-indexed address"));
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@ -6137,6 +6139,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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break;
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case AARCH64_OPND_ADDR_SIMPLE:
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case AARCH64_OPND_ADDR_SIMPLE_2:
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case AARCH64_OPND_SIMD_ADDR_SIMPLE:
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{
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/* [<Xn|SP>{, #<simm>}] */
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@ -6146,7 +6149,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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po_misc_or_fail (parse_address (&str, info));
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if (info->addr.pcrel || info->addr.offset.is_reg
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|| !info->addr.preind || info->addr.postind
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|| info->addr.writeback)
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|| (info->addr.writeback
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&& operands[i] != AARCH64_OPND_ADDR_SIMPLE_2))
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{
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set_syntax_error (_("invalid addressing mode"));
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goto failure;
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@ -6169,6 +6173,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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}
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}
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po_char_or_fail (']');
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if (operands[i] == AARCH64_OPND_ADDR_SIMPLE_2)
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po_char_or_fail ('!');
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break;
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}
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@ -6766,6 +6772,14 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
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&& opnds[1].addr.writeback)
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as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
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break;
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case ldstgv_indexed:
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/* Load operations must load different registers. */
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if ((opcode->opcode & (1 << 22))
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&& opnds[0].reg.regno == opnds[1].addr.base_regno)
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as_warn (_("unpredictable load of register -- `%s'"), str);
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break;
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case ldstpair_off:
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case ldstnapair_offs:
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case ldstpair_indexed:
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@ -121,3 +121,14 @@ Disassembly of section \.text:
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.*: d960001f ldg xzr, \[x0\]
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.*: d96ff000 ldg x0, \[x0, #4080\]
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.*: d9700000 ldg x0, \[x0, #-4096\]
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.*: d9e0001b ldgv x27, \[x0\]!
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.*: d9e00360 ldgv x0, \[x27\]!
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.*: d9e00379 ldgv x25, \[x27\]!
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.*: d9e003e0 ldgv x0, \[sp\]!
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.*: d9e0001f ldgv xzr, \[x0\]!
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.*: d9a00000 stgv x0, \[x0\]!
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.*: d9a0001b stgv x27, \[x0\]!
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.*: d9a00360 stgv x0, \[x27\]!
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.*: d9a00379 stgv x25, \[x27\]!
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.*: d9a003e0 stgv x0, \[sp\]!
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.*: d9a0001f stgv xzr, \[x0\]!
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@ -30,6 +30,14 @@ func:
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\op [sp], #-4096
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.endm
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.macro expand_ldg_bulk op
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\op x27, [x0]!
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\op x0, [x27]!
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\op x25, [x27]!
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\op x0, [sp]!
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\op xzr, [x0]!
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.endm
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# IRG
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expand_3_reg irg
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irg sp, x0
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@ -98,3 +106,8 @@ func:
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ldg xzr, [x0, #0]
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ldg x0, [x0, #4080]
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ldg x0, [x0, #-4096]
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expand_ldg_bulk ldgv
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stgv x0, [x0]!
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expand_ldg_bulk stgv
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@ -12,6 +12,9 @@
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[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
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[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]'
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[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
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[^:]*:[0-9]+: Warning: unpredictable load of register -- `ldgv x1,\[x1\]!'
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[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `ldgv x1,\[x2\]'
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[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `stgv x1,\[x2\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
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[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
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[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
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@ -37,3 +40,7 @@
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgv sp,\[x1\]!'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldgv x0,\[xzr\]!'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgv sp,\[x1\]!'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stgv x0,\[xzr\]!'
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@ -20,6 +20,14 @@ func:
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stgp x1, x2, [x3, #33]
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stgp x1, x2, [x3, #-1025]
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# LDGV : Warn for Xt == Xn
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# STGV : Sould not warn for above
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ldgv x1, [x1]!
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stgv x1, [x1]!
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# Error for no writeback
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ldgv x1, [x2]
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stgv x1, [x2]
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# Illegal SP/XZR registers
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irg xzr, x2, x3
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irg x1, xzr, x3
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@ -46,3 +54,7 @@ func:
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stgp x0, x0, [xzr]
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ldg sp, [x0, #16]
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ldg x0, [xzr, #16]
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ldgv sp, [x1]!
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ldgv x0, [xzr]!
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stgv sp, [x1]!
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stgv x0, [xzr]!
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@ -1,3 +1,8 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
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(aarch64_insn_class): Add ldstgv_indexed.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
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@ -275,6 +275,7 @@ enum aarch64_opnd
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AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
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AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
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AARCH64_OPND_ADDR_SIMPLE_2, /* Address of ld/stgv. */
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AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
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AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
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AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
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@ -561,6 +562,7 @@ enum aarch64_insn_class
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ldstnapair_offs,
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ldstpair_off,
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ldstpair_indexed,
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ldstgv_indexed,
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loadlit,
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log_imm,
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log_shift,
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@ -1,3 +1,18 @@
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* aarch64-asm.c (aarch64_ins_addr_simple_2): New.
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* aarch64-asm.h (ins_addr_simple_2): Declare the above.
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* aarch64-dis.c (aarch64_ext_addr_simple_2): New.
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* aarch64-dis.h (ext_addr_simple_2): Declare the above.
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* aarch64-opc.c (operand_general_constraint_met_p): Add case for
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AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
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(aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
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* aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
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(AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
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* aarch64-asm-2.c: Regenerated.
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* aarch64-dis-2.c: Regenerated.
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* aarch64-opc-2.c: Regenerated.
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2018-11-12 Sudakshina Das <sudi.das@arm.com>
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* aarch64-tbl.h (QL_LDG): New.
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@ -201,390 +201,390 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 757: /* extr */
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value = 757; /* --> extr. */
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break;
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case 988: /* bic */
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case 987: /* and */
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value = 987; /* --> and. */
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case 990: /* bic */
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case 989: /* and */
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value = 989; /* --> and. */
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break;
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case 990: /* mov */
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case 989: /* orr */
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value = 989; /* --> orr. */
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case 992: /* mov */
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case 991: /* orr */
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value = 991; /* --> orr. */
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break;
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case 993: /* tst */
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case 992: /* ands */
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value = 992; /* --> ands. */
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case 995: /* tst */
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case 994: /* ands */
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value = 994; /* --> ands. */
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break;
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case 998: /* uxtw */
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case 997: /* mov */
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case 996: /* orr */
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value = 996; /* --> orr. */
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case 1000: /* uxtw */
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case 999: /* mov */
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case 998: /* orr */
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value = 998; /* --> orr. */
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break;
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case 1000: /* mvn */
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case 999: /* orn */
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value = 999; /* --> orn. */
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case 1002: /* mvn */
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case 1001: /* orn */
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value = 1001; /* --> orn. */
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break;
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case 1004: /* tst */
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case 1003: /* ands */
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value = 1003; /* --> ands. */
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case 1006: /* tst */
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case 1005: /* ands */
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value = 1005; /* --> ands. */
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break;
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case 1130: /* staddb */
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case 1034: /* ldaddb */
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value = 1034; /* --> ldaddb. */
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case 1132: /* staddb */
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case 1036: /* ldaddb */
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value = 1036; /* --> ldaddb. */
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break;
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case 1131: /* staddh */
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case 1035: /* ldaddh */
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value = 1035; /* --> ldaddh. */
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case 1133: /* staddh */
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case 1037: /* ldaddh */
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value = 1037; /* --> ldaddh. */
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break;
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case 1132: /* stadd */
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case 1036: /* ldadd */
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value = 1036; /* --> ldadd. */
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case 1134: /* stadd */
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case 1038: /* ldadd */
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value = 1038; /* --> ldadd. */
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break;
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case 1133: /* staddlb */
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case 1038: /* ldaddlb */
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value = 1038; /* --> ldaddlb. */
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case 1135: /* staddlb */
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case 1040: /* ldaddlb */
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value = 1040; /* --> ldaddlb. */
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break;
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case 1134: /* staddlh */
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case 1041: /* ldaddlh */
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value = 1041; /* --> ldaddlh. */
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case 1136: /* staddlh */
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case 1043: /* ldaddlh */
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value = 1043; /* --> ldaddlh. */
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break;
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case 1135: /* staddl */
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case 1044: /* ldaddl */
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value = 1044; /* --> ldaddl. */
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case 1137: /* staddl */
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case 1046: /* ldaddl */
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value = 1046; /* --> ldaddl. */
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break;
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case 1136: /* stclrb */
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case 1046: /* ldclrb */
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value = 1046; /* --> ldclrb. */
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case 1138: /* stclrb */
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case 1048: /* ldclrb */
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value = 1048; /* --> ldclrb. */
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break;
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case 1137: /* stclrh */
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case 1047: /* ldclrh */
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value = 1047; /* --> ldclrh. */
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case 1139: /* stclrh */
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case 1049: /* ldclrh */
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value = 1049; /* --> ldclrh. */
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break;
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case 1138: /* stclr */
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case 1048: /* ldclr */
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value = 1048; /* --> ldclr. */
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case 1140: /* stclr */
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case 1050: /* ldclr */
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value = 1050; /* --> ldclr. */
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break;
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case 1139: /* stclrlb */
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case 1050: /* ldclrlb */
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value = 1050; /* --> ldclrlb. */
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case 1141: /* stclrlb */
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case 1052: /* ldclrlb */
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value = 1052; /* --> ldclrlb. */
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break;
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case 1140: /* stclrlh */
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case 1053: /* ldclrlh */
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value = 1053; /* --> ldclrlh. */
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case 1142: /* stclrlh */
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case 1055: /* ldclrlh */
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value = 1055; /* --> ldclrlh. */
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break;
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case 1141: /* stclrl */
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case 1056: /* ldclrl */
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value = 1056; /* --> ldclrl. */
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case 1143: /* stclrl */
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case 1058: /* ldclrl */
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value = 1058; /* --> ldclrl. */
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break;
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case 1142: /* steorb */
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case 1058: /* ldeorb */
|
||||
value = 1058; /* --> ldeorb. */
|
||||
case 1144: /* steorb */
|
||||
case 1060: /* ldeorb */
|
||||
value = 1060; /* --> ldeorb. */
|
||||
break;
|
||||
case 1143: /* steorh */
|
||||
case 1059: /* ldeorh */
|
||||
value = 1059; /* --> ldeorh. */
|
||||
case 1145: /* steorh */
|
||||
case 1061: /* ldeorh */
|
||||
value = 1061; /* --> ldeorh. */
|
||||
break;
|
||||
case 1144: /* steor */
|
||||
case 1060: /* ldeor */
|
||||
value = 1060; /* --> ldeor. */
|
||||
case 1146: /* steor */
|
||||
case 1062: /* ldeor */
|
||||
value = 1062; /* --> ldeor. */
|
||||
break;
|
||||
case 1145: /* steorlb */
|
||||
case 1062: /* ldeorlb */
|
||||
value = 1062; /* --> ldeorlb. */
|
||||
case 1147: /* steorlb */
|
||||
case 1064: /* ldeorlb */
|
||||
value = 1064; /* --> ldeorlb. */
|
||||
break;
|
||||
case 1146: /* steorlh */
|
||||
case 1065: /* ldeorlh */
|
||||
value = 1065; /* --> ldeorlh. */
|
||||
case 1148: /* steorlh */
|
||||
case 1067: /* ldeorlh */
|
||||
value = 1067; /* --> ldeorlh. */
|
||||
break;
|
||||
case 1147: /* steorl */
|
||||
case 1068: /* ldeorl */
|
||||
value = 1068; /* --> ldeorl. */
|
||||
case 1149: /* steorl */
|
||||
case 1070: /* ldeorl */
|
||||
value = 1070; /* --> ldeorl. */
|
||||
break;
|
||||
case 1148: /* stsetb */
|
||||
case 1070: /* ldsetb */
|
||||
value = 1070; /* --> ldsetb. */
|
||||
case 1150: /* stsetb */
|
||||
case 1072: /* ldsetb */
|
||||
value = 1072; /* --> ldsetb. */
|
||||
break;
|
||||
case 1149: /* stseth */
|
||||
case 1071: /* ldseth */
|
||||
value = 1071; /* --> ldseth. */
|
||||
case 1151: /* stseth */
|
||||
case 1073: /* ldseth */
|
||||
value = 1073; /* --> ldseth. */
|
||||
break;
|
||||
case 1150: /* stset */
|
||||
case 1072: /* ldset */
|
||||
value = 1072; /* --> ldset. */
|
||||
case 1152: /* stset */
|
||||
case 1074: /* ldset */
|
||||
value = 1074; /* --> ldset. */
|
||||
break;
|
||||
case 1151: /* stsetlb */
|
||||
case 1074: /* ldsetlb */
|
||||
value = 1074; /* --> ldsetlb. */
|
||||
case 1153: /* stsetlb */
|
||||
case 1076: /* ldsetlb */
|
||||
value = 1076; /* --> ldsetlb. */
|
||||
break;
|
||||
case 1152: /* stsetlh */
|
||||
case 1077: /* ldsetlh */
|
||||
value = 1077; /* --> ldsetlh. */
|
||||
case 1154: /* stsetlh */
|
||||
case 1079: /* ldsetlh */
|
||||
value = 1079; /* --> ldsetlh. */
|
||||
break;
|
||||
case 1153: /* stsetl */
|
||||
case 1080: /* ldsetl */
|
||||
value = 1080; /* --> ldsetl. */
|
||||
case 1155: /* stsetl */
|
||||
case 1082: /* ldsetl */
|
||||
value = 1082; /* --> ldsetl. */
|
||||
break;
|
||||
case 1154: /* stsmaxb */
|
||||
case 1082: /* ldsmaxb */
|
||||
value = 1082; /* --> ldsmaxb. */
|
||||
case 1156: /* stsmaxb */
|
||||
case 1084: /* ldsmaxb */
|
||||
value = 1084; /* --> ldsmaxb. */
|
||||
break;
|
||||
case 1155: /* stsmaxh */
|
||||
case 1083: /* ldsmaxh */
|
||||
value = 1083; /* --> ldsmaxh. */
|
||||
case 1157: /* stsmaxh */
|
||||
case 1085: /* ldsmaxh */
|
||||
value = 1085; /* --> ldsmaxh. */
|
||||
break;
|
||||
case 1156: /* stsmax */
|
||||
case 1084: /* ldsmax */
|
||||
value = 1084; /* --> ldsmax. */
|
||||
case 1158: /* stsmax */
|
||||
case 1086: /* ldsmax */
|
||||
value = 1086; /* --> ldsmax. */
|
||||
break;
|
||||
case 1157: /* stsmaxlb */
|
||||
case 1086: /* ldsmaxlb */
|
||||
value = 1086; /* --> ldsmaxlb. */
|
||||
case 1159: /* stsmaxlb */
|
||||
case 1088: /* ldsmaxlb */
|
||||
value = 1088; /* --> ldsmaxlb. */
|
||||
break;
|
||||
case 1158: /* stsmaxlh */
|
||||
case 1089: /* ldsmaxlh */
|
||||
value = 1089; /* --> ldsmaxlh. */
|
||||
case 1160: /* stsmaxlh */
|
||||
case 1091: /* ldsmaxlh */
|
||||
value = 1091; /* --> ldsmaxlh. */
|
||||
break;
|
||||
case 1159: /* stsmaxl */
|
||||
case 1092: /* ldsmaxl */
|
||||
value = 1092; /* --> ldsmaxl. */
|
||||
case 1161: /* stsmaxl */
|
||||
case 1094: /* ldsmaxl */
|
||||
value = 1094; /* --> ldsmaxl. */
|
||||
break;
|
||||
case 1160: /* stsminb */
|
||||
case 1094: /* ldsminb */
|
||||
value = 1094; /* --> ldsminb. */
|
||||
case 1162: /* stsminb */
|
||||
case 1096: /* ldsminb */
|
||||
value = 1096; /* --> ldsminb. */
|
||||
break;
|
||||
case 1161: /* stsminh */
|
||||
case 1095: /* ldsminh */
|
||||
value = 1095; /* --> ldsminh. */
|
||||
case 1163: /* stsminh */
|
||||
case 1097: /* ldsminh */
|
||||
value = 1097; /* --> ldsminh. */
|
||||
break;
|
||||
case 1162: /* stsmin */
|
||||
case 1096: /* ldsmin */
|
||||
value = 1096; /* --> ldsmin. */
|
||||
case 1164: /* stsmin */
|
||||
case 1098: /* ldsmin */
|
||||
value = 1098; /* --> ldsmin. */
|
||||
break;
|
||||
case 1163: /* stsminlb */
|
||||
case 1098: /* ldsminlb */
|
||||
value = 1098; /* --> ldsminlb. */
|
||||
case 1165: /* stsminlb */
|
||||
case 1100: /* ldsminlb */
|
||||
value = 1100; /* --> ldsminlb. */
|
||||
break;
|
||||
case 1164: /* stsminlh */
|
||||
case 1101: /* ldsminlh */
|
||||
value = 1101; /* --> ldsminlh. */
|
||||
case 1166: /* stsminlh */
|
||||
case 1103: /* ldsminlh */
|
||||
value = 1103; /* --> ldsminlh. */
|
||||
break;
|
||||
case 1165: /* stsminl */
|
||||
case 1104: /* ldsminl */
|
||||
value = 1104; /* --> ldsminl. */
|
||||
case 1167: /* stsminl */
|
||||
case 1106: /* ldsminl */
|
||||
value = 1106; /* --> ldsminl. */
|
||||
break;
|
||||
case 1166: /* stumaxb */
|
||||
case 1106: /* ldumaxb */
|
||||
value = 1106; /* --> ldumaxb. */
|
||||
case 1168: /* stumaxb */
|
||||
case 1108: /* ldumaxb */
|
||||
value = 1108; /* --> ldumaxb. */
|
||||
break;
|
||||
case 1167: /* stumaxh */
|
||||
case 1107: /* ldumaxh */
|
||||
value = 1107; /* --> ldumaxh. */
|
||||
case 1169: /* stumaxh */
|
||||
case 1109: /* ldumaxh */
|
||||
value = 1109; /* --> ldumaxh. */
|
||||
break;
|
||||
case 1168: /* stumax */
|
||||
case 1108: /* ldumax */
|
||||
value = 1108; /* --> ldumax. */
|
||||
case 1170: /* stumax */
|
||||
case 1110: /* ldumax */
|
||||
value = 1110; /* --> ldumax. */
|
||||
break;
|
||||
case 1169: /* stumaxlb */
|
||||
case 1110: /* ldumaxlb */
|
||||
value = 1110; /* --> ldumaxlb. */
|
||||
case 1171: /* stumaxlb */
|
||||
case 1112: /* ldumaxlb */
|
||||
value = 1112; /* --> ldumaxlb. */
|
||||
break;
|
||||
case 1170: /* stumaxlh */
|
||||
case 1113: /* ldumaxlh */
|
||||
value = 1113; /* --> ldumaxlh. */
|
||||
case 1172: /* stumaxlh */
|
||||
case 1115: /* ldumaxlh */
|
||||
value = 1115; /* --> ldumaxlh. */
|
||||
break;
|
||||
case 1171: /* stumaxl */
|
||||
case 1116: /* ldumaxl */
|
||||
value = 1116; /* --> ldumaxl. */
|
||||
case 1173: /* stumaxl */
|
||||
case 1118: /* ldumaxl */
|
||||
value = 1118; /* --> ldumaxl. */
|
||||
break;
|
||||
case 1172: /* stuminb */
|
||||
case 1118: /* lduminb */
|
||||
value = 1118; /* --> lduminb. */
|
||||
case 1174: /* stuminb */
|
||||
case 1120: /* lduminb */
|
||||
value = 1120; /* --> lduminb. */
|
||||
break;
|
||||
case 1173: /* stuminh */
|
||||
case 1119: /* lduminh */
|
||||
value = 1119; /* --> lduminh. */
|
||||
case 1175: /* stuminh */
|
||||
case 1121: /* lduminh */
|
||||
value = 1121; /* --> lduminh. */
|
||||
break;
|
||||
case 1174: /* stumin */
|
||||
case 1120: /* ldumin */
|
||||
value = 1120; /* --> ldumin. */
|
||||
case 1176: /* stumin */
|
||||
case 1122: /* ldumin */
|
||||
value = 1122; /* --> ldumin. */
|
||||
break;
|
||||
case 1175: /* stuminlb */
|
||||
case 1122: /* lduminlb */
|
||||
value = 1122; /* --> lduminlb. */
|
||||
case 1177: /* stuminlb */
|
||||
case 1124: /* lduminlb */
|
||||
value = 1124; /* --> lduminlb. */
|
||||
break;
|
||||
case 1176: /* stuminlh */
|
||||
case 1125: /* lduminlh */
|
||||
value = 1125; /* --> lduminlh. */
|
||||
case 1178: /* stuminlh */
|
||||
case 1127: /* lduminlh */
|
||||
value = 1127; /* --> lduminlh. */
|
||||
break;
|
||||
case 1177: /* stuminl */
|
||||
case 1128: /* lduminl */
|
||||
value = 1128; /* --> lduminl. */
|
||||
break;
|
||||
case 1179: /* mov */
|
||||
case 1178: /* movn */
|
||||
value = 1178; /* --> movn. */
|
||||
case 1179: /* stuminl */
|
||||
case 1130: /* lduminl */
|
||||
value = 1130; /* --> lduminl. */
|
||||
break;
|
||||
case 1181: /* mov */
|
||||
case 1180: /* movz */
|
||||
value = 1180; /* --> movz. */
|
||||
case 1180: /* movn */
|
||||
value = 1180; /* --> movn. */
|
||||
break;
|
||||
case 1227: /* autibsp */
|
||||
case 1226: /* autibz */
|
||||
case 1225: /* autiasp */
|
||||
case 1224: /* autiaz */
|
||||
case 1223: /* pacibsp */
|
||||
case 1222: /* pacibz */
|
||||
case 1221: /* paciasp */
|
||||
case 1220: /* paciaz */
|
||||
case 1201: /* psb */
|
||||
case 1200: /* esb */
|
||||
case 1199: /* autib1716 */
|
||||
case 1198: /* autia1716 */
|
||||
case 1197: /* pacib1716 */
|
||||
case 1196: /* pacia1716 */
|
||||
case 1195: /* xpaclri */
|
||||
case 1194: /* sevl */
|
||||
case 1193: /* sev */
|
||||
case 1192: /* wfi */
|
||||
case 1191: /* wfe */
|
||||
case 1190: /* yield */
|
||||
case 1189: /* bti */
|
||||
case 1188: /* csdb */
|
||||
case 1187: /* nop */
|
||||
case 1186: /* hint */
|
||||
value = 1186; /* --> hint. */
|
||||
case 1183: /* mov */
|
||||
case 1182: /* movz */
|
||||
value = 1182; /* --> movz. */
|
||||
break;
|
||||
case 1205: /* pssbb */
|
||||
case 1204: /* ssbb */
|
||||
case 1203: /* dsb */
|
||||
value = 1203; /* --> dsb. */
|
||||
case 1229: /* autibsp */
|
||||
case 1228: /* autibz */
|
||||
case 1227: /* autiasp */
|
||||
case 1226: /* autiaz */
|
||||
case 1225: /* pacibsp */
|
||||
case 1224: /* pacibz */
|
||||
case 1223: /* paciasp */
|
||||
case 1222: /* paciaz */
|
||||
case 1203: /* psb */
|
||||
case 1202: /* esb */
|
||||
case 1201: /* autib1716 */
|
||||
case 1200: /* autia1716 */
|
||||
case 1199: /* pacib1716 */
|
||||
case 1198: /* pacia1716 */
|
||||
case 1197: /* xpaclri */
|
||||
case 1196: /* sevl */
|
||||
case 1195: /* sev */
|
||||
case 1194: /* wfi */
|
||||
case 1193: /* wfe */
|
||||
case 1192: /* yield */
|
||||
case 1191: /* bti */
|
||||
case 1190: /* csdb */
|
||||
case 1189: /* nop */
|
||||
case 1188: /* hint */
|
||||
value = 1188; /* --> hint. */
|
||||
break;
|
||||
case 1216: /* cpp */
|
||||
case 1215: /* dvp */
|
||||
case 1214: /* cfp */
|
||||
case 1213: /* tlbi */
|
||||
case 1212: /* ic */
|
||||
case 1211: /* dc */
|
||||
case 1210: /* at */
|
||||
case 1209: /* sys */
|
||||
value = 1209; /* --> sys. */
|
||||
case 1207: /* pssbb */
|
||||
case 1206: /* ssbb */
|
||||
case 1205: /* dsb */
|
||||
value = 1205; /* --> dsb. */
|
||||
break;
|
||||
case 2025: /* bic */
|
||||
case 1275: /* and */
|
||||
value = 1275; /* --> and. */
|
||||
case 1218: /* cpp */
|
||||
case 1217: /* dvp */
|
||||
case 1216: /* cfp */
|
||||
case 1215: /* tlbi */
|
||||
case 1214: /* ic */
|
||||
case 1213: /* dc */
|
||||
case 1212: /* at */
|
||||
case 1211: /* sys */
|
||||
value = 1211; /* --> sys. */
|
||||
break;
|
||||
case 1258: /* mov */
|
||||
case 2027: /* bic */
|
||||
case 1277: /* and */
|
||||
value = 1277; /* --> and. */
|
||||
break;
|
||||
case 1262: /* movs */
|
||||
case 1278: /* ands */
|
||||
value = 1278; /* --> ands. */
|
||||
case 1260: /* mov */
|
||||
case 1279: /* and */
|
||||
value = 1279; /* --> and. */
|
||||
break;
|
||||
case 2026: /* cmple */
|
||||
case 1313: /* cmpge */
|
||||
value = 1313; /* --> cmpge. */
|
||||
case 1264: /* movs */
|
||||
case 1280: /* ands */
|
||||
value = 1280; /* --> ands. */
|
||||
break;
|
||||
case 2029: /* cmplt */
|
||||
case 1316: /* cmpgt */
|
||||
value = 1316; /* --> cmpgt. */
|
||||
case 2028: /* cmple */
|
||||
case 1315: /* cmpge */
|
||||
value = 1315; /* --> cmpge. */
|
||||
break;
|
||||
case 2027: /* cmplo */
|
||||
case 1318: /* cmphi */
|
||||
value = 1318; /* --> cmphi. */
|
||||
case 2031: /* cmplt */
|
||||
case 1318: /* cmpgt */
|
||||
value = 1318; /* --> cmpgt. */
|
||||
break;
|
||||
case 2028: /* cmpls */
|
||||
case 1321: /* cmphs */
|
||||
value = 1321; /* --> cmphs. */
|
||||
case 2029: /* cmplo */
|
||||
case 1320: /* cmphi */
|
||||
value = 1320; /* --> cmphi. */
|
||||
break;
|
||||
case 1255: /* mov */
|
||||
case 1343: /* cpy */
|
||||
value = 1343; /* --> cpy. */
|
||||
case 2030: /* cmpls */
|
||||
case 1323: /* cmphs */
|
||||
value = 1323; /* --> cmphs. */
|
||||
break;
|
||||
case 1257: /* mov */
|
||||
case 1344: /* cpy */
|
||||
value = 1344; /* --> cpy. */
|
||||
break;
|
||||
case 2036: /* fmov */
|
||||
case 1260: /* mov */
|
||||
case 1345: /* cpy */
|
||||
value = 1345; /* --> cpy. */
|
||||
break;
|
||||
case 1250: /* mov */
|
||||
case 1357: /* dup */
|
||||
value = 1357; /* --> dup. */
|
||||
case 1259: /* mov */
|
||||
case 1346: /* cpy */
|
||||
value = 1346; /* --> cpy. */
|
||||
break;
|
||||
case 2038: /* fmov */
|
||||
case 1262: /* mov */
|
||||
case 1347: /* cpy */
|
||||
value = 1347; /* --> cpy. */
|
||||
break;
|
||||
case 1252: /* mov */
|
||||
case 1249: /* mov */
|
||||
case 1358: /* dup */
|
||||
value = 1358; /* --> dup. */
|
||||
break;
|
||||
case 2035: /* fmov */
|
||||
case 1254: /* mov */
|
||||
case 1359: /* dup */
|
||||
value = 1359; /* --> dup. */
|
||||
break;
|
||||
case 1253: /* mov */
|
||||
case 1360: /* dupm */
|
||||
value = 1360; /* --> dupm. */
|
||||
case 1254: /* mov */
|
||||
case 1251: /* mov */
|
||||
case 1360: /* dup */
|
||||
value = 1360; /* --> dup. */
|
||||
break;
|
||||
case 2030: /* eon */
|
||||
case 1362: /* eor */
|
||||
value = 1362; /* --> eor. */
|
||||
case 2037: /* fmov */
|
||||
case 1256: /* mov */
|
||||
case 1361: /* dup */
|
||||
value = 1361; /* --> dup. */
|
||||
break;
|
||||
case 1263: /* not */
|
||||
case 1255: /* mov */
|
||||
case 1362: /* dupm */
|
||||
value = 1362; /* --> dupm. */
|
||||
break;
|
||||
case 2032: /* eon */
|
||||
case 1364: /* eor */
|
||||
value = 1364; /* --> eor. */
|
||||
break;
|
||||
case 1264: /* nots */
|
||||
case 1365: /* eors */
|
||||
value = 1365; /* --> eors. */
|
||||
case 1265: /* not */
|
||||
case 1366: /* eor */
|
||||
value = 1366; /* --> eor. */
|
||||
break;
|
||||
case 2031: /* facle */
|
||||
case 1370: /* facge */
|
||||
value = 1370; /* --> facge. */
|
||||
case 1266: /* nots */
|
||||
case 1367: /* eors */
|
||||
value = 1367; /* --> eors. */
|
||||
break;
|
||||
case 2032: /* faclt */
|
||||
case 1371: /* facgt */
|
||||
value = 1371; /* --> facgt. */
|
||||
case 2033: /* facle */
|
||||
case 1372: /* facge */
|
||||
value = 1372; /* --> facge. */
|
||||
break;
|
||||
case 2033: /* fcmle */
|
||||
case 1384: /* fcmge */
|
||||
value = 1384; /* --> fcmge. */
|
||||
case 2034: /* faclt */
|
||||
case 1373: /* facgt */
|
||||
value = 1373; /* --> facgt. */
|
||||
break;
|
||||
case 2034: /* fcmlt */
|
||||
case 1386: /* fcmgt */
|
||||
value = 1386; /* --> fcmgt. */
|
||||
case 2035: /* fcmle */
|
||||
case 1386: /* fcmge */
|
||||
value = 1386; /* --> fcmge. */
|
||||
break;
|
||||
case 1247: /* fmov */
|
||||
case 1392: /* fcpy */
|
||||
value = 1392; /* --> fcpy. */
|
||||
case 2036: /* fcmlt */
|
||||
case 1388: /* fcmgt */
|
||||
value = 1388; /* --> fcmgt. */
|
||||
break;
|
||||
case 1246: /* fmov */
|
||||
case 1415: /* fdup */
|
||||
value = 1415; /* --> fdup. */
|
||||
case 1249: /* fmov */
|
||||
case 1394: /* fcpy */
|
||||
value = 1394; /* --> fcpy. */
|
||||
break;
|
||||
case 1248: /* mov */
|
||||
case 1746: /* orr */
|
||||
value = 1746; /* --> orr. */
|
||||
case 1248: /* fmov */
|
||||
case 1417: /* fdup */
|
||||
value = 1417; /* --> fdup. */
|
||||
break;
|
||||
case 2037: /* orn */
|
||||
case 1747: /* orr */
|
||||
value = 1747; /* --> orr. */
|
||||
case 1250: /* mov */
|
||||
case 1748: /* orr */
|
||||
value = 1748; /* --> orr. */
|
||||
break;
|
||||
case 1251: /* mov */
|
||||
case 2039: /* orn */
|
||||
case 1749: /* orr */
|
||||
value = 1749; /* --> orr. */
|
||||
break;
|
||||
case 1261: /* movs */
|
||||
case 1750: /* orrs */
|
||||
value = 1750; /* --> orrs. */
|
||||
case 1253: /* mov */
|
||||
case 1751: /* orr */
|
||||
value = 1751; /* --> orr. */
|
||||
break;
|
||||
case 1256: /* mov */
|
||||
case 1812: /* sel */
|
||||
value = 1812; /* --> sel. */
|
||||
case 1263: /* movs */
|
||||
case 1752: /* orrs */
|
||||
value = 1752; /* --> orrs. */
|
||||
break;
|
||||
case 1259: /* mov */
|
||||
case 1813: /* sel */
|
||||
value = 1813; /* --> sel. */
|
||||
case 1258: /* mov */
|
||||
case 1814: /* sel */
|
||||
value = 1814; /* --> sel. */
|
||||
break;
|
||||
case 1261: /* mov */
|
||||
case 1815: /* sel */
|
||||
value = 1815; /* --> sel. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
|
|
@ -627,7 +627,6 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 27:
|
||||
case 28:
|
||||
case 29:
|
||||
case 159:
|
||||
case 160:
|
||||
case 161:
|
||||
case 162:
|
||||
|
|
@ -637,7 +636,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 166:
|
||||
case 167:
|
||||
case 168:
|
||||
case 181:
|
||||
case 169:
|
||||
case 182:
|
||||
case 183:
|
||||
case 184:
|
||||
|
|
@ -646,8 +645,9 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 187:
|
||||
case 188:
|
||||
case 189:
|
||||
case 193:
|
||||
case 196:
|
||||
case 190:
|
||||
case 194:
|
||||
case 197:
|
||||
return aarch64_ins_regno (self, info, code, inst, errors);
|
||||
case 13:
|
||||
return aarch64_ins_reg_extended (self, info, code, inst, errors);
|
||||
|
|
@ -659,7 +659,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 31:
|
||||
case 32:
|
||||
case 33:
|
||||
case 198:
|
||||
case 199:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 34:
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
|
|
@ -693,9 +693,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 79:
|
||||
case 80:
|
||||
case 81:
|
||||
case 156:
|
||||
case 158:
|
||||
case 173:
|
||||
case 157:
|
||||
case 159:
|
||||
case 174:
|
||||
case 175:
|
||||
case 176:
|
||||
|
|
@ -703,6 +702,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 178:
|
||||
case 179:
|
||||
case 180:
|
||||
case 181:
|
||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||
case 42:
|
||||
case 43:
|
||||
|
|
@ -712,10 +712,10 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 46:
|
||||
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
|
||||
case 50:
|
||||
case 147:
|
||||
case 148:
|
||||
return aarch64_ins_fpimm (self, info, code, inst, errors);
|
||||
case 67:
|
||||
case 154:
|
||||
case 155:
|
||||
return aarch64_ins_limm (self, info, code, inst, errors);
|
||||
case 68:
|
||||
return aarch64_ins_aimm (self, info, code, inst, errors);
|
||||
|
|
@ -725,68 +725,69 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
return aarch64_ins_fbits (self, info, code, inst, errors);
|
||||
case 72:
|
||||
case 73:
|
||||
case 152:
|
||||
case 153:
|
||||
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
|
||||
case 74:
|
||||
case 151:
|
||||
case 152:
|
||||
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
|
||||
case 75:
|
||||
case 76:
|
||||
return aarch64_ins_cond (self, info, code, inst, errors);
|
||||
case 82:
|
||||
case 91:
|
||||
case 92:
|
||||
return aarch64_ins_addr_simple (self, info, code, inst, errors);
|
||||
case 83:
|
||||
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
|
||||
return aarch64_ins_addr_simple_2 (self, info, code, inst, errors);
|
||||
case 84:
|
||||
return aarch64_ins_addr_regoff (self, info, code, inst, errors);
|
||||
case 85:
|
||||
case 86:
|
||||
case 88:
|
||||
case 90:
|
||||
return aarch64_ins_addr_simm (self, info, code, inst, errors);
|
||||
case 87:
|
||||
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
|
||||
case 89:
|
||||
case 91:
|
||||
return aarch64_ins_addr_simm (self, info, code, inst, errors);
|
||||
case 88:
|
||||
return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
|
||||
case 90:
|
||||
return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
|
||||
case 92:
|
||||
return aarch64_ins_addr_offset (self, info, code, inst, errors);
|
||||
case 93:
|
||||
return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
|
||||
return aarch64_ins_addr_offset (self, info, code, inst, errors);
|
||||
case 94:
|
||||
return aarch64_ins_sysreg (self, info, code, inst, errors);
|
||||
return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
|
||||
case 95:
|
||||
return aarch64_ins_pstatefield (self, info, code, inst, errors);
|
||||
return aarch64_ins_sysreg (self, info, code, inst, errors);
|
||||
case 96:
|
||||
return aarch64_ins_pstatefield (self, info, code, inst, errors);
|
||||
case 97:
|
||||
case 98:
|
||||
case 99:
|
||||
case 100:
|
||||
return aarch64_ins_sysins_op (self, info, code, inst, errors);
|
||||
case 101:
|
||||
return aarch64_ins_sysins_op (self, info, code, inst, errors);
|
||||
case 102:
|
||||
return aarch64_ins_barrier (self, info, code, inst, errors);
|
||||
case 103:
|
||||
return aarch64_ins_prfop (self, info, code, inst, errors);
|
||||
return aarch64_ins_barrier (self, info, code, inst, errors);
|
||||
case 104:
|
||||
return aarch64_ins_prfop (self, info, code, inst, errors);
|
||||
case 105:
|
||||
return aarch64_ins_hint (self, info, code, inst, errors);
|
||||
case 106:
|
||||
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
|
||||
return aarch64_ins_hint (self, info, code, inst, errors);
|
||||
case 107:
|
||||
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
|
||||
case 108:
|
||||
case 109:
|
||||
case 110:
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
|
||||
case 111:
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
|
||||
case 112:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
|
||||
case 113:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
|
||||
case 114:
|
||||
case 115:
|
||||
case 116:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
|
||||
case 117:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
|
||||
case 118:
|
||||
case 119:
|
||||
case 120:
|
||||
|
|
@ -799,8 +800,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 127:
|
||||
case 128:
|
||||
case 129:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
|
||||
case 130:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
|
||||
case 131:
|
||||
case 132:
|
||||
case 133:
|
||||
|
|
@ -808,48 +809,49 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 135:
|
||||
case 136:
|
||||
case 137:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
|
||||
case 138:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
|
||||
case 139:
|
||||
case 140:
|
||||
case 141:
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
|
||||
case 142:
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
|
||||
case 143:
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
|
||||
case 144:
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
|
||||
case 145:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
|
||||
case 146:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
|
||||
case 147:
|
||||
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
|
||||
case 148:
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
|
||||
case 149:
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
|
||||
case 150:
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
|
||||
case 151:
|
||||
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
|
||||
case 153:
|
||||
case 154:
|
||||
return aarch64_ins_inv_limm (self, info, code, inst, errors);
|
||||
case 155:
|
||||
case 156:
|
||||
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
|
||||
case 157:
|
||||
case 158:
|
||||
return aarch64_ins_sve_scale (self, info, code, inst, errors);
|
||||
case 169:
|
||||
case 170:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
|
||||
case 171:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
|
||||
case 172:
|
||||
case 173:
|
||||
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
|
||||
case 190:
|
||||
case 191:
|
||||
case 192:
|
||||
case 193:
|
||||
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
|
||||
case 194:
|
||||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||
case 195:
|
||||
case 197:
|
||||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||
case 196:
|
||||
case 198:
|
||||
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -618,6 +618,17 @@ aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
|||
return TRUE;
|
||||
}
|
||||
|
||||
/* Encode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!. */
|
||||
bfd_boolean
|
||||
aarch64_ins_addr_simple_2 (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst,
|
||||
aarch64_operand_error *errors)
|
||||
|
||||
{
|
||||
return aarch64_ins_addr_simple (self, info, code, inst, errors);
|
||||
}
|
||||
|
||||
/* Encode the address operand for e.g.
|
||||
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
|
||||
bfd_boolean
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@ AARCH64_DECL_OPD_INSERTER (ins_limm);
|
|||
AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_ft);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_addr_simple_2);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_addr_offset);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -985,6 +985,23 @@ aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
|||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Decode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!. */
|
||||
bfd_boolean
|
||||
aarch64_ext_addr_simple_2 (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
aarch64_opnd_info *info,
|
||||
aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED,
|
||||
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
|
||||
{
|
||||
/* Rn */
|
||||
info->addr.base_regno = extract_field (FLD_Rn, code, 0);
|
||||
info->addr.writeback = 1;
|
||||
info->addr.preind = 1;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* Decode the address operand for e.g.
|
||||
stlur <Xt>, [<Xn|SP>{, <amount>}]. */
|
||||
bfd_boolean
|
||||
|
|
|
|||
|
|
@ -82,6 +82,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_limm);
|
|||
AARCH64_DECL_OPD_EXTRACTOR (ext_inv_limm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_ft);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple_2);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_offset);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm);
|
||||
|
|
|
|||
|
|
@ -107,6 +107,7 @@ const struct aarch64_operand aarch64_operands[] =
|
|||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a writeback address with base register (no offset)"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
|
||||
|
|
@ -256,24 +257,24 @@ static const unsigned op_enum_table [] =
|
|||
925,
|
||||
931,
|
||||
932,
|
||||
983,
|
||||
984,
|
||||
985,
|
||||
986,
|
||||
987,
|
||||
988,
|
||||
12,
|
||||
636,
|
||||
637,
|
||||
1178,
|
||||
1180,
|
||||
1182,
|
||||
990,
|
||||
1184,
|
||||
992,
|
||||
1183,
|
||||
1181,
|
||||
1179,
|
||||
318,
|
||||
624,
|
||||
635,
|
||||
634,
|
||||
988,
|
||||
990,
|
||||
631,
|
||||
628,
|
||||
620,
|
||||
|
|
@ -283,7 +284,7 @@ static const unsigned op_enum_table [] =
|
|||
630,
|
||||
632,
|
||||
633,
|
||||
998,
|
||||
1000,
|
||||
664,
|
||||
667,
|
||||
670,
|
||||
|
|
@ -300,17 +301,17 @@ static const unsigned op_enum_table [] =
|
|||
391,
|
||||
413,
|
||||
415,
|
||||
1251,
|
||||
1256,
|
||||
1249,
|
||||
1248,
|
||||
1252,
|
||||
1259,
|
||||
1261,
|
||||
1262,
|
||||
1253,
|
||||
1258,
|
||||
1264,
|
||||
1251,
|
||||
1250,
|
||||
1254,
|
||||
1261,
|
||||
1263,
|
||||
1264,
|
||||
1260,
|
||||
1266,
|
||||
1265,
|
||||
131,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1602,6 +1602,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
|||
break;
|
||||
case ldst_imm9:
|
||||
case ldstpair_indexed:
|
||||
case ldstgv_indexed:
|
||||
case asisdlsep:
|
||||
case asisdlsop:
|
||||
if (opnd->addr.writeback == 0)
|
||||
|
|
@ -3556,6 +3557,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||
snprintf (buf, size, "[%s]", name);
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_ADDR_SIMPLE_2:
|
||||
name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
|
||||
snprintf (buf, size, "[%s]!", name);
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_ADDR_REGOFF:
|
||||
case AARCH64_OPND_SVE_ADDR_R:
|
||||
case AARCH64_OPND_SVE_ADDR_RR:
|
||||
|
|
|
|||
|
|
@ -3324,6 +3324,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
|
||||
RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
|
||||
RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
|
||||
MEMTAG_INSN ("ldgv", 0xd9e00000, 0xfffffc00, ldstgv_indexed, OP2 (Rt, ADDR_SIMPLE_2), QL_STLX, 0),
|
||||
MEMTAG_INSN ("stgv", 0xd9a00000, 0xfffffc00, ldstgv_indexed, OP2 (Rt, ADDR_SIMPLE_2), QL_STLX, 0),
|
||||
/* Limited Ordering Regions load/store instructions. */
|
||||
_LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
|
||||
_LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
|
||||
|
|
@ -4648,6 +4650,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
F(FLD_imm26), "26-bit PC-relative address") \
|
||||
Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \
|
||||
"an address with base register (no offset)") \
|
||||
Y(ADDRESS, addr_simple_2, "ADDR_SIMPLE_2", 0, F(), \
|
||||
"a writeback address with base register (no offset)") \
|
||||
Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \
|
||||
"an address with register offset") \
|
||||
Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \
|
||||
|
|
|
|||
Loading…
Reference in New Issue