OpenE2K
/
binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Fix 3 DV bugs, and a few minor cleanups. 

gas/
	* config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle
	postincrement modified registers.  Handle IA64_OPND_R3_2 addl
	source registers.
	(note_register_values): Handle IA64_OPND_R3_2 operands.
gas/testsuite/
	* gas/ia64/dv-raw-err.s: Add new tests for addl and postinc.
	* gas/ia64/dv-raw-err.l: Likewise.
	* gas/ia64/dv-waw-err.l: Update sed pattern.
	* gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment.
	* gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate.
include/opcode/
	* ia64.h (IA64_OPCODE_POSTINC): New.
opcodes/
	* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds.  Delete
	break, mov-immediate, nop.
	* ia64-opc-f.c: Delete fpsub instructions.
	* ia64-opc-m.c: Add POSTINC to all instructions with postincrement
	address operand.  Rewrite using macros to avoid long lines.
	* ia64-opc.h (POSTINC): Define.
	* ia64-asmtab.c: Regenerate.
This commit is contained in:
Jim Wilson 2000-08-16 23:20:15 +00:00
parent d670a150a1
commit 50b81f1903
17 changed files with 6323 additions and 6100 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2000-08-16 Jim Wilson <wilson@cygnus.com>
* config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle
postincrement modified registers. Handle IA64_OPND_R3_2 addl
source registers.
(note_register_values): Handle IA64_OPND_R3_2 operands.
2000-08-16 Jason Eckhardt <jle@cygnus.com>
* config/tc-i860.c (md_operand): Silly typo fixed.

38
gas/config/tc-ia64.c
View File

@ -6820,17 +6820,23 @@ dep->name, idesc->name, (rsrc_write?"write":"read"), note)
{
if (rsrc_write)
{
for (i=0;i < idesc->num_outputs;i++)
{
if (idesc->operands[i] == IA64_OPND_R1
|| idesc->operands[i] == IA64_OPND_R2
|| idesc->operands[i] == IA64_OPND_R3)
{
specs[count] = tmpl;
specs[count++].index =
CURR_SLOT.opnd[i].X_add_number - REG_GR;
}
}
for (i= 0; i < idesc->num_outputs; i++)
if (idesc->operands[i] == IA64_OPND_R1
|| idesc->operands[i] == IA64_OPND_R2
|| idesc->operands[i] == IA64_OPND_R3)
{
specs[count] = tmpl;
specs[count++].index =
CURR_SLOT.opnd[i].X_add_number - REG_GR;
}
if (idesc->flags & IA64_OPCODE_POSTINC)
for (i = 0; i < NELEMS (idesc->operands); i++)
if (idesc->operands[i] == IA64_OPND_MR3)
{
specs[count] = tmpl;
specs[count++].index =
CURR_SLOT.opnd[i].X_add_number - REG_GR;
}
}
else
{
@ -6849,7 +6855,9 @@ dep->name, idesc->name, (rsrc_write?"write":"read"), note)
|| ((i >= idesc->num_outputs)
&& (idesc->operands[i] == IA64_OPND_R1
|| idesc->operands[i] == IA64_OPND_R2
|| idesc->operands[i] == IA64_OPND_R3)))
|| idesc->operands[i] == IA64_OPND_R3
/* addl source register. */
|| idesc->operands[i] == IA64_OPND_R3_2)))
{
specs[count] = tmpl;
specs[count++].index =
@ -7681,6 +7689,12 @@ note_register_values (idesc)
if (regno > 0 && regno < NELEMS(gr_values))
gr_values[regno].known = 0;
}
else if (idesc->operands[i] == IA64_OPND_R3_2)
{
int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
if (regno > 0 && regno < 4)
gr_values[regno].known = 0;
}
else if (idesc->operands[i] == IA64_OPND_P1
|| idesc->operands[i] == IA64_OPND_P2)
{

8
gas/testsuite/ChangeLog
View File

@ -1,3 +1,11 @@
2000-08-16 Jim Wilson <wilson@cygnus.com>
* gas/ia64/dv-raw-err.s: Add new tests for addl and postinc.
* gas/ia64/dv-raw-err.l: Likewise.
* gas/ia64/dv-waw-err.l: Update sed pattern.
* gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment.
* gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate.
2000-08-16 Nick Clifton <nickc@redhat.com>
* gas/arm/inst.s: Add tests for edge cases of shift based

4
gas/testsuite/gas/ia64/dv-raw-err.l
View File

@ -265,3 +265,7 @@
.*:542: Warning: This is the location of the conflicting usage
.*:546: Warning: Use of 'mov' .* RAW dependency 'RR#' \(impliedf\)
.*:545: Warning: This is the location of the conflicting usage
.*:555: Warning: Use of 'addl' .* RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 2
.*:554: Warning: This is the location of the conflicting usage
.*:559: Warning: Use of 'mov' violates RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 32
.*:558: Warning: This is the location of the conflicting usage

12
gas/testsuite/gas/ia64/dv-raw-err.s
View File

@ -545,5 +545,17 @@
mov rr[r4] = r5
mov r6 = rr[r7] // impliedf
;;
srlz.d
;;
// RSE
// GR%, additional cases
// addl
mov r2 = r32
addl r3 = 12345, r2 // impliedf, IA64_OPND_R3_2
;;
// postinc
ld8 r2 = [r32], 8
mov r8 = r32 // impliedf
;;
L:

2
gas/testsuite/gas/ia64/dv-waw-err.l
View File

@ -349,5 +349,5 @@
.*:504: Warning: This is the location of the conflicting usage
.*:508: Warning: Use of 'mov' .* WAW dependency 'PSR\.up' \(impliedf\)
.*:507: Warning: This is the location of the conflicting usage
.*:513: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\)
.*:513: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\), specific resource number is 7
.*:512: Warning: This is the location of the conflicting usage

595
gas/testsuite/gas/ia64/opc-f.d
View File

File diff suppressed because it is too large Load Diff

4
gas/testsuite/gas/ia64/opc-f.pl
View File

@ -14,8 +14,8 @@ foreach $i ( "fma", "fma.s", "fma.d", "fpma",
}
foreach $i ( "fmpy", "fmpy.s", "fmpy.d", "fpmpy",
"fadd", "fadd.s", "fadd.d", #"fpadd", ??? ias doesn't eat it
"fsub", "fsub.s", "fsub.d", "fpsub",
"fadd", "fadd.s", "fadd.d",
"fsub", "fsub.s", "fsub.d",
"fnmpy", "fnmpy.s", "fnmpy.d", "fpnmpy" ) {
foreach $s (@sf) {
print "\t${i}${s} f4 = f5, f6\n";

6
gas/testsuite/gas/ia64/opc-f.s
View File

@ -134,12 +134,6 @@ _start:
fsub.d.s2 f4 = f5, f6
fsub.d.s3 f4 = f5, f6
fpsub f4 = f5, f6
fpsub.s0 f4 = f5, f6
fpsub.s1 f4 = f5, f6
fpsub.s2 f4 = f5, f6
fpsub.s3 f4 = f5, f6
fnmpy f4 = f5, f6
fnmpy.s0 f4 = f5, f6
fnmpy.s1 f4 = f5, f6

4
include/opcode/ChangeLog
View File

@ -1,3 +1,7 @@
2000-08-16 Jim Wilson <wilson@cygnus.com>
* ia64.h (IA64_OPCODE_POSTINC): New.
2000-08-15 H.J. Lu <hjl@gnu.org>
* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the

3
include/opcode/ia64.h
View File

@ -300,7 +300,8 @@ struct ia64_opcode
#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */
#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */
#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */
#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */
/* A macro to extract the major opcode from an instruction. */
#define IA64_OP(i) (((i) >> 37) & 0xf)

10
opcodes/ChangeLog
View File

@ -1,3 +1,13 @@
2000-08-16 Jim Wilson <wilson@cygnus.com>
* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete
break, mov-immediate, nop.
* ia64-opc-f.c: Delete fpsub instructions.
* ia64-opc-m.c: Add POSTINC to all instructions with postincrement
address operand. Rewrite using macros to avoid long lines.
* ia64-opc.h (POSTINC): Define.
* ia64-asmtab.c: Regenerate.
2000-08-15 Jim Wilson <wilson@cygnus.com>
* ia64-ic.tbl: Add missing entries.

10837
opcodes/ia64-asmtab.c
View File

File diff suppressed because it is too large Load Diff

2
opcodes/ia64-ic.tbl
View File

@ -202,7 +202,7 @@ pr-norm-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==]
pr-norm-writers-int; IC:pr-gen-writers-int[Field(ctype)==]
pr-or-writers; IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}]
pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, break, nop.b, nop, IC:ReservedBQP
pr-readers-nobr-nomovpr; add, addp4, and, andcm, break.f, break.i, break.m, break.x, break, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-immediate, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, nop, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, tbit, thash, tnat, tpa, ttag, IC:unpack, IC:xchg, xma, xmpy, xor, IC:zxt
pr-readers-nobr-nomovpr; add, addl, addp4, adds, and, andcm, break.f, break.i, break.m, break.x, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, tbit, thash, tnat, tpa, ttag, IC:unpack, IC:xchg, xma, xmpy, xor, IC:zxt
pr-unc-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==unc]+11, fprcpa+11, fprsqrta+11, frcpa+11, frsqrta+11
pr-unc-writers-int; IC:pr-gen-writers-int[Field(ctype)==unc]+11
pr-writers; IC:pr-writers-int, IC:pr-writers-fp

6
opcodes/ia64-opc-f.c
View File

@ -530,12 +530,6 @@ struct ia64_opcode ia64_opcodes_f[] =
{"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}},
{"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}},
{"fpsub.s0", f, OpXaSfF4 (0xb, 1, 0, 1), {F1, F3, F2}, PSEUDO},
{"fpsub", f, OpXaSfF4 (0xb, 1, 0, 1), {F1, F3, F2}, PSEUDO},
{"fpsub.s1", f, OpXaSfF4 (0xb, 1, 1, 1), {F1, F3, F2}, PSEUDO},
{"fpsub.s2", f, OpXaSfF4 (0xb, 1, 2, 1), {F1, F3, F2}, PSEUDO},
{"fpsub.s3", f, OpXaSfF4 (0xb, 1, 3, 1), {F1, F3, F2}, PSEUDO},
{"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO},

884
opcodes/ia64-opc-m.c
View File

@ -262,117 +262,119 @@ struct ia64_opcode ia64_opcodes_m[] =
{"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}},
/* integer load w/increment by register */
{"ld1", M, OpMXX6aHint (4, 1, 0, 0x00, 0), {R1, MR3, R2}},
{"ld1.nt1", M, OpMXX6aHint (4, 1, 0, 0x00, 1), {R1, MR3, R2}},
{"ld1.nta", M, OpMXX6aHint (4, 1, 0, 0x00, 3), {R1, MR3, R2}},
{"ld2", M, OpMXX6aHint (4, 1, 0, 0x01, 0), {R1, MR3, R2}},
{"ld2.nt1", M, OpMXX6aHint (4, 1, 0, 0x01, 1), {R1, MR3, R2}},
{"ld2.nta", M, OpMXX6aHint (4, 1, 0, 0x01, 3), {R1, MR3, R2}},
{"ld4", M, OpMXX6aHint (4, 1, 0, 0x02, 0), {R1, MR3, R2}},
{"ld4.nt1", M, OpMXX6aHint (4, 1, 0, 0x02, 1), {R1, MR3, R2}},
{"ld4.nta", M, OpMXX6aHint (4, 1, 0, 0x02, 3), {R1, MR3, R2}},
{"ld8", M, OpMXX6aHint (4, 1, 0, 0x03, 0), {R1, MR3, R2}},
{"ld8.nt1", M, OpMXX6aHint (4, 1, 0, 0x03, 1), {R1, MR3, R2}},
{"ld8.nta", M, OpMXX6aHint (4, 1, 0, 0x03, 3), {R1, MR3, R2}},
{"ld1.s", M, OpMXX6aHint (4, 1, 0, 0x04, 0), {R1, MR3, R2}},
{"ld1.s.nt1", M, OpMXX6aHint (4, 1, 0, 0x04, 1), {R1, MR3, R2}},
{"ld1.s.nta", M, OpMXX6aHint (4, 1, 0, 0x04, 3), {R1, MR3, R2}},
{"ld2.s", M, OpMXX6aHint (4, 1, 0, 0x05, 0), {R1, MR3, R2}},
{"ld2.s.nt1", M, OpMXX6aHint (4, 1, 0, 0x05, 1), {R1, MR3, R2}},
{"ld2.s.nta", M, OpMXX6aHint (4, 1, 0, 0x05, 3), {R1, MR3, R2}},
{"ld4.s", M, OpMXX6aHint (4, 1, 0, 0x06, 0), {R1, MR3, R2}},
{"ld4.s.nt1", M, OpMXX6aHint (4, 1, 0, 0x06, 1), {R1, MR3, R2}},
{"ld4.s.nta", M, OpMXX6aHint (4, 1, 0, 0x06, 3), {R1, MR3, R2}},
{"ld8.s", M, OpMXX6aHint (4, 1, 0, 0x07, 0), {R1, MR3, R2}},
{"ld8.s.nt1", M, OpMXX6aHint (4, 1, 0, 0x07, 1), {R1, MR3, R2}},
{"ld8.s.nta", M, OpMXX6aHint (4, 1, 0, 0x07, 3), {R1, MR3, R2}},
{"ld1.a", M, OpMXX6aHint (4, 1, 0, 0x08, 0), {R1, MR3, R2}},
{"ld1.a.nt1", M, OpMXX6aHint (4, 1, 0, 0x08, 1), {R1, MR3, R2}},
{"ld1.a.nta", M, OpMXX6aHint (4, 1, 0, 0x08, 3), {R1, MR3, R2}},
{"ld2.a", M, OpMXX6aHint (4, 1, 0, 0x09, 0), {R1, MR3, R2}},
{"ld2.a.nt1", M, OpMXX6aHint (4, 1, 0, 0x09, 1), {R1, MR3, R2}},
{"ld2.a.nta", M, OpMXX6aHint (4, 1, 0, 0x09, 3), {R1, MR3, R2}},
{"ld4.a", M, OpMXX6aHint (4, 1, 0, 0x0a, 0), {R1, MR3, R2}},
{"ld4.a.nt1", M, OpMXX6aHint (4, 1, 0, 0x0a, 1), {R1, MR3, R2}},
{"ld4.a.nta", M, OpMXX6aHint (4, 1, 0, 0x0a, 3), {R1, MR3, R2}},
{"ld8.a", M, OpMXX6aHint (4, 1, 0, 0x0b, 0), {R1, MR3, R2}},
{"ld8.a.nt1", M, OpMXX6aHint (4, 1, 0, 0x0b, 1), {R1, MR3, R2}},
{"ld8.a.nta", M, OpMXX6aHint (4, 1, 0, 0x0b, 3), {R1, MR3, R2}},
{"ld1.sa", M, OpMXX6aHint (4, 1, 0, 0x0c, 0), {R1, MR3, R2}},
{"ld1.sa.nt1", M, OpMXX6aHint (4, 1, 0, 0x0c, 1), {R1, MR3, R2}},
{"ld1.sa.nta", M, OpMXX6aHint (4, 1, 0, 0x0c, 3), {R1, MR3, R2}},
{"ld2.sa", M, OpMXX6aHint (4, 1, 0, 0x0d, 0), {R1, MR3, R2}},
{"ld2.sa.nt1", M, OpMXX6aHint (4, 1, 0, 0x0d, 1), {R1, MR3, R2}},
{"ld2.sa.nta", M, OpMXX6aHint (4, 1, 0, 0x0d, 3), {R1, MR3, R2}},
{"ld4.sa", M, OpMXX6aHint (4, 1, 0, 0x0e, 0), {R1, MR3, R2}},
{"ld4.sa.nt1", M, OpMXX6aHint (4, 1, 0, 0x0e, 1), {R1, MR3, R2}},
{"ld4.sa.nta", M, OpMXX6aHint (4, 1, 0, 0x0e, 3), {R1, MR3, R2}},
{"ld8.sa", M, OpMXX6aHint (4, 1, 0, 0x0f, 0), {R1, MR3, R2}},
{"ld8.sa.nt1", M, OpMXX6aHint (4, 1, 0, 0x0f, 1), {R1, MR3, R2}},
{"ld8.sa.nta", M, OpMXX6aHint (4, 1, 0, 0x0f, 3), {R1, MR3, R2}},
{"ld1.bias", M, OpMXX6aHint (4, 1, 0, 0x10, 0), {R1, MR3, R2}},
{"ld1.bias.nt1", M, OpMXX6aHint (4, 1, 0, 0x10, 1), {R1, MR3, R2}},
{"ld1.bias.nta", M, OpMXX6aHint (4, 1, 0, 0x10, 3), {R1, MR3, R2}},
{"ld2.bias", M, OpMXX6aHint (4, 1, 0, 0x11, 0), {R1, MR3, R2}},
{"ld2.bias.nt1", M, OpMXX6aHint (4, 1, 0, 0x11, 1), {R1, MR3, R2}},
{"ld2.bias.nta", M, OpMXX6aHint (4, 1, 0, 0x11, 3), {R1, MR3, R2}},
{"ld4.bias", M, OpMXX6aHint (4, 1, 0, 0x12, 0), {R1, MR3, R2}},
{"ld4.bias.nt1", M, OpMXX6aHint (4, 1, 0, 0x12, 1), {R1, MR3, R2}},
{"ld4.bias.nta", M, OpMXX6aHint (4, 1, 0, 0x12, 3), {R1, MR3, R2}},
{"ld8.bias", M, OpMXX6aHint (4, 1, 0, 0x13, 0), {R1, MR3, R2}},
{"ld8.bias.nt1", M, OpMXX6aHint (4, 1, 0, 0x13, 1), {R1, MR3, R2}},
{"ld8.bias.nta", M, OpMXX6aHint (4, 1, 0, 0x13, 3), {R1, MR3, R2}},
{"ld1.acq", M, OpMXX6aHint (4, 1, 0, 0x14, 0), {R1, MR3, R2}},
{"ld1.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x14, 1), {R1, MR3, R2}},
{"ld1.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x14, 3), {R1, MR3, R2}},
{"ld2.acq", M, OpMXX6aHint (4, 1, 0, 0x15, 0), {R1, MR3, R2}},
{"ld2.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x15, 1), {R1, MR3, R2}},
{"ld2.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x15, 3), {R1, MR3, R2}},
{"ld4.acq", M, OpMXX6aHint (4, 1, 0, 0x16, 0), {R1, MR3, R2}},
{"ld4.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x16, 1), {R1, MR3, R2}},
{"ld4.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x16, 3), {R1, MR3, R2}},
{"ld8.acq", M, OpMXX6aHint (4, 1, 0, 0x17, 0), {R1, MR3, R2}},
{"ld8.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x17, 1), {R1, MR3, R2}},
{"ld8.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x17, 3), {R1, MR3, R2}},
{"ld8.fill", M, OpMXX6aHint (4, 1, 0, 0x1b, 0), {R1, MR3, R2}},
{"ld8.fill.nt1", M, OpMXX6aHint (4, 1, 0, 0x1b, 1), {R1, MR3, R2}},
{"ld8.fill.nta", M, OpMXX6aHint (4, 1, 0, 0x1b, 3), {R1, MR3, R2}},
{"ld1.c.clr", M, OpMXX6aHint (4, 1, 0, 0x20, 0), {R1, MR3, R2}},
{"ld1.c.clr.nt1", M, OpMXX6aHint (4, 1, 0, 0x20, 1), {R1, MR3, R2}},
{"ld1.c.clr.nta", M, OpMXX6aHint (4, 1, 0, 0x20, 3), {R1, MR3, R2}},
{"ld2.c.clr", M, OpMXX6aHint (4, 1, 0, 0x21, 0), {R1, MR3, R2}},
{"ld2.c.clr.nt1", M, OpMXX6aHint (4, 1, 0, 0x21, 1), {R1, MR3, R2}},
{"ld2.c.clr.nta", M, OpMXX6aHint (4, 1, 0, 0x21, 3), {R1, MR3, R2}},
{"ld4.c.clr", M, OpMXX6aHint (4, 1, 0, 0x22, 0), {R1, MR3, R2}},
{"ld4.c.clr.nt1", M, OpMXX6aHint (4, 1, 0, 0x22, 1), {R1, MR3, R2}},
{"ld4.c.clr.nta", M, OpMXX6aHint (4, 1, 0, 0x22, 3), {R1, MR3, R2}},
{"ld8.c.clr", M, OpMXX6aHint (4, 1, 0, 0x23, 0), {R1, MR3, R2}},
{"ld8.c.clr.nt1", M, OpMXX6aHint (4, 1, 0, 0x23, 1), {R1, MR3, R2}},
{"ld8.c.clr.nta", M, OpMXX6aHint (4, 1, 0, 0x23, 3), {R1, MR3, R2}},
{"ld1.c.nc", M, OpMXX6aHint (4, 1, 0, 0x24, 0), {R1, MR3, R2}},
{"ld1.c.nc.nt1", M, OpMXX6aHint (4, 1, 0, 0x24, 1), {R1, MR3, R2}},
{"ld1.c.nc.nta", M, OpMXX6aHint (4, 1, 0, 0x24, 3), {R1, MR3, R2}},
{"ld2.c.nc", M, OpMXX6aHint (4, 1, 0, 0x25, 0), {R1, MR3, R2}},
{"ld2.c.nc.nt1", M, OpMXX6aHint (4, 1, 0, 0x25, 1), {R1, MR3, R2}},
{"ld2.c.nc.nta", M, OpMXX6aHint (4, 1, 0, 0x25, 3), {R1, MR3, R2}},
{"ld4.c.nc", M, OpMXX6aHint (4, 1, 0, 0x26, 0), {R1, MR3, R2}},
{"ld4.c.nc.nt1", M, OpMXX6aHint (4, 1, 0, 0x26, 1), {R1, MR3, R2}},
{"ld4.c.nc.nta", M, OpMXX6aHint (4, 1, 0, 0x26, 3), {R1, MR3, R2}},
{"ld8.c.nc", M, OpMXX6aHint (4, 1, 0, 0x27, 0), {R1, MR3, R2}},
{"ld8.c.nc.nt1", M, OpMXX6aHint (4, 1, 0, 0x27, 1), {R1, MR3, R2}},
{"ld8.c.nc.nta", M, OpMXX6aHint (4, 1, 0, 0x27, 3), {R1, MR3, R2}},
{"ld1.c.clr.acq", M, OpMXX6aHint (4, 1, 0, 0x28, 0), {R1, MR3, R2}},
{"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x28, 1), {R1, MR3, R2}},
{"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x28, 3), {R1, MR3, R2}},
{"ld2.c.clr.acq", M, OpMXX6aHint (4, 1, 0, 0x29, 0), {R1, MR3, R2}},
{"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x29, 1), {R1, MR3, R2}},
{"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x29, 3), {R1, MR3, R2}},
{"ld4.c.clr.acq", M, OpMXX6aHint (4, 1, 0, 0x2a, 0), {R1, MR3, R2}},
{"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x2a, 1), {R1, MR3, R2}},
{"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x2a, 3), {R1, MR3, R2}},
{"ld8.c.clr.acq", M, OpMXX6aHint (4, 1, 0, 0x2b, 0), {R1, MR3, R2}},
{"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x2b, 1), {R1, MR3, R2}},
{"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x2b, 3), {R1, MR3, R2}},
#define LDINCREG(c,h) M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTINC,
{"ld1", LDINCREG (0x00, 0)},
{"ld1.nt1", LDINCREG (0x00, 1)},
{"ld1.nta", LDINCREG (0x00, 3)},
{"ld2", LDINCREG (0x01, 0)},
{"ld2.nt1", LDINCREG (0x01, 1)},
{"ld2.nta", LDINCREG (0x01, 3)},
{"ld4", LDINCREG (0x02, 0)},
{"ld4.nt1", LDINCREG (0x02, 1)},
{"ld4.nta", LDINCREG (0x02, 3)},
{"ld8", LDINCREG (0x03, 0)},
{"ld8.nt1", LDINCREG (0x03, 1)},
{"ld8.nta", LDINCREG (0x03, 3)},
{"ld1.s", LDINCREG (0x04, 0)},
{"ld1.s.nt1", LDINCREG (0x04, 1)},
{"ld1.s.nta", LDINCREG (0x04, 3)},
{"ld2.s", LDINCREG (0x05, 0)},
{"ld2.s.nt1", LDINCREG (0x05, 1)},
{"ld2.s.nta", LDINCREG (0x05, 3)},
{"ld4.s", LDINCREG (0x06, 0)},
{"ld4.s.nt1", LDINCREG (0x06, 1)},
{"ld4.s.nta", LDINCREG (0x06, 3)},
{"ld8.s", LDINCREG (0x07, 0)},
{"ld8.s.nt1", LDINCREG (0x07, 1)},
{"ld8.s.nta", LDINCREG (0x07, 3)},
{"ld1.a", LDINCREG (0x08, 0)},
{"ld1.a.nt1", LDINCREG (0x08, 1)},
{"ld1.a.nta", LDINCREG (0x08, 3)},
{"ld2.a", LDINCREG (0x09, 0)},
{"ld2.a.nt1", LDINCREG (0x09, 1)},
{"ld2.a.nta", LDINCREG (0x09, 3)},
{"ld4.a", LDINCREG (0x0a, 0)},
{"ld4.a.nt1", LDINCREG (0x0a, 1)},
{"ld4.a.nta", LDINCREG (0x0a, 3)},
{"ld8.a", LDINCREG (0x0b, 0)},
{"ld8.a.nt1", LDINCREG (0x0b, 1)},
{"ld8.a.nta", LDINCREG (0x0b, 3)},
{"ld1.sa", LDINCREG (0x0c, 0)},
{"ld1.sa.nt1", LDINCREG (0x0c, 1)},
{"ld1.sa.nta", LDINCREG (0x0c, 3)},
{"ld2.sa", LDINCREG (0x0d, 0)},
{"ld2.sa.nt1", LDINCREG (0x0d, 1)},
{"ld2.sa.nta", LDINCREG (0x0d, 3)},
{"ld4.sa", LDINCREG (0x0e, 0)},
{"ld4.sa.nt1", LDINCREG (0x0e, 1)},
{"ld4.sa.nta", LDINCREG (0x0e, 3)},
{"ld8.sa", LDINCREG (0x0f, 0)},
{"ld8.sa.nt1", LDINCREG (0x0f, 1)},
{"ld8.sa.nta", LDINCREG (0x0f, 3)},
{"ld1.bias", LDINCREG (0x10, 0)},
{"ld1.bias.nt1", LDINCREG (0x10, 1)},
{"ld1.bias.nta", LDINCREG (0x10, 3)},
{"ld2.bias", LDINCREG (0x11, 0)},
{"ld2.bias.nt1", LDINCREG (0x11, 1)},
{"ld2.bias.nta", LDINCREG (0x11, 3)},
{"ld4.bias", LDINCREG (0x12, 0)},
{"ld4.bias.nt1", LDINCREG (0x12, 1)},
{"ld4.bias.nta", LDINCREG (0x12, 3)},
{"ld8.bias", LDINCREG (0x13, 0)},
{"ld8.bias.nt1", LDINCREG (0x13, 1)},
{"ld8.bias.nta", LDINCREG (0x13, 3)},
{"ld1.acq", LDINCREG (0x14, 0)},
{"ld1.acq.nt1", LDINCREG (0x14, 1)},
{"ld1.acq.nta", LDINCREG (0x14, 3)},
{"ld2.acq", LDINCREG (0x15, 0)},
{"ld2.acq.nt1", LDINCREG (0x15, 1)},
{"ld2.acq.nta", LDINCREG (0x15, 3)},
{"ld4.acq", LDINCREG (0x16, 0)},
{"ld4.acq.nt1", LDINCREG (0x16, 1)},
{"ld4.acq.nta", LDINCREG (0x16, 3)},
{"ld8.acq", LDINCREG (0x17, 0)},
{"ld8.acq.nt1", LDINCREG (0x17, 1)},
{"ld8.acq.nta", LDINCREG (0x17, 3)},
{"ld8.fill", LDINCREG (0x1b, 0)},
{"ld8.fill.nt1", LDINCREG (0x1b, 1)},
{"ld8.fill.nta", LDINCREG (0x1b, 3)},
{"ld1.c.clr", LDINCREG (0x20, 0)},
{"ld1.c.clr.nt1", LDINCREG (0x20, 1)},
{"ld1.c.clr.nta", LDINCREG (0x20, 3)},
{"ld2.c.clr", LDINCREG (0x21, 0)},
{"ld2.c.clr.nt1", LDINCREG (0x21, 1)},
{"ld2.c.clr.nta", LDINCREG (0x21, 3)},
{"ld4.c.clr", LDINCREG (0x22, 0)},
{"ld4.c.clr.nt1", LDINCREG (0x22, 1)},
{"ld4.c.clr.nta", LDINCREG (0x22, 3)},
{"ld8.c.clr", LDINCREG (0x23, 0)},
{"ld8.c.clr.nt1", LDINCREG (0x23, 1)},
{"ld8.c.clr.nta", LDINCREG (0x23, 3)},
{"ld1.c.nc", LDINCREG (0x24, 0)},
{"ld1.c.nc.nt1", LDINCREG (0x24, 1)},
{"ld1.c.nc.nta", LDINCREG (0x24, 3)},
{"ld2.c.nc", LDINCREG (0x25, 0)},
{"ld2.c.nc.nt1", LDINCREG (0x25, 1)},
{"ld2.c.nc.nta", LDINCREG (0x25, 3)},
{"ld4.c.nc", LDINCREG (0x26, 0)},
{"ld4.c.nc.nt1", LDINCREG (0x26, 1)},
{"ld4.c.nc.nta", LDINCREG (0x26, 3)},
{"ld8.c.nc", LDINCREG (0x27, 0)},
{"ld8.c.nc.nt1", LDINCREG (0x27, 1)},
{"ld8.c.nc.nta", LDINCREG (0x27, 3)},
{"ld1.c.clr.acq", LDINCREG (0x28, 0)},
{"ld1.c.clr.acq.nt1", LDINCREG (0x28, 1)},
{"ld1.c.clr.acq.nta", LDINCREG (0x28, 3)},
{"ld2.c.clr.acq", LDINCREG (0x29, 0)},
{"ld2.c.clr.acq.nt1", LDINCREG (0x29, 1)},
{"ld2.c.clr.acq.nta", LDINCREG (0x29, 3)},
{"ld4.c.clr.acq", LDINCREG (0x2a, 0)},
{"ld4.c.clr.acq.nt1", LDINCREG (0x2a, 1)},
{"ld4.c.clr.acq.nta", LDINCREG (0x2a, 3)},
{"ld8.c.clr.acq", LDINCREG (0x2b, 0)},
{"ld8.c.clr.acq.nt1", LDINCREG (0x2b, 1)},
{"ld8.c.clr.acq.nta", LDINCREG (0x2b, 3)},
#undef LDINCREG
{"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}},
{"st1.nta", M, OpMXX6aHint (4, 0, 0, 0x30, 3), {MR3, R2}},
@ -451,137 +453,141 @@ struct ia64_opcode ia64_opcodes_m[] =
{"getf.d", M, OpMXX6a (4, 0, 1, 0x1f), {R1, F2}},
/* integer load w/increment by immediate */
{"ld1", M, OpX6aHint (5, 0x00, 0), {R1, MR3, IMM9b}},
{"ld1.nt1", M, OpX6aHint (5, 0x00, 1), {R1, MR3, IMM9b}},
{"ld1.nta", M, OpX6aHint (5, 0x00, 3), {R1, MR3, IMM9b}},
{"ld2", M, OpX6aHint (5, 0x01, 0), {R1, MR3, IMM9b}},
{"ld2.nt1", M, OpX6aHint (5, 0x01, 1), {R1, MR3, IMM9b}},
{"ld2.nta", M, OpX6aHint (5, 0x01, 3), {R1, MR3, IMM9b}},
{"ld4", M, OpX6aHint (5, 0x02, 0), {R1, MR3, IMM9b}},
{"ld4.nt1", M, OpX6aHint (5, 0x02, 1), {R1, MR3, IMM9b}},
{"ld4.nta", M, OpX6aHint (5, 0x02, 3), {R1, MR3, IMM9b}},
{"ld8", M, OpX6aHint (5, 0x03, 0), {R1, MR3, IMM9b}},
{"ld8.nt1", M, OpX6aHint (5, 0x03, 1), {R1, MR3, IMM9b}},
{"ld8.nta", M, OpX6aHint (5, 0x03, 3), {R1, MR3, IMM9b}},
{"ld1.s", M, OpX6aHint (5, 0x04, 0), {R1, MR3, IMM9b}},
{"ld1.s.nt1", M, OpX6aHint (5, 0x04, 1), {R1, MR3, IMM9b}},
{"ld1.s.nta", M, OpX6aHint (5, 0x04, 3), {R1, MR3, IMM9b}},
{"ld2.s", M, OpX6aHint (5, 0x05, 0), {R1, MR3, IMM9b}},
{"ld2.s.nt1", M, OpX6aHint (5, 0x05, 1), {R1, MR3, IMM9b}},
{"ld2.s.nta", M, OpX6aHint (5, 0x05, 3), {R1, MR3, IMM9b}},
{"ld4.s", M, OpX6aHint (5, 0x06, 0), {R1, MR3, IMM9b}},
{"ld4.s.nt1", M, OpX6aHint (5, 0x06, 1), {R1, MR3, IMM9b}},
{"ld4.s.nta", M, OpX6aHint (5, 0x06, 3), {R1, MR3, IMM9b}},
{"ld8.s", M, OpX6aHint (5, 0x07, 0), {R1, MR3, IMM9b}},
{"ld8.s.nt1", M, OpX6aHint (5, 0x07, 1), {R1, MR3, IMM9b}},
{"ld8.s.nta", M, OpX6aHint (5, 0x07, 3), {R1, MR3, IMM9b}},
{"ld1.a", M, OpX6aHint (5, 0x08, 0), {R1, MR3, IMM9b}},
{"ld1.a.nt1", M, OpX6aHint (5, 0x08, 1), {R1, MR3, IMM9b}},
{"ld1.a.nta", M, OpX6aHint (5, 0x08, 3), {R1, MR3, IMM9b}},
{"ld2.a", M, OpX6aHint (5, 0x09, 0), {R1, MR3, IMM9b}},
{"ld2.a.nt1", M, OpX6aHint (5, 0x09, 1), {R1, MR3, IMM9b}},
{"ld2.a.nta", M, OpX6aHint (5, 0x09, 3), {R1, MR3, IMM9b}},
{"ld4.a", M, OpX6aHint (5, 0x0a, 0), {R1, MR3, IMM9b}},
{"ld4.a.nt1", M, OpX6aHint (5, 0x0a, 1), {R1, MR3, IMM9b}},
{"ld4.a.nta", M, OpX6aHint (5, 0x0a, 3), {R1, MR3, IMM9b}},
{"ld8.a", M, OpX6aHint (5, 0x0b, 0), {R1, MR3, IMM9b}},
{"ld8.a.nt1", M, OpX6aHint (5, 0x0b, 1), {R1, MR3, IMM9b}},
{"ld8.a.nta", M, OpX6aHint (5, 0x0b, 3), {R1, MR3, IMM9b}},
{"ld1.sa", M, OpX6aHint (5, 0x0c, 0), {R1, MR3, IMM9b}},
{"ld1.sa.nt1", M, OpX6aHint (5, 0x0c, 1), {R1, MR3, IMM9b}},
{"ld1.sa.nta", M, OpX6aHint (5, 0x0c, 3), {R1, MR3, IMM9b}},
{"ld2.sa", M, OpX6aHint (5, 0x0d, 0), {R1, MR3, IMM9b}},
{"ld2.sa.nt1", M, OpX6aHint (5, 0x0d, 1), {R1, MR3, IMM9b}},
{"ld2.sa.nta", M, OpX6aHint (5, 0x0d, 3), {R1, MR3, IMM9b}},
{"ld4.sa", M, OpX6aHint (5, 0x0e, 0), {R1, MR3, IMM9b}},
{"ld4.sa.nt1", M, OpX6aHint (5, 0x0e, 1), {R1, MR3, IMM9b}},
{"ld4.sa.nta", M, OpX6aHint (5, 0x0e, 3), {R1, MR3, IMM9b}},
{"ld8.sa", M, OpX6aHint (5, 0x0f, 0), {R1, MR3, IMM9b}},
{"ld8.sa.nt1", M, OpX6aHint (5, 0x0f, 1), {R1, MR3, IMM9b}},
{"ld8.sa.nta", M, OpX6aHint (5, 0x0f, 3), {R1, MR3, IMM9b}},
{"ld1.bias", M, OpX6aHint (5, 0x10, 0), {R1, MR3, IMM9b}},
{"ld1.bias.nt1", M, OpX6aHint (5, 0x10, 1), {R1, MR3, IMM9b}},
{"ld1.bias.nta", M, OpX6aHint (5, 0x10, 3), {R1, MR3, IMM9b}},
{"ld2.bias", M, OpX6aHint (5, 0x11, 0), {R1, MR3, IMM9b}},
{"ld2.bias.nt1", M, OpX6aHint (5, 0x11, 1), {R1, MR3, IMM9b}},
{"ld2.bias.nta", M, OpX6aHint (5, 0x11, 3), {R1, MR3, IMM9b}},
{"ld4.bias", M, OpX6aHint (5, 0x12, 0), {R1, MR3, IMM9b}},
{"ld4.bias.nt1", M, OpX6aHint (5, 0x12, 1), {R1, MR3, IMM9b}},
{"ld4.bias.nta", M, OpX6aHint (5, 0x12, 3), {R1, MR3, IMM9b}},
{"ld8.bias", M, OpX6aHint (5, 0x13, 0), {R1, MR3, IMM9b}},
{"ld8.bias.nt1", M, OpX6aHint (5, 0x13, 1), {R1, MR3, IMM9b}},
{"ld8.bias.nta", M, OpX6aHint (5, 0x13, 3), {R1, MR3, IMM9b}},
{"ld1.acq", M, OpX6aHint (5, 0x14, 0), {R1, MR3, IMM9b}},
{"ld1.acq.nt1", M, OpX6aHint (5, 0x14, 1), {R1, MR3, IMM9b}},
{"ld1.acq.nta", M, OpX6aHint (5, 0x14, 3), {R1, MR3, IMM9b}},
{"ld2.acq", M, OpX6aHint (5, 0x15, 0), {R1, MR3, IMM9b}},
{"ld2.acq.nt1", M, OpX6aHint (5, 0x15, 1), {R1, MR3, IMM9b}},
{"ld2.acq.nta", M, OpX6aHint (5, 0x15, 3), {R1, MR3, IMM9b}},
{"ld4.acq", M, OpX6aHint (5, 0x16, 0), {R1, MR3, IMM9b}},
{"ld4.acq.nt1", M, OpX6aHint (5, 0x16, 1), {R1, MR3, IMM9b}},
{"ld4.acq.nta", M, OpX6aHint (5, 0x16, 3), {R1, MR3, IMM9b}},
{"ld8.acq", M, OpX6aHint (5, 0x17, 0), {R1, MR3, IMM9b}},
{"ld8.acq.nt1", M, OpX6aHint (5, 0x17, 1), {R1, MR3, IMM9b}},
{"ld8.acq.nta", M, OpX6aHint (5, 0x17, 3), {R1, MR3, IMM9b}},
{"ld8.fill", M, OpX6aHint (5, 0x1b, 0), {R1, MR3, IMM9b}},
{"ld8.fill.nt1", M, OpX6aHint (5, 0x1b, 1), {R1, MR3, IMM9b}},
{"ld8.fill.nta", M, OpX6aHint (5, 0x1b, 3), {R1, MR3, IMM9b}},
{"ld1.c.clr", M, OpX6aHint (5, 0x20, 0), {R1, MR3, IMM9b}},
{"ld1.c.clr.nt1", M, OpX6aHint (5, 0x20, 1), {R1, MR3, IMM9b}},
{"ld1.c.clr.nta", M, OpX6aHint (5, 0x20, 3), {R1, MR3, IMM9b}},
{"ld2.c.clr", M, OpX6aHint (5, 0x21, 0), {R1, MR3, IMM9b}},
{"ld2.c.clr.nt1", M, OpX6aHint (5, 0x21, 1), {R1, MR3, IMM9b}},
{"ld2.c.clr.nta", M, OpX6aHint (5, 0x21, 3), {R1, MR3, IMM9b}},
{"ld4.c.clr", M, OpX6aHint (5, 0x22, 0), {R1, MR3, IMM9b}},
{"ld4.c.clr.nt1", M, OpX6aHint (5, 0x22, 1), {R1, MR3, IMM9b}},
{"ld4.c.clr.nta", M, OpX6aHint (5, 0x22, 3), {R1, MR3, IMM9b}},
{"ld8.c.clr", M, OpX6aHint (5, 0x23, 0), {R1, MR3, IMM9b}},
{"ld8.c.clr.nt1", M, OpX6aHint (5, 0x23, 1), {R1, MR3, IMM9b}},
{"ld8.c.clr.nta", M, OpX6aHint (5, 0x23, 3), {R1, MR3, IMM9b}},
{"ld1.c.nc", M, OpX6aHint (5, 0x24, 0), {R1, MR3, IMM9b}},
{"ld1.c.nc.nt1", M, OpX6aHint (5, 0x24, 1), {R1, MR3, IMM9b}},
{"ld1.c.nc.nta", M, OpX6aHint (5, 0x24, 3), {R1, MR3, IMM9b}},
{"ld2.c.nc", M, OpX6aHint (5, 0x25, 0), {R1, MR3, IMM9b}},
{"ld2.c.nc.nt1", M, OpX6aHint (5, 0x25, 1), {R1, MR3, IMM9b}},
{"ld2.c.nc.nta", M, OpX6aHint (5, 0x25, 3), {R1, MR3, IMM9b}},
{"ld4.c.nc", M, OpX6aHint (5, 0x26, 0), {R1, MR3, IMM9b}},
{"ld4.c.nc.nt1", M, OpX6aHint (5, 0x26, 1), {R1, MR3, IMM9b}},
{"ld4.c.nc.nta", M, OpX6aHint (5, 0x26, 3), {R1, MR3, IMM9b}},
{"ld8.c.nc", M, OpX6aHint (5, 0x27, 0), {R1, MR3, IMM9b}},
{"ld8.c.nc.nt1", M, OpX6aHint (5, 0x27, 1), {R1, MR3, IMM9b}},
{"ld8.c.nc.nta", M, OpX6aHint (5, 0x27, 3), {R1, MR3, IMM9b}},
{"ld1.c.clr.acq", M, OpX6aHint (5, 0x28, 0), {R1, MR3, IMM9b}},
{"ld1.c.clr.acq.nt1", M, OpX6aHint (5, 0x28, 1), {R1, MR3, IMM9b}},
{"ld1.c.clr.acq.nta", M, OpX6aHint (5, 0x28, 3), {R1, MR3, IMM9b}},
{"ld2.c.clr.acq", M, OpX6aHint (5, 0x29, 0), {R1, MR3, IMM9b}},
{"ld2.c.clr.acq.nt1", M, OpX6aHint (5, 0x29, 1), {R1, MR3, IMM9b}},
{"ld2.c.clr.acq.nta", M, OpX6aHint (5, 0x29, 3), {R1, MR3, IMM9b}},
{"ld4.c.clr.acq", M, OpX6aHint (5, 0x2a, 0), {R1, MR3, IMM9b}},
{"ld4.c.clr.acq.nt1", M, OpX6aHint (5, 0x2a, 1), {R1, MR3, IMM9b}},
{"ld4.c.clr.acq.nta", M, OpX6aHint (5, 0x2a, 3), {R1, MR3, IMM9b}},
{"ld8.c.clr.acq", M, OpX6aHint (5, 0x2b, 0), {R1, MR3, IMM9b}},
{"ld8.c.clr.acq.nt1", M, OpX6aHint (5, 0x2b, 1), {R1, MR3, IMM9b}},
{"ld8.c.clr.acq.nta", M, OpX6aHint (5, 0x2b, 3), {R1, MR3, IMM9b}},
#define LDINCIMMED(c,h) M, OpX6aHint (5, c, h), {R1, MR3, IMM9b}, POSTINC
{"ld1", LDINCIMMED (0x00, 0)},
{"ld1.nt1", LDINCIMMED (0x00, 1)},
{"ld1.nta", LDINCIMMED (0x00, 3)},
{"ld2", LDINCIMMED (0x01, 0)},
{"ld2.nt1", LDINCIMMED (0x01, 1)},
{"ld2.nta", LDINCIMMED (0x01, 3)},
{"ld4", LDINCIMMED (0x02, 0)},
{"ld4.nt1", LDINCIMMED (0x02, 1)},
{"ld4.nta", LDINCIMMED (0x02, 3)},
{"ld8", LDINCIMMED (0x03, 0)},
{"ld8.nt1", LDINCIMMED (0x03, 1)},
{"ld8.nta", LDINCIMMED (0x03, 3)},
{"ld1.s", LDINCIMMED (0x04, 0)},
{"ld1.s.nt1", LDINCIMMED (0x04, 1)},
{"ld1.s.nta", LDINCIMMED (0x04, 3)},
{"ld2.s", LDINCIMMED (0x05, 0)},
{"ld2.s.nt1", LDINCIMMED (0x05, 1)},
{"ld2.s.nta", LDINCIMMED (0x05, 3)},
{"ld4.s", LDINCIMMED (0x06, 0)},
{"ld4.s.nt1", LDINCIMMED (0x06, 1)},
{"ld4.s.nta", LDINCIMMED (0x06, 3)},
{"ld8.s", LDINCIMMED (0x07, 0)},
{"ld8.s.nt1", LDINCIMMED (0x07, 1)},
{"ld8.s.nta", LDINCIMMED (0x07, 3)},
{"ld1.a", LDINCIMMED (0x08, 0)},
{"ld1.a.nt1", LDINCIMMED (0x08, 1)},
{"ld1.a.nta", LDINCIMMED (0x08, 3)},
{"ld2.a", LDINCIMMED (0x09, 0)},
{"ld2.a.nt1", LDINCIMMED (0x09, 1)},
{"ld2.a.nta", LDINCIMMED (0x09, 3)},
{"ld4.a", LDINCIMMED (0x0a, 0)},
{"ld4.a.nt1", LDINCIMMED (0x0a, 1)},
{"ld4.a.nta", LDINCIMMED (0x0a, 3)},
{"ld8.a", LDINCIMMED (0x0b, 0)},
{"ld8.a.nt1", LDINCIMMED (0x0b, 1)},
{"ld8.a.nta", LDINCIMMED (0x0b, 3)},
{"ld1.sa", LDINCIMMED (0x0c, 0)},
{"ld1.sa.nt1", LDINCIMMED (0x0c, 1)},
{"ld1.sa.nta", LDINCIMMED (0x0c, 3)},
{"ld2.sa", LDINCIMMED (0x0d, 0)},
{"ld2.sa.nt1", LDINCIMMED (0x0d, 1)},
{"ld2.sa.nta", LDINCIMMED (0x0d, 3)},
{"ld4.sa", LDINCIMMED (0x0e, 0)},
{"ld4.sa.nt1", LDINCIMMED (0x0e, 1)},
{"ld4.sa.nta", LDINCIMMED (0x0e, 3)},
{"ld8.sa", LDINCIMMED (0x0f, 0)},
{"ld8.sa.nt1", LDINCIMMED (0x0f, 1)},
{"ld8.sa.nta", LDINCIMMED (0x0f, 3)},
{"ld1.bias", LDINCIMMED (0x10, 0)},
{"ld1.bias.nt1", LDINCIMMED (0x10, 1)},
{"ld1.bias.nta", LDINCIMMED (0x10, 3)},
{"ld2.bias", LDINCIMMED (0x11, 0)},
{"ld2.bias.nt1", LDINCIMMED (0x11, 1)},
{"ld2.bias.nta", LDINCIMMED (0x11, 3)},
{"ld4.bias", LDINCIMMED (0x12, 0)},
{"ld4.bias.nt1", LDINCIMMED (0x12, 1)},
{"ld4.bias.nta", LDINCIMMED (0x12, 3)},
{"ld8.bias", LDINCIMMED (0x13, 0)},
{"ld8.bias.nt1", LDINCIMMED (0x13, 1)},
{"ld8.bias.nta", LDINCIMMED (0x13, 3)},
{"ld1.acq", LDINCIMMED (0x14, 0)},
{"ld1.acq.nt1", LDINCIMMED (0x14, 1)},
{"ld1.acq.nta", LDINCIMMED (0x14, 3)},
{"ld2.acq", LDINCIMMED (0x15, 0)},
{"ld2.acq.nt1", LDINCIMMED (0x15, 1)},
{"ld2.acq.nta", LDINCIMMED (0x15, 3)},
{"ld4.acq", LDINCIMMED (0x16, 0)},
{"ld4.acq.nt1", LDINCIMMED (0x16, 1)},
{"ld4.acq.nta", LDINCIMMED (0x16, 3)},
{"ld8.acq", LDINCIMMED (0x17, 0)},
{"ld8.acq.nt1", LDINCIMMED (0x17, 1)},
{"ld8.acq.nta", LDINCIMMED (0x17, 3)},
{"ld8.fill", LDINCIMMED (0x1b, 0)},
{"ld8.fill.nt1", LDINCIMMED (0x1b, 1)},
{"ld8.fill.nta", LDINCIMMED (0x1b, 3)},
{"ld1.c.clr", LDINCIMMED (0x20, 0)},
{"ld1.c.clr.nt1", LDINCIMMED (0x20, 1)},
{"ld1.c.clr.nta", LDINCIMMED (0x20, 3)},
{"ld2.c.clr", LDINCIMMED (0x21, 0)},
{"ld2.c.clr.nt1", LDINCIMMED (0x21, 1)},
{"ld2.c.clr.nta", LDINCIMMED (0x21, 3)},
{"ld4.c.clr", LDINCIMMED (0x22, 0)},
{"ld4.c.clr.nt1", LDINCIMMED (0x22, 1)},
{"ld4.c.clr.nta", LDINCIMMED (0x22, 3)},
{"ld8.c.clr", LDINCIMMED (0x23, 0)},
{"ld8.c.clr.nt1", LDINCIMMED (0x23, 1)},
{"ld8.c.clr.nta", LDINCIMMED (0x23, 3)},
{"ld1.c.nc", LDINCIMMED (0x24, 0)},
{"ld1.c.nc.nt1", LDINCIMMED (0x24, 1)},
{"ld1.c.nc.nta", LDINCIMMED (0x24, 3)},
{"ld2.c.nc", LDINCIMMED (0x25, 0)},
{"ld2.c.nc.nt1", LDINCIMMED (0x25, 1)},
{"ld2.c.nc.nta", LDINCIMMED (0x25, 3)},
{"ld4.c.nc", LDINCIMMED (0x26, 0)},
{"ld4.c.nc.nt1", LDINCIMMED (0x26, 1)},
{"ld4.c.nc.nta", LDINCIMMED (0x26, 3)},
{"ld8.c.nc", LDINCIMMED (0x27, 0)},
{"ld8.c.nc.nt1", LDINCIMMED (0x27, 1)},
{"ld8.c.nc.nta", LDINCIMMED (0x27, 3)},
{"ld1.c.clr.acq", LDINCIMMED (0x28, 0)},
{"ld1.c.clr.acq.nt1", LDINCIMMED (0x28, 1)},
{"ld1.c.clr.acq.nta", LDINCIMMED (0x28, 3)},
{"ld2.c.clr.acq", LDINCIMMED (0x29, 0)},
{"ld2.c.clr.acq.nt1", LDINCIMMED (0x29, 1)},
{"ld2.c.clr.acq.nta", LDINCIMMED (0x29, 3)},
{"ld4.c.clr.acq", LDINCIMMED (0x2a, 0)},
{"ld4.c.clr.acq.nt1", LDINCIMMED (0x2a, 1)},
{"ld4.c.clr.acq.nta", LDINCIMMED (0x2a, 3)},
{"ld8.c.clr.acq", LDINCIMMED (0x2b, 0)},
{"ld8.c.clr.acq.nt1", LDINCIMMED (0x2b, 1)},
{"ld8.c.clr.acq.nta", LDINCIMMED (0x2b, 3)},
#undef LDINCIMMED
/* store w/increment by immediate */
{"st1", M, OpX6aHint (5, 0x30, 0), {MR3, R2, IMM9a}},
{"st1.nta", M, OpX6aHint (5, 0x30, 3), {MR3, R2, IMM9a}},
{"st2", M, OpX6aHint (5, 0x31, 0), {MR3, R2, IMM9a}},
{"st2.nta", M, OpX6aHint (5, 0x31, 3), {MR3, R2, IMM9a}},
{"st4", M, OpX6aHint (5, 0x32, 0), {MR3, R2, IMM9a}},
{"st4.nta", M, OpX6aHint (5, 0x32, 3), {MR3, R2, IMM9a}},
{"st8", M, OpX6aHint (5, 0x33, 0), {MR3, R2, IMM9a}},
{"st8.nta", M, OpX6aHint (5, 0x33, 3), {MR3, R2, IMM9a}},
{"st1.rel", M, OpX6aHint (5, 0x34, 0), {MR3, R2, IMM9a}},
{"st1.rel.nta", M, OpX6aHint (5, 0x34, 3), {MR3, R2, IMM9a}},
{"st2.rel", M, OpX6aHint (5, 0x35, 0), {MR3, R2, IMM9a}},
{"st2.rel.nta", M, OpX6aHint (5, 0x35, 3), {MR3, R2, IMM9a}},
{"st4.rel", M, OpX6aHint (5, 0x36, 0), {MR3, R2, IMM9a}},
{"st4.rel.nta", M, OpX6aHint (5, 0x36, 3), {MR3, R2, IMM9a}},
{"st8.rel", M, OpX6aHint (5, 0x37, 0), {MR3, R2, IMM9a}},
{"st8.rel.nta", M, OpX6aHint (5, 0x37, 3), {MR3, R2, IMM9a}},
{"st8.spill", M, OpX6aHint (5, 0x3b, 0), {MR3, R2, IMM9a}},
{"st8.spill.nta", M, OpX6aHint (5, 0x3b, 3), {MR3, R2, IMM9a}},
#define STINCIMMED(c,h) M, OpX6aHint (5, c, h), {MR3, R2, IMM9a}, POSTINC
{"st1", STINCIMMED (0x30, 0)},
{"st1.nta", STINCIMMED (0x30, 3)},
{"st2", STINCIMMED (0x31, 0)},
{"st2.nta", STINCIMMED (0x31, 3)},
{"st4", STINCIMMED (0x32, 0)},
{"st4.nta", STINCIMMED (0x32, 3)},
{"st8", STINCIMMED (0x33, 0)},
{"st8.nta", STINCIMMED (0x33, 3)},
{"st1.rel", STINCIMMED (0x34, 0)},
{"st1.rel.nta", STINCIMMED (0x34, 3)},
{"st2.rel", STINCIMMED (0x35, 0)},
{"st2.rel.nta", STINCIMMED (0x35, 3)},
{"st4.rel", STINCIMMED (0x36, 0)},
{"st4.rel.nta", STINCIMMED (0x36, 3)},
{"st8.rel", STINCIMMED (0x37, 0)},
{"st8.rel.nta", STINCIMMED (0x37, 3)},
{"st8.spill", STINCIMMED (0x3b, 0)},
{"st8.spill.nta", STINCIMMED (0x3b, 3)},
#undef STINCIMMED
/* floating-point load */
{"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}},
@ -660,81 +666,84 @@ struct ia64_opcode ia64_opcodes_m[] =
{"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x24, 1), {F1, MR3}},
{"ldfe.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x24, 3), {F1, MR3}},
{"ldfs", M, OpMXX6aHint (6, 1, 0, 0x02, 0), {F1, MR3, R2}},
{"ldfs.nt1", M, OpMXX6aHint (6, 1, 0, 0x02, 1), {F1, MR3, R2}},
{"ldfs.nta", M, OpMXX6aHint (6, 1, 0, 0x02, 3), {F1, MR3, R2}},
{"ldfd", M, OpMXX6aHint (6, 1, 0, 0x03, 0), {F1, MR3, R2}},
{"ldfd.nt1", M, OpMXX6aHint (6, 1, 0, 0x03, 1), {F1, MR3, R2}},
{"ldfd.nta", M, OpMXX6aHint (6, 1, 0, 0x03, 3), {F1, MR3, R2}},
{"ldf8", M, OpMXX6aHint (6, 1, 0, 0x01, 0), {F1, MR3, R2}},
{"ldf8.nt1", M, OpMXX6aHint (6, 1, 0, 0x01, 1), {F1, MR3, R2}},
{"ldf8.nta", M, OpMXX6aHint (6, 1, 0, 0x01, 3), {F1, MR3, R2}},
{"ldfe", M, OpMXX6aHint (6, 1, 0, 0x00, 0), {F1, MR3, R2}},
{"ldfe.nt1", M, OpMXX6aHint (6, 1, 0, 0x00, 1), {F1, MR3, R2}},
{"ldfe.nta", M, OpMXX6aHint (6, 1, 0, 0x00, 3), {F1, MR3, R2}},
{"ldfs.s", M, OpMXX6aHint (6, 1, 0, 0x06, 0), {F1, MR3, R2}},
{"ldfs.s.nt1", M, OpMXX6aHint (6, 1, 0, 0x06, 1), {F1, MR3, R2}},
{"ldfs.s.nta", M, OpMXX6aHint (6, 1, 0, 0x06, 3), {F1, MR3, R2}},
{"ldfd.s", M, OpMXX6aHint (6, 1, 0, 0x07, 0), {F1, MR3, R2}},
{"ldfd.s.nt1", M, OpMXX6aHint (6, 1, 0, 0x07, 1), {F1, MR3, R2}},
{"ldfd.s.nta", M, OpMXX6aHint (6, 1, 0, 0x07, 3), {F1, MR3, R2}},
{"ldf8.s", M, OpMXX6aHint (6, 1, 0, 0x05, 0), {F1, MR3, R2}},
{"ldf8.s.nt1", M, OpMXX6aHint (6, 1, 0, 0x05, 1), {F1, MR3, R2}},
{"ldf8.s.nta", M, OpMXX6aHint (6, 1, 0, 0x05, 3), {F1, MR3, R2}},
{"ldfe.s", M, OpMXX6aHint (6, 1, 0, 0x04, 0), {F1, MR3, R2}},
{"ldfe.s.nt1", M, OpMXX6aHint (6, 1, 0, 0x04, 1), {F1, MR3, R2}},
{"ldfe.s.nta", M, OpMXX6aHint (6, 1, 0, 0x04, 3), {F1, MR3, R2}},
{"ldfs.a", M, OpMXX6aHint (6, 1, 0, 0x0a, 0), {F1, MR3, R2}},
{"ldfs.a.nt1", M, OpMXX6aHint (6, 1, 0, 0x0a, 1), {F1, MR3, R2}},
{"ldfs.a.nta", M, OpMXX6aHint (6, 1, 0, 0x0a, 3), {F1, MR3, R2}},
{"ldfd.a", M, OpMXX6aHint (6, 1, 0, 0x0b, 0), {F1, MR3, R2}},
{"ldfd.a.nt1", M, OpMXX6aHint (6, 1, 0, 0x0b, 1), {F1, MR3, R2}},
{"ldfd.a.nta", M, OpMXX6aHint (6, 1, 0, 0x0b, 3), {F1, MR3, R2}},
{"ldf8.a", M, OpMXX6aHint (6, 1, 0, 0x09, 0), {F1, MR3, R2}},
{"ldf8.a.nt1", M, OpMXX6aHint (6, 1, 0, 0x09, 1), {F1, MR3, R2}},
{"ldf8.a.nta", M, OpMXX6aHint (6, 1, 0, 0x09, 3), {F1, MR3, R2}},
{"ldfe.a", M, OpMXX6aHint (6, 1, 0, 0x08, 0), {F1, MR3, R2}},
{"ldfe.a.nt1", M, OpMXX6aHint (6, 1, 0, 0x08, 1), {F1, MR3, R2}},
{"ldfe.a.nta", M, OpMXX6aHint (6, 1, 0, 0x08, 3), {F1, MR3, R2}},
{"ldfs.sa", M, OpMXX6aHint (6, 1, 0, 0x0e, 0), {F1, MR3, R2}},
{"ldfs.sa.nt1", M, OpMXX6aHint (6, 1, 0, 0x0e, 1), {F1, MR3, R2}},
{"ldfs.sa.nta", M, OpMXX6aHint (6, 1, 0, 0x0e, 3), {F1, MR3, R2}},
{"ldfd.sa", M, OpMXX6aHint (6, 1, 0, 0x0f, 0), {F1, MR3, R2}},
{"ldfd.sa.nt1", M, OpMXX6aHint (6, 1, 0, 0x0f, 1), {F1, MR3, R2}},
{"ldfd.sa.nta", M, OpMXX6aHint (6, 1, 0, 0x0f, 3), {F1, MR3, R2}},
{"ldf8.sa", M, OpMXX6aHint (6, 1, 0, 0x0d, 0), {F1, MR3, R2}},
{"ldf8.sa.nt1", M, OpMXX6aHint (6, 1, 0, 0x0d, 1), {F1, MR3, R2}},
{"ldf8.sa.nta", M, OpMXX6aHint (6, 1, 0, 0x0d, 3), {F1, MR3, R2}},
{"ldfe.sa", M, OpMXX6aHint (6, 1, 0, 0x0c, 0), {F1, MR3, R2}},
{"ldfe.sa.nt1", M, OpMXX6aHint (6, 1, 0, 0x0c, 1), {F1, MR3, R2}},
{"ldfe.sa.nta", M, OpMXX6aHint (6, 1, 0, 0x0c, 3), {F1, MR3, R2}},
{"ldf.fill", M, OpMXX6aHint (6, 1, 0, 0x1b, 0), {F1, MR3, R2}},
{"ldf.fill.nt1", M, OpMXX6aHint (6, 1, 0, 0x1b, 1), {F1, MR3, R2}},
{"ldf.fill.nta", M, OpMXX6aHint (6, 1, 0, 0x1b, 3), {F1, MR3, R2}},
{"ldfs.c.clr", M, OpMXX6aHint (6, 1, 0, 0x22, 0), {F1, MR3, R2}},
{"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 1, 0, 0x22, 1), {F1, MR3, R2}},
{"ldfs.c.clr.nta", M, OpMXX6aHint (6, 1, 0, 0x22, 3), {F1, MR3, R2}},
{"ldfd.c.clr", M, OpMXX6aHint (6, 1, 0, 0x23, 0), {F1, MR3, R2}},
{"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 1, 0, 0x23, 1), {F1, MR3, R2}},
{"ldfd.c.clr.nta", M, OpMXX6aHint (6, 1, 0, 0x23, 3), {F1, MR3, R2}},
{"ldf8.c.clr", M, OpMXX6aHint (6, 1, 0, 0x21, 0), {F1, MR3, R2}},
{"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 1, 0, 0x21, 1), {F1, MR3, R2}},
{"ldf8.c.clr.nta", M, OpMXX6aHint (6, 1, 0, 0x21, 3), {F1, MR3, R2}},
{"ldfe.c.clr", M, OpMXX6aHint (6, 1, 0, 0x20, 0), {F1, MR3, R2}},
{"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 1, 0, 0x20, 1), {F1, MR3, R2}},
{"ldfe.c.clr.nta", M, OpMXX6aHint (6, 1, 0, 0x20, 3), {F1, MR3, R2}},
{"ldfs.c.nc", M, OpMXX6aHint (6, 1, 0, 0x26, 0), {F1, MR3, R2}},
{"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 1, 0, 0x26, 1), {F1, MR3, R2}},
{"ldfs.c.nc.nta", M, OpMXX6aHint (6, 1, 0, 0x26, 3), {F1, MR3, R2}},
{"ldfd.c.nc", M, OpMXX6aHint (6, 1, 0, 0x27, 0), {F1, MR3, R2}},
{"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 1, 0, 0x27, 1), {F1, MR3, R2}},
{"ldfd.c.nc.nta", M, OpMXX6aHint (6, 1, 0, 0x27, 3), {F1, MR3, R2}},
{"ldf8.c.nc", M, OpMXX6aHint (6, 1, 0, 0x25, 0), {F1, MR3, R2}},
{"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 1, 0, 0x25, 1), {F1, MR3, R2}},
{"ldf8.c.nc.nta", M, OpMXX6aHint (6, 1, 0, 0x25, 3), {F1, MR3, R2}},
{"ldfe.c.nc", M, OpMXX6aHint (6, 1, 0, 0x24, 0), {F1, MR3, R2}},
{"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 1, 0, 0x24, 1), {F1, MR3, R2}},
{"ldfe.c.nc.nta", M, OpMXX6aHint (6, 1, 0, 0x24, 3), {F1, MR3, R2}},
/* floating-point load w/increment by register */
#define FLDINCREG(c,h) M, OpMXX6aHint (6, 1, 0, c, h), {F1, MR3, R2}, POSTINC
{"ldfs", FLDINCREG (0x02, 0)},
{"ldfs.nt1", FLDINCREG (0x02, 1)},
{"ldfs.nta", FLDINCREG (0x02, 3)},
{"ldfd", FLDINCREG (0x03, 0)},
{"ldfd.nt1", FLDINCREG (0x03, 1)},
{"ldfd.nta", FLDINCREG (0x03, 3)},
{"ldf8", FLDINCREG (0x01, 0)},
{"ldf8.nt1", FLDINCREG (0x01, 1)},
{"ldf8.nta", FLDINCREG (0x01, 3)},
{"ldfe", FLDINCREG (0x00, 0)},
{"ldfe.nt1", FLDINCREG (0x00, 1)},
{"ldfe.nta", FLDINCREG (0x00, 3)},
{"ldfs.s", FLDINCREG (0x06, 0)},
{"ldfs.s.nt1", FLDINCREG (0x06, 1)},
{"ldfs.s.nta", FLDINCREG (0x06, 3)},
{"ldfd.s", FLDINCREG (0x07, 0)},
{"ldfd.s.nt1", FLDINCREG (0x07, 1)},
{"ldfd.s.nta", FLDINCREG (0x07, 3)},
{"ldf8.s", FLDINCREG (0x05, 0)},
{"ldf8.s.nt1", FLDINCREG (0x05, 1)},
{"ldf8.s.nta", FLDINCREG (0x05, 3)},
{"ldfe.s", FLDINCREG (0x04, 0)},
{"ldfe.s.nt1", FLDINCREG (0x04, 1)},
{"ldfe.s.nta", FLDINCREG (0x04, 3)},
{"ldfs.a", FLDINCREG (0x0a, 0)},
{"ldfs.a.nt1", FLDINCREG (0x0a, 1)},
{"ldfs.a.nta", FLDINCREG (0x0a, 3)},
{"ldfd.a", FLDINCREG (0x0b, 0)},
{"ldfd.a.nt1", FLDINCREG (0x0b, 1)},
{"ldfd.a.nta", FLDINCREG (0x0b, 3)},
{"ldf8.a", FLDINCREG (0x09, 0)},
{"ldf8.a.nt1", FLDINCREG (0x09, 1)},
{"ldf8.a.nta", FLDINCREG (0x09, 3)},
{"ldfe.a", FLDINCREG (0x08, 0)},
{"ldfe.a.nt1", FLDINCREG (0x08, 1)},
{"ldfe.a.nta", FLDINCREG (0x08, 3)},
{"ldfs.sa", FLDINCREG (0x0e, 0)},
{"ldfs.sa.nt1", FLDINCREG (0x0e, 1)},
{"ldfs.sa.nta", FLDINCREG (0x0e, 3)},
{"ldfd.sa", FLDINCREG (0x0f, 0)},
{"ldfd.sa.nt1", FLDINCREG (0x0f, 1)},
{"ldfd.sa.nta", FLDINCREG (0x0f, 3)},
{"ldf8.sa", FLDINCREG (0x0d, 0)},
{"ldf8.sa.nt1", FLDINCREG (0x0d, 1)},
{"ldf8.sa.nta", FLDINCREG (0x0d, 3)},
{"ldfe.sa", FLDINCREG (0x0c, 0)},
{"ldfe.sa.nt1", FLDINCREG (0x0c, 1)},
{"ldfe.sa.nta", FLDINCREG (0x0c, 3)},
{"ldf.fill", FLDINCREG (0x1b, 0)},
{"ldf.fill.nt1", FLDINCREG (0x1b, 1)},
{"ldf.fill.nta", FLDINCREG (0x1b, 3)},
{"ldfs.c.clr", FLDINCREG (0x22, 0)},
{"ldfs.c.clr.nt1", FLDINCREG (0x22, 1)},
{"ldfs.c.clr.nta", FLDINCREG (0x22, 3)},
{"ldfd.c.clr", FLDINCREG (0x23, 0)},
{"ldfd.c.clr.nt1", FLDINCREG (0x23, 1)},
{"ldfd.c.clr.nta", FLDINCREG (0x23, 3)},
{"ldf8.c.clr", FLDINCREG (0x21, 0)},
{"ldf8.c.clr.nt1", FLDINCREG (0x21, 1)},
{"ldf8.c.clr.nta", FLDINCREG (0x21, 3)},
{"ldfe.c.clr", FLDINCREG (0x20, 0)},
{"ldfe.c.clr.nt1", FLDINCREG (0x20, 1)},
{"ldfe.c.clr.nta", FLDINCREG (0x20, 3)},
{"ldfs.c.nc", FLDINCREG (0x26, 0)},
{"ldfs.c.nc.nt1", FLDINCREG (0x26, 1)},
{"ldfs.c.nc.nta", FLDINCREG (0x26, 3)},
{"ldfd.c.nc", FLDINCREG (0x27, 0)},
{"ldfd.c.nc.nt1", FLDINCREG (0x27, 1)},
{"ldfd.c.nc.nta", FLDINCREG (0x27, 3)},
{"ldf8.c.nc", FLDINCREG (0x25, 0)},
{"ldf8.c.nc.nt1", FLDINCREG (0x25, 1)},
{"ldf8.c.nc.nta", FLDINCREG (0x25, 3)},
{"ldfe.c.nc", FLDINCREG (0x24, 0)},
{"ldfe.c.nc.nt1", FLDINCREG (0x24, 1)},
{"ldfe.c.nc.nta", FLDINCREG (0x24, 3)},
#undef FLDINCREG
/* floating-point store */
{"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}},
@ -805,7 +814,7 @@ struct ia64_opcode ia64_opcodes_m[] =
{"ldfp8.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x25, 3), {F1, F2, MR3}},
/* floating-point load pair w/increment by immediate */
#define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}
#define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}, POSTINC
{"ldfps", LD (0x02, 0, C8)},
{"ldfps.nt1", LD (0x02, 1, C8)},
{"ldfps.nta", LD (0x02, 3, C8)},
@ -881,22 +890,24 @@ struct ia64_opcode ia64_opcodes_m[] =
{"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2f, 3), {MR3}},
/* line prefetch w/increment by register */
{"lfetch", M0, OpMXX6aHint (6, 1, 0, 0x2c, 0), {MR3, R2}},
{"lfetch.nt1", M0, OpMXX6aHint (6, 1, 0, 0x2c, 1), {MR3, R2}},
{"lfetch.nt2", M0, OpMXX6aHint (6, 1, 0, 0x2c, 2), {MR3, R2}},
{"lfetch.nta", M0, OpMXX6aHint (6, 1, 0, 0x2c, 3), {MR3, R2}},
{"lfetch.excl", M0, OpMXX6aHint (6, 1, 0, 0x2d, 0), {MR3, R2}},
{"lfetch.excl.nt1", M0, OpMXX6aHint (6, 1, 0, 0x2d, 1), {MR3, R2}},
{"lfetch.excl.nt2", M0, OpMXX6aHint (6, 1, 0, 0x2d, 2), {MR3, R2}},
{"lfetch.excl.nta", M0, OpMXX6aHint (6, 1, 0, 0x2d, 3), {MR3, R2}},
{"lfetch.fault", M0, OpMXX6aHint (6, 1, 0, 0x2e, 0), {MR3, R2}},
{"lfetch.fault.nt1", M0, OpMXX6aHint (6, 1, 0, 0x2e, 1), {MR3, R2}},
{"lfetch.fault.nt2", M0, OpMXX6aHint (6, 1, 0, 0x2e, 2), {MR3, R2}},
{"lfetch.fault.nta", M0, OpMXX6aHint (6, 1, 0, 0x2e, 3), {MR3, R2}},
{"lfetch.fault.excl", M0, OpMXX6aHint (6, 1, 0, 0x2f, 0), {MR3, R2}},
{"lfetch.fault.excl.nt1", M0, OpMXX6aHint (6, 1, 0, 0x2f, 1), {MR3, R2}},
{"lfetch.fault.excl.nt2", M0, OpMXX6aHint (6, 1, 0, 0x2f, 2), {MR3, R2}},
{"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 1, 0, 0x2f, 3), {MR3, R2}},
#define LFETCHINCREG(c,h) M0, OpMXX6aHint (6, 1, 0, c, h), {MR3, R2}, POSTINC
{"lfetch", LFETCHINCREG (0x2c, 0)},
{"lfetch.nt1", LFETCHINCREG (0x2c, 1)},
{"lfetch.nt2", LFETCHINCREG (0x2c, 2)},
{"lfetch.nta", LFETCHINCREG (0x2c, 3)},
{"lfetch.excl", LFETCHINCREG (0x2d, 0)},
{"lfetch.excl.nt1", LFETCHINCREG (0x2d, 1)},
{"lfetch.excl.nt2", LFETCHINCREG (0x2d, 2)},
{"lfetch.excl.nta", LFETCHINCREG (0x2d, 3)},
{"lfetch.fault", LFETCHINCREG (0x2e, 0)},
{"lfetch.fault.nt1", LFETCHINCREG (0x2e, 1)},
{"lfetch.fault.nt2", LFETCHINCREG (0x2e, 2)},
{"lfetch.fault.nta", LFETCHINCREG (0x2e, 3)},
{"lfetch.fault.excl", LFETCHINCREG (0x2f, 0)},
{"lfetch.fault.excl.nt1", LFETCHINCREG (0x2f, 1)},
{"lfetch.fault.excl.nt2", LFETCHINCREG (0x2f, 2)},
{"lfetch.fault.excl.nta", LFETCHINCREG (0x2f, 3)},
#undef LFETCHINCREG
/* semaphore operations */
{"setf.sig", M, OpMXX6a (6, 0, 1, 0x1c), {F1, R2}},
@ -904,111 +915,118 @@ struct ia64_opcode ia64_opcodes_m[] =
{"setf.s", M, OpMXX6a (6, 0, 1, 0x1e), {F1, R2}},
{"setf.d", M, OpMXX6a (6, 0, 1, 0x1f), {F1, R2}},
{"ldfs", M, OpX6aHint (7, 0x02, 0), {F1, MR3, IMM9b}},
{"ldfs.nt1", M, OpX6aHint (7, 0x02, 1), {F1, MR3, IMM9b}},
{"ldfs.nta", M, OpX6aHint (7, 0x02, 3), {F1, MR3, IMM9b}},
{"ldfd", M, OpX6aHint (7, 0x03, 0), {F1, MR3, IMM9b}},
{"ldfd.nt1", M, OpX6aHint (7, 0x03, 1), {F1, MR3, IMM9b}},
{"ldfd.nta", M, OpX6aHint (7, 0x03, 3), {F1, MR3, IMM9b}},
{"ldf8", M, OpX6aHint (7, 0x01, 0), {F1, MR3, IMM9b}},
{"ldf8.nt1", M, OpX6aHint (7, 0x01, 1), {F1, MR3, IMM9b}},
{"ldf8.nta", M, OpX6aHint (7, 0x01, 3), {F1, MR3, IMM9b}},
{"ldfe", M, OpX6aHint (7, 0x00, 0), {F1, MR3, IMM9b}},
{"ldfe.nt1", M, OpX6aHint (7, 0x00, 1), {F1, MR3, IMM9b}},
{"ldfe.nta", M, OpX6aHint (7, 0x00, 3), {F1, MR3, IMM9b}},
{"ldfs.s", M, OpX6aHint (7, 0x06, 0), {F1, MR3, IMM9b}},
{"ldfs.s.nt1", M, OpX6aHint (7, 0x06, 1), {F1, MR3, IMM9b}},
{"ldfs.s.nta", M, OpX6aHint (7, 0x06, 3), {F1, MR3, IMM9b}},
{"ldfd.s", M, OpX6aHint (7, 0x07, 0), {F1, MR3, IMM9b}},
{"ldfd.s.nt1", M, OpX6aHint (7, 0x07, 1), {F1, MR3, IMM9b}},
{"ldfd.s.nta", M, OpX6aHint (7, 0x07, 3), {F1, MR3, IMM9b}},
{"ldf8.s", M, OpX6aHint (7, 0x05, 0), {F1, MR3, IMM9b}},
{"ldf8.s.nt1", M, OpX6aHint (7, 0x05, 1), {F1, MR3, IMM9b}},
{"ldf8.s.nta", M, OpX6aHint (7, 0x05, 3), {F1, MR3, IMM9b}},
{"ldfe.s", M, OpX6aHint (7, 0x04, 0), {F1, MR3, IMM9b}},
{"ldfe.s.nt1", M, OpX6aHint (7, 0x04, 1), {F1, MR3, IMM9b}},
{"ldfe.s.nta", M, OpX6aHint (7, 0x04, 3), {F1, MR3, IMM9b}},
{"ldfs.a", M, OpX6aHint (7, 0x0a, 0), {F1, MR3, IMM9b}},
{"ldfs.a.nt1", M, OpX6aHint (7, 0x0a, 1), {F1, MR3, IMM9b}},
{"ldfs.a.nta", M, OpX6aHint (7, 0x0a, 3), {F1, MR3, IMM9b}},
{"ldfd.a", M, OpX6aHint (7, 0x0b, 0), {F1, MR3, IMM9b}},
{"ldfd.a.nt1", M, OpX6aHint (7, 0x0b, 1), {F1, MR3, IMM9b}},
{"ldfd.a.nta", M, OpX6aHint (7, 0x0b, 3), {F1, MR3, IMM9b}},
{"ldf8.a", M, OpX6aHint (7, 0x09, 0), {F1, MR3, IMM9b}},
{"ldf8.a.nt1", M, OpX6aHint (7, 0x09, 1), {F1, MR3, IMM9b}},
{"ldf8.a.nta", M, OpX6aHint (7, 0x09, 3), {F1, MR3, IMM9b}},
{"ldfe.a", M, OpX6aHint (7, 0x08, 0), {F1, MR3, IMM9b}},
{"ldfe.a.nt1", M, OpX6aHint (7, 0x08, 1), {F1, MR3, IMM9b}},
{"ldfe.a.nta", M, OpX6aHint (7, 0x08, 3), {F1, MR3, IMM9b}},
{"ldfs.sa", M, OpX6aHint (7, 0x0e, 0), {F1, MR3, IMM9b}},
{"ldfs.sa.nt1", M, OpX6aHint (7, 0x0e, 1), {F1, MR3, IMM9b}},
{"ldfs.sa.nta", M, OpX6aHint (7, 0x0e, 3), {F1, MR3, IMM9b}},
{"ldfd.sa", M, OpX6aHint (7, 0x0f, 0), {F1, MR3, IMM9b}},
{"ldfd.sa.nt1", M, OpX6aHint (7, 0x0f, 1), {F1, MR3, IMM9b}},
{"ldfd.sa.nta", M, OpX6aHint (7, 0x0f, 3), {F1, MR3, IMM9b}},
{"ldf8.sa", M, OpX6aHint (7, 0x0d, 0), {F1, MR3, IMM9b}},
{"ldf8.sa.nt1", M, OpX6aHint (7, 0x0d, 1), {F1, MR3, IMM9b}},
{"ldf8.sa.nta", M, OpX6aHint (7, 0x0d, 3), {F1, MR3, IMM9b}},
{"ldfe.sa", M, OpX6aHint (7, 0x0c, 0), {F1, MR3, IMM9b}},
{"ldfe.sa.nt1", M, OpX6aHint (7, 0x0c, 1), {F1, MR3, IMM9b}},
{"ldfe.sa.nta", M, OpX6aHint (7, 0x0c, 3), {F1, MR3, IMM9b}},
{"ldf.fill", M, OpX6aHint (7, 0x1b, 0), {F1, MR3, IMM9b}},
{"ldf.fill.nt1", M, OpX6aHint (7, 0x1b, 1), {F1, MR3, IMM9b}},
{"ldf.fill.nta", M, OpX6aHint (7, 0x1b, 3), {F1, MR3, IMM9b}},
{"ldfs.c.clr", M, OpX6aHint (7, 0x22, 0), {F1, MR3, IMM9b}},
{"ldfs.c.clr.nt1", M, OpX6aHint (7, 0x22, 1), {F1, MR3, IMM9b}},
{"ldfs.c.clr.nta", M, OpX6aHint (7, 0x22, 3), {F1, MR3, IMM9b}},
{"ldfd.c.clr", M, OpX6aHint (7, 0x23, 0), {F1, MR3, IMM9b}},
{"ldfd.c.clr.nt1", M, OpX6aHint (7, 0x23, 1), {F1, MR3, IMM9b}},
{"ldfd.c.clr.nta", M, OpX6aHint (7, 0x23, 3), {F1, MR3, IMM9b}},
{"ldf8.c.clr", M, OpX6aHint (7, 0x21, 0), {F1, MR3, IMM9b}},
{"ldf8.c.clr.nt1", M, OpX6aHint (7, 0x21, 1), {F1, MR3, IMM9b}},
{"ldf8.c.clr.nta", M, OpX6aHint (7, 0x21, 3), {F1, MR3, IMM9b}},
{"ldfe.c.clr", M, OpX6aHint (7, 0x20, 0), {F1, MR3, IMM9b}},
{"ldfe.c.clr.nt1", M, OpX6aHint (7, 0x20, 1), {F1, MR3, IMM9b}},
{"ldfe.c.clr.nta", M, OpX6aHint (7, 0x20, 3), {F1, MR3, IMM9b}},
{"ldfs.c.nc", M, OpX6aHint (7, 0x26, 0), {F1, MR3, IMM9b}},
{"ldfs.c.nc.nt1", M, OpX6aHint (7, 0x26, 1), {F1, MR3, IMM9b}},
{"ldfs.c.nc.nta", M, OpX6aHint (7, 0x26, 3), {F1, MR3, IMM9b}},
{"ldfd.c.nc", M, OpX6aHint (7, 0x27, 0), {F1, MR3, IMM9b}},
{"ldfd.c.nc.nt1", M, OpX6aHint (7, 0x27, 1), {F1, MR3, IMM9b}},
{"ldfd.c.nc.nta", M, OpX6aHint (7, 0x27, 3), {F1, MR3, IMM9b}},
{"ldf8.c.nc", M, OpX6aHint (7, 0x25, 0), {F1, MR3, IMM9b}},
{"ldf8.c.nc.nt1", M, OpX6aHint (7, 0x25, 1), {F1, MR3, IMM9b}},
{"ldf8.c.nc.nta", M, OpX6aHint (7, 0x25, 3), {F1, MR3, IMM9b}},
{"ldfe.c.nc", M, OpX6aHint (7, 0x24, 0), {F1, MR3, IMM9b}},
{"ldfe.c.nc.nt1", M, OpX6aHint (7, 0x24, 1), {F1, MR3, IMM9b}},
{"ldfe.c.nc.nta", M, OpX6aHint (7, 0x24, 3), {F1, MR3, IMM9b}},
/* floating-point load w/increment by immediate */
#define FLDINCIMMED(c,h) M, OpX6aHint (7, c, h), {F1, MR3, IMM9b}, POSTINC
{"ldfs", FLDINCIMMED (0x02, 0)},
{"ldfs.nt1", FLDINCIMMED (0x02, 1)},
{"ldfs.nta", FLDINCIMMED (0x02, 3)},
{"ldfd", FLDINCIMMED (0x03, 0)},
{"ldfd.nt1", FLDINCIMMED (0x03, 1)},
{"ldfd.nta", FLDINCIMMED (0x03, 3)},
{"ldf8", FLDINCIMMED (0x01, 0)},
{"ldf8.nt1", FLDINCIMMED (0x01, 1)},
{"ldf8.nta", FLDINCIMMED (0x01, 3)},
{"ldfe", FLDINCIMMED (0x00, 0)},
{"ldfe.nt1", FLDINCIMMED (0x00, 1)},
{"ldfe.nta", FLDINCIMMED (0x00, 3)},
{"ldfs.s", FLDINCIMMED (0x06, 0)},
{"ldfs.s.nt1", FLDINCIMMED (0x06, 1)},
{"ldfs.s.nta", FLDINCIMMED (0x06, 3)},
{"ldfd.s", FLDINCIMMED (0x07, 0)},
{"ldfd.s.nt1", FLDINCIMMED (0x07, 1)},
{"ldfd.s.nta", FLDINCIMMED (0x07, 3)},
{"ldf8.s", FLDINCIMMED (0x05, 0)},
{"ldf8.s.nt1", FLDINCIMMED (0x05, 1)},
{"ldf8.s.nta", FLDINCIMMED (0x05, 3)},
{"ldfe.s", FLDINCIMMED (0x04, 0)},
{"ldfe.s.nt1", FLDINCIMMED (0x04, 1)},
{"ldfe.s.nta", FLDINCIMMED (0x04, 3)},
{"ldfs.a", FLDINCIMMED (0x0a, 0)},
{"ldfs.a.nt1", FLDINCIMMED (0x0a, 1)},
{"ldfs.a.nta", FLDINCIMMED (0x0a, 3)},
{"ldfd.a", FLDINCIMMED (0x0b, 0)},
{"ldfd.a.nt1", FLDINCIMMED (0x0b, 1)},
{"ldfd.a.nta", FLDINCIMMED (0x0b, 3)},
{"ldf8.a", FLDINCIMMED (0x09, 0)},
{"ldf8.a.nt1", FLDINCIMMED (0x09, 1)},
{"ldf8.a.nta", FLDINCIMMED (0x09, 3)},
{"ldfe.a", FLDINCIMMED (0x08, 0)},
{"ldfe.a.nt1", FLDINCIMMED (0x08, 1)},
{"ldfe.a.nta", FLDINCIMMED (0x08, 3)},
{"ldfs.sa", FLDINCIMMED (0x0e, 0)},
{"ldfs.sa.nt1", FLDINCIMMED (0x0e, 1)},
{"ldfs.sa.nta", FLDINCIMMED (0x0e, 3)},
{"ldfd.sa", FLDINCIMMED (0x0f, 0)},
{"ldfd.sa.nt1", FLDINCIMMED (0x0f, 1)},
{"ldfd.sa.nta", FLDINCIMMED (0x0f, 3)},
{"ldf8.sa", FLDINCIMMED (0x0d, 0)},
{"ldf8.sa.nt1", FLDINCIMMED (0x0d, 1)},
{"ldf8.sa.nta", FLDINCIMMED (0x0d, 3)},
{"ldfe.sa", FLDINCIMMED (0x0c, 0)},
{"ldfe.sa.nt1", FLDINCIMMED (0x0c, 1)},
{"ldfe.sa.nta", FLDINCIMMED (0x0c, 3)},
{"ldf.fill", FLDINCIMMED (0x1b, 0)},
{"ldf.fill.nt1", FLDINCIMMED (0x1b, 1)},
{"ldf.fill.nta", FLDINCIMMED (0x1b, 3)},
{"ldfs.c.clr", FLDINCIMMED (0x22, 0)},
{"ldfs.c.clr.nt1", FLDINCIMMED (0x22, 1)},
{"ldfs.c.clr.nta", FLDINCIMMED (0x22, 3)},
{"ldfd.c.clr", FLDINCIMMED (0x23, 0)},
{"ldfd.c.clr.nt1", FLDINCIMMED (0x23, 1)},
{"ldfd.c.clr.nta", FLDINCIMMED (0x23, 3)},
{"ldf8.c.clr", FLDINCIMMED (0x21, 0)},
{"ldf8.c.clr.nt1", FLDINCIMMED (0x21, 1)},
{"ldf8.c.clr.nta", FLDINCIMMED (0x21, 3)},
{"ldfe.c.clr", FLDINCIMMED (0x20, 0)},
{"ldfe.c.clr.nt1", FLDINCIMMED (0x20, 1)},
{"ldfe.c.clr.nta", FLDINCIMMED (0x20, 3)},
{"ldfs.c.nc", FLDINCIMMED (0x26, 0)},
{"ldfs.c.nc.nt1", FLDINCIMMED (0x26, 1)},
{"ldfs.c.nc.nta", FLDINCIMMED (0x26, 3)},
{"ldfd.c.nc", FLDINCIMMED (0x27, 0)},
{"ldfd.c.nc.nt1", FLDINCIMMED (0x27, 1)},
{"ldfd.c.nc.nta", FLDINCIMMED (0x27, 3)},
{"ldf8.c.nc", FLDINCIMMED (0x25, 0)},
{"ldf8.c.nc.nt1", FLDINCIMMED (0x25, 1)},
{"ldf8.c.nc.nta", FLDINCIMMED (0x25, 3)},
{"ldfe.c.nc", FLDINCIMMED (0x24, 0)},
{"ldfe.c.nc.nt1", FLDINCIMMED (0x24, 1)},
{"ldfe.c.nc.nta", FLDINCIMMED (0x24, 3)},
#undef FLDINCIMMED
/* floating-point store w/increment by immediate */
{"stfs", M, OpX6aHint (7, 0x32, 0), {MR3, F2, IMM9a}},
{"stfs.nta", M, OpX6aHint (7, 0x32, 3), {MR3, F2, IMM9a}},
{"stfd", M, OpX6aHint (7, 0x33, 0), {MR3, F2, IMM9a}},
{"stfd.nta", M, OpX6aHint (7, 0x33, 3), {MR3, F2, IMM9a}},
{"stf8", M, OpX6aHint (7, 0x31, 0), {MR3, F2, IMM9a}},
{"stf8.nta", M, OpX6aHint (7, 0x31, 3), {MR3, F2, IMM9a}},
{"stfe", M, OpX6aHint (7, 0x30, 0), {MR3, F2, IMM9a}},
{"stfe.nta", M, OpX6aHint (7, 0x30, 3), {MR3, F2, IMM9a}},
{"stf.spill", M, OpX6aHint (7, 0x3b, 0), {MR3, F2, IMM9a}},
{"stf.spill.nta", M, OpX6aHint (7, 0x3b, 3), {MR3, F2, IMM9a}},
#define FSTINCIMMED(c,h) M, OpX6aHint (7, c, h), {MR3, F2, IMM9a}, POSTINC
{"stfs", FSTINCIMMED (0x32, 0)},
{"stfs.nta", FSTINCIMMED (0x32, 3)},
{"stfd", FSTINCIMMED (0x33, 0)},
{"stfd.nta", FSTINCIMMED (0x33, 3)},
{"stf8", FSTINCIMMED (0x31, 0)},
{"stf8.nta", FSTINCIMMED (0x31, 3)},
{"stfe", FSTINCIMMED (0x30, 0)},
{"stfe.nta", FSTINCIMMED (0x30, 3)},
{"stf.spill", FSTINCIMMED (0x3b, 0)},
{"stf.spill.nta", FSTINCIMMED (0x3b, 3)},
#undef FSTINCIMMED
/* line prefetch w/increment by immediate */
{"lfetch", M0, OpX6aHint (7, 0x2c, 0), {MR3, IMM9b}},
{"lfetch.nt1", M0, OpX6aHint (7, 0x2c, 1), {MR3, IMM9b}},
{"lfetch.nt2", M0, OpX6aHint (7, 0x2c, 2), {MR3, IMM9b}},
{"lfetch.nta", M0, OpX6aHint (7, 0x2c, 3), {MR3, IMM9b}},
{"lfetch.excl", M0, OpX6aHint (7, 0x2d, 0), {MR3, IMM9b}},
{"lfetch.excl.nt1", M0, OpX6aHint (7, 0x2d, 1), {MR3, IMM9b}},
{"lfetch.excl.nt2", M0, OpX6aHint (7, 0x2d, 2), {MR3, IMM9b}},
{"lfetch.excl.nta", M0, OpX6aHint (7, 0x2d, 3), {MR3, IMM9b}},
{"lfetch.fault", M0, OpX6aHint (7, 0x2e, 0), {MR3, IMM9b}},
{"lfetch.fault.nt1", M0, OpX6aHint (7, 0x2e, 1), {MR3, IMM9b}},
{"lfetch.fault.nt2", M0, OpX6aHint (7, 0x2e, 2), {MR3, IMM9b}},
{"lfetch.fault.nta", M0, OpX6aHint (7, 0x2e, 3), {MR3, IMM9b}},
{"lfetch.fault.excl", M0, OpX6aHint (7, 0x2f, 0), {MR3, IMM9b}},
{"lfetch.fault.excl.nt1", M0, OpX6aHint (7, 0x2f, 1), {MR3, IMM9b}},
{"lfetch.fault.excl.nt2", M0, OpX6aHint (7, 0x2f, 2), {MR3, IMM9b}},
{"lfetch.fault.excl.nta", M0, OpX6aHint (7, 0x2f, 3), {MR3, IMM9b}},
#define LFETCHINCIMMED(c,h) M0, OpX6aHint (7, c, h), {MR3, IMM9b}, POSTINC
{"lfetch", LFETCHINCIMMED (0x2c, 0)},
{"lfetch.nt1", LFETCHINCIMMED (0x2c, 1)},
{"lfetch.nt2", LFETCHINCIMMED (0x2c, 2)},
{"lfetch.nta", LFETCHINCIMMED (0x2c, 3)},
{"lfetch.excl", LFETCHINCIMMED (0x2d, 0)},
{"lfetch.excl.nt1", LFETCHINCIMMED (0x2d, 1)},
{"lfetch.excl.nt2", LFETCHINCIMMED (0x2d, 2)},
{"lfetch.excl.nta", LFETCHINCIMMED (0x2d, 3)},
{"lfetch.fault", LFETCHINCIMMED (0x2e, 0)},
{"lfetch.fault.nt1", LFETCHINCIMMED (0x2e, 1)},
{"lfetch.fault.nt2", LFETCHINCIMMED (0x2e, 2)},
{"lfetch.fault.nta", LFETCHINCIMMED (0x2e, 3)},
{"lfetch.fault.excl", LFETCHINCIMMED (0x2f, 0)},
{"lfetch.fault.excl.nt1", LFETCHINCIMMED (0x2f, 1)},
{"lfetch.fault.excl.nt2", LFETCHINCIMMED (0x2f, 2)},
{"lfetch.fault.excl.nta", LFETCHINCIMMED (0x2f, 3)},
#undef LFETCHINCIMMED
{0}
};

1
opcodes/ia64-opc.h
View File

@ -40,6 +40,7 @@
#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3
#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT
#define MOD_RRBS IA64_OPCODE_MOD_RRBS
#define POSTINC IA64_OPCODE_POSTINC
#define AR_CCV IA64_OPND_AR_CCV
#define AR_PFS IA64_OPND_AR_PFS