[AArch64] Support RAS extension for ARMv8 onwards.

The RAS extension was introduced as part of the ARMv8.2 architecture where it is a required feature. It is also available as an optional feature for ARMv8 and ARMv8.1. In binutils, the RAS extension is currently enabled by default for -march=armv8.2-a but is not available for -march=armv8 or -march=armv8.1-a. This patch adds the feature extension '+ras' to enable the RAS extension for ARMv8 and ARMv8.1, it is disabled by default. gas/ 2016-04-20 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "ras". * doc/c-aarch64.texi (AArch64 Extensions): Add "ras". * testsuite/gas/aarch64/armv8-ras-1.d: New. * testsuite/gas/aarch64/armv8-ras-1.s: New. * testsuite/gas/aarch64/illegal-ras-1.d: New. * testsuite/gas/aarch64/illegal-ras-1.s: New. Change-Id: I824fb9bc8cf846bcc03aa17a726efb1350d78b9d
2016-04-20 09:31:49 +01:00 · 2016-04-20 09:31:49 +01:00 · 50cc854c48
parent 87d455c042
commit 50cc854c48
8 changed files with 249 additions and 0 deletions
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@ -1,3 +1,12 @@
+2016-04-20  Matthew Wahab  <matthew.wahab@arm.com>
+
+	* config/tc-aarch64.c (aarch64_features): Add "ras".
+	* doc/c-aarch64.texi (AArch64 Extensions): Add "ras".
+	* testsuite/gas/aarch64/armv8-ras-1.d: New.
+	* testsuite/gas/aarch64/armv8-ras-1.s: New.
+	* testsuite/gas/aarch64/illegal-ras-1.d: New.
+	* testsuite/gas/aarch64/illegal-ras-1.s: New.
+
 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>

 	* testsuite/gas/arc/nps400-6.d: New file.
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@ -7809,6 +7809,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
  {"simd",		AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
  {"pan",		AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0)},
  {"lor",		AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0)},
+  {"ras",		AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0)},
  {"rdma",		AARCH64_FEATURE (AARCH64_FEATURE_SIMD
 					 | AARCH64_FEATURE_RDMA, 0)},
  {"fp16",		AARCH64_FEATURE (AARCH64_FEATURE_F16
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@ -145,6 +145,9 @@ automatically cause those extensions to be disabled.
 @tab Enable Privileged Access Never support.
@item @code{profile} @tab ARMv8.2-A @tab No
 @tab Enable statistical profiling extensions.
+@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
+ @tab Enable the Reliability, Availability and Serviceability
+ extension.
@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
--- a/gas/testsuite/gas/aarch64/armv8-ras-1.d
+++ b/gas/testsuite/gas/aarch64/armv8-ras-1.d
@ -0,0 +1,68 @@
+#as: -march=armv8-a+ras
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+[^:]+:	d503221f 	esb
+[^:]+:	d503221f 	esb
+[^:]+:	d5385305 	mrs	x5, erridr_el1
+[^:]+:	d5185327 	msr	errselr_el1, x7
+[^:]+:	d5385327 	mrs	x7, errselr_el1
+[^:]+:	d5385405 	mrs	x5, erxfr_el1
+[^:]+:	d5185425 	msr	erxctlr_el1, x5
+[^:]+:	d5385425 	mrs	x5, erxctlr_el1
+[^:]+:	d5185445 	msr	erxstatus_el1, x5
+[^:]+:	d5385445 	mrs	x5, erxstatus_el1
+[^:]+:	d5185465 	msr	erxaddr_el1, x5
+[^:]+:	d5385465 	mrs	x5, erxaddr_el1
+[^:]+:	d5185505 	msr	erxmisc0_el1, x5
+[^:]+:	d5385505 	mrs	x5, erxmisc0_el1
+[^:]+:	d5185525 	msr	erxmisc1_el1, x5
+[^:]+:	d5385525 	mrs	x5, erxmisc1_el1
+[^:]+:	d53c5265 	mrs	x5, vsesr_el2
+[^:]+:	d518c125 	msr	disr_el1, x5
+[^:]+:	d538c125 	mrs	x5, disr_el1
+[^:]+:	d53cc125 	mrs	x5, vdisr_el2
+[^:]+:	d503221f 	esb
+[^:]+:	d503221f 	esb
+[^:]+:	d5385305 	mrs	x5, erridr_el1
+[^:]+:	d5185327 	msr	errselr_el1, x7
+[^:]+:	d5385327 	mrs	x7, errselr_el1
+[^:]+:	d5385405 	mrs	x5, erxfr_el1
+[^:]+:	d5185425 	msr	erxctlr_el1, x5
+[^:]+:	d5385425 	mrs	x5, erxctlr_el1
+[^:]+:	d5185445 	msr	erxstatus_el1, x5
+[^:]+:	d5385445 	mrs	x5, erxstatus_el1
+[^:]+:	d5185465 	msr	erxaddr_el1, x5
+[^:]+:	d5385465 	mrs	x5, erxaddr_el1
+[^:]+:	d5185505 	msr	erxmisc0_el1, x5
+[^:]+:	d5385505 	mrs	x5, erxmisc0_el1
+[^:]+:	d5185525 	msr	erxmisc1_el1, x5
+[^:]+:	d5385525 	mrs	x5, erxmisc1_el1
+[^:]+:	d53c5265 	mrs	x5, vsesr_el2
+[^:]+:	d518c125 	msr	disr_el1, x5
+[^:]+:	d538c125 	mrs	x5, disr_el1
+[^:]+:	d53cc125 	mrs	x5, vdisr_el2
+[^:]+:	d503221f 	esb
+[^:]+:	d503221f 	esb
+[^:]+:	d5385305 	mrs	x5, erridr_el1
+[^:]+:	d5185327 	msr	errselr_el1, x7
+[^:]+:	d5385327 	mrs	x7, errselr_el1
+[^:]+:	d5385405 	mrs	x5, erxfr_el1
+[^:]+:	d5185425 	msr	erxctlr_el1, x5
+[^:]+:	d5385425 	mrs	x5, erxctlr_el1
+[^:]+:	d5185445 	msr	erxstatus_el1, x5
+[^:]+:	d5385445 	mrs	x5, erxstatus_el1
+[^:]+:	d5185465 	msr	erxaddr_el1, x5
+[^:]+:	d5385465 	mrs	x5, erxaddr_el1
+[^:]+:	d5185505 	msr	erxmisc0_el1, x5
+[^:]+:	d5385505 	mrs	x5, erxmisc0_el1
+[^:]+:	d5185525 	msr	erxmisc1_el1, x5
+[^:]+:	d5385525 	mrs	x5, erxmisc1_el1
+[^:]+:	d53c5265 	mrs	x5, vsesr_el2
+[^:]+:	d518c125 	msr	disr_el1, x5
+[^:]+:	d538c125 	mrs	x5, disr_el1
+[^:]+:	d53cc125 	mrs	x5, vdisr_el2
--- a/gas/testsuite/gas/aarch64/armv8-ras-1.s
+++ b/gas/testsuite/gas/aarch64/armv8-ras-1.s
@ -0,0 +1,73 @@
+	/* ARMv8 RAS Extension.  */
+	.text
+
+	.macro rw_sys_reg sys_reg xreg r w
+	.ifc \w, 1
+	msr \sys_reg, \xreg
+	.endif
+	.ifc \r, 1
+	mrs \xreg, \sys_reg
+	.endif
+	.endm
+
+	/* ARMv8-A.  */
+	.arch armv8-a+ras
+	esb
+	hint #0x10
+
+	rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
+
+	rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
+
+	rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
+
+	rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
+
+	/* ARMv8.1-A.  */
+
+	.arch armv8.1-a+ras
+	esb
+	hint #0x10
+
+	rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
+
+	rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
+
+	rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
+
+	rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
+
+	/* ARMv8.2-A.  */
+
+	.arch armv8.2-a+ras
+	esb
+	hint #0x10
+
+	rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
+
+	rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
+
+	rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
+
+	rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
--- a/gas/testsuite/gas/aarch64/illegal-ras-1.d
+++ b/gas/testsuite/gas/aarch64/illegal-ras-1.d
@ -0,0 +1,4 @@
+#name: Illegal RAS instruction use.
+#source: illegal-ras-1.s
+#as: -march=armv8-a -mno-verbose-error
+#error-output: illegal-ras-1.l
--- a/gas/testsuite/gas/aarch64/illegal-ras-1.l
+++ b/gas/testsuite/gas/aarch64/illegal-ras-1.l
@ -0,0 +1,39 @@
+[^:]+: Assembler messages:
+^[^:]+:[0-9]+: Error: selected processor does not support `esb'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erridr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxfr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el2'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el2'
+^[^:]+:[0-9]+: Error: selected processor does not support `esb'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erridr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxfr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el2'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
+^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el2'
--- a/gas/testsuite/gas/aarch64/illegal-ras-1.s
+++ b/gas/testsuite/gas/aarch64/illegal-ras-1.s
@ -0,0 +1,52 @@
+	/* Incorrect use of the RAS extension instructions. */
+	.text
+
+	.macro rw_sys_reg sys_reg xreg r w
+	.ifc \w, 1
+	msr \sys_reg, \xreg
+	.endif
+	.ifc \r, 1
+	mrs \xreg, \sys_reg
+	.endif
+	.endm
+
+	/* ARMv8-A.  */
+	.arch armv8-a
+	esb
+	hint #0x10
+
+	rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
+
+	rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
+
+	rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
+
+	rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
+
+	/* ARMv8.1-A.  */
+
+	.arch armv8.1-a
+	esb
+	hint #0x10
+
+	rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
+
+	rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
+
+	rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
+
+	rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
+	rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
+	rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0