[AArch64] Support RAS extension for ARMv8 onwards.
The RAS extension was introduced as part of the ARMv8.2 architecture where it is a required feature. It is also available as an optional feature for ARMv8 and ARMv8.1. In binutils, the RAS extension is currently enabled by default for -march=armv8.2-a but is not available for -march=armv8 or -march=armv8.1-a. This patch adds the feature extension '+ras' to enable the RAS extension for ARMv8 and ARMv8.1, it is disabled by default. gas/ 2016-04-20 Matthew Wahab <matthew.wahab@arm.com> * config/tc-aarch64.c (aarch64_features): Add "ras". * doc/c-aarch64.texi (AArch64 Extensions): Add "ras". * testsuite/gas/aarch64/armv8-ras-1.d: New. * testsuite/gas/aarch64/armv8-ras-1.s: New. * testsuite/gas/aarch64/illegal-ras-1.d: New. * testsuite/gas/aarch64/illegal-ras-1.s: New. Change-Id: I824fb9bc8cf846bcc03aa17a726efb1350d78b9d
This commit is contained in:
parent
87d455c042
commit
50cc854c48
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@ -1,3 +1,12 @@
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2016-04-20 Matthew Wahab <matthew.wahab@arm.com>
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* config/tc-aarch64.c (aarch64_features): Add "ras".
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* doc/c-aarch64.texi (AArch64 Extensions): Add "ras".
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* testsuite/gas/aarch64/armv8-ras-1.d: New.
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* testsuite/gas/aarch64/armv8-ras-1.s: New.
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* testsuite/gas/aarch64/illegal-ras-1.d: New.
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* testsuite/gas/aarch64/illegal-ras-1.s: New.
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2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
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2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
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* testsuite/gas/arc/nps400-6.d: New file.
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* testsuite/gas/arc/nps400-6.d: New file.
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@ -7809,6 +7809,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
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{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
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{"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0)},
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{"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0)},
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{"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0)},
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{"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0)},
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{"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0)},
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{"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
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{"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
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| AARCH64_FEATURE_RDMA, 0)},
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| AARCH64_FEATURE_RDMA, 0)},
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{"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
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{"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
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@ -145,6 +145,9 @@ automatically cause those extensions to be disabled.
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@tab Enable Privileged Access Never support.
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@tab Enable Privileged Access Never support.
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@item @code{profile} @tab ARMv8.2-A @tab No
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@item @code{profile} @tab ARMv8.2-A @tab No
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@tab Enable statistical profiling extensions.
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@tab Enable statistical profiling extensions.
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@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
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@tab Enable the Reliability, Availability and Serviceability
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extension.
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@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
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@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
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@tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
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@tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
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@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
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@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
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@ -0,0 +1,68 @@
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#as: -march=armv8-a+ras
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#objdump: -dr
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.*: file format .*
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Disassembly of section \.text:
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0000000000000000 <.*>:
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[^:]+: d503221f esb
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[^:]+: d503221f esb
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[^:]+: d5385305 mrs x5, erridr_el1
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[^:]+: d5185327 msr errselr_el1, x7
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[^:]+: d5385327 mrs x7, errselr_el1
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[^:]+: d5385405 mrs x5, erxfr_el1
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[^:]+: d5185425 msr erxctlr_el1, x5
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[^:]+: d5385425 mrs x5, erxctlr_el1
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[^:]+: d5185445 msr erxstatus_el1, x5
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[^:]+: d5385445 mrs x5, erxstatus_el1
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[^:]+: d5185465 msr erxaddr_el1, x5
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[^:]+: d5385465 mrs x5, erxaddr_el1
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[^:]+: d5185505 msr erxmisc0_el1, x5
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[^:]+: d5385505 mrs x5, erxmisc0_el1
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[^:]+: d5185525 msr erxmisc1_el1, x5
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[^:]+: d5385525 mrs x5, erxmisc1_el1
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[^:]+: d53c5265 mrs x5, vsesr_el2
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[^:]+: d518c125 msr disr_el1, x5
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[^:]+: d538c125 mrs x5, disr_el1
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[^:]+: d53cc125 mrs x5, vdisr_el2
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[^:]+: d503221f esb
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[^:]+: d503221f esb
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[^:]+: d5385305 mrs x5, erridr_el1
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[^:]+: d5185327 msr errselr_el1, x7
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[^:]+: d5385327 mrs x7, errselr_el1
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[^:]+: d5385405 mrs x5, erxfr_el1
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[^:]+: d5185425 msr erxctlr_el1, x5
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[^:]+: d5385425 mrs x5, erxctlr_el1
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[^:]+: d5185445 msr erxstatus_el1, x5
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[^:]+: d5385445 mrs x5, erxstatus_el1
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[^:]+: d5185465 msr erxaddr_el1, x5
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[^:]+: d5385465 mrs x5, erxaddr_el1
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[^:]+: d5185505 msr erxmisc0_el1, x5
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[^:]+: d5385505 mrs x5, erxmisc0_el1
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[^:]+: d5185525 msr erxmisc1_el1, x5
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[^:]+: d5385525 mrs x5, erxmisc1_el1
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[^:]+: d53c5265 mrs x5, vsesr_el2
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[^:]+: d518c125 msr disr_el1, x5
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[^:]+: d538c125 mrs x5, disr_el1
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[^:]+: d53cc125 mrs x5, vdisr_el2
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[^:]+: d503221f esb
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[^:]+: d503221f esb
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[^:]+: d5385305 mrs x5, erridr_el1
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[^:]+: d5185327 msr errselr_el1, x7
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[^:]+: d5385327 mrs x7, errselr_el1
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[^:]+: d5385405 mrs x5, erxfr_el1
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[^:]+: d5185425 msr erxctlr_el1, x5
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[^:]+: d5385425 mrs x5, erxctlr_el1
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[^:]+: d5185445 msr erxstatus_el1, x5
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[^:]+: d5385445 mrs x5, erxstatus_el1
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[^:]+: d5185465 msr erxaddr_el1, x5
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[^:]+: d5385465 mrs x5, erxaddr_el1
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[^:]+: d5185505 msr erxmisc0_el1, x5
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[^:]+: d5385505 mrs x5, erxmisc0_el1
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[^:]+: d5185525 msr erxmisc1_el1, x5
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[^:]+: d5385525 mrs x5, erxmisc1_el1
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[^:]+: d53c5265 mrs x5, vsesr_el2
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[^:]+: d518c125 msr disr_el1, x5
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[^:]+: d538c125 mrs x5, disr_el1
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[^:]+: d53cc125 mrs x5, vdisr_el2
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@ -0,0 +1,73 @@
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/* ARMv8 RAS Extension. */
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.text
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.macro rw_sys_reg sys_reg xreg r w
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.ifc \w, 1
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msr \sys_reg, \xreg
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.endif
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.ifc \r, 1
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mrs \xreg, \sys_reg
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.endif
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.endm
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/* ARMv8-A. */
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.arch armv8-a+ras
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esb
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hint #0x10
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rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
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rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
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/* ARMv8.1-A. */
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.arch armv8.1-a+ras
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esb
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hint #0x10
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rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
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rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
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/* ARMv8.2-A. */
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.arch armv8.2-a+ras
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esb
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hint #0x10
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rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
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rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
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@ -0,0 +1,4 @@
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#name: Illegal RAS instruction use.
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#source: illegal-ras-1.s
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#as: -march=armv8-a -mno-verbose-error
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#error-output: illegal-ras-1.l
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@ -0,0 +1,39 @@
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[^:]+: Assembler messages:
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^[^:]+:[0-9]+: Error: selected processor does not support `esb'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erridr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxfr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el2'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el2'
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^[^:]+:[0-9]+: Error: selected processor does not support `esb'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erridr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'errselr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxfr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxctlr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxstatus_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxaddr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc0_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'erxmisc1_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el2'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'disr_el1'
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^[^:]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el2'
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@ -0,0 +1,52 @@
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/* Incorrect use of the RAS extension instructions. */
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.text
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.macro rw_sys_reg sys_reg xreg r w
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.ifc \w, 1
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msr \sys_reg, \xreg
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.endif
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.ifc \r, 1
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mrs \xreg, \sys_reg
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.endif
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.endm
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/* ARMv8-A. */
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.arch armv8-a
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esb
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hint #0x10
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rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
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rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
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rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
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rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
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/* ARMv8.1-A. */
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.arch armv8.1-a
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esb
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hint #0x10
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||||||
|
|
||||||
|
rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
|
||||||
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rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
|
||||||
|
|
||||||
|
rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
|
||||||
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rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
|
||||||
|
rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
|
||||||
|
rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
|
||||||
|
|
||||||
|
rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
|
||||||
|
rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
|
||||||
|
|
||||||
|
rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
|
||||||
|
rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
|
||||||
|
rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
|
Loading…
Reference in New Issue