gas/testsuite/
2008-08-27 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/intel.s: Add tests for fidivr. * gas/i386/intel.d: Updated. opcodes/ 2008-08-27 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Correct fidivr operand size. * i386-tbl.h: Regenerated.
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@ -1,3 +1,9 @@
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2008-08-27 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/intel.s: Add tests for fidivr.
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* gas/i386/intel.d: Updated.
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2008-08-26 Jie Zhang <jie.zhang@analog.com>
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2008-08-26 Jie Zhang <jie.zhang@analog.com>
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* gas/bfin/arith_mode.d: New test.
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* gas/bfin/arith_mode.d: New test.
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@ -688,4 +688,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
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[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
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[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
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[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
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[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
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[ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\)
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[ ]*[a-f0-9]+: de 3b fidivr \(%ebx\)
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[ ]*[a-f0-9]+: da 3b fidivrl \(%ebx\)
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#pass
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#pass
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@ -686,3 +686,6 @@ fsubrp
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fsubrp st(3)
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fsubrp st(3)
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fsubrp st(3),st
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fsubrp st(3),st
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fsubrp st,st(3)
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fsubrp st,st(3)
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fidivr word ptr [ebx]
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fidivr dword ptr [ebx]
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@ -1,3 +1,9 @@
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2008-08-27 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Correct fidivr operand size.
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* i386-tbl.h: Regenerated.
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2008-08-24 Alan Modra <amodra@bigpond.net.au>
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2008-08-24 Alan Modra <amodra@bigpond.net.au>
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* configure.in: Update a number of obsolete autoconf macros.
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* configure.in: Update a number of obsolete autoconf macros.
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@ -698,7 +698,7 @@ fdivr, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|U
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fdivr, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
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fdivr, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
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fdivr, 2, 0xd8f8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc }
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fdivr, 2, 0xd8f8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc }
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fdivr, 1, 0xd8, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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fdivr, 1, 0xd8, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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fidivr, 1, 0xde, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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fidivr, 1, 0xde, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
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fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
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fdivrp, 1, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
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fdivrp, 1, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }
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@ -5120,7 +5120,7 @@ const template i386_optab[] =
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1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
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1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0,
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0, 0, 1, 0, 0, 0 } } } },
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0, 0, 1, 0, 0, 0 } } } },
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{ "fdivrp", 2, 0xdef8, None, 2,
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{ "fdivrp", 2, 0xdef8, None, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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