2009-10-16 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h: Use enum instead of nested macros.
This commit is contained in:
H.J. Lu
parent
2927aacaee
commit
52a6c1fedd
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@ -1,3 +1,7 @@
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2009-10-16 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.h: Use enum instead of nested macros.
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2009-10-16 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c: Simplify enums.
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@ -30,90 +30,93 @@
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/* Position of cpu flags bitfiled. */
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/* i186 or better required */
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#define Cpu186 0
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/* i286 or better required */
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#define Cpu286 (Cpu186 + 1)
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/* i386 or better required */
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#define Cpu386 (Cpu286 + 1)
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/* i486 or better required */
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#define Cpu486 (Cpu386 + 1)
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/* i585 or better required */
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#define Cpu586 (Cpu486 + 1)
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/* i686 or better required */
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#define Cpu686 (Cpu586 + 1)
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/* CLFLUSH Instuction support required */
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#define CpuClflush (Cpu686 + 1)
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/* SYSCALL Instuctions support required */
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#define CpuSYSCALL (CpuClflush + 1)
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/* Floating point support required */
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#define Cpu8087 (CpuSYSCALL + 1)
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/* i287 support required */
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#define Cpu287 (Cpu8087 + 1)
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/* i387 support required */
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#define Cpu387 (Cpu287 + 1)
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/* i686 and floating point support required */
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#define Cpu687 (Cpu387 + 1)
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/* SSE3 and floating point support required */
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#define CpuFISTTP (Cpu687 + 1)
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/* MMX support required */
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#define CpuMMX (CpuFISTTP + 1)
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/* SSE support required */
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#define CpuSSE (CpuMMX + 1)
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/* SSE2 support required */
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#define CpuSSE2 (CpuSSE + 1)
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/* 3dnow! support required */
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#define Cpu3dnow (CpuSSE2 + 1)
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/* 3dnow! Extensions support required */
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#define Cpu3dnowA (Cpu3dnow + 1)
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/* SSE3 support required */
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#define CpuSSE3 (Cpu3dnowA + 1)
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/* VIA PadLock required */
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#define CpuPadLock (CpuSSE3 + 1)
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/* AMD Secure Virtual Machine Ext-s required */
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#define CpuSVME (CpuPadLock + 1)
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/* VMX Instructions required */
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#define CpuVMX (CpuSVME + 1)
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/* SMX Instructions required */
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#define CpuSMX (CpuVMX + 1)
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/* SSSE3 support required */
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#define CpuSSSE3 (CpuSMX + 1)
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/* SSE4a support required */
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#define CpuSSE4a (CpuSSSE3 + 1)
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/* ABM New Instructions required */
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#define CpuABM (CpuSSE4a + 1)
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/* SSE4.1 support required */
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#define CpuSSE4_1 (CpuABM + 1)
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/* SSE4.2 support required */
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#define CpuSSE4_2 (CpuSSE4_1 + 1)
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/* AVX support required */
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#define CpuAVX (CpuSSE4_2 + 1)
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/* Intel L1OM support required */
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#define CpuL1OM (CpuAVX + 1)
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/* Xsave/xrstor New Instuctions support required */
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#define CpuXsave (CpuL1OM + 1)
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/* AES support required */
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#define CpuAES (CpuXsave + 1)
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/* PCLMUL support required */
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#define CpuPCLMUL (CpuAES + 1)
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/* FMA support required */
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#define CpuFMA (CpuPCLMUL + 1)
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/* FMA4 support required */
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#define CpuFMA4 (CpuFMA + 1)
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/* MOVBE Instuction support required */
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#define CpuMovbe (CpuFMA4 + 1)
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/* EPT Instructions required */
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#define CpuEPT (CpuMovbe + 1)
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/* RDTSCP Instuction support required */
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#define CpuRdtscp (CpuEPT + 1)
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/* 64bit support available, used by -march= in assembler. */
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#define CpuLM (CpuRdtscp + 1)
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/* 64bit support required */
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#define Cpu64 (CpuLM + 1)
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/* Not supported in the 64bit mode */
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#define CpuNo64 (Cpu64 + 1)
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/* The last bitfield in i386_cpu_flags. */
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#define CpuMax CpuNo64
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enum
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{
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/* i186 or better required */
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Cpu186 = 0,
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/* i286 or better required */
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Cpu286,
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/* i386 or better required */
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Cpu386,
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/* i486 or better required */
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Cpu486,
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/* i585 or better required */
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Cpu586,
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/* i686 or better required */
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Cpu686,
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/* CLFLUSH Instuction support required */
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CpuClflush,
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/* SYSCALL Instuctions support required */
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CpuSYSCALL,
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/* Floating point support required */
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Cpu8087,
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/* i287 support required */
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Cpu287,
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/* i387 support required */
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Cpu387,
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/* i686 and floating point support required */
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Cpu687,
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/* SSE3 and floating point support required */
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CpuFISTTP,
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/* MMX support required */
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CpuMMX,
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/* SSE support required */
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CpuSSE,
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/* SSE2 support required */
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CpuSSE2,
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/* 3dnow! support required */
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Cpu3dnow,
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/* 3dnow! Extensions support required */
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Cpu3dnowA,
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/* SSE3 support required */
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CpuSSE3,
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/* VIA PadLock required */
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CpuPadLock,
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/* AMD Secure Virtual Machine Ext-s required */
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CpuSVME,
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/* VMX Instructions required */
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CpuVMX,
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/* SMX Instructions required */
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CpuSMX,
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/* SSSE3 support required */
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CpuSSSE3,
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/* SSE4a support required */
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CpuSSE4a,
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/* ABM New Instructions required */
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CpuABM,
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/* SSE4.1 support required */
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CpuSSE4_1,
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/* SSE4.2 support required */
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CpuSSE4_2,
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/* AVX support required */
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CpuAVX,
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/* Intel L1OM support required */
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CpuL1OM,
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/* Xsave/xrstor New Instuctions support required */
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CpuXsave,
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/* AES support required */
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CpuAES,
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/* PCLMUL support required */
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CpuPCLMUL,
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/* FMA support required */
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CpuFMA,
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/* FMA4 support required */
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CpuFMA4,
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/* MOVBE Instuction support required */
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CpuMovbe,
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/* EPT Instructions required */
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CpuEPT,
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/* RDTSCP Instuction support required */
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CpuRdtscp,
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/* 64bit support available, used by -march= in assembler. */
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CpuLM,
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/* 64bit support required */
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Cpu64,
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/* Not supported in the 64bit mode */
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CpuNo64,
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/* The last bitfield in i386_cpu_flags. */
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CpuMax = CpuNo64
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};
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#define CpuNumOfUints \
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(CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
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@ -180,123 +183,125 @@ typedef union i386_cpu_flags
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/* Position of opcode_modifier bits. */
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/* has direction bit. */
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#define D 0
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/* set if operands can be words or dwords encoded the canonical way */
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#define W (D + 1)
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/* Skip the current insn and use the next insn in i386-opc.tbl to swap
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operand in encoding. */
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#define S (W + 1)
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/* insn has a modrm byte. */
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#define Modrm (S + 1)
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/* register is in low 3 bits of opcode */
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#define ShortForm (Modrm + 1)
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/* special case for jump insns. */
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#define Jump (ShortForm + 1)
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/* call and jump */
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#define JumpDword (Jump + 1)
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/* loop and jecxz */
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#define JumpByte (JumpDword + 1)
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/* special case for intersegment leaps/calls */
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#define JumpInterSegment (JumpByte + 1)
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/* FP insn memory format bit, sized by 0x4 */
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#define FloatMF (JumpInterSegment + 1)
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/* src/dest swap for floats. */
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#define FloatR (FloatMF + 1)
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/* has float insn direction bit. */
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#define FloatD (FloatR + 1)
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/* needs size prefix if in 32-bit mode */
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#define Size16 (FloatD + 1)
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/* needs size prefix if in 16-bit mode */
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#define Size32 (Size16 + 1)
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/* needs size prefix if in 64-bit mode */
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#define Size64 (Size32 + 1)
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/* instruction ignores operand size prefix and in Intel mode ignores
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mnemonic size suffix check. */
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#define IgnoreSize (Size64 + 1)
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/* default insn size depends on mode */
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#define DefaultSize (IgnoreSize + 1)
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/* b suffix on instruction illegal */
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#define No_bSuf (DefaultSize + 1)
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/* w suffix on instruction illegal */
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#define No_wSuf (No_bSuf + 1)
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/* l suffix on instruction illegal */
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#define No_lSuf (No_wSuf + 1)
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/* s suffix on instruction illegal */
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#define No_sSuf (No_lSuf + 1)
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/* q suffix on instruction illegal */
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#define No_qSuf (No_sSuf + 1)
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/* long double suffix on instruction illegal */
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#define No_ldSuf (No_qSuf + 1)
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/* instruction needs FWAIT */
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#define FWait (No_ldSuf + 1)
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/* quick test for string instructions */
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#define IsString (FWait + 1)
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/* fake an extra reg operand for clr, imul and special register
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processing for some instructions. */
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#define RegKludge (IsString + 1)
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/* The first operand must be xmm0 */
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#define FirstXmm0 (RegKludge + 1)
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/* An implicit xmm0 as the first operand */
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#define Implicit1stXmm0 (FirstXmm0 + 1)
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/* BYTE is OK in Intel syntax. */
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#define ByteOkIntel (Implicit1stXmm0 + 1)
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/* Convert to DWORD */
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#define ToDword (ByteOkIntel + 1)
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/* Convert to QWORD */
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#define ToQword (ToDword + 1)
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/* Address prefix changes operand 0 */
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#define AddrPrefixOp0 (ToQword + 1)
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/* opcode is a prefix */
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#define IsPrefix (AddrPrefixOp0 + 1)
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/* instruction has extension in 8 bit imm */
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#define ImmExt (IsPrefix + 1)
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/* instruction don't need Rex64 prefix. */
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#define NoRex64 (ImmExt + 1)
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/* instruction require Rex64 prefix. */
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#define Rex64 (NoRex64 + 1)
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/* deprecated fp insn, gets a warning */
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#define Ugh (Rex64 + 1)
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/* insn has VEX prefix:
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enum
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{
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/* has direction bit. */
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D = 0,
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/* set if operands can be words or dwords encoded the canonical way */
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W,
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/* Skip the current insn and use the next insn in i386-opc.tbl to swap
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operand in encoding. */
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S,
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/* insn has a modrm byte. */
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Modrm,
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/* register is in low 3 bits of opcode */
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ShortForm,
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/* special case for jump insns. */
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Jump,
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/* call and jump */
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JumpDword,
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/* loop and jecxz */
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JumpByte,
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/* special case for intersegment leaps/calls */
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JumpInterSegment,
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/* FP insn memory format bit, sized by 0x4 */
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FloatMF,
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/* src/dest swap for floats. */
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FloatR,
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/* has float insn direction bit. */
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FloatD,
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/* needs size prefix if in 32-bit mode */
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Size16,
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/* needs size prefix if in 16-bit mode */
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Size32,
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/* needs size prefix if in 64-bit mode */
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Size64,
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/* instruction ignores operand size prefix and in Intel mode ignores
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mnemonic size suffix check. */
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IgnoreSize,
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/* default insn size depends on mode */
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DefaultSize,
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/* b suffix on instruction illegal */
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No_bSuf,
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/* w suffix on instruction illegal */
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No_wSuf,
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/* l suffix on instruction illegal */
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No_lSuf,
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/* s suffix on instruction illegal */
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No_sSuf,
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/* q suffix on instruction illegal */
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No_qSuf,
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/* long double suffix on instruction illegal */
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No_ldSuf,
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/* instruction needs FWAIT */
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FWait,
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/* quick test for string instructions */
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IsString,
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/* fake an extra reg operand for clr, imul and special register
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processing for some instructions. */
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RegKludge,
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/* The first operand must be xmm0 */
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FirstXmm0,
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/* An implicit xmm0 as the first operand */
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Implicit1stXmm0,
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/* BYTE is OK in Intel syntax. */
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ByteOkIntel,
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/* Convert to DWORD */
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ToDword,
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/* Convert to QWORD */
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ToQword,
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/* Address prefix changes operand 0 */
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AddrPrefixOp0,
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/* opcode is a prefix */
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IsPrefix,
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/* instruction has extension in 8 bit imm */
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ImmExt,
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/* instruction don't need Rex64 prefix. */
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NoRex64,
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/* instruction require Rex64 prefix. */
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Rex64,
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/* deprecated fp insn, gets a warning */
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Ugh,
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/* insn has VEX prefix:
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1: 128bit VEX prefix.
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2: 256bit VEX prefix.
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*/
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#define Vex (Ugh + 1)
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/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
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We use VexNDS on insns with VEX DDS since the register-only source
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is the second source register. */
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#define VexNDS (Vex + 1)
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/* insn has VEX NDD. Register destination is encoded in Vex
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prefix. */
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#define VexNDD (VexNDS + 1)
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/* insn has VEX W0. */
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#define VexW0 (VexNDD + 1)
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/* insn has VEX W1. */
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#define VexW1 (VexW0 + 1)
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/* insn has VEX 0x0F opcode prefix. */
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#define Vex0F (VexW1 + 1)
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/* insn has VEX 0x0F38 opcode prefix. */
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#define Vex0F38 (Vex0F + 1)
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/* insn has VEX 0x0F3A opcode prefix. */
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#define Vex0F3A (Vex0F38 + 1)
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/* insn has VEX prefix with 3 soures. */
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#define Vex3Sources (Vex0F3A + 1)
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/* instruction has VEX 8 bit imm */
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#define VexImmExt (Vex3Sources + 1)
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/* SSE to AVX support required */
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#define SSE2AVX (VexImmExt + 1)
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/* No AVX equivalent */
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#define NoAVX (SSE2AVX + 1)
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/* Compatible with old (<= 2.8.1) versions of gcc */
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#define OldGcc (NoAVX + 1)
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/* AT&T mnemonic. */
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#define ATTMnemonic (OldGcc + 1)
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/* AT&T syntax. */
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#define ATTSyntax (ATTMnemonic + 1)
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/* Intel syntax. */
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#define IntelSyntax (ATTSyntax + 1)
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/* The last bitfield in i386_opcode_modifier. */
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#define Opcode_Modifier_Max IntelSyntax
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*/
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Vex,
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/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
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We use VexNDS on insns with VEX DDS since the register-only source
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is the second source register. */
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VexNDS,
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/* insn has VEX NDD. Register destination is encoded in Vex prefix. */
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VexNDD,
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/* insn has VEX W0. */
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VexW0,
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/* insn has VEX W1. */
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VexW1,
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/* insn has VEX 0x0F opcode prefix. */
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Vex0F,
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/* insn has VEX 0x0F38 opcode prefix. */
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Vex0F38,
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/* insn has VEX 0x0F3A opcode prefix. */
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Vex0F3A,
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/* insn has VEX prefix with 3 soures. */
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Vex3Sources,
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/* instruction has VEX 8 bit imm */
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VexImmExt,
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/* SSE to AVX support required */
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SSE2AVX,
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/* No AVX equivalent */
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NoAVX,
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/* Compatible with old (<= 2.8.1) versions of gcc */
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OldGcc,
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/* AT&T mnemonic. */
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ATTMnemonic,
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/* AT&T syntax. */
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ATTSyntax,
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/* Intel syntax. */
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IntelSyntax,
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/* The last bitfield in i386_opcode_modifier. */
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Opcode_Modifier_Max
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};
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typedef struct i386_opcode_modifier
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{
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@ -357,108 +362,111 @@ typedef struct i386_opcode_modifier
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/* Position of operand_type bits. */
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/* 8bit register */
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#define Reg8 0
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/* 16bit register */
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#define Reg16 (Reg8 + 1)
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/* 32bit register */
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#define Reg32 (Reg16 + 1)
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/* 64bit register */
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#define Reg64 (Reg32 + 1)
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/* Floating pointer stack register */
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#define FloatReg (Reg64 + 1)
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/* MMX register */
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#define RegMMX (FloatReg + 1)
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/* SSE register */
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#define RegXMM (RegMMX + 1)
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/* AVX registers */
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#define RegYMM (RegXMM + 1)
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/* Control register */
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#define Control (RegYMM + 1)
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/* Debug register */
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#define Debug (Control + 1)
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/* Test register */
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#define Test (Debug + 1)
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/* 2 bit segment register */
|
||||
#define SReg2 (Test + 1)
|
||||
/* 3 bit segment register */
|
||||
#define SReg3 (SReg2 + 1)
|
||||
/* 1 bit immediate */
|
||||
#define Imm1 (SReg3 + 1)
|
||||
/* 8 bit immediate */
|
||||
#define Imm8 (Imm1 + 1)
|
||||
/* 8 bit immediate sign extended */
|
||||
#define Imm8S (Imm8 + 1)
|
||||
/* 16 bit immediate */
|
||||
#define Imm16 (Imm8S + 1)
|
||||
/* 32 bit immediate */
|
||||
#define Imm32 (Imm16 + 1)
|
||||
/* 32 bit immediate sign extended */
|
||||
#define Imm32S (Imm32 + 1)
|
||||
/* 64 bit immediate */
|
||||
#define Imm64 (Imm32S + 1)
|
||||
/* 8bit/16bit/32bit displacements are used in different ways,
|
||||
depending on the instruction. For jumps, they specify the
|
||||
size of the PC relative displacement, for instructions with
|
||||
memory operand, they specify the size of the offset relative
|
||||
to the base register, and for instructions with memory offset
|
||||
such as `mov 1234,%al' they specify the size of the offset
|
||||
relative to the segment base. */
|
||||
/* 8 bit displacement */
|
||||
#define Disp8 (Imm64 + 1)
|
||||
/* 16 bit displacement */
|
||||
#define Disp16 (Disp8 + 1)
|
||||
/* 32 bit displacement */
|
||||
#define Disp32 (Disp16 + 1)
|
||||
/* 32 bit signed displacement */
|
||||
#define Disp32S (Disp32 + 1)
|
||||
/* 64 bit displacement */
|
||||
#define Disp64 (Disp32S + 1)
|
||||
/* Accumulator %al/%ax/%eax/%rax */
|
||||
#define Acc (Disp64 + 1)
|
||||
/* Floating pointer top stack register %st(0) */
|
||||
#define FloatAcc (Acc + 1)
|
||||
/* Register which can be used for base or index in memory operand. */
|
||||
#define BaseIndex (FloatAcc + 1)
|
||||
/* Register to hold in/out port addr = dx */
|
||||
#define InOutPortReg (BaseIndex + 1)
|
||||
/* Register to hold shift count = cl */
|
||||
#define ShiftCount (InOutPortReg + 1)
|
||||
/* Absolute address for jump. */
|
||||
#define JumpAbsolute (ShiftCount + 1)
|
||||
/* String insn operand with fixed es segment */
|
||||
#define EsSeg (JumpAbsolute + 1)
|
||||
/* RegMem is for instructions with a modrm byte where the register
|
||||
destination operand should be encoded in the mod and regmem fields.
|
||||
Normally, it will be encoded in the reg field. We add a RegMem
|
||||
flag to the destination register operand to indicate that it should
|
||||
be encoded in the regmem field. */
|
||||
#define RegMem (EsSeg + 1)
|
||||
/* Memory. */
|
||||
#define Mem (RegMem + 1)
|
||||
/* BYTE memory. */
|
||||
#define Byte (Mem + 1)
|
||||
/* WORD memory. 2 byte */
|
||||
#define Word (Byte + 1)
|
||||
/* DWORD memory. 4 byte */
|
||||
#define Dword (Word + 1)
|
||||
/* FWORD memory. 6 byte */
|
||||
#define Fword (Dword + 1)
|
||||
/* QWORD memory. 8 byte */
|
||||
#define Qword (Fword + 1)
|
||||
/* TBYTE memory. 10 byte */
|
||||
#define Tbyte (Qword + 1)
|
||||
/* XMMWORD memory. */
|
||||
#define Xmmword (Tbyte + 1)
|
||||
/* YMMWORD memory. */
|
||||
#define Ymmword (Xmmword + 1)
|
||||
/* Unspecified memory size. */
|
||||
#define Unspecified (Ymmword + 1)
|
||||
/* Any memory size. */
|
||||
#define Anysize (Unspecified + 1)
|
||||
enum
|
||||
{
|
||||
/* 8bit register */
|
||||
Reg8 = 0,
|
||||
/* 16bit register */
|
||||
Reg16,
|
||||
/* 32bit register */
|
||||
Reg32,
|
||||
/* 64bit register */
|
||||
Reg64,
|
||||
/* Floating pointer stack register */
|
||||
FloatReg,
|
||||
/* MMX register */
|
||||
RegMMX,
|
||||
/* SSE register */
|
||||
RegXMM,
|
||||
/* AVX registers */
|
||||
RegYMM,
|
||||
/* Control register */
|
||||
Control,
|
||||
/* Debug register */
|
||||
Debug,
|
||||
/* Test register */
|
||||
Test,
|
||||
/* 2 bit segment register */
|
||||
SReg2,
|
||||
/* 3 bit segment register */
|
||||
SReg3,
|
||||
/* 1 bit immediate */
|
||||
Imm1,
|
||||
/* 8 bit immediate */
|
||||
Imm8,
|
||||
/* 8 bit immediate sign extended */
|
||||
Imm8S,
|
||||
/* 16 bit immediate */
|
||||
Imm16,
|
||||
/* 32 bit immediate */
|
||||
Imm32,
|
||||
/* 32 bit immediate sign extended */
|
||||
Imm32S,
|
||||
/* 64 bit immediate */
|
||||
Imm64,
|
||||
/* 8bit/16bit/32bit displacements are used in different ways,
|
||||
depending on the instruction. For jumps, they specify the
|
||||
size of the PC relative displacement, for instructions with
|
||||
memory operand, they specify the size of the offset relative
|
||||
to the base register, and for instructions with memory offset
|
||||
such as `mov 1234,%al' they specify the size of the offset
|
||||
relative to the segment base. */
|
||||
/* 8 bit displacement */
|
||||
Disp8,
|
||||
/* 16 bit displacement */
|
||||
Disp16,
|
||||
/* 32 bit displacement */
|
||||
Disp32,
|
||||
/* 32 bit signed displacement */
|
||||
Disp32S,
|
||||
/* 64 bit displacement */
|
||||
Disp64,
|
||||
/* Accumulator %al/%ax/%eax/%rax */
|
||||
Acc,
|
||||
/* Floating pointer top stack register %st(0) */
|
||||
FloatAcc,
|
||||
/* Register which can be used for base or index in memory operand. */
|
||||
BaseIndex,
|
||||
/* Register to hold in/out port addr = dx */
|
||||
InOutPortReg,
|
||||
/* Register to hold shift count = cl */
|
||||
ShiftCount,
|
||||
/* Absolute address for jump. */
|
||||
JumpAbsolute,
|
||||
/* String insn operand with fixed es segment */
|
||||
EsSeg,
|
||||
/* RegMem is for instructions with a modrm byte where the register
|
||||
destination operand should be encoded in the mod and regmem fields.
|
||||
Normally, it will be encoded in the reg field. We add a RegMem
|
||||
flag to the destination register operand to indicate that it should
|
||||
be encoded in the regmem field. */
|
||||
RegMem,
|
||||
/* Memory. */
|
||||
Mem,
|
||||
/* BYTE memory. */
|
||||
Byte,
|
||||
/* WORD memory. 2 byte */
|
||||
Word,
|
||||
/* DWORD memory. 4 byte */
|
||||
Dword,
|
||||
/* FWORD memory. 6 byte */
|
||||
Fword,
|
||||
/* QWORD memory. 8 byte */
|
||||
Qword,
|
||||
/* TBYTE memory. 10 byte */
|
||||
Tbyte,
|
||||
/* XMMWORD memory. */
|
||||
Xmmword,
|
||||
/* YMMWORD memory. */
|
||||
Ymmword,
|
||||
/* Unspecified memory size. */
|
||||
Unspecified,
|
||||
/* Any memory size. */
|
||||
Anysize,
|
||||
|
||||
/* The last bitfield in i386_operand_type. */
|
||||
#define OTMax Anysize
|
||||
/* The last bitfield in i386_operand_type. */
|
||||
OTMax
|
||||
};
|
||||
|
||||
#define OTNumOfUints \
|
||||
(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
|
||||
|
|
|
|||
Loading…
Reference in New Issue