opcodes/
2006-11-30 Jan Beulich <jbeulich@novell.com> * i386-dis.c (zAX): New. (Xz): New. (Yzr): New. (z_mode): New. (z_mode_ax_reg): New. (putop): New suffix character 'G'. (dis386): Use it for in, out, ins, and outs. (intel_operand_size): Handle z_mode. (OP_REG): Delete unreachable case indir_dx_reg. (OP_IMREG): Fix Intel syntax output for case indir_dx_reg. Handle z_mode_ax_reg. (OP_ESreg): Fix Intel syntax operand size handling. (OP_DSreg): Likewise. gas/testsuite/ 2006-11-30 Jan Beulich <jbeulich@novell.com> * gas/i386/x86-64-io.[sd]: New. * gas/i386/x86-64-io-intel.d: New. * gas/i386/x86-64-io-suffix.d: New. * gas/i386/i386.exp: Run new tests.
This commit is contained in:
parent
a35ca55aee
commit
52fd6d9416
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@ -1,3 +1,10 @@
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2006-11-30 Jan Beulich <jbeulich@novell.com>
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* gas/i386/x86-64-io.[sd]: New.
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* gas/i386/x86-64-io-intel.d: New.
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* gas/i386/x86-64-io-suffix.d: New.
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* gas/i386/i386.exp: Run new tests.
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2006-11-30 Jan Beulich <jbeulich@novell.com>
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2006-11-30 Jan Beulich <jbeulich@novell.com>
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* gas/i386/intel.s: Use Intel syntax in Intel syntax test.
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* gas/i386/intel.s: Use Intel syntax in Intel syntax test.
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@ -157,6 +157,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-rep-suffix"
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run_dump_test "x86-64-rep-suffix"
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run_dump_test "x86-64-cbw"
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run_dump_test "x86-64-cbw"
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run_dump_test "x86-64-cbw-intel"
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run_dump_test "x86-64-cbw-intel"
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run_dump_test "x86-64-io"
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run_dump_test "x86-64-io-intel"
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run_dump_test "x86-64-io-suffix"
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run_dump_test "x86-64-gidt"
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run_dump_test "x86-64-gidt"
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run_dump_test "x86-64-nops"
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run_dump_test "x86-64-nops"
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if ![istarget "*-*-mingw64*"] then {
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if ![istarget "*-*-mingw64*"] then {
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@ -0,0 +1,28 @@
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#source: x86-64-io.s
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#objdump: -dwMintel
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#name: x86-64 rex64 in/out (Intel disassembly)
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.*: +file format .*
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Disassembly of section .text:
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0+000 <_in>:
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0: 48 ed rex64 in eax,dx
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2: 66 data16
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3: 48 ed rex64 in eax,dx
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0+005 <_out>:
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5: 48 ef rex64 out dx,eax
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7: 66 data16
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8: 48 ef rex64 out dx,eax
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0+00a <_ins>:
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a: 48 6d rex64 ins DWORD PTR es:\[rdi\],dx
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c: 66 data16
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d: 48 6d rex64 ins DWORD PTR es:\[rdi\],dx
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0+00f <_outs>:
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f: 48 6f rex64 outs dx,DWORD PTR ds:\[rsi\]
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11: 66 data16
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12: 48 6f rex64 outs dx,DWORD PTR ds:\[rsi\]
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#pass
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@ -0,0 +1,28 @@
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#source: x86-64-io.s
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#objdump: -dwMsuffix
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#name: x86-64 rex64 in/out w/ suffix
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.*: +file format .*
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Disassembly of section .text:
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0+000 <_in>:
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0: 48 ed rex64 inl \(%dx\),%eax
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2: 66 data16
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3: 48 ed rex64 inl \(%dx\),%eax
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0+005 <_out>:
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5: 48 ef rex64 outl %eax,\(%dx\)
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7: 66 data16
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8: 48 ef rex64 outl %eax,\(%dx\)
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0+00a <_ins>:
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a: 48 6d rex64 insl \(%dx\),%es:\(%rdi\)
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c: 66 data16
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d: 48 6d rex64 insl \(%dx\),%es:\(%rdi\)
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0+00f <_outs>:
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f: 48 6f rex64 outsl %ds:\(%rsi\),\(%dx\)
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11: 66 data16
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12: 48 6f rex64 outsl %ds:\(%rsi\),\(%dx\)
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#pass
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@ -0,0 +1,27 @@
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#objdump: -dw
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#name: x86-64 rex64 in/out
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.*: +file format .*
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Disassembly of section .text:
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0+000 <_in>:
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0: 48 ed rex64 in \(%dx\),%eax
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2: 66 data16
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3: 48 ed rex64 in \(%dx\),%eax
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0+005 <_out>:
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5: 48 ef rex64 out %eax,\(%dx\)
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7: 66 data16
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8: 48 ef rex64 out %eax,\(%dx\)
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0+00a <_ins>:
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a: 48 6d rex64 insl \(%dx\),%es:\(%rdi\)
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c: 66 data16
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d: 48 6d rex64 insl \(%dx\),%es:\(%rdi\)
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0+00f <_outs>:
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f: 48 6f rex64 outsl %ds:\(%rsi\),\(%dx\)
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11: 66 data16
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12: 48 6f rex64 outsl %ds:\(%rsi\),\(%dx\)
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#pass
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@ -0,0 +1,16 @@
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.intel_syntax noprefix
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.text
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_in:
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rex64 in eax,dx
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rex64 in ax,dx
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_out:
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rex64 out dx,eax
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rex64 out dx,ax
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_ins:
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rex64 insd
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rex64 insw
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_outs:
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rex64 outsd
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rex64 outsw
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.p2align 4,0
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@ -1,3 +1,19 @@
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2006-11-30 Jan Beulich <jbeulich@novell.com>
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* i386-dis.c (zAX): New.
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(Xz): New.
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(Yzr): New.
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(z_mode): New.
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(z_mode_ax_reg): New.
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(putop): New suffix character 'G'.
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(dis386): Use it for in, out, ins, and outs.
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(intel_operand_size): Handle z_mode.
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(OP_REG): Delete unreachable case indir_dx_reg.
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(OP_IMREG): Fix Intel syntax output for case indir_dx_reg. Handle
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z_mode_ax_reg.
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(OP_ESreg): Fix Intel syntax operand size handling.
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(OP_DSreg): Likewise.
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2006-11-30 Jan Beulich <jbeulich@novell.com>
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2006-11-30 Jan Beulich <jbeulich@novell.com>
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* i386-dis.c (dis386): Use 'R' and 'O' for cbw/cwd unconditionally.
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* i386-dis.c (dis386): Use 'R' and 'O' for cbw/cwd unconditionally.
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@ -289,6 +289,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define BH OP_IMREG, bh_reg
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#define BH OP_IMREG, bh_reg
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#define AX OP_IMREG, ax_reg
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#define AX OP_IMREG, ax_reg
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#define DX OP_IMREG, dx_reg
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#define DX OP_IMREG, dx_reg
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#define zAX OP_IMREG, z_mode_ax_reg
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#define indirDX OP_IMREG, indir_dx_reg
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#define indirDX OP_IMREG, indir_dx_reg
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#define Sw OP_SEG, w_mode
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#define Sw OP_SEG, w_mode
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@ -297,6 +298,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define Ov OP_OFF64, v_mode
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#define Ov OP_OFF64, v_mode
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#define Xb OP_DSreg, eSI_reg
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#define Xb OP_DSreg, eSI_reg
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#define Xv OP_DSreg, eSI_reg
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#define Xv OP_DSreg, eSI_reg
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#define Xz OP_DSreg, eSI_reg
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#define Yb OP_ESreg, eDI_reg
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#define Yb OP_ESreg, eDI_reg
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#define Yv OP_ESreg, eDI_reg
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#define Yv OP_ESreg, eDI_reg
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#define DSBX OP_DSreg, eBX_reg
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#define DSBX OP_DSreg, eBX_reg
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@ -325,6 +327,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define Xvr REP_Fixup, eSI_reg
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#define Xvr REP_Fixup, eSI_reg
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#define Ybr REP_Fixup, eDI_reg
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#define Ybr REP_Fixup, eDI_reg
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#define Yvr REP_Fixup, eDI_reg
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#define Yvr REP_Fixup, eDI_reg
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#define Yzr REP_Fixup, eDI_reg
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#define indirDXr REP_Fixup, indir_dx_reg
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#define indirDXr REP_Fixup, indir_dx_reg
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#define ALr REP_Fixup, al_reg
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#define ALr REP_Fixup, al_reg
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#define eAXr REP_Fixup, eAX_reg
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#define eAXr REP_Fixup, eAX_reg
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@ -352,6 +355,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define f_mode 13 /* 4- or 6-byte pointer operand */
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#define f_mode 13 /* 4- or 6-byte pointer operand */
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#define const_1_mode 14
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#define const_1_mode 14
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#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
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#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
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#define z_mode 16 /* non-quad operand size depends on prefixes */
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#define es_reg 100
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#define es_reg 100
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#define cs_reg 101
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#define cs_reg 101
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@ -396,6 +400,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define rSI_reg 138
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#define rSI_reg 138
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#define rDI_reg 139
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#define rDI_reg 139
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#define z_mode_ax_reg 149
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#define indir_dx_reg 150
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#define indir_dx_reg 150
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#define FLOATCODE 1
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#define FLOATCODE 1
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@ -500,6 +505,7 @@ struct dis386 {
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. size prefix
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. size prefix
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'E' => print 'e' if 32-bit form of jcxz
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'E' => print 'e' if 32-bit form of jcxz
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'F' => print 'w' or 'l' depending on address size prefix (loop insns)
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'F' => print 'w' or 'l' depending on address size prefix (loop insns)
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'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
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'H' => print ",pt" or ",pn" branch hint
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'H' => print ",pt" or ",pn" branch hint
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'I' => honor following macro letter even in Intel mode (implemented only
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'I' => honor following macro letter even in Intel mode (implemented only
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. for some of the macro letters)
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. for some of the macro letters)
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@ -654,9 +660,9 @@ static const struct dis386 dis386[] = {
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{ "pushT", sIb, XX, XX, XX },
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{ "pushT", sIb, XX, XX, XX },
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{ "imulS", Gv, Ev, sIb, XX },
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{ "imulS", Gv, Ev, sIb, XX },
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{ "ins{b||b|}", Ybr, indirDX, XX, XX },
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{ "ins{b||b|}", Ybr, indirDX, XX, XX },
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{ "ins{R||R|}", Yvr, indirDX, XX, XX },
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{ "ins{R||G|}", Yzr, indirDX, XX, XX },
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{ "outs{b||b|}", indirDXr, Xb, XX, XX },
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{ "outs{b||b|}", indirDXr, Xb, XX, XX },
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{ "outs{R||R|}", indirDXr, Xv, XX, XX },
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{ "outs{R||G|}", indirDXr, Xz, XX, XX },
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/* 70 */
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/* 70 */
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{ "joH", Jb, XX, cond_jump_flag, XX },
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{ "joH", Jb, XX, cond_jump_flag, XX },
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{ "jnoH", Jb, XX, cond_jump_flag, XX },
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{ "jnoH", Jb, XX, cond_jump_flag, XX },
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@ -789,18 +795,18 @@ static const struct dis386 dis386[] = {
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{ "loopFH", Jb, XX, loop_jcxz_flag, XX },
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{ "loopFH", Jb, XX, loop_jcxz_flag, XX },
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{ "jEcxzH", Jb, XX, loop_jcxz_flag, XX },
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{ "jEcxzH", Jb, XX, loop_jcxz_flag, XX },
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{ "inB", AL, Ib, XX, XX },
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{ "inB", AL, Ib, XX, XX },
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{ "inS", eAX, Ib, XX, XX },
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{ "inG", zAX, Ib, XX, XX },
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{ "outB", Ib, AL, XX, XX },
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{ "outB", Ib, AL, XX, XX },
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{ "outS", Ib, eAX, XX, XX },
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{ "outG", Ib, zAX, XX, XX },
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/* e8 */
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/* e8 */
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{ "callT", Jv, XX, XX, XX },
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{ "callT", Jv, XX, XX, XX },
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{ "jmpT", Jv, XX, XX, XX },
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{ "jmpT", Jv, XX, XX, XX },
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{ "Jjmp{T|}", Ap, XX, XX, XX },
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{ "Jjmp{T|}", Ap, XX, XX, XX },
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{ "jmp", Jb, XX, XX, XX },
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{ "jmp", Jb, XX, XX, XX },
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{ "inB", AL, indirDX, XX, XX },
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{ "inB", AL, indirDX, XX, XX },
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{ "inS", eAX, indirDX, XX, XX },
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{ "inG", zAX, indirDX, XX, XX },
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{ "outB", indirDX, AL, XX, XX },
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{ "outB", indirDX, AL, XX, XX },
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{ "outS", indirDX, eAX, XX, XX },
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{ "outG", indirDX, zAX, XX, XX },
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/* f0 */
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/* f0 */
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{ "(bad)", XX, XX, XX, XX }, /* lock prefix */
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{ "(bad)", XX, XX, XX, XX }, /* lock prefix */
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{ "icebp", XX, XX, XX, XX },
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{ "icebp", XX, XX, XX, XX },
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@ -3767,6 +3773,16 @@ putop (const char *template, int sizeflag)
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used_prefixes |= (prefixes & PREFIX_ADDR);
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used_prefixes |= (prefixes & PREFIX_ADDR);
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}
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}
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break;
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break;
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case 'G':
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if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
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break;
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if ((rex & REX_MODE64) || (sizeflag & DFLAG))
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*obufp++ = 'l';
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else
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*obufp++ = 'w';
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if (!(rex & REX_MODE64))
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used_prefixes |= (prefixes & PREFIX_DATA);
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break;
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case 'H':
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case 'H':
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if (intel_syntax)
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if (intel_syntax)
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break;
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break;
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@ -4101,6 +4117,13 @@ intel_operand_size (int bytemode, int sizeflag)
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oappend ("WORD PTR ");
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oappend ("WORD PTR ");
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used_prefixes |= (prefixes & PREFIX_DATA);
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used_prefixes |= (prefixes & PREFIX_DATA);
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break;
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break;
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case z_mode:
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if ((rex & REX_MODE64) || (sizeflag & DFLAG))
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*obufp++ = 'D';
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oappend ("WORD PTR ");
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if (!(rex & REX_MODE64))
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used_prefixes |= (prefixes & PREFIX_DATA);
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break;
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case d_mode:
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case d_mode:
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oappend ("DWORD PTR ");
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oappend ("DWORD PTR ");
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break;
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break;
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@ -4551,12 +4574,6 @@ OP_REG (int code, int sizeflag)
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switch (code)
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switch (code)
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{
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{
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case indir_dx_reg:
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if (intel_syntax)
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s = "[dx]";
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else
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s = "(%dx)";
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break;
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case ax_reg: case cx_reg: case dx_reg: case bx_reg:
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case ax_reg: case cx_reg: case dx_reg: case bx_reg:
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case sp_reg: case bp_reg: case si_reg: case di_reg:
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case sp_reg: case bp_reg: case si_reg: case di_reg:
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s = names16[code - ax_reg + add];
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s = names16[code - ax_reg + add];
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@ -4609,7 +4626,7 @@ OP_IMREG (int code, int sizeflag)
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{
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{
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case indir_dx_reg:
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case indir_dx_reg:
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if (intel_syntax)
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if (intel_syntax)
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s = "[dx]";
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s = "dx";
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else
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else
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s = "(%dx)";
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s = "(%dx)";
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break;
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break;
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@ -4640,6 +4657,14 @@ OP_IMREG (int code, int sizeflag)
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s = names16[code - eAX_reg];
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s = names16[code - eAX_reg];
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used_prefixes |= (prefixes & PREFIX_DATA);
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used_prefixes |= (prefixes & PREFIX_DATA);
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break;
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break;
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case z_mode_ax_reg:
|
||||||
|
if ((rex & REX_MODE64) || (sizeflag & DFLAG))
|
||||||
|
s = *names32;
|
||||||
|
else
|
||||||
|
s = *names16;
|
||||||
|
if (!(rex & REX_MODE64))
|
||||||
|
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
s = INTERNAL_DISASSEMBLER_ERROR;
|
s = INTERNAL_DISASSEMBLER_ERROR;
|
||||||
break;
|
break;
|
||||||
|
@ -4953,7 +4978,22 @@ static void
|
||||||
OP_ESreg (int code, int sizeflag)
|
OP_ESreg (int code, int sizeflag)
|
||||||
{
|
{
|
||||||
if (intel_syntax)
|
if (intel_syntax)
|
||||||
intel_operand_size (codep[-1] & 1 ? v_mode : b_mode, sizeflag);
|
{
|
||||||
|
switch (codep[-1])
|
||||||
|
{
|
||||||
|
case 0x6d: /* insw/insl */
|
||||||
|
intel_operand_size (z_mode, sizeflag);
|
||||||
|
break;
|
||||||
|
case 0xa5: /* movsw/movsl/movsq */
|
||||||
|
case 0xa7: /* cmpsw/cmpsl/cmpsq */
|
||||||
|
case 0xab: /* stosw/stosl */
|
||||||
|
case 0xaf: /* scasw/scasl */
|
||||||
|
intel_operand_size (v_mode, sizeflag);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
intel_operand_size (b_mode, sizeflag);
|
||||||
|
}
|
||||||
|
}
|
||||||
oappend ("%es:" + intel_syntax);
|
oappend ("%es:" + intel_syntax);
|
||||||
ptr_reg (code, sizeflag);
|
ptr_reg (code, sizeflag);
|
||||||
}
|
}
|
||||||
|
@ -4962,10 +5002,21 @@ static void
|
||||||
OP_DSreg (int code, int sizeflag)
|
OP_DSreg (int code, int sizeflag)
|
||||||
{
|
{
|
||||||
if (intel_syntax)
|
if (intel_syntax)
|
||||||
intel_operand_size (codep[-1] != 0xd7 && (codep[-1] & 1)
|
{
|
||||||
? v_mode
|
switch (codep[-1])
|
||||||
: b_mode,
|
{
|
||||||
sizeflag);
|
case 0x6f: /* outsw/outsl */
|
||||||
|
intel_operand_size (z_mode, sizeflag);
|
||||||
|
break;
|
||||||
|
case 0xa5: /* movsw/movsl/movsq */
|
||||||
|
case 0xa7: /* cmpsw/cmpsl/cmpsq */
|
||||||
|
case 0xad: /* lodsw/lodsl/lodsq */
|
||||||
|
intel_operand_size (v_mode, sizeflag);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
intel_operand_size (b_mode, sizeflag);
|
||||||
|
}
|
||||||
|
}
|
||||||
if ((prefixes
|
if ((prefixes
|
||||||
& (PREFIX_CS
|
& (PREFIX_CS
|
||||||
| PREFIX_DS
|
| PREFIX_DS
|
||||||
|
|
Loading…
Reference in New Issue