sim: moxie: rename TRACE to MOXIE_TRACE_INSN
We want to add new common trace helpers including "TRACE", so rename the moxie one to MOXIE_TRACE_INSN. This also matches what the code is doing.
This commit is contained in:
Mike Frysinger
parent
3604cb1f8c
commit
53d2389fd0
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@ -1,3 +1,9 @@
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2015-06-12 Mike Frysinger <vapier@gentoo.org>
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* interp.c (TRACE): Rename to ...
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(MOXIE_TRACE_INSN): ... this.
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(sim_engine_run): Change TRACE to MOXIE_TRACE_INSN.
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2015-04-18 Mike Frysinger <vapier@gentoo.org>
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* sim-main.h (SIM_CPU): Delete.
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@ -232,7 +232,7 @@ convert_target_flags (unsigned int tflags)
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/* TODO: Move to sim-trace.h. */
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static FILE *tracefile;
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static const int tracing = 0;
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#define TRACE(str) if (tracing) fprintf(tracefile,"0x%08x, %s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", opc, str, cpu.asregs.regs[0], cpu.asregs.regs[1], cpu.asregs.regs[2], cpu.asregs.regs[3], cpu.asregs.regs[4], cpu.asregs.regs[5], cpu.asregs.regs[6], cpu.asregs.regs[7], cpu.asregs.regs[8], cpu.asregs.regs[9], cpu.asregs.regs[10], cpu.asregs.regs[11], cpu.asregs.regs[12], cpu.asregs.regs[13], cpu.asregs.regs[14], cpu.asregs.regs[15]);
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#define MOXIE_TRACE_INSN(str) if (tracing) fprintf(tracefile,"0x%08x, %s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", opc, str, cpu.asregs.regs[0], cpu.asregs.regs[1], cpu.asregs.regs[2], cpu.asregs.regs[3], cpu.asregs.regs[4], cpu.asregs.regs[5], cpu.asregs.regs[6], cpu.asregs.regs[7], cpu.asregs.regs[8], cpu.asregs.regs[9], cpu.asregs.regs[10], cpu.asregs.regs[11], cpu.asregs.regs[12], cpu.asregs.regs[13], cpu.asregs.regs[14], cpu.asregs.regs[15]);
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void
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sim_engine_run (SIM_DESC sd,
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@ -268,76 +268,76 @@ sim_engine_run (SIM_DESC sd,
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{
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case 0x00: /* beq */
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{
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TRACE("beq");
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MOXIE_TRACE_INSN ("beq");
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if (cpu.asregs.cc & CC_EQ)
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pc += INST2OFFSET(inst);
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}
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break;
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case 0x01: /* bne */
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{
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TRACE("bne");
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MOXIE_TRACE_INSN ("bne");
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if (! (cpu.asregs.cc & CC_EQ))
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pc += INST2OFFSET(inst);
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}
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break;
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case 0x02: /* blt */
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{
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TRACE("blt");
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MOXIE_TRACE_INSN ("blt");
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if (cpu.asregs.cc & CC_LT)
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pc += INST2OFFSET(inst);
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} break;
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case 0x03: /* bgt */
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{
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TRACE("bgt");
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MOXIE_TRACE_INSN ("bgt");
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if (cpu.asregs.cc & CC_GT)
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pc += INST2OFFSET(inst);
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}
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break;
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case 0x04: /* bltu */
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{
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TRACE("bltu");
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MOXIE_TRACE_INSN ("bltu");
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if (cpu.asregs.cc & CC_LTU)
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pc += INST2OFFSET(inst);
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}
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break;
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case 0x05: /* bgtu */
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{
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TRACE("bgtu");
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MOXIE_TRACE_INSN ("bgtu");
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if (cpu.asregs.cc & CC_GTU)
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pc += INST2OFFSET(inst);
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}
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break;
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case 0x06: /* bge */
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{
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TRACE("bge");
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MOXIE_TRACE_INSN ("bge");
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if (cpu.asregs.cc & (CC_GT | CC_EQ))
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pc += INST2OFFSET(inst);
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}
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break;
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case 0x07: /* ble */
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{
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TRACE("ble");
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MOXIE_TRACE_INSN ("ble");
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if (cpu.asregs.cc & (CC_LT | CC_EQ))
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pc += INST2OFFSET(inst);
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}
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break;
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case 0x08: /* bgeu */
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{
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TRACE("bgeu");
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MOXIE_TRACE_INSN ("bgeu");
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if (cpu.asregs.cc & (CC_GTU | CC_EQ))
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pc += INST2OFFSET(inst);
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}
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break;
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case 0x09: /* bleu */
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{
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TRACE("bleu");
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MOXIE_TRACE_INSN ("bleu");
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if (cpu.asregs.cc & (CC_LTU | CC_EQ))
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pc += INST2OFFSET(inst);
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}
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break;
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default:
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{
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TRACE("SIGILL3");
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MOXIE_TRACE_INSN ("SIGILL3");
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sim_engine_halt (sd, NULL, NULL, pc, sim_stopped, SIM_SIGILL);
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break;
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}
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@ -355,7 +355,7 @@ sim_engine_run (SIM_DESC sd,
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unsigned av = cpu.asregs.regs[a];
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unsigned v = (inst & 0xff);
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TRACE("inc");
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MOXIE_TRACE_INSN ("inc");
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cpu.asregs.regs[a] = av + v;
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}
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break;
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@ -365,7 +365,7 @@ sim_engine_run (SIM_DESC sd,
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unsigned av = cpu.asregs.regs[a];
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unsigned v = (inst & 0xff);
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TRACE("dec");
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MOXIE_TRACE_INSN ("dec");
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cpu.asregs.regs[a] = av - v;
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}
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break;
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@ -374,7 +374,7 @@ sim_engine_run (SIM_DESC sd,
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int a = (inst >> 8) & 0xf;
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unsigned v = (inst & 0xff);
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TRACE("gsr");
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MOXIE_TRACE_INSN ("gsr");
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cpu.asregs.regs[a] = cpu.asregs.sregs[v];
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}
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break;
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@ -383,12 +383,12 @@ sim_engine_run (SIM_DESC sd,
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int a = (inst >> 8) & 0xf;
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unsigned v = (inst & 0xff);
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TRACE("ssr");
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MOXIE_TRACE_INSN ("ssr");
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cpu.asregs.sregs[v] = cpu.asregs.regs[a];
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}
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break;
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default:
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TRACE("SIGILL2");
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MOXIE_TRACE_INSN ("SIGILL2");
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sim_engine_halt (sd, NULL, NULL, pc, sim_stopped, SIM_SIGILL);
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break;
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}
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@ -402,7 +402,7 @@ sim_engine_run (SIM_DESC sd,
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{
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case 0x00: /* bad */
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opc = opcode;
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TRACE("SIGILL0");
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MOXIE_TRACE_INSN ("SIGILL0");
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sim_engine_halt (sd, NULL, NULL, pc, sim_stopped, SIM_SIGILL);
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break;
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case 0x01: /* ldi.l (immediate) */
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@ -410,7 +410,7 @@ sim_engine_run (SIM_DESC sd,
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int reg = (inst >> 4) & 0xf;
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unsigned int val = EXTRACT_WORD(pc+2);
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TRACE("ldi.l");
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MOXIE_TRACE_INSN ("ldi.l");
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cpu.asregs.regs[reg] = val;
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pc += 4;
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}
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@ -420,7 +420,7 @@ sim_engine_run (SIM_DESC sd,
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int dest = (inst >> 4) & 0xf;
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int src = (inst ) & 0xf;
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TRACE("mov");
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MOXIE_TRACE_INSN ("mov");
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cpu.asregs.regs[dest] = cpu.asregs.regs[src];
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}
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break;
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@ -429,7 +429,7 @@ sim_engine_run (SIM_DESC sd,
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unsigned int fn = EXTRACT_WORD(pc+2);
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unsigned int sp = cpu.asregs.regs[1];
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TRACE("jsra");
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MOXIE_TRACE_INSN ("jsra");
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/* Save a slot for the static chain. */
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sp -= 4;
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@ -451,7 +451,7 @@ sim_engine_run (SIM_DESC sd,
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{
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unsigned int sp = cpu.asregs.regs[0];
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TRACE("ret");
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MOXIE_TRACE_INSN ("ret");
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/* Pop the frame pointer. */
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cpu.asregs.regs[0] = rlat (scpu, opc, sp);
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@ -475,7 +475,7 @@ sim_engine_run (SIM_DESC sd,
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unsigned av = cpu.asregs.regs[a];
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unsigned bv = cpu.asregs.regs[b];
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TRACE("add.l");
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MOXIE_TRACE_INSN ("add.l");
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cpu.asregs.regs[a] = av + bv;
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}
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break;
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@ -485,7 +485,7 @@ sim_engine_run (SIM_DESC sd,
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int b = inst & 0xf;
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int sp = cpu.asregs.regs[a] - 4;
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TRACE("push");
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MOXIE_TRACE_INSN ("push");
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wlat (scpu, opc, sp, cpu.asregs.regs[b]);
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cpu.asregs.regs[a] = sp;
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}
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@ -496,7 +496,7 @@ sim_engine_run (SIM_DESC sd,
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int b = inst & 0xf;
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int sp = cpu.asregs.regs[a];
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TRACE("pop");
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MOXIE_TRACE_INSN ("pop");
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cpu.asregs.regs[b] = rlat (scpu, opc, sp);
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cpu.asregs.regs[a] = sp + 4;
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}
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@ -506,7 +506,7 @@ sim_engine_run (SIM_DESC sd,
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int reg = (inst >> 4) & 0xf;
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unsigned int addr = EXTRACT_WORD(pc+2);
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TRACE("lda.l");
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MOXIE_TRACE_INSN ("lda.l");
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cpu.asregs.regs[reg] = rlat (scpu, opc, addr);
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pc += 4;
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}
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@ -516,7 +516,7 @@ sim_engine_run (SIM_DESC sd,
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int reg = (inst >> 4) & 0xf;
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unsigned int addr = EXTRACT_WORD(pc+2);
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TRACE("sta.l");
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MOXIE_TRACE_INSN ("sta.l");
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wlat (scpu, opc, addr, cpu.asregs.regs[reg]);
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pc += 4;
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}
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@ -527,7 +527,7 @@ sim_engine_run (SIM_DESC sd,
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int dest = (inst >> 4) & 0xf;
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int xv;
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TRACE("ld.l");
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MOXIE_TRACE_INSN ("ld.l");
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xv = cpu.asregs.regs[src];
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cpu.asregs.regs[dest] = rlat (scpu, opc, xv);
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}
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@ -537,7 +537,7 @@ sim_engine_run (SIM_DESC sd,
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int dest = (inst >> 4) & 0xf;
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int val = inst & 0xf;
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TRACE("st.l");
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MOXIE_TRACE_INSN ("st.l");
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wlat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
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}
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break;
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@ -547,7 +547,7 @@ sim_engine_run (SIM_DESC sd,
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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TRACE("ldo.l");
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MOXIE_TRACE_INSN ("ldo.l");
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addr += cpu.asregs.regs[b];
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cpu.asregs.regs[a] = rlat (scpu, opc, addr);
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pc += 2;
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@ -559,7 +559,7 @@ sim_engine_run (SIM_DESC sd,
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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TRACE("sto.l");
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MOXIE_TRACE_INSN ("sto.l");
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addr += cpu.asregs.regs[a];
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wlat (scpu, opc, addr, cpu.asregs.regs[b]);
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pc += 2;
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@ -573,7 +573,7 @@ sim_engine_run (SIM_DESC sd,
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int va = cpu.asregs.regs[a];
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int vb = cpu.asregs.regs[b];
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TRACE("cmp");
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MOXIE_TRACE_INSN ("cmp");
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if (va == vb)
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cc = CC_EQ;
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else
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@ -595,7 +595,7 @@ sim_engine_run (SIM_DESC sd,
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int b = inst & 0xf;
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signed char bv = cpu.asregs.regs[b];
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TRACE("sex.b");
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MOXIE_TRACE_INSN ("sex.b");
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cpu.asregs.regs[a] = (int) bv;
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}
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break;
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@ -605,7 +605,7 @@ sim_engine_run (SIM_DESC sd,
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int b = inst & 0xf;
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signed short bv = cpu.asregs.regs[b];
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TRACE("sex.s");
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MOXIE_TRACE_INSN ("sex.s");
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cpu.asregs.regs[a] = (int) bv;
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}
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break;
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@ -615,7 +615,7 @@ sim_engine_run (SIM_DESC sd,
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int b = inst & 0xf;
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signed char bv = cpu.asregs.regs[b];
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TRACE("zex.b");
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MOXIE_TRACE_INSN ("zex.b");
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cpu.asregs.regs[a] = (int) bv & 0xff;
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}
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break;
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@ -625,7 +625,7 @@ sim_engine_run (SIM_DESC sd,
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int b = inst & 0xf;
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signed short bv = cpu.asregs.regs[b];
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TRACE("zex.s");
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MOXIE_TRACE_INSN ("zex.s");
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cpu.asregs.regs[a] = (int) bv & 0xffff;
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}
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break;
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@ -638,7 +638,7 @@ sim_engine_run (SIM_DESC sd,
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unsigned long long r =
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(unsigned long long) av * (unsigned long long) bv;
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TRACE("umul.x");
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MOXIE_TRACE_INSN ("umul.x");
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cpu.asregs.regs[a] = r >> 32;
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}
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break;
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@ -651,7 +651,7 @@ sim_engine_run (SIM_DESC sd,
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signed long long r =
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(signed long long) av * (signed long long) bv;
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TRACE("mul.x");
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MOXIE_TRACE_INSN ("mul.x");
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cpu.asregs.regs[a] = r >> 32;
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}
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break;
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@ -660,7 +660,7 @@ sim_engine_run (SIM_DESC sd,
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case 0x18: /* bad */
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{
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opc = opcode;
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TRACE("SIGILL0");
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MOXIE_TRACE_INSN ("SIGILL0");
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sim_engine_halt (sd, NULL, NULL, pc, sim_stopped, SIM_SIGILL);
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break;
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}
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@ -669,7 +669,7 @@ sim_engine_run (SIM_DESC sd,
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unsigned int fn = cpu.asregs.regs[(inst >> 4) & 0xf];
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unsigned int sp = cpu.asregs.regs[1];
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TRACE("jsr");
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MOXIE_TRACE_INSN ("jsr");
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/* Save a slot for the static chain. */
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sp -= 4;
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@ -692,7 +692,7 @@ sim_engine_run (SIM_DESC sd,
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{
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unsigned int tgt = EXTRACT_WORD(pc+2);
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TRACE("jmpa");
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MOXIE_TRACE_INSN ("jmpa");
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pc = tgt - 2;
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}
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break;
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@ -701,7 +701,7 @@ sim_engine_run (SIM_DESC sd,
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int reg = (inst >> 4) & 0xf;
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unsigned int val = EXTRACT_WORD(pc+2);
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TRACE("ldi.b");
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MOXIE_TRACE_INSN ("ldi.b");
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cpu.asregs.regs[reg] = val;
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pc += 4;
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}
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@ -712,7 +712,7 @@ sim_engine_run (SIM_DESC sd,
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int dest = (inst >> 4) & 0xf;
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int xv;
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TRACE("ld.b");
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MOXIE_TRACE_INSN ("ld.b");
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xv = cpu.asregs.regs[src];
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cpu.asregs.regs[dest] = rbat (scpu, opc, xv);
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}
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@ -722,7 +722,7 @@ sim_engine_run (SIM_DESC sd,
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int reg = (inst >> 4) & 0xf;
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unsigned int addr = EXTRACT_WORD(pc+2);
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TRACE("lda.b");
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MOXIE_TRACE_INSN ("lda.b");
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cpu.asregs.regs[reg] = rbat (scpu, opc, addr);
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pc += 4;
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}
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@ -732,7 +732,7 @@ sim_engine_run (SIM_DESC sd,
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int dest = (inst >> 4) & 0xf;
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int val = inst & 0xf;
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TRACE("st.b");
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MOXIE_TRACE_INSN ("st.b");
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wbat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
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}
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break;
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@ -741,7 +741,7 @@ sim_engine_run (SIM_DESC sd,
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int reg = (inst >> 4) & 0xf;
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unsigned int addr = EXTRACT_WORD(pc+2);
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TRACE("sta.b");
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MOXIE_TRACE_INSN ("sta.b");
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wbat (scpu, opc, addr, cpu.asregs.regs[reg]);
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pc += 4;
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}
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@ -752,7 +752,7 @@ sim_engine_run (SIM_DESC sd,
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unsigned int val = EXTRACT_WORD(pc+2);
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TRACE("ldi.s");
|
||||
MOXIE_TRACE_INSN ("ldi.s");
|
||||
cpu.asregs.regs[reg] = val;
|
||||
pc += 4;
|
||||
}
|
||||
|
|
@ -763,7 +763,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int dest = (inst >> 4) & 0xf;
|
||||
int xv;
|
||||
|
||||
TRACE("ld.s");
|
||||
MOXIE_TRACE_INSN ("ld.s");
|
||||
xv = cpu.asregs.regs[src];
|
||||
cpu.asregs.regs[dest] = rsat (scpu, opc, xv);
|
||||
}
|
||||
|
|
@ -773,7 +773,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int reg = (inst >> 4) & 0xf;
|
||||
unsigned int addr = EXTRACT_WORD(pc+2);
|
||||
|
||||
TRACE("lda.s");
|
||||
MOXIE_TRACE_INSN ("lda.s");
|
||||
cpu.asregs.regs[reg] = rsat (scpu, opc, addr);
|
||||
pc += 4;
|
||||
}
|
||||
|
|
@ -783,7 +783,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int dest = (inst >> 4) & 0xf;
|
||||
int val = inst & 0xf;
|
||||
|
||||
TRACE("st.s");
|
||||
MOXIE_TRACE_INSN ("st.s");
|
||||
wsat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
|
||||
}
|
||||
break;
|
||||
|
|
@ -792,7 +792,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int reg = (inst >> 4) & 0xf;
|
||||
unsigned int addr = EXTRACT_WORD(pc+2);
|
||||
|
||||
TRACE("sta.s");
|
||||
MOXIE_TRACE_INSN ("sta.s");
|
||||
wsat (scpu, opc, addr, cpu.asregs.regs[reg]);
|
||||
pc += 4;
|
||||
}
|
||||
|
|
@ -801,7 +801,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
{
|
||||
int reg = (inst >> 4) & 0xf;
|
||||
|
||||
TRACE("jmp");
|
||||
MOXIE_TRACE_INSN ("jmp");
|
||||
pc = cpu.asregs.regs[reg] - 2;
|
||||
}
|
||||
break;
|
||||
|
|
@ -811,7 +811,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int b = inst & 0xf;
|
||||
int av, bv;
|
||||
|
||||
TRACE("and");
|
||||
MOXIE_TRACE_INSN ("and");
|
||||
av = cpu.asregs.regs[a];
|
||||
bv = cpu.asregs.regs[b];
|
||||
cpu.asregs.regs[a] = av & bv;
|
||||
|
|
@ -824,7 +824,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int av = cpu.asregs.regs[a];
|
||||
int bv = cpu.asregs.regs[b];
|
||||
|
||||
TRACE("lshr");
|
||||
MOXIE_TRACE_INSN ("lshr");
|
||||
cpu.asregs.regs[a] = (unsigned) ((unsigned) av >> bv);
|
||||
}
|
||||
break;
|
||||
|
|
@ -835,7 +835,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int av = cpu.asregs.regs[a];
|
||||
int bv = cpu.asregs.regs[b];
|
||||
|
||||
TRACE("ashl");
|
||||
MOXIE_TRACE_INSN ("ashl");
|
||||
cpu.asregs.regs[a] = av << bv;
|
||||
}
|
||||
break;
|
||||
|
|
@ -846,7 +846,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
unsigned av = cpu.asregs.regs[a];
|
||||
unsigned bv = cpu.asregs.regs[b];
|
||||
|
||||
TRACE("sub.l");
|
||||
MOXIE_TRACE_INSN ("sub.l");
|
||||
cpu.asregs.regs[a] = av - bv;
|
||||
}
|
||||
break;
|
||||
|
|
@ -856,7 +856,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int b = inst & 0xf;
|
||||
int bv = cpu.asregs.regs[b];
|
||||
|
||||
TRACE("neg");
|
||||
MOXIE_TRACE_INSN ("neg");
|
||||
cpu.asregs.regs[a] = - bv;
|
||||
}
|
||||
break;
|
||||
|
|
@ -866,7 +866,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int b = inst & 0xf;
|
||||
int av, bv;
|
||||
|
||||
TRACE("or");
|
||||
MOXIE_TRACE_INSN ("or");
|
||||
av = cpu.asregs.regs[a];
|
||||
bv = cpu.asregs.regs[b];
|
||||
cpu.asregs.regs[a] = av | bv;
|
||||
|
|
@ -878,7 +878,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int b = inst & 0xf;
|
||||
int bv = cpu.asregs.regs[b];
|
||||
|
||||
TRACE("not");
|
||||
MOXIE_TRACE_INSN ("not");
|
||||
cpu.asregs.regs[a] = 0xffffffff ^ bv;
|
||||
}
|
||||
break;
|
||||
|
|
@ -889,7 +889,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int av = cpu.asregs.regs[a];
|
||||
int bv = cpu.asregs.regs[b];
|
||||
|
||||
TRACE("ashr");
|
||||
MOXIE_TRACE_INSN ("ashr");
|
||||
cpu.asregs.regs[a] = av >> bv;
|
||||
}
|
||||
break;
|
||||
|
|
@ -899,7 +899,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int b = inst & 0xf;
|
||||
int av, bv;
|
||||
|
||||
TRACE("xor");
|
||||
MOXIE_TRACE_INSN ("xor");
|
||||
av = cpu.asregs.regs[a];
|
||||
bv = cpu.asregs.regs[b];
|
||||
cpu.asregs.regs[a] = av ^ bv;
|
||||
|
|
@ -912,7 +912,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
unsigned av = cpu.asregs.regs[a];
|
||||
unsigned bv = cpu.asregs.regs[b];
|
||||
|
||||
TRACE("mul.l");
|
||||
MOXIE_TRACE_INSN ("mul.l");
|
||||
cpu.asregs.regs[a] = av * bv;
|
||||
}
|
||||
break;
|
||||
|
|
@ -920,7 +920,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
{
|
||||
unsigned int inum = EXTRACT_WORD(pc+2);
|
||||
|
||||
TRACE("swi");
|
||||
MOXIE_TRACE_INSN ("swi");
|
||||
/* Set the special registers appropriately. */
|
||||
cpu.asregs.sregs[2] = 3; /* MOXIE_EX_SWI */
|
||||
cpu.asregs.sregs[3] = inum;
|
||||
|
|
@ -1002,7 +1002,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int av = cpu.asregs.regs[a];
|
||||
int bv = cpu.asregs.regs[b];
|
||||
|
||||
TRACE("div.l");
|
||||
MOXIE_TRACE_INSN ("div.l");
|
||||
cpu.asregs.regs[a] = av / bv;
|
||||
}
|
||||
break;
|
||||
|
|
@ -1013,7 +1013,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
unsigned int av = cpu.asregs.regs[a];
|
||||
unsigned int bv = cpu.asregs.regs[b];
|
||||
|
||||
TRACE("udiv.l");
|
||||
MOXIE_TRACE_INSN ("udiv.l");
|
||||
cpu.asregs.regs[a] = (av / bv);
|
||||
}
|
||||
break;
|
||||
|
|
@ -1024,7 +1024,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int av = cpu.asregs.regs[a];
|
||||
int bv = cpu.asregs.regs[b];
|
||||
|
||||
TRACE("mod.l");
|
||||
MOXIE_TRACE_INSN ("mod.l");
|
||||
cpu.asregs.regs[a] = av % bv;
|
||||
}
|
||||
break;
|
||||
|
|
@ -1035,12 +1035,12 @@ sim_engine_run (SIM_DESC sd,
|
|||
unsigned int av = cpu.asregs.regs[a];
|
||||
unsigned int bv = cpu.asregs.regs[b];
|
||||
|
||||
TRACE("umod.l");
|
||||
MOXIE_TRACE_INSN ("umod.l");
|
||||
cpu.asregs.regs[a] = (av % bv);
|
||||
}
|
||||
break;
|
||||
case 0x35: /* brk */
|
||||
TRACE("brk");
|
||||
MOXIE_TRACE_INSN ("brk");
|
||||
sim_engine_halt (sd, NULL, NULL, pc, sim_stopped, SIM_SIGTRAP);
|
||||
pc -= 2; /* Adjust pc */
|
||||
break;
|
||||
|
|
@ -1050,7 +1050,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int a = (inst >> 4) & 0xf;
|
||||
int b = inst & 0xf;
|
||||
|
||||
TRACE("ldo.b");
|
||||
MOXIE_TRACE_INSN ("ldo.b");
|
||||
addr += cpu.asregs.regs[b];
|
||||
cpu.asregs.regs[a] = rbat (scpu, opc, addr);
|
||||
pc += 2;
|
||||
|
|
@ -1062,7 +1062,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int a = (inst >> 4) & 0xf;
|
||||
int b = inst & 0xf;
|
||||
|
||||
TRACE("sto.b");
|
||||
MOXIE_TRACE_INSN ("sto.b");
|
||||
addr += cpu.asregs.regs[a];
|
||||
wbat (scpu, opc, addr, cpu.asregs.regs[b]);
|
||||
pc += 2;
|
||||
|
|
@ -1074,7 +1074,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int a = (inst >> 4) & 0xf;
|
||||
int b = inst & 0xf;
|
||||
|
||||
TRACE("ldo.s");
|
||||
MOXIE_TRACE_INSN ("ldo.s");
|
||||
addr += cpu.asregs.regs[b];
|
||||
cpu.asregs.regs[a] = rsat (scpu, opc, addr);
|
||||
pc += 2;
|
||||
|
|
@ -1086,7 +1086,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
int a = (inst >> 4) & 0xf;
|
||||
int b = inst & 0xf;
|
||||
|
||||
TRACE("sto.s");
|
||||
MOXIE_TRACE_INSN ("sto.s");
|
||||
addr += cpu.asregs.regs[a];
|
||||
wsat (scpu, opc, addr, cpu.asregs.regs[b]);
|
||||
pc += 2;
|
||||
|
|
@ -1094,7 +1094,7 @@ sim_engine_run (SIM_DESC sd,
|
|||
break;
|
||||
default:
|
||||
opc = opcode;
|
||||
TRACE("SIGILL1");
|
||||
MOXIE_TRACE_INSN ("SIGILL1");
|
||||
sim_engine_halt (sd, NULL, NULL, pc, sim_stopped, SIM_SIGILL);
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue