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Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE.

Browse Source 
Related specifications can be found at
https://developer.arm.com/ip-products/processors.

gas	* NEWS: Mention the Arm and AArch64 new processors.
	* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,
	Cortex-A77, cortex-A65AE, and Cortex-A76AE.
	* doc/c-aarch64.texi: Document new CPUs.
	* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.
	* testsuite/gas/aarch64/nop-asm.s: New test.

bfd	* cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65,
	 Cortex-A77, cortex-A65AE, and Cortex-A76AE.
This commit is contained in:
Dennis Zhang 2019-08-20 17:13:29 +01:00 committed by Nick Clifton
parent b4e87f2c1e
commit 546053acfa
14 changed files with 122 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
bfd/ChangeLog
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@ -1,3 +1,8 @@
2019-08-20 Dennis Zhang <dennis.zhang@arm.com>
* cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65,
Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-08-20 Tamar Christina <tamar.christina@arm.com>
* elf32-arm.c (elf32_thumb2_plt_entry, elf32_arm_plt_thumb_stub,

9
bfd/cpu-aarch64.c
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@ -68,10 +68,11 @@ static struct
}
processors[] =
{
/* These two are example CPUs supported in GCC, once we have real
CPUs they will be removed. */
{ bfd_mach_aarch64, "example-1" },
{ bfd_mach_aarch64, "example-2" }
{ bfd_mach_aarch64, "cortex-a34" },
{ bfd_mach_aarch64, "cortex-a65" },
{ bfd_mach_aarch64, "cortex-a65ae" },
{ bfd_mach_aarch64, "cortex-a76ae" },
{ bfd_mach_aarch64, "cortex-a77" }
};
static bfd_boolean

13
gas/ChangeLog
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@ -1,3 +1,16 @@
2019-08-20 Dennis Zhang <dennis.zhang@arm.com>
* NEWS: Mention the Arm and AArch64 new processors.
* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,
Cortex-A77, cortex-A65AE, and Cortex-A76AE.
* doc/c-aarch64.texi: Document new CPUs.
* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.
* testsuite/gas/aarch64/nop-asm.s: New test.
2019-08-19 Faraz Shahbazker <fshahbazker@wavecomp.com>
* config/tc-mips.c (fix_bad_misaligned_address): New function.

6
gas/NEWS
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@ -8,6 +8,12 @@
to set the default behavior. Set the default if the configure option is not used
to "no".
* Add support for the Arm Cortex-A76AE, Cortex-A77 and Cortex-M35P
processors.
* Add support for the AArch64 Cortex-A34, Cortex-A65, Cortex-A65AE,
Cortex-A76AE, and Cortex-A77 processors.
Changes in 2.32:
* Add -mvexwig=[0|1] option to x86 assembler to control encoding of

22
gas/config/tc-aarch64.c
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@ -8799,6 +8799,8 @@ struct aarch64_cpu_option_table
recognized by GCC. */
static const struct aarch64_cpu_option_table aarch64_cpus[] = {
{"all", AARCH64_ANY, NULL},
{"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8,
AARCH64_FEATURE_CRC), "Cortex-A34"},
{"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8,
AARCH64_FEATURE_CRC), "Cortex-A35"},
{"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8,
@ -8818,6 +8820,26 @@ static const struct aarch64_cpu_option_table aarch64_cpus[] = {
{"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD),
"Cortex-A76"},
{"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_DOTPROD
| AARCH64_FEATURE_SSBS),
"Cortex-A76AE"},
{"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_DOTPROD
| AARCH64_FEATURE_SSBS),
"Cortex-A77"},
{"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_DOTPROD
| AARCH64_FEATURE_SSBS),
"Cortex-A65"},
{"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_DOTPROD
| AARCH64_FEATURE_SSBS),
"Cortex-A65AE"},
{"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD

5
gas/doc/c-aarch64.texi
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@ -55,14 +55,19 @@ file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
This option specifies the target processor. The assembler will issue an error
message if an attempt is made to assemble an instruction which will not execute
on the target processor. The following processor names are recognized:
@code{cortex-a34},
@code{cortex-a35},
@code{cortex-a53},
@code{cortex-a55},
@code{cortex-a57},
@code{cortex-a65},
@code{cortex-a65ae},
@code{cortex-a72},
@code{cortex-a73},
@code{cortex-a75},
@code{cortex-a76},
@code{cortex-a76ae},
@code{cortex-a77},
@code{ares},
@code{exynos-m1},
@code{falkor},

6
gas/testsuite/gas/aarch64/cpu-cortex-a34.d Normal file
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@ -0,0 +1,6 @@
# name: Assemble and dump for cortex-a34 CPU
# source: nop-asm.s
# as: -mcpu=cortex-a34
# objdump: -d -mcortex-a34
#...

6
gas/testsuite/gas/aarch64/cpu-cortex-a65.d Normal file
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@ -0,0 +1,6 @@
# name: Assemble and dump for cortex-a65 CPU
# source: nop-asm.s
# as: -mcpu=cortex-a65
# objdump: -d -mcortex-a65
#...

6
gas/testsuite/gas/aarch64/cpu-cortex-a65ae.d Normal file
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@ -0,0 +1,6 @@
# name: Assemble and dump for cortex-a65ae CPU
# source: nop-asm.s
# as: -mcpu=cortex-a65ae
# objdump: -d -mcortex-a65ae
#...

6
gas/testsuite/gas/aarch64/cpu-cortex-a76ae.d Normal file
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@ -0,0 +1,6 @@
# name: Assemble and dump for cortex-a76ae CPU
# source: nop-asm.s
# as: -mcpu=cortex-a76ae
# objdump: -d -mcortex-a76ae
#...

6
gas/testsuite/gas/aarch64/cpu-cortex-a77.d Normal file
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@ -0,0 +1,6 @@
# name: Assemble and dump for cortex-a77 CPU
# source: nop-asm.s
# as: -mcpu=cortex-a77
# objdump: -d -mcortex-a77
#...

1
gas/testsuite/gas/aarch64/nop-asm.s Normal file
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@ -0,0 +1 @@
nop

19
gas/testsuite/gas/arm/pr24907.d Normal file
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@ -0,0 +1,19 @@
# name: Disassembling variable width insns with relocs (PR 24907)
# as:
# objdump: -d
# This test is only valid on ELF based ports.
#notarget: *-*-pe *-*-wince *-*-vxworks
.*: +file format .*arm.*
Disassembly of section \.text:
0+000 <foo>:
0: 46c0 nop ; .*
2: f7ff fffe bl 0 <log_func>
6: e002 b\.n e <func\+0x2>
8: f7ff fffe bl c <func>
0+000c <func>:
c: 46c0 nop ; .*
e: 46c0 nop ; .*

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gas/testsuite/gas/arm/pr24907.s Normal file
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@ -0,0 +1,16 @@
.syntax unified
.text
.thumb
.global foo
foo:
nop
bl log_func
b.n .L1
bl func
.global func
func:
nop
.L1:
nop