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t-pke2.trc t-pke2.vif1expect: Update the testcase to use the 

correct registers permitted by gpus.
This commit is contained in:
Jillian Ye 1998-04-20 21:56:01 +00:00
parent 1e50f1b441
commit 54a0a7df08
3 changed files with 14 additions and 9 deletions
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5
sim/testsuite/sky/ChangeLog
View File

@ -1,3 +1,8 @@
Mon Apr 20 19:05:41 1998 Jillian Ye <jillian@cygnus.com>
* t-pke2.trc t-pke2.vif1expect : Update the testcase
to work with sce gpu2 lib.
Fri Apr 17 14:17:17 1998 Doug Evans <devans@canuck.cygnus.com>
* Makefile.in (ULIMIT): New variable.

6
sim/testsuite/sky/t-pke2.trc
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@ -118,7 +118,7 @@
1 0x00000000_0000004e_00000000_01000096 0x00000000 ....
1 0x00000000_00000047_00000000_00070000 0x00000000 ....
1 0x00000000_00000046_00000000_00000001 0x00000000 ....
1 0x00000000_00000059_00000000_00000000 0x00000000 ....
1 0x00000000_0000005a_01e00280_00000000 0x00000000 ....
1 0x00000000_0000005b_00000000_00000003 0x00000000 ....
1 0x00000000_00000048_00000000_00000000 0x00000000 ....
1 0x00000000_00000049_01e00280_00000000 0x00000000 ....
1 0x00000000_00000050_00000000_00000003 0x00000000 ....
#

12
sim/testsuite/sky/t-pke2.vif1expect
View File

@ -912,9 +912,9 @@
# Write 16 bytes to 0x10006010: 96 00 00 01 00 00 00 00 4e 00 00 00 00 00 00 00
# Write 16 bytes to 0x10006010: 00 00 07 00 00 00 00 00 47 00 00 00 00 00 00 00
# Write 16 bytes to 0x10006010: 01 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00
# Write 16 bytes to 0x10006010: 00 00 00 00 00 00 00 00 59 00 00 00 00 00 00 00
# Write 16 bytes to 0x10006010: 00 00 00 00 80 02 e0 01 5a 00 00 00 00 00 00 00
# Write 16 bytes to 0x10006010: 03 00 00 00 00 00 00 00 5b 00 00 00 00 00 00 00
# Write 16 bytes to 0x10006010: 00 00 00 00 00 00 00 00 48 00 00 00 00 00 00 00
# Write 16 bytes to 0x10006010: 00 00 00 00 80 02 e0 01 49 00 00 00 00 00 00 00
# Write 16 bytes to 0x10006010: 03 00 00 00 00 00 00 00 50 00 00 00 00 00 00 00
# Reg STAT:PPS = 0x0
1 0x5100000b_00000000_00000000_00000000 0x00000000 PPPP
1 0x00000000_0000000e_10000000_0000800a 0x00000000 ....
@ -925,7 +925,7 @@
1 0x00000000_0000004e_00000000_01000096 0x00000000 ....
1 0x00000000_00000047_00000000_00070000 0x00000000 ....
1 0x00000000_00000046_00000000_00000001 0x00000000 ....
1 0x00000000_00000059_00000000_00000000 0x00000000 ....
1 0x00000000_0000005a_01e00280_00000000 0x00000000 ....
1 0x00000000_0000005b_00000000_00000003 0x00000000 ....
1 0x00000000_00000048_00000000_00000000 0x00000000 ....
1 0x00000000_00000049_01e00280_00000000 0x00000000 ....
1 0x00000000_00000050_00000000_00000003 0x00000000 ....
# Reg STAT:FQC = 0x0