(enum reg): Rearrange registers, remove 'ccfg' and 'pc'.
(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. (enum operand_type): Rearrange operands, edit comments. replace us<N> with ui<N> for unsigned immediate. replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped displacements (respectively). replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. (instruction type): Add NO_TYPE_INS. (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. (operand_entry): New field - 'flags'. (operand flags): New.
This commit is contained in:
Tomer Levi
parent
4030fa5ade
commit
5531e44c20
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@ -41,20 +41,16 @@ typedef enum
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uhi, ulo,
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/* Processor Status Register. */
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psr,
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/* Configuration Register. */
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cfg,
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/* Coprocessor Configuration Register. */
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cpcfg,
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/* Cashe Configuration Register. */
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ccfg,
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/* Interrupt Base Register. */
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intbase,
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/* Interrupt Stack Pointer Register. */
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isp,
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/* Configuration Register. */
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cfg,
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/* Coprocessor Configuration Register. */
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cpcfg,
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/* Coprocessor Enable Register. */
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cen,
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/* Program Counter Register. */
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pc,
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/* Not a register. */
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nullregister,
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MAX_REG
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@ -83,13 +79,11 @@ copreg;
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typedef enum
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{
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CRX_PC_REGTYPE, /* pc type */
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CRX_R_REGTYPE, /* r<N> */
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CRX_U_REGTYPE, /* u<N> */
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CRX_C_REGTYPE, /* c<N> */
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CRX_CS_REGTYPE, /* cs<N> */
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CRX_MTPR_REGTYPE, /* mtpr */
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CRX_CFG_REGTYPE /* *hi|lo, *cfg, psr */
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CRX_CFG_REGTYPE /* configuration register */
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}
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reg_type;
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@ -117,40 +111,38 @@ typedef enum
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argtype;
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/* CRX operand types :
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The operand types correspond to instructions operands
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Operand Types :
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cst4 - 4-bit encoded constant
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iN - N-bit immediate field
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d, dispsN - N-bit immediate signed displacement
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dispuN - N-bit immediate unsigned displacement
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absN - N-bit absolute address
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rbase - 4-bit genaral-purpose register specifier
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regr - 4-bit genaral-purpose register specifier
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regr8 - 8-bit register address space
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copregr - coprocessor register
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copsregr - coprocessor special register
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scl2 - 2-bit scaling factor for memory index
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ridx - register index. */
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The operand types correspond to instructions operands. */
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typedef enum
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{
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dummy, cst4, disps9,
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/* Immediate operands. */
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dummy,
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/* 4-bit encoded constant. */
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cst4,
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/* N-bit immediate. */
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i16, i32,
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/* Unsigned immediate operands. */
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us3, us4, us5, us16,
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/* Signed displacement operands. */
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d5, d9, d17, d25, d33,
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/* Absolute operands. */
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/* N-bit unsigned immediate. */
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ui3, ui4, ui5, ui16,
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/* N-bit signed displacement. */
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disps9, disps17, disps25, disps32,
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/* N-bit unsigned displacement. */
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dispu5,
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/* N-bit escaped displacement. */
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dispe9,
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/* N-bit absolute address. */
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abs16, abs32,
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/* Register relative operands. */
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/* Register relative. */
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rbase, rbase_cst4,
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rbase_dispu8, rbase_dispu12, rbase_dispu16, rbase_dispu28, rbase_dispu32,
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/* Index operands. */
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rbase_ridx_scl2_dispu6, rbase_ridx_scl2_dispu22,
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/* Register and processor register operands. */
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regr, regr8, copregr,copregr8,copsregr,
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rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32,
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/* Register index. */
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rindex_disps6, rindex_disps22,
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/* 4-bit genaral-purpose register specifier. */
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regr,
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/* 8-bit register address space. */
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regr8,
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/* coprocessor register. */
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copregr,
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/* coprocessor special register. */
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copsregr,
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/* Not an operand. */
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nulloperand,
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/* Maximum supported operand. */
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@ -160,6 +152,7 @@ operand_type;
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/* CRX instruction types. */
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#define NO_TYPE_INS 0
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#define ARITH_INS 1
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#define LD_STOR_INS 2
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#define BRANCH_INS 3
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@ -192,23 +185,37 @@ operand_type;
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#define REG_LIST CRX_INS_MAX
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/* The operands in binary and assembly are placed in reverse order.
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load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */
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#define REVERSE_MATCH (REG_LIST << 1)
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#define REVERSE_MATCH (1 << 6)
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/* Kind of displacement map used DISPU[BWD]4. */
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#define DISPUB4 (REVERSE_MATCH << 1)
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#define DISPUW4 (DISPUB4 << 1)
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#define DISPUD4 (DISPUW4 << 1)
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#define CST4MAP (DISPUB4 | DISPUW4 | DISPUD4)
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#define DISPUB4 (1 << 7)
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#define DISPUW4 (1 << 8)
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#define DISPUD4 (1 << 9)
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#define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4)
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/* Printing formats, where the instruction prefix isn't consecutive. */
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#define FMT_1 (DISPUD4 << 1) /* 0xF0F00000 */
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#define FMT_2 (FMT_1 << 1) /* 0xFFF0FF00 */
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#define FMT_3 (FMT_2 << 1) /* 0xFFF00F00 */
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#define FMT_4 (FMT_3 << 1) /* 0xFFF0F000 */
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#define FMT_5 (FMT_4 << 1) /* 0xFFF0FFF0 */
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#define FMT_1 (1 << 10) /* 0xF0F00000 */
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#define FMT_2 (1 << 11) /* 0xFFF0FF00 */
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#define FMT_3 (1 << 12) /* 0xFFF00F00 */
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#define FMT_4 (1 << 13) /* 0xFFF0F000 */
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#define FMT_5 (1 << 14) /* 0xFFF0FFF0 */
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#define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
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#define RELAXABLE (FMT_5 << 1)
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/* Indicates whether this instruction can be relaxed. */
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#define RELAXABLE (1 << 15)
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/* Indicates that instruction uses user registers (and not
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general-purpose registers) as operands. */
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#define USER_REG (1 << 16)
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/* Indicates that instruction can perfom a cst4 mapping. */
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#define CST4MAP (1 << 17)
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/* Instruction shouldn't allow 'sp' usage. */
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#define NO_SP (1 << 18)
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/* Instruction shouldn't allow to push a register which is used as a rptr. */
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#define NO_RPTR (1 << 19)
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/* Maximum operands per instruction. */
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#define MAX_OPERANDS 5
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@ -219,6 +226,24 @@ operand_type;
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/* Maximum instruction length. */
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#define MAX_INST_LEN 256
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/* Values defined for the flags field of a struct operand_entry. */
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/* Operand must be an unsigned number. */
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#define OPERAND_UNSIGNED (1 << 0)
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/* Operand must be a signed number. */
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#define OPERAND_SIGNED (1 << 1)
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/* A cst4 operand. */
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#define OPERAND_CST4 (1 << 2)
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/* Operand must be an even number. */
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#define OPERAND_EVEN (1 << 3)
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/* Operand is shifted right. */
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#define OPERAND_SHIFT (1 << 4)
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/* Operand is shifted right and decremented. */
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#define OPERAND_SHIFT_DEC (1 << 5)
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/* Operand has reserved escape sequences. */
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#define OPERAND_ESC (1 << 6)
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/* Single operand description. */
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typedef struct
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@ -300,6 +325,8 @@ typedef struct
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unsigned int bit_size;
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/* Argument type. */
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argtype arg_type;
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/* One bit syntax flags. */
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int flags;
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}
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operand_entry;
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