OpenE2K
/
binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Move common aarch64 HW breakpoint/watchpoint code to nat/ 

When I look at test fails related to watchpoint on aarch64-linux,
I find there are some code duplicates between GDB and GDBserver.
This patch is to move some of them to a nat/aarch64-linux-hw-point.{h,c}.

The only change I do is about the dr_changed_t typedef, which was
ULONGEST in GDB and 'unsigned long long' in GDBserver.  Each bit
of dr_changed_t represents a status of each HW breakpoint or
watchpoint register, and the max number of HW breakpoint or watchpoint
registers is 16, so the width of 'unsigned long long' is sufficient.

gdb:

2015-07-17  Yao Qi  <yao.qi@linaro.org>

	* Makefile.in (HFILES_NO_SRCDIR): Add
	nat/aarch64-linux-hw-point.h.
	(aarch64-linux-hw-point.o): New rule.
	* nat/aarch64-linux-hw-point.h: New file.
	* nat/aarch64-linux-hw-point.c: New file.
	* aarch64-linux-nat.c: Include nat/aarch64-linux-hw-point.h.
	(AARCH64_HBP_MAX_NUM): Move to nat/aarch64-linux-hw-point.h.
	(AARCH64_HWP_MAX_NUM, AARCH64_HBP_ALIGNMENT): Likewise.
	(AARCH64_HWP_ALIGNMENT): Likewise.
	(AARCH64_HWP_MAX_LEN_PER_REG): Likewise.
	(AARCH64_DEBUG_NUM_SLOTS, AARCH64_DEBUG_ARCH): Likewise.
	(AARCH64_DEBUG_ARCH_V8, DR_MARK_ALL_CHANGED): Likewise.
	(DR_MARK_N_CHANGED, DR_CLEAR_CHANGED): Likewise.
	(DR_HAS_CHANGED, DR_N_HAS_CHANGE): Likewise.
	(aarch64_num_bp_regs, aarch64_num_wp_regs): Likewise.
	(struct aarch64_debug_reg_state): Likewise.
	(struct arch_lwp_info):	Likewise.
	(aarch64_linux_set_debug_regs): Likewise.
	(aarch64_notify_debug_reg_change): Remove static.
	(aarch64_align_watchpoint): Likewise.
	(DR_CONTROL_ENABLED, DR_CONTROL_LENGTH): Likewise.
	(aarch64_watchpoint_length): Likewise.
	(aarch64_point_encode_ctrl_reg): Likewise
	(aarch64_point_is_aligned): Likewise.
	(aarch64_dr_state_insert_one_point): Likewise.
	(aarch64_dr_state_remove_one_point): Likewise.
	(aarch64_handle_breakpoint): Likewise.
	(aarch64_handle_aligned_watchpoint): Likewise.
	(aarch64_handle_unaligned_watchpoint): Likewise.
	(aarch64_handle_watchpoint): Likewise.
	* config/aarch64/linux.mh (NAT_FILE): Add
	aarch64-linux-hw-point.o.

gdb/gdbserver:

2015-07-17  Yao Qi  <yao.qi@linaro.org>

	* Makefile.in (aarch64-linux-hw-point.o): New rule.
	* configure.srv (srv_tgtobj): Append aarch64-linux-hw-point.o.
	* linux-aarch64-low.c: Include nat/aarch64-linux-hw-point.h.
	(AARCH64_HBP_MAX_NUM): Move to nat/aarch64-linux-hw-point.h.
	(AARCH64_HWP_MAX_NUM, AARCH64_HBP_ALIGNMENT): Likewise.
	(AARCH64_HWP_ALIGNMENT): Likewise.
	(AARCH64_HWP_MAX_LEN_PER_REG): Likewise.
	(AARCH64_DEBUG_NUM_SLOTS, AARCH64_DEBUG_ARCH): Likewise.
	(aarch64_num_bp_regs, aarch64_num_wp_regs): Likewise.
	(AARCH64_DEBUG_ARCH_V8, DR_MARK_ALL_CHANGED): Likewise.
	(DR_MARK_N_CHANGED, DR_CLEAR_CHANGED): Likewise.
	(DR_HAS_CHANGED, DR_N_HAS_CHANGE): Likewise.
	(struct aarch64_debug_reg_state): Likewise.
	(struct arch_lwp_info):	Likewise.
	(aarch64_align_watchpoint): Likewise.
	(DR_CONTROL_ENABLED, DR_CONTROL_LENGTH): Likewise.
	(aarch64_watchpoint_length): Likewise.
	(aarch64_point_encode_ctrl_reg): Likewise
	(aarch64_point_is_aligned): Likewise.
	(aarch64_align_watchpoint): Likewise.
	(aarch64_linux_set_debug_regs):
	(aarch64_dr_state_insert_one_point): Likewise.
	(aarch64_dr_state_remove_one_point): Likewise.
	(aarch64_handle_breakpoint): Likewise.
	(aarch64_handle_aligned_watchpoint): Likewise.
	(aarch64_handle_unaligned_watchpoint): Likewise.
	(aarch64_handle_watchpoint): Likewise.
This commit is contained in:
Yao Qi 2015-07-17 14:32:40 +01:00
parent c67ca4de63
commit 554717a3ed
10 changed files with 767 additions and 1218 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
gdb/ChangeLog
View File

@ -1,3 +1,38 @@
2015-07-17 Yao Qi <yao.qi@linaro.org>
* Makefile.in (HFILES_NO_SRCDIR): Add
nat/aarch64-linux-hw-point.h.
(aarch64-linux-hw-point.o): New rule.
* nat/aarch64-linux-hw-point.h: New file.
* nat/aarch64-linux-hw-point.c: New file.
* aarch64-linux-nat.c: Include nat/aarch64-linux-hw-point.h.
(AARCH64_HBP_MAX_NUM): Move to nat/aarch64-linux-hw-point.h.
(AARCH64_HWP_MAX_NUM, AARCH64_HBP_ALIGNMENT): Likewise.
(AARCH64_HWP_ALIGNMENT): Likewise.
(AARCH64_HWP_MAX_LEN_PER_REG): Likewise.
(AARCH64_DEBUG_NUM_SLOTS, AARCH64_DEBUG_ARCH): Likewise.
(AARCH64_DEBUG_ARCH_V8, DR_MARK_ALL_CHANGED): Likewise.
(DR_MARK_N_CHANGED, DR_CLEAR_CHANGED): Likewise.
(DR_HAS_CHANGED, DR_N_HAS_CHANGE): Likewise.
(aarch64_num_bp_regs, aarch64_num_wp_regs): Likewise.
(struct aarch64_debug_reg_state): Likewise.
(struct arch_lwp_info): Likewise.
(aarch64_linux_set_debug_regs): Likewise.
(aarch64_notify_debug_reg_change): Remove static.
(aarch64_align_watchpoint): Likewise.
(DR_CONTROL_ENABLED, DR_CONTROL_LENGTH): Likewise.
(aarch64_watchpoint_length): Likewise.
(aarch64_point_encode_ctrl_reg): Likewise
(aarch64_point_is_aligned): Likewise.
(aarch64_dr_state_insert_one_point): Likewise.
(aarch64_dr_state_remove_one_point): Likewise.
(aarch64_handle_breakpoint): Likewise.
(aarch64_handle_aligned_watchpoint): Likewise.
(aarch64_handle_unaligned_watchpoint): Likewise.
(aarch64_handle_watchpoint): Likewise.
* config/aarch64/linux.mh (NAT_FILE): Add
aarch64-linux-hw-point.o.
2015-07-17 Yao Qi <yao.qi@linaro.org>
* aarch64-linux-nat.c (aarch64_handle_breakpoint): Add argument

6
gdb/Makefile.in
View File

@ -933,7 +933,7 @@ tui/tui-windata.h tui/tui-data.h tui/tui-win.h tui/tui-stack.h \
tui/tui-winsource.h tui/tui-regs.h tui/tui-io.h tui/tui-layout.h \
tui/tui-source.h sol2-tdep.h gregset.h sh-tdep.h sh64-tdep.h \
expression.h score-tdep.h gdb_select.h ser-tcp.h \
extension.h extension-priv.h \
extension.h extension-priv.h nat/aarch64-linux-hw-point.h \
build-id.h buildsym.h valprint.h \
typeprint.h mi/mi-getopt.h mi/mi-parse.h mi/mi-console.h \
mi/mi-out.h mi/mi-main.h mi/mi-common.h mi/mi-cmds.h linux-nat.h \
@ -2327,6 +2327,10 @@ linux-namespaces.o: ${srcdir}/nat/linux-namespaces.c
$(COMPILE) $(srcdir)/nat/linux-namespaces.c
$(POSTCOMPILE)
aarch64-linux-hw-point.o: ${srcdir}/nat/aarch64-linux-hw-point.c
$(COMPILE) $(srcdir)/nat/aarch64-linux-hw-point.c
$(POSTCOMPILE)
#
# gdb/tui/ dependencies
#

600
gdb/aarch64-linux-nat.c
View File

@ -30,6 +30,7 @@
#include "aarch64-tdep.h"
#include "aarch64-linux-tdep.h"
#include "aarch32-linux-nat.h"
#include "nat/aarch64-linux-hw-point.h"
#include "elf/external.h"
#include "elf/common.h"
@ -63,130 +64,6 @@ get_thread_id (ptid_t ptid)
return tid;
}
/* Macro definitions, data structures, and code for the hardware
breakpoint and hardware watchpoint support follow. We use the
following abbreviations throughout the code:
hw - hardware
bp - breakpoint
wp - watchpoint */
/* Maximum number of hardware breakpoint and watchpoint registers.
Neither of these values may exceed the width of dr_changed_t
measured in bits. */
#define AARCH64_HBP_MAX_NUM 16
#define AARCH64_HWP_MAX_NUM 16
/* Alignment requirement in bytes for addresses written to
hardware breakpoint and watchpoint value registers.
A ptrace call attempting to set an address that does not meet the
alignment criteria will fail. Limited support has been provided in
this port for unaligned watchpoints, such that from a GDB user
perspective, an unaligned watchpoint may be requested.
This is achieved by minimally enlarging the watched area to meet the
alignment requirement, and if necessary, splitting the watchpoint
over several hardware watchpoint registers. */
#define AARCH64_HBP_ALIGNMENT 4
#define AARCH64_HWP_ALIGNMENT 8
/* The maximum length of a memory region that can be watched by one
hardware watchpoint register. */
#define AARCH64_HWP_MAX_LEN_PER_REG 8
/* ptrace hardware breakpoint resource info is formatted as follows:
31 24 16 8 0
+---------------+--------------+---------------+---------------+
| RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
+---------------+--------------+---------------+---------------+ */
/* Macros to extract fields from the hardware debug information word. */
#define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
#define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
/* Macro for the expected version of the ARMv8-A debug architecture. */
#define AARCH64_DEBUG_ARCH_V8 0x6
/* Number of hardware breakpoints/watchpoints the target supports.
They are initialized with values obtained via the ptrace calls
with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
static int aarch64_num_bp_regs;
static int aarch64_num_wp_regs;
/* Each bit of a variable of this type is used to indicate whether a
hardware breakpoint or watchpoint setting has been changed since
the last update.
Bit N corresponds to the Nth hardware breakpoint or watchpoint
setting which is managed in aarch64_debug_reg_state, where N is
valid between 0 and the total number of the hardware breakpoint or
watchpoint debug registers minus 1.
When bit N is 1, the corresponding breakpoint or watchpoint setting
has changed, and therefore the corresponding hardware debug
register needs to be updated via the ptrace interface.
In the per-thread arch-specific data area, we define two such
variables for per-thread hardware breakpoint and watchpoint
settings respectively.
This type is part of the mechanism which helps reduce the number of
ptrace calls to the kernel, i.e. avoid asking the kernel to write
to the debug registers with unchanged values. */
typedef ULONGEST dr_changed_t;
/* Set each of the lower M bits of X to 1; assert X is wide enough. */
#define DR_MARK_ALL_CHANGED(x, m) \
do \
{ \
gdb_assert (sizeof ((x)) * 8 >= (m)); \
(x) = (((dr_changed_t)1 << (m)) - 1); \
} while (0)
#define DR_MARK_N_CHANGED(x, n) \
do \
{ \
(x) |= ((dr_changed_t)1 << (n)); \
} while (0)
#define DR_CLEAR_CHANGED(x) \
do \
{ \
(x) = 0; \
} while (0)
#define DR_HAS_CHANGED(x) ((x) != 0)
#define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
/* Structure for managing the hardware breakpoint/watchpoint resources.
DR_ADDR_* stores the address, DR_CTRL_* stores the control register
content, and DR_REF_COUNT_* counts the numbers of references to the
corresponding bp/wp, by which way the limited hardware resources
are not wasted on duplicated bp/wp settings (though so far gdb has
done a good job by not sending duplicated bp/wp requests). */
struct aarch64_debug_reg_state
{
/* hardware breakpoint */
CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
/* hardware watchpoint */
CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
};
/* Per-process data. We don't bind this to a per-inferior registry
because of targets like x86 GNU/Linux that need to keep track of
processes that aren't bound to any inferior (e.g., fork children,
@ -286,52 +163,6 @@ aarch64_get_debug_reg_state (pid_t pid)
return &aarch64_process_info_get (pid)->state;
}
/* Per-thread arch-specific data we want to keep. */
struct arch_lwp_info
{
/* When bit N is 1, it indicates the Nth hardware breakpoint or
watchpoint register pair needs to be updated when the thread is
resumed; see aarch64_linux_prepare_to_resume. */
dr_changed_t dr_changed_bp;
dr_changed_t dr_changed_wp;
};
/* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
registers with data from *STATE. */
static void
aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
int tid, int watchpoint)
{
int i, count;
struct iovec iov;
struct user_hwdebug_state regs;
const CORE_ADDR *addr;
const unsigned int *ctrl;
memset (&regs, 0, sizeof (regs));
iov.iov_base = &regs;
count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
if (count == 0)
return;
iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
+ sizeof (regs.dbg_regs [count - 1]));
for (i = 0; i < count; i++)
{
regs.dbg_regs[i].addr = addr[i];
regs.dbg_regs[i].ctrl = ctrl[i];
}
if (ptrace (PTRACE_SETREGSET, tid,
watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
(void *) &iov))
error (_("Unexpected error setting hardware debug registers"));
}
struct aarch64_dr_update_callback_param
{
int is_watchpoint;
@ -407,7 +238,7 @@ debug_reg_change_callback (struct lwp_info *lwp, void *ptr)
thread's arch-specific data area, the actual updating will be done
when the thread is resumed. */
static void
void
aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
int is_watchpoint, unsigned int idx)
{
@ -420,39 +251,6 @@ aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
iterate_over_lwps (pid_ptid, debug_reg_change_callback, (void *) &param);
}
/* Print the values of the cached breakpoint/watchpoint registers. */
static void
aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
const char *func, CORE_ADDR addr,
int len, int type)
{
int i;
debug_printf ("%s", func);
if (addr || len)
debug_printf (" (addr=0x%08lx, len=%d, type=%s)",
(unsigned long) addr, len,
type == hw_write ? "hw-write-watchpoint"
: (type == hw_read ? "hw-read-watchpoint"
: (type == hw_access ? "hw-access-watchpoint"
: (type == hw_execute ? "hw-breakpoint"
: "??unknown??"))));
debug_printf (":\n");
debug_printf ("\tBREAKPOINTs:\n");
for (i = 0; i < aarch64_num_bp_regs; i++)
debug_printf ("\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
i, state->dr_addr_bp[i],
state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
debug_printf ("\tWATCHPOINTs:\n");
for (i = 0; i < aarch64_num_wp_regs; i++)
debug_printf ("\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n",
i, state->dr_addr_wp[i],
state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
}
/* Fill GDB's register array with the general-purpose register values
from the current thread. */
@ -956,80 +754,6 @@ aarch64_linux_read_description (struct target_ops *ops)
return tdesc_aarch64;
}
/* Given the (potentially unaligned) watchpoint address in ADDR and
length in LEN, return the aligned address and aligned length in
*ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
aligned address and length will be valid values to write to the
hardware watchpoint value and control registers.
The given watchpoint may get truncated if more than one hardware
register is needed to cover the watched region. *NEXT_ADDR_P
and *NEXT_LEN_P, if non-NULL, will return the address and length
of the remaining part of the watchpoint (which can be processed
by calling this routine again to generate another aligned address
and length pair.
See the comment above the function of the same name in
gdbserver/linux-aarch64-low.c for more information. */
static void
aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
int *aligned_len_p, CORE_ADDR *next_addr_p,
int *next_len_p)
{
int aligned_len;
unsigned int offset;
CORE_ADDR aligned_addr;
const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
/* As assumed by the algorithm. */
gdb_assert (alignment == max_wp_len);
if (len <= 0)
return;
/* Address to be put into the hardware watchpoint value register
must be aligned. */
offset = addr & (alignment - 1);
aligned_addr = addr - offset;
gdb_assert (offset >= 0 && offset < alignment);
gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
gdb_assert (offset + len > 0);
if (offset + len >= max_wp_len)
{
/* Need more than one watchpoint registers; truncate it at the
alignment boundary. */
aligned_len = max_wp_len;
len -= (max_wp_len - offset);
addr += (max_wp_len - offset);
gdb_assert ((addr & (alignment - 1)) == 0);
}
else
{
/* Find the smallest valid length that is large enough to
accommodate this watchpoint. */
static const unsigned char
aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
{ 1, 2, 4, 4, 8, 8, 8, 8 };
aligned_len = aligned_len_array[offset + len - 1];
addr += len;
len = 0;
}
if (aligned_addr_p)
*aligned_addr_p = aligned_addr;
if (aligned_len_p)
*aligned_len_p = aligned_len;
if (next_addr_p)
*next_addr_p = addr;
if (next_len_p)
*next_len_p = len;
}
/* Returns the number of hardware watchpoints of type TYPE that we can
set. Value is positive if we can set CNT watchpoints, zero if
setting watchpoints of type TYPE is not supported, and negative if
@ -1054,257 +778,6 @@ aarch64_linux_can_use_hw_breakpoint (struct target_ops *self,
return 1;
}
/* ptrace expects control registers to be formatted as follows:
31 13 5 3 1 0
+--------------------------------+----------+------+------+----+
| RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
+--------------------------------+----------+------+------+----+
The TYPE field is ignored for breakpoints. */
#define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
#define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
/* Utility function that returns the length in bytes of a watchpoint
according to the content of a hardware debug control register CTRL.
Note that the kernel currently only supports the following Byte
Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
that for a hardware watchpoint, its valid length can only be 1
byte, 2 bytes, 4 bytes or 8 bytes. */
static inline unsigned int
aarch64_watchpoint_length (unsigned int ctrl)
{
switch (DR_CONTROL_LENGTH (ctrl))
{
case 0x01:
return 1;
case 0x03:
return 2;
case 0x0f:
return 4;
case 0xff:
return 8;
default:
return 0;
}
}
/* Given the hardware breakpoint or watchpoint type TYPE and its
length LEN, return the expected encoding for a hardware
breakpoint/watchpoint control register. */
static unsigned int
aarch64_point_encode_ctrl_reg (int type, int len)
{
unsigned int ctrl, ttype;
/* type */
switch (type)
{
case hw_write:
ttype = 2;
break;
case hw_read:
ttype = 1;
break;
case hw_access:
ttype = 3;
break;
case hw_execute:
ttype = 0;
break;
default:
perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
}
ctrl = ttype << 3;
/* length bitmask */
ctrl |= ((1 << len) - 1) << 5;
/* enabled at el0 */
ctrl |= (2 << 1) | 1;
return ctrl;
}
/* Addresses to be written to the hardware breakpoint and watchpoint
value registers need to be aligned; the alignment is 4-byte and
8-type respectively. Linux kernel rejects any non-aligned address
it receives from the related ptrace call. Furthermore, the kernel
currently only supports the following Byte Address Select (BAS)
values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
watchpoint to be accepted by the kernel (via ptrace call), its
valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
Despite these limitations, the unaligned watchpoint is supported in
this port.
Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
static int
aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
{
unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
: AARCH64_HBP_ALIGNMENT;
if (addr & (alignment - 1))
return 0;
if (len != 8 && len != 4 && len != 2 && len != 1)
return 0;
return 1;
}
/* Record the insertion of one breakpoint/watchpoint, as represented
by ADDR and CTRL, in the cached debug register state area *STATE. */
static int
aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
enum target_hw_bp_type type, CORE_ADDR addr,
int len)
{
int i, idx, num_regs, is_watchpoint;
unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
CORE_ADDR *dr_addr_p;
/* Set up state pointers. */
is_watchpoint = (type != hw_execute);
gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
if (is_watchpoint)
{
num_regs = aarch64_num_wp_regs;
dr_addr_p = state->dr_addr_wp;
dr_ctrl_p = state->dr_ctrl_wp;
dr_ref_count = state->dr_ref_count_wp;
}
else
{
num_regs = aarch64_num_bp_regs;
dr_addr_p = state->dr_addr_bp;
dr_ctrl_p = state->dr_ctrl_bp;
dr_ref_count = state->dr_ref_count_bp;
}
ctrl = aarch64_point_encode_ctrl_reg (type, len);
/* Find an existing or free register in our cache. */
idx = -1;
for (i = 0; i < num_regs; ++i)
{
if ((dr_ctrl_p[i] & 1) == 0)
{
gdb_assert (dr_ref_count[i] == 0);
idx = i;
/* no break; continue hunting for an existing one. */
}
else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
{
gdb_assert (dr_ref_count[i] != 0);
idx = i;
break;
}
}
/* No space. */
if (idx == -1)
return -1;
/* Update our cache. */
if ((dr_ctrl_p[idx] & 1) == 0)
{
/* new entry */
dr_addr_p[idx] = addr;
dr_ctrl_p[idx] = ctrl;
dr_ref_count[idx] = 1;
/* Notify the change. */
aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
}
else
{
/* existing entry */
dr_ref_count[idx]++;
}
return 0;
}
/* Record the removal of one breakpoint/watchpoint, as represented by
ADDR and CTRL, in the cached debug register state area *STATE. */
static int
aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
enum target_hw_bp_type type, CORE_ADDR addr,
int len)
{
int i, num_regs, is_watchpoint;
unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
CORE_ADDR *dr_addr_p;
/* Set up state pointers. */
is_watchpoint = (type != hw_execute);
gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
if (is_watchpoint)
{
num_regs = aarch64_num_wp_regs;
dr_addr_p = state->dr_addr_wp;
dr_ctrl_p = state->dr_ctrl_wp;
dr_ref_count = state->dr_ref_count_wp;
}
else
{
num_regs = aarch64_num_bp_regs;
dr_addr_p = state->dr_addr_bp;
dr_ctrl_p = state->dr_ctrl_bp;
dr_ref_count = state->dr_ref_count_bp;
}
ctrl = aarch64_point_encode_ctrl_reg (type, len);
/* Find the entry that matches the ADDR and CTRL. */
for (i = 0; i < num_regs; ++i)
if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
{
gdb_assert (dr_ref_count[i] != 0);
break;
}
/* Not found. */
if (i == num_regs)
return -1;
/* Clear our cache. */
if (--dr_ref_count[i] == 0)
{
/* Clear the enable bit. */
ctrl &= ~1;
dr_addr_p[i] = 0;
dr_ctrl_p[i] = ctrl;
/* Notify the change. */
aarch64_notify_debug_reg_change (state, is_watchpoint, i);
}
return 0;
}
/* Implement insertion and removal of a single breakpoint. */
static int
aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
int len, int is_insert,
struct aarch64_debug_reg_state *state)
{
/* The hardware breakpoint on AArch64 should always be 4-byte
aligned. */
if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
return -1;
if (is_insert)
return aarch64_dr_state_insert_one_point (state, type, addr, len);
else
return aarch64_dr_state_remove_one_point (state, type, addr, len);
}
/* Insert a hardware-assisted breakpoint at BP_TGT->reqstd_address.
Return 0 on success, -1 on failure. */
@ -1368,75 +841,6 @@ aarch64_linux_remove_hw_breakpoint (struct target_ops *self,
return ret;
}
/* This is essentially the same as aarch64_handle_breakpoint, apart
from that it is an aligned watchpoint to be handled. */
static int
aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
int len, int is_insert,
struct aarch64_debug_reg_state *state)
{
if (is_insert)
return aarch64_dr_state_insert_one_point (state, type, addr, len);
else
return aarch64_dr_state_remove_one_point (state, type, addr, len);
}
/* Insert/remove unaligned watchpoint by calling
aarch64_align_watchpoint repeatedly until the whole watched region,
as represented by ADDR and LEN, has been properly aligned and ready
to be written to one or more hardware watchpoint registers.
IS_INSERT indicates whether this is an insertion or a deletion.
Return 0 if succeed. */
static int
aarch64_handle_unaligned_watchpoint (int type, CORE_ADDR addr, int len,
int is_insert,
struct aarch64_debug_reg_state *state)
{
while (len > 0)
{
CORE_ADDR aligned_addr;
int aligned_len, ret;
aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
&addr, &len);
if (is_insert)
ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
aligned_len);
else
ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
aligned_len);
if (show_debug_regs)
debug_printf (
"handle_unaligned_watchpoint: is_insert: %d\n"
" aligned_addr: 0x%08lx, aligned_len: %d\n"
" next_addr: 0x%08lx, next_len: %d\n",
is_insert, aligned_addr, aligned_len, addr, len);
if (ret != 0)
return ret;
}
return 0;
}
/* Implements insertion and removal of a single watchpoint. */
static int
aarch64_handle_watchpoint (int type, CORE_ADDR addr, int len, int is_insert,
struct aarch64_debug_reg_state *state)
{
if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert,
state);
else
return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert,
state);
}
/* Implement the "to_insert_watchpoint" target_ops method.
Insert a watchpoint to watch a memory region which starts at

2
gdb/config/aarch64/linux.mh
View File

@ -22,7 +22,7 @@ NAT_FILE= config/nm-linux.h
NATDEPFILES= inf-ptrace.o fork-child.o aarch64-linux-nat.o aarch32-linux-nat.o \
proc-service.o linux-thread-db.o linux-nat.o linux-fork.o \
linux-procfs.o linux-ptrace.o linux-osdata.o linux-waitpid.o \
linux-personality.o linux-namespaces.o
linux-personality.o linux-namespaces.o aarch64-linux-hw-point.o
NAT_CDEPS = $(srcdir)/proc-service.list
LOADLIBES= -ldl $(RDYNAMIC)

30
gdb/gdbserver/ChangeLog
View File

@ -1,3 +1,33 @@
2015-07-17 Yao Qi <yao.qi@linaro.org>
* Makefile.in (aarch64-linux-hw-point.o): New rule.
* configure.srv (srv_tgtobj): Append aarch64-linux-hw-point.o.
* linux-aarch64-low.c: Include nat/aarch64-linux-hw-point.h.
(AARCH64_HBP_MAX_NUM): Move to nat/aarch64-linux-hw-point.h.
(AARCH64_HWP_MAX_NUM, AARCH64_HBP_ALIGNMENT): Likewise.
(AARCH64_HWP_ALIGNMENT): Likewise.
(AARCH64_HWP_MAX_LEN_PER_REG): Likewise.
(AARCH64_DEBUG_NUM_SLOTS, AARCH64_DEBUG_ARCH): Likewise.
(aarch64_num_bp_regs, aarch64_num_wp_regs): Likewise.
(AARCH64_DEBUG_ARCH_V8, DR_MARK_ALL_CHANGED): Likewise.
(DR_MARK_N_CHANGED, DR_CLEAR_CHANGED): Likewise.
(DR_HAS_CHANGED, DR_N_HAS_CHANGE): Likewise.
(struct aarch64_debug_reg_state): Likewise.
(struct arch_lwp_info): Likewise.
(aarch64_align_watchpoint): Likewise.
(DR_CONTROL_ENABLED, DR_CONTROL_LENGTH): Likewise.
(aarch64_watchpoint_length): Likewise.
(aarch64_point_encode_ctrl_reg): Likewise
(aarch64_point_is_aligned): Likewise.
(aarch64_align_watchpoint): Likewise.
(aarch64_linux_set_debug_regs):
(aarch64_dr_state_insert_one_point): Likewise.
(aarch64_dr_state_remove_one_point): Likewise.
(aarch64_handle_breakpoint): Likewise.
(aarch64_handle_aligned_watchpoint): Likewise.
(aarch64_handle_unaligned_watchpoint): Likewise.
(aarch64_handle_watchpoint): Likewise.
2015-07-17 Yao Qi <yao.qi@linaro.org>
* linux-aarch64-low.c (aarch64_handle_breakpoint): Add argument state

3
gdb/gdbserver/Makefile.in
View File

@ -606,6 +606,9 @@ ppc-linux.o: ../nat/ppc-linux.c
linux-personality.o: ../nat/linux-personality.c
$(COMPILE) $<
$(POSTCOMPILE)
aarch64-linux-hw-point.o: ../nat/aarch64-linux-hw-point.c
$(COMPILE) $<
$(POSTCOMPILE)
btrace-common.o: ../common/btrace-common.c
$(COMPILE) $<
$(POSTCOMPILE)

2
gdb/gdbserver/configure.srv
View File

@ -49,7 +49,7 @@ srv_linux_obj="linux-low.o linux-osdata.o linux-procfs.o linux-ptrace.o linux-wa
case "${target}" in
aarch64*-*-linux*)
srv_regobj="aarch64.o"
srv_tgtobj="linux-aarch64-low.o"
srv_tgtobj="linux-aarch64-low.o aarch64-linux-hw-point.o"
srv_tgtobj="${srv_tgtobj} $srv_linux_obj"
srv_xmlfiles="aarch64.xml"
srv_xmlfiles="${srv_xmlfiles} aarch64-core.xml"

618
gdb/gdbserver/linux-aarch64-low.c
View File

@ -21,6 +21,7 @@
#include "server.h"
#include "linux-low.h"
#include "nat/aarch64-linux-hw-point.h"
#include "elf/common.h"
#include <signal.h>
@ -51,109 +52,6 @@ extern const struct target_desc *tdesc_aarch64;
#define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
/* Here starts the macro definitions, data structures, and code for
the hardware breakpoint and hardware watchpoint support. The
following is the abbreviations that are used frequently in the code
and comment:
hw - hardware
bp - breakpoint
wp - watchpoint */
/* Maximum number of hardware breakpoint and watchpoint registers.
Neither of these values may exceed the width of dr_changed_t
measured in bits. */
#define AARCH64_HBP_MAX_NUM 16
#define AARCH64_HWP_MAX_NUM 16
/* Alignment requirement in bytes of hardware breakpoint and
watchpoint address. This is the requirement for the addresses that
can be written to the hardware breakpoint/watchpoint value
registers. The kernel currently does not do any alignment on
addresses when receiving a writing request (via ptrace call) to
these debug registers, and it will reject any address that is
unaligned.
Some limited support has been provided in this gdbserver port for
unaligned watchpoints, so that from a gdb user point of view, an
unaligned watchpoint can still be set. This is achieved by
minimally enlarging the watched area to meet the alignment
requirement, and if necessary, splitting the watchpoint over
several hardware watchpoint registers. */
#define AARCH64_HBP_ALIGNMENT 4
#define AARCH64_HWP_ALIGNMENT 8
/* The maximum length of a memory region that can be watched by one
hardware watchpoint register. */
#define AARCH64_HWP_MAX_LEN_PER_REG 8
/* Each bit of a variable of this type is used to indicate whether a
hardware breakpoint or watchpoint setting has been changed since
the last updating. Bit N corresponds to the Nth hardware
breakpoint or watchpoint setting which is managed in
aarch64_debug_reg_state. Where N is valid between 0 and the total
number of the hardware breakpoint or watchpoint debug registers
minus 1. When the bit N is 1, it indicates the corresponding
breakpoint or watchpoint setting is changed, and thus the
corresponding hardware debug register needs to be updated via the
ptrace interface.
In the per-thread arch-specific data area, we define two such
variables for per-thread hardware breakpoint and watchpoint
settings respectively.
This type is part of the mechanism which helps reduce the number of
ptrace calls to the kernel, i.e. avoid asking the kernel to write
to the debug registers with unchanged values. */
typedef unsigned long long dr_changed_t;
/* Set each of the lower M bits of X to 1; assert X is wide enough. */
#define DR_MARK_ALL_CHANGED(x, m) \
do \
{ \
gdb_assert (sizeof ((x)) * 8 >= (m)); \
(x) = (((dr_changed_t)1 << (m)) - 1); \
} while (0)
#define DR_MARK_N_CHANGED(x, n) \
do \
{ \
(x) |= ((dr_changed_t)1 << (n)); \
} while (0)
#define DR_CLEAR_CHANGED(x) \
do \
{ \
(x) = 0; \
} while (0)
#define DR_HAS_CHANGED(x) ((x) != 0)
#define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
/* Structure for managing the hardware breakpoint/watchpoint resources.
DR_ADDR_* stores the address, DR_CTRL_* stores the control register
content, and DR_REF_COUNT_* counts the numbers of references to the
corresponding bp/wp, by which way the limited hardware resources
are not wasted on duplicated bp/wp settings (though so far gdb has
done a good job by not sending duplicated bp/wp requests). */
struct aarch64_debug_reg_state
{
/* hardware breakpoint */
CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
/* hardware watchpoint */
CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
};
/* Per-process arch-specific data we want to keep. */
struct arch_process_info
@ -171,24 +69,6 @@ struct arch_process_info
struct aarch64_debug_reg_state debug_reg_state;
};
/* Per-thread arch-specific data we want to keep. */
struct arch_lwp_info
{
/* When bit N is 1, it indicates the Nth hardware breakpoint or
watchpoint register pair needs to be updated when the thread is
resumed; see aarch64_linux_prepare_to_resume. */
dr_changed_t dr_changed_bp;
dr_changed_t dr_changed_wp;
};
/* Number of hardware breakpoints/watchpoints the target supports.
They are initialized with values obtained via the ptrace calls
with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
static int aarch64_num_bp_regs;
static int aarch64_num_wp_regs;
/* Implementation of linux_target_ops method "cannot_store_register". */
static int
@ -303,40 +183,6 @@ aarch64_breakpoint_at (CORE_ADDR where)
return 0;
}
/* Print the values of the cached breakpoint/watchpoint registers.
This is enabled via the "set debug-hw-points" monitor command. */
static void
aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
const char *func, CORE_ADDR addr,
int len, enum target_hw_bp_type type)
{
int i;
debug_printf ("%s", func);
if (addr || len)
debug_printf (" (addr=0x%08lx, len=%d, type=%s)",
(unsigned long) addr, len,
type == hw_write ? "hw-write-watchpoint"
: (type == hw_read ? "hw-read-watchpoint"
: (type == hw_access ? "hw-access-watchpoint"
: (type == hw_execute ? "hw-breakpoint"
: "??unknown??"))));
debug_printf (":\n");
debug_printf ("\tBREAKPOINTs:\n");
for (i = 0; i < aarch64_num_bp_regs; i++)
debug_printf ("\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
i, paddress (state->dr_addr_bp[i]),
state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
debug_printf ("\tWATCHPOINTs:\n");
for (i = 0; i < aarch64_num_wp_regs; i++)
debug_printf ("\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n",
i, paddress (state->dr_addr_wp[i]),
state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
}
static void
aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state)
{
@ -357,241 +203,6 @@ aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state)
}
}
/* ptrace expects control registers to be formatted as follows:
31 13 5 3 1 0
+--------------------------------+----------+------+------+----+
| RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
+--------------------------------+----------+------+------+----+
The TYPE field is ignored for breakpoints. */
#define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
#define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
/* Utility function that returns the length in bytes of a watchpoint
according to the content of a hardware debug control register CTRL.
Note that the kernel currently only supports the following Byte
Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
that for a hardware watchpoint, its valid length can only be 1
byte, 2 bytes, 4 bytes or 8 bytes. */
static inline unsigned int
aarch64_watchpoint_length (unsigned int ctrl)
{
switch (DR_CONTROL_LENGTH (ctrl))
{
case 0x01:
return 1;
case 0x03:
return 2;
case 0x0f:
return 4;
case 0xff:
return 8;
default:
return 0;
}
}
/* Given the hardware breakpoint or watchpoint type TYPE and its
length LEN, return the expected encoding for a hardware
breakpoint/watchpoint control register. */
static unsigned int
aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len)
{
unsigned int ctrl, ttype;
/* type */
switch (type)
{
case hw_write:
ttype = 2;
break;
case hw_read:
ttype = 1;
break;
case hw_access:
ttype = 3;
break;
case hw_execute:
ttype = 0;
break;
default:
perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
}
/* type */
ctrl = ttype << 3;
/* length bitmask */
ctrl |= ((1 << len) - 1) << 5;
/* enabled at el0 */
ctrl |= (2 << 1) | 1;
return ctrl;
}
/* Addresses to be written to the hardware breakpoint and watchpoint
value registers need to be aligned; the alignment is 4-byte and
8-type respectively. Linux kernel rejects any non-aligned address
it receives from the related ptrace call. Furthermore, the kernel
currently only supports the following Byte Address Select (BAS)
values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
watchpoint to be accepted by the kernel (via ptrace call), its
valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
Despite these limitations, the unaligned watchpoint is supported in
this gdbserver port.
Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
static int
aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
{
unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
: AARCH64_HBP_ALIGNMENT;
if (addr & (alignment - 1))
return 0;
if (len != 8 && len != 4 && len != 2 && len != 1)
return 0;
return 1;
}
/* Given the (potentially unaligned) watchpoint address in ADDR and
length in LEN, return the aligned address and aligned length in
*ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
aligned address and length will be valid to be written to the
hardware watchpoint value and control registers. See the comment
above aarch64_point_is_aligned for the information about the
alignment requirement. The given watchpoint may get truncated if
more than one hardware register is needed to cover the watched
region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the
address and length of the remaining part of the watchpoint (which
can be processed by calling this routine again to generate another
aligned address and length pair.
Essentially, unaligned watchpoint is achieved by minimally
enlarging the watched area to meet the alignment requirement, and
if necessary, splitting the watchpoint over several hardware
watchpoint registers. The trade-off is that there will be
false-positive hits for the read-type or the access-type hardware
watchpoints; for the write type, which is more commonly used, there
will be no such issues, as the higher-level breakpoint management
in gdb always examines the exact watched region for any content
change, and transparently resumes a thread from a watchpoint trap
if there is no change to the watched region.
Another limitation is that because the watched region is enlarged,
the watchpoint fault address returned by
aarch64_stopped_data_address may be outside of the original watched
region, especially when the triggering instruction is accessing a
larger region. When the fault address is not within any known
range, watchpoints_triggered in gdb will get confused, as the
higher-level watchpoint management is only aware of original
watched regions, and will think that some unknown watchpoint has
been triggered. In such a case, gdb may stop without displaying
any detailed information.
Once the kernel provides the full support for Byte Address Select
(BAS) in the hardware watchpoint control register, these
limitations can be largely relaxed with some further work. */
static void
aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
int *aligned_len_p, CORE_ADDR *next_addr_p,
int *next_len_p)
{
int aligned_len;
unsigned int offset;
CORE_ADDR aligned_addr;
const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
/* As assumed by the algorithm. */
gdb_assert (alignment == max_wp_len);
if (len <= 0)
return;
/* Address to be put into the hardware watchpoint value register
must be aligned. */
offset = addr & (alignment - 1);
aligned_addr = addr - offset;
gdb_assert (offset >= 0 && offset < alignment);
gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
gdb_assert ((offset + len) > 0);
if (offset + len >= max_wp_len)
{
/* Need more than one watchpoint registers; truncate it at the
alignment boundary. */
aligned_len = max_wp_len;
len -= (max_wp_len - offset);
addr += (max_wp_len - offset);
gdb_assert ((addr & (alignment - 1)) == 0);
}
else
{
/* Find the smallest valid length that is large enough to
accommodate this watchpoint. */
static const unsigned char
aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
{ 1, 2, 4, 4, 8, 8, 8, 8 };
aligned_len = aligned_len_array[offset + len - 1];
addr += len;
len = 0;
}
if (aligned_addr_p != NULL)
*aligned_addr_p = aligned_addr;
if (aligned_len_p != NULL)
*aligned_len_p = aligned_len;
if (next_addr_p != NULL)
*next_addr_p = addr;
if (next_len_p != NULL)
*next_len_p = len;
}
/* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
registers with data from *STATE. */
static void
aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
int tid, int watchpoint)
{
int i, count;
struct iovec iov;
struct user_hwdebug_state regs;
const CORE_ADDR *addr;
const unsigned int *ctrl;
memset (&regs, 0, sizeof (regs));
iov.iov_base = &regs;
count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
if (count == 0)
return;
iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
+ sizeof (regs.dbg_regs [count - 1]));
for (i = 0; i < count; i++)
{
regs.dbg_regs[i].addr = addr[i];
regs.dbg_regs[i].ctrl = ctrl[i];
}
if (ptrace (PTRACE_SETREGSET, tid,
watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
(void *) &iov))
error (_("Unexpected error setting hardware debug registers"));
}
struct aarch64_dr_update_callback_param
{
int pid;
@ -714,222 +325,6 @@ aarch64_get_debug_reg_state ()
return &proc->priv->arch_private->debug_reg_state;
}
/* Record the insertion of one breakpoint/watchpoint, as represented
by ADDR and CTRL, in the process' arch-specific data area *STATE. */
static int
aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
enum target_hw_bp_type type,
CORE_ADDR addr, int len)
{
int i, idx, num_regs, is_watchpoint;
unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
CORE_ADDR *dr_addr_p;
/* Set up state pointers. */
is_watchpoint = (type != hw_execute);
gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
if (is_watchpoint)
{
num_regs = aarch64_num_wp_regs;
dr_addr_p = state->dr_addr_wp;
dr_ctrl_p = state->dr_ctrl_wp;
dr_ref_count = state->dr_ref_count_wp;
}
else
{
num_regs = aarch64_num_bp_regs;
dr_addr_p = state->dr_addr_bp;
dr_ctrl_p = state->dr_ctrl_bp;
dr_ref_count = state->dr_ref_count_bp;
}
ctrl = aarch64_point_encode_ctrl_reg (type, len);
/* Find an existing or free register in our cache. */
idx = -1;
for (i = 0; i < num_regs; ++i)
{
if ((dr_ctrl_p[i] & 1) == 0)
{
gdb_assert (dr_ref_count[i] == 0);
idx = i;
/* no break; continue hunting for an exising one. */
}
else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
{
gdb_assert (dr_ref_count[i] != 0);
idx = i;
break;
}
}
/* No space. */
if (idx == -1)
return -1;
/* Update our cache. */
if ((dr_ctrl_p[idx] & 1) == 0)
{
/* new entry */
dr_addr_p[idx] = addr;
dr_ctrl_p[idx] = ctrl;
dr_ref_count[idx] = 1;
/* Notify the change. */
aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
}
else
{
/* existing entry */
dr_ref_count[idx]++;
}
return 0;
}
/* Record the removal of one breakpoint/watchpoint, as represented by
ADDR and CTRL, in the process' arch-specific data area *STATE. */
static int
aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
enum target_hw_bp_type type,
CORE_ADDR addr, int len)
{
int i, num_regs, is_watchpoint;
unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
CORE_ADDR *dr_addr_p;
/* Set up state pointers. */
is_watchpoint = (type != hw_execute);
gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
if (is_watchpoint)
{
num_regs = aarch64_num_wp_regs;
dr_addr_p = state->dr_addr_wp;
dr_ctrl_p = state->dr_ctrl_wp;
dr_ref_count = state->dr_ref_count_wp;
}
else
{
num_regs = aarch64_num_bp_regs;
dr_addr_p = state->dr_addr_bp;
dr_ctrl_p = state->dr_ctrl_bp;
dr_ref_count = state->dr_ref_count_bp;
}
ctrl = aarch64_point_encode_ctrl_reg (type, len);
/* Find the entry that matches the ADDR and CTRL. */
for (i = 0; i < num_regs; ++i)
if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
{
gdb_assert (dr_ref_count[i] != 0);
break;
}
/* Not found. */
if (i == num_regs)
return -1;
/* Clear our cache. */
if (--dr_ref_count[i] == 0)
{
/* Clear the enable bit. */
ctrl &= ~1;
dr_addr_p[i] = 0;
dr_ctrl_p[i] = ctrl;
/* Notify the change. */
aarch64_notify_debug_reg_change (state, is_watchpoint, i);
}
return 0;
}
static int
aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
int len, int is_insert,
struct aarch64_debug_reg_state *state)
{
/* The hardware breakpoint on AArch64 should always be 4-byte
aligned. */
if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
return -1;
if (is_insert)
return aarch64_dr_state_insert_one_point (state, type, addr, len);
else
return aarch64_dr_state_remove_one_point (state, type, addr, len);
}
/* This is essentially the same as aarch64_handle_breakpoint, apart
from that it is an aligned watchpoint to be handled. */
static int
aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
CORE_ADDR addr, int len, int is_insert,
struct aarch64_debug_reg_state *state)
{
if (is_insert)
return aarch64_dr_state_insert_one_point (state, type, addr, len);
else
return aarch64_dr_state_remove_one_point (state, type, addr, len);
}
/* Insert/remove unaligned watchpoint by calling
aarch64_align_watchpoint repeatedly until the whole watched region,
as represented by ADDR and LEN, has been properly aligned and ready
to be written to one or more hardware watchpoint registers.
IS_INSERT indicates whether this is an insertion or a deletion.
Return 0 if succeed. */
static int
aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
CORE_ADDR addr, int len, int is_insert,
struct aarch64_debug_reg_state *state)
{
while (len > 0)
{
CORE_ADDR aligned_addr;
int aligned_len, ret;
aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
&addr, &len);
if (is_insert)
ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
aligned_len);
else
ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
aligned_len);
if (show_debug_regs)
debug_printf (
"handle_unaligned_watchpoint: is_insert: %d\n"
" aligned_addr: 0x%s, aligned_len: %d\n"
" next_addr: 0x%s, next_len: %d\n",
is_insert, paddress (aligned_addr), aligned_len,
paddress (addr), len);
if (ret != 0)
return ret;
}
return 0;
}
static int
aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
int len, int is_insert,
struct aarch64_debug_reg_state *state)
{
if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert,
state);
else
return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert,
state);
}
/* Implementation of linux_target_ops method "supports_z_point_type". */
static int
@ -1187,17 +582,6 @@ aarch64_linux_prepare_to_resume (struct lwp_info *lwp)
}
}
/* ptrace hardware breakpoint resource info is formatted as follows:
31 24 16 8 0
+---------------+--------------+---------------+---------------+
| RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
+---------------+--------------+---------------+---------------+ */
#define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
#define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
#define AARCH64_DEBUG_ARCH_V8 0x6
/* Implementation of linux_target_ops method "arch_setup". */
static void

505
gdb/nat/aarch64-linux-hw-point.c Normal file
View File

@ -0,0 +1,505 @@
/* Copyright (C) 2009-2015 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "common-defs.h"
#include "break-common.h"
#include "aarch64-linux-hw-point.h"
#include <sys/uio.h>
#include <asm/ptrace.h>
#include <sys/ptrace.h>
#include <elf.h>
/* Number of hardware breakpoints/watchpoints the target supports.
They are initialized with values obtained via the ptrace calls
with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */
int aarch64_num_bp_regs;
int aarch64_num_wp_regs;
/* Utility function that returns the length in bytes of a watchpoint
according to the content of a hardware debug control register CTRL.
Note that the kernel currently only supports the following Byte
Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
that for a hardware watchpoint, its valid length can only be 1
byte, 2 bytes, 4 bytes or 8 bytes. */
unsigned int
aarch64_watchpoint_length (unsigned int ctrl)
{
switch (DR_CONTROL_LENGTH (ctrl))
{
case 0x01:
return 1;
case 0x03:
return 2;
case 0x0f:
return 4;
case 0xff:
return 8;
default:
return 0;
}
}
/* Given the hardware breakpoint or watchpoint type TYPE and its
length LEN, return the expected encoding for a hardware
breakpoint/watchpoint control register. */
static unsigned int
aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len)
{
unsigned int ctrl, ttype;
/* type */
switch (type)
{
case hw_write:
ttype = 2;
break;
case hw_read:
ttype = 1;
break;
case hw_access:
ttype = 3;
break;
case hw_execute:
ttype = 0;
break;
default:
perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
}
ctrl = ttype << 3;
/* length bitmask */
ctrl |= ((1 << len) - 1) << 5;
/* enabled at el0 */
ctrl |= (2 << 1) | 1;
return ctrl;
}
/* Addresses to be written to the hardware breakpoint and watchpoint
value registers need to be aligned; the alignment is 4-byte and
8-type respectively. Linux kernel rejects any non-aligned address
it receives from the related ptrace call. Furthermore, the kernel
currently only supports the following Byte Address Select (BAS)
values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
watchpoint to be accepted by the kernel (via ptrace call), its
valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
Despite these limitations, the unaligned watchpoint is supported in
this port.
Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */
static int
aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
{
unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
: AARCH64_HBP_ALIGNMENT;
if (addr & (alignment - 1))
return 0;
if (len != 8 && len != 4 && len != 2 && len != 1)
return 0;
return 1;
}
/* Given the (potentially unaligned) watchpoint address in ADDR and
length in LEN, return the aligned address and aligned length in
*ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned
aligned address and length will be valid values to write to the
hardware watchpoint value and control registers.
The given watchpoint may get truncated if more than one hardware
register is needed to cover the watched region. *NEXT_ADDR_P
and *NEXT_LEN_P, if non-NULL, will return the address and length
of the remaining part of the watchpoint (which can be processed
by calling this routine again to generate another aligned address
and length pair.
Essentially, unaligned watchpoint is achieved by minimally
enlarging the watched area to meet the alignment requirement, and
if necessary, splitting the watchpoint over several hardware
watchpoint registers. The trade-off is that there will be
false-positive hits for the read-type or the access-type hardware
watchpoints; for the write type, which is more commonly used, there
will be no such issues, as the higher-level breakpoint management
in gdb always examines the exact watched region for any content
change, and transparently resumes a thread from a watchpoint trap
if there is no change to the watched region.
Another limitation is that because the watched region is enlarged,
the watchpoint fault address returned by
aarch64_stopped_data_address may be outside of the original watched
region, especially when the triggering instruction is accessing a
larger region. When the fault address is not within any known
range, watchpoints_triggered in gdb will get confused, as the
higher-level watchpoint management is only aware of original
watched regions, and will think that some unknown watchpoint has
been triggered. In such a case, gdb may stop without displaying
any detailed information.
Once the kernel provides the full support for Byte Address Select
(BAS) in the hardware watchpoint control register, these
limitations can be largely relaxed with some further work. */
static void
aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
int *aligned_len_p, CORE_ADDR *next_addr_p,
int *next_len_p)
{
int aligned_len;
unsigned int offset;
CORE_ADDR aligned_addr;
const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
/* As assumed by the algorithm. */
gdb_assert (alignment == max_wp_len);
if (len <= 0)
return;
/* Address to be put into the hardware watchpoint value register
must be aligned. */
offset = addr & (alignment - 1);
aligned_addr = addr - offset;
gdb_assert (offset >= 0 && offset < alignment);
gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
gdb_assert (offset + len > 0);
if (offset + len >= max_wp_len)
{
/* Need more than one watchpoint registers; truncate it at the
alignment boundary. */
aligned_len = max_wp_len;
len -= (max_wp_len - offset);
addr += (max_wp_len - offset);
gdb_assert ((addr & (alignment - 1)) == 0);
}
else
{
/* Find the smallest valid length that is large enough to
accommodate this watchpoint. */
static const unsigned char
aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
{ 1, 2, 4, 4, 8, 8, 8, 8 };
aligned_len = aligned_len_array[offset + len - 1];
addr += len;
len = 0;
}
if (aligned_addr_p)
*aligned_addr_p = aligned_addr;
if (aligned_len_p)
*aligned_len_p = aligned_len;
if (next_addr_p)
*next_addr_p = addr;
if (next_len_p)
*next_len_p = len;
}
/* Record the insertion of one breakpoint/watchpoint, as represented
by ADDR and CTRL, in the process' arch-specific data area *STATE. */
static int
aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
enum target_hw_bp_type type,
CORE_ADDR addr, int len)
{
int i, idx, num_regs, is_watchpoint;
unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
CORE_ADDR *dr_addr_p;
/* Set up state pointers. */
is_watchpoint = (type != hw_execute);
gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
if (is_watchpoint)
{
num_regs = aarch64_num_wp_regs;
dr_addr_p = state->dr_addr_wp;
dr_ctrl_p = state->dr_ctrl_wp;
dr_ref_count = state->dr_ref_count_wp;
}
else
{
num_regs = aarch64_num_bp_regs;
dr_addr_p = state->dr_addr_bp;
dr_ctrl_p = state->dr_ctrl_bp;
dr_ref_count = state->dr_ref_count_bp;
}
ctrl = aarch64_point_encode_ctrl_reg (type, len);
/* Find an existing or free register in our cache. */
idx = -1;
for (i = 0; i < num_regs; ++i)
{
if ((dr_ctrl_p[i] & 1) == 0)
{
gdb_assert (dr_ref_count[i] == 0);
idx = i;
/* no break; continue hunting for an exising one. */
}
else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
{
gdb_assert (dr_ref_count[i] != 0);
idx = i;
break;
}
}
/* No space. */
if (idx == -1)
return -1;
/* Update our cache. */
if ((dr_ctrl_p[idx] & 1) == 0)
{
/* new entry */
dr_addr_p[idx] = addr;
dr_ctrl_p[idx] = ctrl;
dr_ref_count[idx] = 1;
/* Notify the change. */
aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
}
else
{
/* existing entry */
dr_ref_count[idx]++;
}
return 0;
}
/* Record the removal of one breakpoint/watchpoint, as represented by
ADDR and CTRL, in the process' arch-specific data area *STATE. */
static int
aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
enum target_hw_bp_type type,
CORE_ADDR addr, int len)
{
int i, num_regs, is_watchpoint;
unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
CORE_ADDR *dr_addr_p;
/* Set up state pointers. */
is_watchpoint = (type != hw_execute);
gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
if (is_watchpoint)
{
num_regs = aarch64_num_wp_regs;
dr_addr_p = state->dr_addr_wp;
dr_ctrl_p = state->dr_ctrl_wp;
dr_ref_count = state->dr_ref_count_wp;
}
else
{
num_regs = aarch64_num_bp_regs;
dr_addr_p = state->dr_addr_bp;
dr_ctrl_p = state->dr_ctrl_bp;
dr_ref_count = state->dr_ref_count_bp;
}
ctrl = aarch64_point_encode_ctrl_reg (type, len);
/* Find the entry that matches the ADDR and CTRL. */
for (i = 0; i < num_regs; ++i)
if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
{
gdb_assert (dr_ref_count[i] != 0);
break;
}
/* Not found. */
if (i == num_regs)
return -1;
/* Clear our cache. */
if (--dr_ref_count[i] == 0)
{
/* Clear the enable bit. */
ctrl &= ~1;
dr_addr_p[i] = 0;
dr_ctrl_p[i] = ctrl;
/* Notify the change. */
aarch64_notify_debug_reg_change (state, is_watchpoint, i);
}
return 0;
}
int
aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
int len, int is_insert,
struct aarch64_debug_reg_state *state)
{
/* The hardware breakpoint on AArch64 should always be 4-byte
aligned. */
if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
return -1;
if (is_insert)
return aarch64_dr_state_insert_one_point (state, type, addr, len);
else
return aarch64_dr_state_remove_one_point (state, type, addr, len);
}
/* This is essentially the same as aarch64_handle_breakpoint, apart
from that it is an aligned watchpoint to be handled. */
static int
aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
CORE_ADDR addr, int len, int is_insert,
struct aarch64_debug_reg_state *state)
{
if (is_insert)
return aarch64_dr_state_insert_one_point (state, type, addr, len);
else
return aarch64_dr_state_remove_one_point (state, type, addr, len);
}
/* Insert/remove unaligned watchpoint by calling
aarch64_align_watchpoint repeatedly until the whole watched region,
as represented by ADDR and LEN, has been properly aligned and ready
to be written to one or more hardware watchpoint registers.
IS_INSERT indicates whether this is an insertion or a deletion.
Return 0 if succeed. */
static int
aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
CORE_ADDR addr, int len, int is_insert,
struct aarch64_debug_reg_state *state)
{
while (len > 0)
{
CORE_ADDR aligned_addr;
int aligned_len, ret;
aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
&addr, &len);
if (is_insert)
ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
aligned_len);
else
ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
aligned_len);
if (show_debug_regs)
debug_printf (
"handle_unaligned_watchpoint: is_insert: %d\n"
" aligned_addr: %s, aligned_len: %d\n"
" next_addr: %s, next_len: %d\n",
is_insert, core_addr_to_string_nz (aligned_addr), aligned_len,
core_addr_to_string_nz (addr), len);
if (ret != 0)
return ret;
}
return 0;
}
int
aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
int len, int is_insert,
struct aarch64_debug_reg_state *state)
{
if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert,
state);
else
return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert,
state);
}
/* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
registers with data from *STATE. */
void
aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
int tid, int watchpoint)
{
int i, count;
struct iovec iov;
struct user_hwdebug_state regs;
const CORE_ADDR *addr;
const unsigned int *ctrl;
memset (&regs, 0, sizeof (regs));
iov.iov_base = &regs;
count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
if (count == 0)
return;
iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
+ sizeof (regs.dbg_regs [count - 1]));
for (i = 0; i < count; i++)
{
regs.dbg_regs[i].addr = addr[i];
regs.dbg_regs[i].ctrl = ctrl[i];
}
if (ptrace (PTRACE_SETREGSET, tid,
watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
(void *) &iov))
error (_("Unexpected error setting hardware debug registers"));
}
/* Print the values of the cached breakpoint/watchpoint registers. */
void
aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
const char *func, CORE_ADDR addr,
int len, enum target_hw_bp_type type)
{
int i;
debug_printf ("%s", func);
if (addr || len)
debug_printf (" (addr=0x%08lx, len=%d, type=%s)",
(unsigned long) addr, len,
type == hw_write ? "hw-write-watchpoint"
: (type == hw_read ? "hw-read-watchpoint"
: (type == hw_access ? "hw-access-watchpoint"
: (type == hw_execute ? "hw-breakpoint"
: "??unknown??"))));
debug_printf (":\n");
debug_printf ("\tBREAKPOINTs:\n");
for (i = 0; i < aarch64_num_bp_regs; i++)
debug_printf ("\tBP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
i, core_addr_to_string_nz (state->dr_addr_bp[i]),
state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
debug_printf ("\tWATCHPOINTs:\n");
for (i = 0; i < aarch64_num_wp_regs; i++)
debug_printf ("\tWP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
i, core_addr_to_string_nz (state->dr_addr_wp[i]),
state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
}

184
gdb/nat/aarch64-linux-hw-point.h Normal file
View File

@ -0,0 +1,184 @@
/* Copyright (C) 2009-2015 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef AARCH64_LINUX_HW_POINT_H
#define AARCH64_LINUX_HW_POINT_H 1
/* Macro definitions, data structures, and code for the hardware
breakpoint and hardware watchpoint support follow. We use the
following abbreviations throughout the code:
hw - hardware
bp - breakpoint
wp - watchpoint */
/* Maximum number of hardware breakpoint and watchpoint registers.
Neither of these values may exceed the width of dr_changed_t
measured in bits. */
#define AARCH64_HBP_MAX_NUM 16
#define AARCH64_HWP_MAX_NUM 16
/* Alignment requirement in bytes for addresses written to
hardware breakpoint and watchpoint value registers.
A ptrace call attempting to set an address that does not meet the
alignment criteria will fail. Limited support has been provided in
this port for unaligned watchpoints, such that from a GDB user
perspective, an unaligned watchpoint may be requested.
This is achieved by minimally enlarging the watched area to meet the
alignment requirement, and if necessary, splitting the watchpoint
over several hardware watchpoint registers. */
#define AARCH64_HBP_ALIGNMENT 4
#define AARCH64_HWP_ALIGNMENT 8
/* The maximum length of a memory region that can be watched by one
hardware watchpoint register. */
#define AARCH64_HWP_MAX_LEN_PER_REG 8
/* ptrace hardware breakpoint resource info is formatted as follows:
31 24 16 8 0
+---------------+--------------+---------------+---------------+
| RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS |
+---------------+--------------+---------------+---------------+ */
/* Macros to extract fields from the hardware debug information word. */
#define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
#define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
/* Macro for the expected version of the ARMv8-A debug architecture. */
#define AARCH64_DEBUG_ARCH_V8 0x6
/* ptrace expects control registers to be formatted as follows:
31 13 5 3 1 0
+--------------------------------+----------+------+------+----+
| RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN |
+--------------------------------+----------+------+------+----+
The TYPE field is ignored for breakpoints. */
#define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1)
#define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff)
/* Each bit of a variable of this type is used to indicate whether a
hardware breakpoint or watchpoint setting has been changed since
the last update.
Bit N corresponds to the Nth hardware breakpoint or watchpoint
setting which is managed in aarch64_debug_reg_state, where N is
valid between 0 and the total number of the hardware breakpoint or
watchpoint debug registers minus 1.
When bit N is 1, the corresponding breakpoint or watchpoint setting
has changed, and therefore the corresponding hardware debug
register needs to be updated via the ptrace interface.
In the per-thread arch-specific data area, we define two such
variables for per-thread hardware breakpoint and watchpoint
settings respectively.
This type is part of the mechanism which helps reduce the number of
ptrace calls to the kernel, i.e. avoid asking the kernel to write
to the debug registers with unchanged values. */
typedef unsigned long long dr_changed_t;
/* Set each of the lower M bits of X to 1; assert X is wide enough. */
#define DR_MARK_ALL_CHANGED(x, m) \
do \
{ \
gdb_assert (sizeof ((x)) * 8 >= (m)); \
(x) = (((dr_changed_t)1 << (m)) - 1); \
} while (0)
#define DR_MARK_N_CHANGED(x, n) \
do \
{ \
(x) |= ((dr_changed_t)1 << (n)); \
} while (0)
#define DR_CLEAR_CHANGED(x) \
do \
{ \
(x) = 0; \
} while (0)
#define DR_HAS_CHANGED(x) ((x) != 0)
#define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
/* Structure for managing the hardware breakpoint/watchpoint resources.
DR_ADDR_* stores the address, DR_CTRL_* stores the control register
content, and DR_REF_COUNT_* counts the numbers of references to the
corresponding bp/wp, by which way the limited hardware resources
are not wasted on duplicated bp/wp settings (though so far gdb has
done a good job by not sending duplicated bp/wp requests). */
struct aarch64_debug_reg_state
{
/* hardware breakpoint */
CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
/* hardware watchpoint */
CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
};
/* Per-thread arch-specific data we want to keep. */
struct arch_lwp_info
{
/* When bit N is 1, it indicates the Nth hardware breakpoint or
watchpoint register pair needs to be updated when the thread is
resumed; see aarch64_linux_prepare_to_resume. */
dr_changed_t dr_changed_bp;
dr_changed_t dr_changed_wp;
};
extern int aarch64_num_bp_regs;
extern int aarch64_num_wp_regs;
unsigned int aarch64_watchpoint_length (unsigned int ctrl);
int aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
int len, int is_insert,
struct aarch64_debug_reg_state *state);
int aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
int len, int is_insert,
struct aarch64_debug_reg_state *state);
void aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state,
int is_watchpoint, unsigned int idx);
void aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
int tid, int watchpoint);
void aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
const char *func, CORE_ADDR addr,
int len, enum target_hw_bp_type type);
#endif /* AARCH64_LINUX_HW_POINT_H */