Add ATPCS register naming support
This commit is contained in:
Nick Clifton
parent
2c1c4c6219
commit
557537a556
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@ -1,5 +1,9 @@
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2000-01-31 Geoff Keating <geoffk@cygnus.com>
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2000-01-31 Nick Clifton <nickc@cygnus.com>
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* config/tc-arm.c (reg_table): Add support for ATPCS register
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naming conventions.
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2000-01-31 Geoff Keating <geoffk@cygnus.com>
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* config/obj-coff.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Don't define if
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already defined.
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* config/tc-ppc.h [OBJ_XCOFF] (OBJ_COPY_SYMBOL_ATTRIBUTES):
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@ -857,20 +857,22 @@ struct reg_entry
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#define REG_LR 14
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#define REG_SP 13
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/* These are the standard names; Users can add aliases with .req */
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/* These are the standard names. Users can add aliases with .req */
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static CONST struct reg_entry reg_table[] =
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{
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/* Processor Register Numbers */
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/* Processor Register Numbers. */
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{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
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{"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
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{"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
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{"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
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/* APCS conventions */
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/* APCS conventions. */
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{"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
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{"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
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{"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
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{"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
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/* FP Registers */
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/* ATPCS additions to APCS conventions. */
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{"wr", 7}, {"v8", 11},
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/* FP Registers. */
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{"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
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{"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
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{"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
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@ -881,6 +883,13 @@ static CONST struct reg_entry reg_table[] =
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{"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
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{"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
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{"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
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/* ATPCS additions to float register names. */
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{"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
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{"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
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{"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
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{"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
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/* FIXME: At some point we need to add VFP register names. */
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/* Array terminator. */
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{NULL, 0}
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};
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@ -1,3 +1,11 @@
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2000-01-31 Nick Clifton <nickc@cygnus.com>
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* gas/arm/inst.s: Include test of ATPCS register naming
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conventions.
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* gas/arm/float.s: Include test of ATPCS register naming
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conventions.
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Fri Jan 21 12:48:06 2000 H.J. Lu <hjl@gnu.org>
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* gas/i386/general.l: Support a.out.
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@ -4,21 +4,21 @@
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mvfeqe f3, f5
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mvfeqd f4, #1.0
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mvfs f4, f7
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mvfsp f0, f1
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mvfdm f3, f4
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mvfez f7, f7
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mvfsp s0, s1
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mvfdm s3, s4
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mvfez s7, s7
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adfe f0, f1, #2.0
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adfeqe f1, f2, #0.5
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adfsm f3, f4, f5
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adfeqe f1, s2, #0.5
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adfsm f3, f4, s5
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sufd f0, f0, #2.0
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sufs f1, f2, #10.0
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sufneez f3, f4, f5
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sufd d0, f0, #2.0
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sufs d1, d2, #10.0
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sufneez d3, d4, d5
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rsfs f1, f1, #0.0
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rsfdp f3, f0, #5.0
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rsfled f7, f6, f0
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rsfled f7, s6, f0
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mufd f0, f0, f0
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mufez f1, f2, #3.0
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@ -34,9 +34,9 @@
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powd f0, f2, f3
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pows f1, f3, #0e1e1
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powcsez f4, f7, #1
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powcsez f4, d7, #1
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rpws f7, f6, f7
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rpws f7, d6, f7
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rpweqd f0, f1, f2
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rpwem f2, f2, f3
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@ -9,25 +9,25 @@
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mov r8, r9, asr r10
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mov r11, r12, asl r13
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mov r14, r15, rrx
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moval r1, r2
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moveq r2, r3
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movne r4, r5
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movlt r6, r7
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movge r8, r9
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movle r10, r11
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movgt r12, r13
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moval a2, a3
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moveq a3, a4
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movne v1, v2
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movlt v3, v4
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movge v5, v6
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movle v7, v8
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movgt ip, sp
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movcc r1, r2
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movcs r1, r3
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movmi r3, r6
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movpl r7, r9
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movpl wr, sb
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movvs r1, r8
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movvc r9, r1, lsr #31
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movhi r8, r15
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movls r15, r14
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movvc SB, r1, lsr #31
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movhi r8, pc
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movls PC, lr
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movhs r9, r8
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movul r1, r3
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movs r0, r8
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movuls r0, r7
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movuls r0, WR
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add r0, r1, #10
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add r2, r3, r4
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@ -129,10 +129,10 @@
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mulne r0, r1, r0
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mullss r9, r8, r7
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mla r1, r9, r10, r11
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mlas r3, r4, r9, r12
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mlalt r9, r8, r7, r13
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mlages r4, r1, r3, r14
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mla r1, r9, sl, fp
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mlas r3, r4, r9, IP
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mlalt r9, r8, r7, SP
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mlages r4, r1, r3, LR
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ldr r0, [r1]
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ldr r1, [r1, r2]
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@ -165,7 +165,7 @@ bar:
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ldmia r0, {r1}
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ldmeqib r2, {r3, r4, r5}
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ldmalda r3, {r0-r15}^
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ldmdb r11!, {r0-r8, r10}
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ldmdb FP!, {r0-r8, SL}
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ldmed r1, {r0, r1, r2}|0xf0
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ldmfd r2, {r3, r4}+{r5, r6, r7, r8}
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ldmea r3, 3
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